Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1 | ; RUN: opt -S -mtriple=amdgcn-- -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=SI %s |
| 2 | ; RUN: opt -S -mtriple=amdgcn-- -mcpu=tonga -amdgpu-codegenprepare %s | FileCheck -check-prefix=GCN -check-prefix=VI %s |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 3 | |
Konstantin Zhuravlyov | f74fc60 | 2016-10-07 14:22:58 +0000 | [diff] [blame] | 4 | ; GCN-LABEL: @add_i3( |
| 5 | ; SI: %r = add i3 %a, %b |
| 6 | ; SI-NEXT: ret i3 %r |
| 7 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 8 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 9 | ; VI-NEXT: %[[R_32:[0-9]+]] = add i32 %[[A_32]], %[[B_32]] |
| 10 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 11 | ; VI-NEXT: ret i3 %[[R_3]] |
| 12 | define i3 @add_i3(i3 %a, i3 %b) { |
| 13 | %r = add i3 %a, %b |
| 14 | ret i3 %r |
| 15 | } |
| 16 | |
| 17 | ; GCN-LABEL: @add_nsw_i3( |
| 18 | ; SI: %r = add nsw i3 %a, %b |
| 19 | ; SI-NEXT: ret i3 %r |
| 20 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 21 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 22 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nsw i32 %[[A_32]], %[[B_32]] |
| 23 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 24 | ; VI-NEXT: ret i3 %[[R_3]] |
| 25 | define i3 @add_nsw_i3(i3 %a, i3 %b) { |
| 26 | %r = add nsw i3 %a, %b |
| 27 | ret i3 %r |
| 28 | } |
| 29 | |
| 30 | ; GCN-LABEL: @add_nuw_i3( |
| 31 | ; SI: %r = add nuw i3 %a, %b |
| 32 | ; SI-NEXT: ret i3 %r |
| 33 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 34 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 35 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw i32 %[[A_32]], %[[B_32]] |
| 36 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 37 | ; VI-NEXT: ret i3 %[[R_3]] |
| 38 | define i3 @add_nuw_i3(i3 %a, i3 %b) { |
| 39 | %r = add nuw i3 %a, %b |
| 40 | ret i3 %r |
| 41 | } |
| 42 | |
| 43 | ; GCN-LABEL: @add_nuw_nsw_i3( |
| 44 | ; SI: %r = add nuw nsw i3 %a, %b |
| 45 | ; SI-NEXT: ret i3 %r |
| 46 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 47 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 48 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw i32 %[[A_32]], %[[B_32]] |
| 49 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 50 | ; VI-NEXT: ret i3 %[[R_3]] |
| 51 | define i3 @add_nuw_nsw_i3(i3 %a, i3 %b) { |
| 52 | %r = add nuw nsw i3 %a, %b |
| 53 | ret i3 %r |
| 54 | } |
| 55 | |
| 56 | ; GCN-LABEL: @sub_i3( |
| 57 | ; SI: %r = sub i3 %a, %b |
| 58 | ; SI-NEXT: ret i3 %r |
| 59 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 60 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 61 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub i32 %[[A_32]], %[[B_32]] |
| 62 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 63 | ; VI-NEXT: ret i3 %[[R_3]] |
| 64 | define i3 @sub_i3(i3 %a, i3 %b) { |
| 65 | %r = sub i3 %a, %b |
| 66 | ret i3 %r |
| 67 | } |
| 68 | |
| 69 | ; GCN-LABEL: @sub_nsw_i3( |
| 70 | ; SI: %r = sub nsw i3 %a, %b |
| 71 | ; SI-NEXT: ret i3 %r |
| 72 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 73 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 74 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nsw i32 %[[A_32]], %[[B_32]] |
| 75 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 76 | ; VI-NEXT: ret i3 %[[R_3]] |
| 77 | define i3 @sub_nsw_i3(i3 %a, i3 %b) { |
| 78 | %r = sub nsw i3 %a, %b |
| 79 | ret i3 %r |
| 80 | } |
| 81 | |
| 82 | ; GCN-LABEL: @sub_nuw_i3( |
| 83 | ; SI: %r = sub nuw i3 %a, %b |
| 84 | ; SI-NEXT: ret i3 %r |
| 85 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 86 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 87 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw i32 %[[A_32]], %[[B_32]] |
| 88 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 89 | ; VI-NEXT: ret i3 %[[R_3]] |
| 90 | define i3 @sub_nuw_i3(i3 %a, i3 %b) { |
| 91 | %r = sub nuw i3 %a, %b |
| 92 | ret i3 %r |
| 93 | } |
| 94 | |
| 95 | ; GCN-LABEL: @sub_nuw_nsw_i3( |
| 96 | ; SI: %r = sub nuw nsw i3 %a, %b |
| 97 | ; SI-NEXT: ret i3 %r |
| 98 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 99 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 100 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw nsw i32 %[[A_32]], %[[B_32]] |
| 101 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 102 | ; VI-NEXT: ret i3 %[[R_3]] |
| 103 | define i3 @sub_nuw_nsw_i3(i3 %a, i3 %b) { |
| 104 | %r = sub nuw nsw i3 %a, %b |
| 105 | ret i3 %r |
| 106 | } |
| 107 | |
| 108 | ; GCN-LABEL: @mul_i3( |
| 109 | ; SI: %r = mul i3 %a, %b |
| 110 | ; SI-NEXT: ret i3 %r |
| 111 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 112 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 113 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul i32 %[[A_32]], %[[B_32]] |
| 114 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 115 | ; VI-NEXT: ret i3 %[[R_3]] |
| 116 | define i3 @mul_i3(i3 %a, i3 %b) { |
| 117 | %r = mul i3 %a, %b |
| 118 | ret i3 %r |
| 119 | } |
| 120 | |
| 121 | ; GCN-LABEL: @mul_nsw_i3( |
| 122 | ; SI: %r = mul nsw i3 %a, %b |
| 123 | ; SI-NEXT: ret i3 %r |
| 124 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 125 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 126 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nsw i32 %[[A_32]], %[[B_32]] |
| 127 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 128 | ; VI-NEXT: ret i3 %[[R_3]] |
| 129 | define i3 @mul_nsw_i3(i3 %a, i3 %b) { |
| 130 | %r = mul nsw i3 %a, %b |
| 131 | ret i3 %r |
| 132 | } |
| 133 | |
| 134 | ; GCN-LABEL: @mul_nuw_i3( |
| 135 | ; SI: %r = mul nuw i3 %a, %b |
| 136 | ; SI-NEXT: ret i3 %r |
| 137 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 138 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 139 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw i32 %[[A_32]], %[[B_32]] |
| 140 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 141 | ; VI-NEXT: ret i3 %[[R_3]] |
| 142 | define i3 @mul_nuw_i3(i3 %a, i3 %b) { |
| 143 | %r = mul nuw i3 %a, %b |
| 144 | ret i3 %r |
| 145 | } |
| 146 | |
| 147 | ; GCN-LABEL: @mul_nuw_nsw_i3( |
| 148 | ; SI: %r = mul nuw nsw i3 %a, %b |
| 149 | ; SI-NEXT: ret i3 %r |
| 150 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 151 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 152 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw nsw i32 %[[A_32]], %[[B_32]] |
| 153 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 154 | ; VI-NEXT: ret i3 %[[R_3]] |
| 155 | define i3 @mul_nuw_nsw_i3(i3 %a, i3 %b) { |
| 156 | %r = mul nuw nsw i3 %a, %b |
| 157 | ret i3 %r |
| 158 | } |
| 159 | |
| 160 | ; GCN-LABEL: @urem_i3( |
| 161 | ; SI: %r = urem i3 %a, %b |
| 162 | ; SI-NEXT: ret i3 %r |
| 163 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 164 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 165 | ; VI-NEXT: %[[R_32:[0-9]+]] = urem i32 %[[A_32]], %[[B_32]] |
| 166 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 167 | ; VI-NEXT: ret i3 %[[R_3]] |
| 168 | define i3 @urem_i3(i3 %a, i3 %b) { |
| 169 | %r = urem i3 %a, %b |
| 170 | ret i3 %r |
| 171 | } |
| 172 | |
| 173 | ; GCN-LABEL: @srem_i3( |
| 174 | ; SI: %r = srem i3 %a, %b |
| 175 | ; SI-NEXT: ret i3 %r |
| 176 | ; VI: %[[A_32:[0-9]+]] = sext i3 %a to i32 |
| 177 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i3 %b to i32 |
| 178 | ; VI-NEXT: %[[R_32:[0-9]+]] = srem i32 %[[A_32]], %[[B_32]] |
| 179 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 180 | ; VI-NEXT: ret i3 %[[R_3]] |
| 181 | define i3 @srem_i3(i3 %a, i3 %b) { |
| 182 | %r = srem i3 %a, %b |
| 183 | ret i3 %r |
| 184 | } |
| 185 | |
| 186 | ; GCN-LABEL: @shl_i3( |
| 187 | ; SI: %r = shl i3 %a, %b |
| 188 | ; SI-NEXT: ret i3 %r |
| 189 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 190 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 191 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl i32 %[[A_32]], %[[B_32]] |
| 192 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 193 | ; VI-NEXT: ret i3 %[[R_3]] |
| 194 | define i3 @shl_i3(i3 %a, i3 %b) { |
| 195 | %r = shl i3 %a, %b |
| 196 | ret i3 %r |
| 197 | } |
| 198 | |
| 199 | ; GCN-LABEL: @shl_nsw_i3( |
| 200 | ; SI: %r = shl nsw i3 %a, %b |
| 201 | ; SI-NEXT: ret i3 %r |
| 202 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 203 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 204 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nsw i32 %[[A_32]], %[[B_32]] |
| 205 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 206 | ; VI-NEXT: ret i3 %[[R_3]] |
| 207 | define i3 @shl_nsw_i3(i3 %a, i3 %b) { |
| 208 | %r = shl nsw i3 %a, %b |
| 209 | ret i3 %r |
| 210 | } |
| 211 | |
| 212 | ; GCN-LABEL: @shl_nuw_i3( |
| 213 | ; SI: %r = shl nuw i3 %a, %b |
| 214 | ; SI-NEXT: ret i3 %r |
| 215 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 216 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 217 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw i32 %[[A_32]], %[[B_32]] |
| 218 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 219 | ; VI-NEXT: ret i3 %[[R_3]] |
| 220 | define i3 @shl_nuw_i3(i3 %a, i3 %b) { |
| 221 | %r = shl nuw i3 %a, %b |
| 222 | ret i3 %r |
| 223 | } |
| 224 | |
| 225 | ; GCN-LABEL: @shl_nuw_nsw_i3( |
| 226 | ; SI: %r = shl nuw nsw i3 %a, %b |
| 227 | ; SI-NEXT: ret i3 %r |
| 228 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 229 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 230 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw nsw i32 %[[A_32]], %[[B_32]] |
| 231 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 232 | ; VI-NEXT: ret i3 %[[R_3]] |
| 233 | define i3 @shl_nuw_nsw_i3(i3 %a, i3 %b) { |
| 234 | %r = shl nuw nsw i3 %a, %b |
| 235 | ret i3 %r |
| 236 | } |
| 237 | |
| 238 | ; GCN-LABEL: @lshr_i3( |
| 239 | ; SI: %r = lshr i3 %a, %b |
| 240 | ; SI-NEXT: ret i3 %r |
| 241 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 242 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 243 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr i32 %[[A_32]], %[[B_32]] |
| 244 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 245 | ; VI-NEXT: ret i3 %[[R_3]] |
| 246 | define i3 @lshr_i3(i3 %a, i3 %b) { |
| 247 | %r = lshr i3 %a, %b |
| 248 | ret i3 %r |
| 249 | } |
| 250 | |
| 251 | ; GCN-LABEL: @lshr_exact_i3( |
| 252 | ; SI: %r = lshr exact i3 %a, %b |
| 253 | ; SI-NEXT: ret i3 %r |
| 254 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 255 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 256 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr exact i32 %[[A_32]], %[[B_32]] |
| 257 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 258 | ; VI-NEXT: ret i3 %[[R_3]] |
| 259 | define i3 @lshr_exact_i3(i3 %a, i3 %b) { |
| 260 | %r = lshr exact i3 %a, %b |
| 261 | ret i3 %r |
| 262 | } |
| 263 | |
| 264 | ; GCN-LABEL: @ashr_i3( |
| 265 | ; SI: %r = ashr i3 %a, %b |
| 266 | ; SI-NEXT: ret i3 %r |
| 267 | ; VI: %[[A_32:[0-9]+]] = sext i3 %a to i32 |
| 268 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i3 %b to i32 |
| 269 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]] |
| 270 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 271 | ; VI-NEXT: ret i3 %[[R_3]] |
| 272 | define i3 @ashr_i3(i3 %a, i3 %b) { |
| 273 | %r = ashr i3 %a, %b |
| 274 | ret i3 %r |
| 275 | } |
| 276 | |
| 277 | ; GCN-LABEL: @ashr_exact_i3( |
| 278 | ; SI: %r = ashr exact i3 %a, %b |
| 279 | ; SI-NEXT: ret i3 %r |
| 280 | ; VI: %[[A_32:[0-9]+]] = sext i3 %a to i32 |
| 281 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i3 %b to i32 |
| 282 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]] |
| 283 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 284 | ; VI-NEXT: ret i3 %[[R_3]] |
| 285 | define i3 @ashr_exact_i3(i3 %a, i3 %b) { |
| 286 | %r = ashr exact i3 %a, %b |
| 287 | ret i3 %r |
| 288 | } |
| 289 | |
| 290 | ; GCN-LABEL: @and_i3( |
| 291 | ; SI: %r = and i3 %a, %b |
| 292 | ; SI-NEXT: ret i3 %r |
| 293 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 294 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 295 | ; VI-NEXT: %[[R_32:[0-9]+]] = and i32 %[[A_32]], %[[B_32]] |
| 296 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 297 | ; VI-NEXT: ret i3 %[[R_3]] |
| 298 | define i3 @and_i3(i3 %a, i3 %b) { |
| 299 | %r = and i3 %a, %b |
| 300 | ret i3 %r |
| 301 | } |
| 302 | |
| 303 | ; GCN-LABEL: @or_i3( |
| 304 | ; SI: %r = or i3 %a, %b |
| 305 | ; SI-NEXT: ret i3 %r |
| 306 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 307 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 308 | ; VI-NEXT: %[[R_32:[0-9]+]] = or i32 %[[A_32]], %[[B_32]] |
| 309 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 310 | ; VI-NEXT: ret i3 %[[R_3]] |
| 311 | define i3 @or_i3(i3 %a, i3 %b) { |
| 312 | %r = or i3 %a, %b |
| 313 | ret i3 %r |
| 314 | } |
| 315 | |
| 316 | ; GCN-LABEL: @xor_i3( |
| 317 | ; SI: %r = xor i3 %a, %b |
| 318 | ; SI-NEXT: ret i3 %r |
| 319 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 320 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i3 %b to i32 |
| 321 | ; VI-NEXT: %[[R_32:[0-9]+]] = xor i32 %[[A_32]], %[[B_32]] |
| 322 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[R_32]] to i3 |
| 323 | ; VI-NEXT: ret i3 %[[R_3]] |
| 324 | define i3 @xor_i3(i3 %a, i3 %b) { |
| 325 | %r = xor i3 %a, %b |
| 326 | ret i3 %r |
| 327 | } |
| 328 | |
| 329 | ; GCN-LABEL: @select_eq_i3( |
| 330 | ; SI: %cmp = icmp eq i3 %a, %b |
| 331 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 332 | ; SI-NEXT: ret i3 %sel |
| 333 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 334 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 335 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp eq i32 %[[A_32_0]], %[[B_32_0]] |
| 336 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 337 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 338 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 339 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 340 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 341 | define i3 @select_eq_i3(i3 %a, i3 %b) { |
| 342 | %cmp = icmp eq i3 %a, %b |
| 343 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 344 | ret i3 %sel |
| 345 | } |
| 346 | |
| 347 | ; GCN-LABEL: @select_ne_i3( |
| 348 | ; SI: %cmp = icmp ne i3 %a, %b |
| 349 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 350 | ; SI-NEXT: ret i3 %sel |
| 351 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 352 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 353 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ne i32 %[[A_32_0]], %[[B_32_0]] |
| 354 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 355 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 356 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 357 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 358 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 359 | define i3 @select_ne_i3(i3 %a, i3 %b) { |
| 360 | %cmp = icmp ne i3 %a, %b |
| 361 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 362 | ret i3 %sel |
| 363 | } |
| 364 | |
| 365 | ; GCN-LABEL: @select_ugt_i3( |
| 366 | ; SI: %cmp = icmp ugt i3 %a, %b |
| 367 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 368 | ; SI-NEXT: ret i3 %sel |
| 369 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 370 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 371 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ugt i32 %[[A_32_0]], %[[B_32_0]] |
| 372 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 373 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 374 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 375 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 376 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 377 | define i3 @select_ugt_i3(i3 %a, i3 %b) { |
| 378 | %cmp = icmp ugt i3 %a, %b |
| 379 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 380 | ret i3 %sel |
| 381 | } |
| 382 | |
| 383 | ; GCN-LABEL: @select_uge_i3( |
| 384 | ; SI: %cmp = icmp uge i3 %a, %b |
| 385 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 386 | ; SI-NEXT: ret i3 %sel |
| 387 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 388 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 389 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp uge i32 %[[A_32_0]], %[[B_32_0]] |
| 390 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 391 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 392 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 393 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 394 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 395 | define i3 @select_uge_i3(i3 %a, i3 %b) { |
| 396 | %cmp = icmp uge i3 %a, %b |
| 397 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 398 | ret i3 %sel |
| 399 | } |
| 400 | |
| 401 | ; GCN-LABEL: @select_ult_i3( |
| 402 | ; SI: %cmp = icmp ult i3 %a, %b |
| 403 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 404 | ; SI-NEXT: ret i3 %sel |
| 405 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 406 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 407 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ult i32 %[[A_32_0]], %[[B_32_0]] |
| 408 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 409 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 410 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 411 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 412 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 413 | define i3 @select_ult_i3(i3 %a, i3 %b) { |
| 414 | %cmp = icmp ult i3 %a, %b |
| 415 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 416 | ret i3 %sel |
| 417 | } |
| 418 | |
| 419 | ; GCN-LABEL: @select_ule_i3( |
| 420 | ; SI: %cmp = icmp ule i3 %a, %b |
| 421 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 422 | ; SI-NEXT: ret i3 %sel |
| 423 | ; VI: %[[A_32_0:[0-9]+]] = zext i3 %a to i32 |
| 424 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i3 %b to i32 |
| 425 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ule i32 %[[A_32_0]], %[[B_32_0]] |
| 426 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i3 %a to i32 |
| 427 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i3 %b to i32 |
| 428 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 429 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 430 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 431 | define i3 @select_ule_i3(i3 %a, i3 %b) { |
| 432 | %cmp = icmp ule i3 %a, %b |
| 433 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 434 | ret i3 %sel |
| 435 | } |
| 436 | |
| 437 | ; GCN-LABEL: @select_sgt_i3( |
| 438 | ; SI: %cmp = icmp sgt i3 %a, %b |
| 439 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 440 | ; SI-NEXT: ret i3 %sel |
| 441 | ; VI: %[[A_32_0:[0-9]+]] = sext i3 %a to i32 |
| 442 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i3 %b to i32 |
| 443 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sgt i32 %[[A_32_0]], %[[B_32_0]] |
| 444 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i3 %a to i32 |
| 445 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i3 %b to i32 |
| 446 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 447 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 448 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 449 | define i3 @select_sgt_i3(i3 %a, i3 %b) { |
| 450 | %cmp = icmp sgt i3 %a, %b |
| 451 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 452 | ret i3 %sel |
| 453 | } |
| 454 | |
| 455 | ; GCN-LABEL: @select_sge_i3( |
| 456 | ; SI: %cmp = icmp sge i3 %a, %b |
| 457 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 458 | ; SI-NEXT: ret i3 %sel |
| 459 | ; VI: %[[A_32_0:[0-9]+]] = sext i3 %a to i32 |
| 460 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i3 %b to i32 |
| 461 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sge i32 %[[A_32_0]], %[[B_32_0]] |
| 462 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i3 %a to i32 |
| 463 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i3 %b to i32 |
| 464 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 465 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 466 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 467 | define i3 @select_sge_i3(i3 %a, i3 %b) { |
| 468 | %cmp = icmp sge i3 %a, %b |
| 469 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 470 | ret i3 %sel |
| 471 | } |
| 472 | |
| 473 | ; GCN-LABEL: @select_slt_i3( |
| 474 | ; SI: %cmp = icmp slt i3 %a, %b |
| 475 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 476 | ; SI-NEXT: ret i3 %sel |
| 477 | ; VI: %[[A_32_0:[0-9]+]] = sext i3 %a to i32 |
| 478 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i3 %b to i32 |
| 479 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp slt i32 %[[A_32_0]], %[[B_32_0]] |
| 480 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i3 %a to i32 |
| 481 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i3 %b to i32 |
| 482 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 483 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 484 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 485 | define i3 @select_slt_i3(i3 %a, i3 %b) { |
| 486 | %cmp = icmp slt i3 %a, %b |
| 487 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 488 | ret i3 %sel |
| 489 | } |
| 490 | |
| 491 | ; GCN-LABEL: @select_sle_i3( |
| 492 | ; SI: %cmp = icmp sle i3 %a, %b |
| 493 | ; SI-NEXT: %sel = select i1 %cmp, i3 %a, i3 %b |
| 494 | ; SI-NEXT: ret i3 %sel |
| 495 | ; VI: %[[A_32_0:[0-9]+]] = sext i3 %a to i32 |
| 496 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i3 %b to i32 |
| 497 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sle i32 %[[A_32_0]], %[[B_32_0]] |
| 498 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i3 %a to i32 |
| 499 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i3 %b to i32 |
| 500 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 501 | ; VI-NEXT: %[[SEL_3:[0-9]+]] = trunc i32 %[[SEL_32]] to i3 |
| 502 | ; VI-NEXT: ret i3 %[[SEL_3]] |
| 503 | define i3 @select_sle_i3(i3 %a, i3 %b) { |
| 504 | %cmp = icmp sle i3 %a, %b |
| 505 | %sel = select i1 %cmp, i3 %a, i3 %b |
| 506 | ret i3 %sel |
| 507 | } |
| 508 | |
| 509 | declare i3 @llvm.bitreverse.i3(i3) |
| 510 | ; GCN-LABEL: @bitreverse_i3( |
| 511 | ; SI: %brev = call i3 @llvm.bitreverse.i3(i3 %a) |
| 512 | ; SI-NEXT: ret i3 %brev |
| 513 | ; VI: %[[A_32:[0-9]+]] = zext i3 %a to i32 |
| 514 | ; VI-NEXT: %[[R_32:[0-9]+]] = call i32 @llvm.bitreverse.i32(i32 %[[A_32]]) |
| 515 | ; VI-NEXT: %[[S_32:[0-9]+]] = lshr i32 %[[R_32]], 29 |
| 516 | ; VI-NEXT: %[[R_3:[0-9]+]] = trunc i32 %[[S_32]] to i3 |
| 517 | ; VI-NEXT: ret i3 %[[R_3]] |
| 518 | define i3 @bitreverse_i3(i3 %a) { |
| 519 | %brev = call i3 @llvm.bitreverse.i3(i3 %a) |
| 520 | ret i3 %brev |
| 521 | } |
| 522 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 523 | ; GCN-LABEL: @add_i16( |
| 524 | ; SI: %r = add i16 %a, %b |
| 525 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 526 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 527 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 528 | ; VI-NEXT: %[[R_32:[0-9]+]] = add i32 %[[A_32]], %[[B_32]] |
| 529 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 530 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 531 | define i16 @add_i16(i16 %a, i16 %b) { |
| 532 | %r = add i16 %a, %b |
| 533 | ret i16 %r |
| 534 | } |
| 535 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 536 | ; GCN-LABEL: @add_nsw_i16( |
| 537 | ; SI: %r = add nsw i16 %a, %b |
| 538 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 539 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 540 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 541 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nsw i32 %[[A_32]], %[[B_32]] |
| 542 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 543 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 544 | define i16 @add_nsw_i16(i16 %a, i16 %b) { |
| 545 | %r = add nsw i16 %a, %b |
| 546 | ret i16 %r |
| 547 | } |
| 548 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 549 | ; GCN-LABEL: @add_nuw_i16( |
| 550 | ; SI: %r = add nuw i16 %a, %b |
| 551 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 552 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 553 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 554 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw i32 %[[A_32]], %[[B_32]] |
| 555 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 556 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 557 | define i16 @add_nuw_i16(i16 %a, i16 %b) { |
| 558 | %r = add nuw i16 %a, %b |
| 559 | ret i16 %r |
| 560 | } |
| 561 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 562 | ; GCN-LABEL: @add_nuw_nsw_i16( |
| 563 | ; SI: %r = add nuw nsw i16 %a, %b |
| 564 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 565 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 566 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 567 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw i32 %[[A_32]], %[[B_32]] |
| 568 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 569 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 570 | define i16 @add_nuw_nsw_i16(i16 %a, i16 %b) { |
| 571 | %r = add nuw nsw i16 %a, %b |
| 572 | ret i16 %r |
| 573 | } |
| 574 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 575 | ; GCN-LABEL: @sub_i16( |
| 576 | ; SI: %r = sub i16 %a, %b |
| 577 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 578 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 579 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 580 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub i32 %[[A_32]], %[[B_32]] |
| 581 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 582 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 583 | define i16 @sub_i16(i16 %a, i16 %b) { |
| 584 | %r = sub i16 %a, %b |
| 585 | ret i16 %r |
| 586 | } |
| 587 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 588 | ; GCN-LABEL: @sub_nsw_i16( |
| 589 | ; SI: %r = sub nsw i16 %a, %b |
| 590 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 591 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 592 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 593 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nsw i32 %[[A_32]], %[[B_32]] |
| 594 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 595 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 596 | define i16 @sub_nsw_i16(i16 %a, i16 %b) { |
| 597 | %r = sub nsw i16 %a, %b |
| 598 | ret i16 %r |
| 599 | } |
| 600 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 601 | ; GCN-LABEL: @sub_nuw_i16( |
| 602 | ; SI: %r = sub nuw i16 %a, %b |
| 603 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 604 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 605 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 606 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw i32 %[[A_32]], %[[B_32]] |
| 607 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 608 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 609 | define i16 @sub_nuw_i16(i16 %a, i16 %b) { |
| 610 | %r = sub nuw i16 %a, %b |
| 611 | ret i16 %r |
| 612 | } |
| 613 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 614 | ; GCN-LABEL: @sub_nuw_nsw_i16( |
| 615 | ; SI: %r = sub nuw nsw i16 %a, %b |
| 616 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 617 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 618 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 619 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw nsw i32 %[[A_32]], %[[B_32]] |
| 620 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 621 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 622 | define i16 @sub_nuw_nsw_i16(i16 %a, i16 %b) { |
| 623 | %r = sub nuw nsw i16 %a, %b |
| 624 | ret i16 %r |
| 625 | } |
| 626 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 627 | ; GCN-LABEL: @mul_i16( |
| 628 | ; SI: %r = mul i16 %a, %b |
| 629 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 630 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 631 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 632 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul i32 %[[A_32]], %[[B_32]] |
| 633 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 634 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 635 | define i16 @mul_i16(i16 %a, i16 %b) { |
| 636 | %r = mul i16 %a, %b |
| 637 | ret i16 %r |
| 638 | } |
| 639 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 640 | ; GCN-LABEL: @mul_nsw_i16( |
| 641 | ; SI: %r = mul nsw i16 %a, %b |
| 642 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 643 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 644 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 645 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nsw i32 %[[A_32]], %[[B_32]] |
| 646 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 647 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 648 | define i16 @mul_nsw_i16(i16 %a, i16 %b) { |
| 649 | %r = mul nsw i16 %a, %b |
| 650 | ret i16 %r |
| 651 | } |
| 652 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 653 | ; GCN-LABEL: @mul_nuw_i16( |
| 654 | ; SI: %r = mul nuw i16 %a, %b |
| 655 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 656 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 657 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 658 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw i32 %[[A_32]], %[[B_32]] |
| 659 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 660 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 661 | define i16 @mul_nuw_i16(i16 %a, i16 %b) { |
| 662 | %r = mul nuw i16 %a, %b |
| 663 | ret i16 %r |
| 664 | } |
| 665 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 666 | ; GCN-LABEL: @mul_nuw_nsw_i16( |
| 667 | ; SI: %r = mul nuw nsw i16 %a, %b |
| 668 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 669 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 670 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 671 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw nsw i32 %[[A_32]], %[[B_32]] |
| 672 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 673 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 674 | define i16 @mul_nuw_nsw_i16(i16 %a, i16 %b) { |
| 675 | %r = mul nuw nsw i16 %a, %b |
| 676 | ret i16 %r |
| 677 | } |
| 678 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 679 | ; GCN-LABEL: @urem_i16( |
| 680 | ; SI: %r = urem i16 %a, %b |
| 681 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 682 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 683 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 684 | ; VI-NEXT: %[[R_32:[0-9]+]] = urem i32 %[[A_32]], %[[B_32]] |
| 685 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 686 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 687 | define i16 @urem_i16(i16 %a, i16 %b) { |
| 688 | %r = urem i16 %a, %b |
| 689 | ret i16 %r |
| 690 | } |
| 691 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 692 | ; GCN-LABEL: @srem_i16( |
| 693 | ; SI: %r = srem i16 %a, %b |
| 694 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 695 | ; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 696 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32 |
| 697 | ; VI-NEXT: %[[R_32:[0-9]+]] = srem i32 %[[A_32]], %[[B_32]] |
| 698 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 699 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 700 | define i16 @srem_i16(i16 %a, i16 %b) { |
| 701 | %r = srem i16 %a, %b |
| 702 | ret i16 %r |
| 703 | } |
| 704 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 705 | ; GCN-LABEL: @shl_i16( |
| 706 | ; SI: %r = shl i16 %a, %b |
| 707 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 708 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 709 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 710 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl i32 %[[A_32]], %[[B_32]] |
| 711 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 712 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 713 | define i16 @shl_i16(i16 %a, i16 %b) { |
| 714 | %r = shl i16 %a, %b |
| 715 | ret i16 %r |
| 716 | } |
| 717 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 718 | ; GCN-LABEL: @shl_nsw_i16( |
| 719 | ; SI: %r = shl nsw i16 %a, %b |
| 720 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 721 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 722 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 723 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nsw i32 %[[A_32]], %[[B_32]] |
| 724 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 725 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 726 | define i16 @shl_nsw_i16(i16 %a, i16 %b) { |
| 727 | %r = shl nsw i16 %a, %b |
| 728 | ret i16 %r |
| 729 | } |
| 730 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 731 | ; GCN-LABEL: @shl_nuw_i16( |
| 732 | ; SI: %r = shl nuw i16 %a, %b |
| 733 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 734 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 735 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 736 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw i32 %[[A_32]], %[[B_32]] |
| 737 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 738 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 739 | define i16 @shl_nuw_i16(i16 %a, i16 %b) { |
| 740 | %r = shl nuw i16 %a, %b |
| 741 | ret i16 %r |
| 742 | } |
| 743 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 744 | ; GCN-LABEL: @shl_nuw_nsw_i16( |
| 745 | ; SI: %r = shl nuw nsw i16 %a, %b |
| 746 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 747 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 748 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 749 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw nsw i32 %[[A_32]], %[[B_32]] |
| 750 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 751 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 752 | define i16 @shl_nuw_nsw_i16(i16 %a, i16 %b) { |
| 753 | %r = shl nuw nsw i16 %a, %b |
| 754 | ret i16 %r |
| 755 | } |
| 756 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 757 | ; GCN-LABEL: @lshr_i16( |
| 758 | ; SI: %r = lshr i16 %a, %b |
| 759 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 760 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 761 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 762 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr i32 %[[A_32]], %[[B_32]] |
| 763 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 764 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 765 | define i16 @lshr_i16(i16 %a, i16 %b) { |
| 766 | %r = lshr i16 %a, %b |
| 767 | ret i16 %r |
| 768 | } |
| 769 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 770 | ; GCN-LABEL: @lshr_exact_i16( |
| 771 | ; SI: %r = lshr exact i16 %a, %b |
| 772 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 773 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 774 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 775 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr exact i32 %[[A_32]], %[[B_32]] |
| 776 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 777 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 778 | define i16 @lshr_exact_i16(i16 %a, i16 %b) { |
| 779 | %r = lshr exact i16 %a, %b |
| 780 | ret i16 %r |
| 781 | } |
| 782 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 783 | ; GCN-LABEL: @ashr_i16( |
| 784 | ; SI: %r = ashr i16 %a, %b |
| 785 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | 691e2e0 | 2016-10-03 18:29:01 +0000 | [diff] [blame] | 786 | ; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 787 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32 |
| 788 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr i32 %[[A_32]], %[[B_32]] |
| 789 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 790 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 791 | define i16 @ashr_i16(i16 %a, i16 %b) { |
| 792 | %r = ashr i16 %a, %b |
| 793 | ret i16 %r |
| 794 | } |
| 795 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 796 | ; GCN-LABEL: @ashr_exact_i16( |
| 797 | ; SI: %r = ashr exact i16 %a, %b |
| 798 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | 691e2e0 | 2016-10-03 18:29:01 +0000 | [diff] [blame] | 799 | ; VI: %[[A_32:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 800 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext i16 %b to i32 |
| 801 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact i32 %[[A_32]], %[[B_32]] |
| 802 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 803 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 804 | define i16 @ashr_exact_i16(i16 %a, i16 %b) { |
| 805 | %r = ashr exact i16 %a, %b |
| 806 | ret i16 %r |
| 807 | } |
| 808 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 809 | ; GCN-LABEL: @and_i16( |
| 810 | ; SI: %r = and i16 %a, %b |
| 811 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 812 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 813 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 814 | ; VI-NEXT: %[[R_32:[0-9]+]] = and i32 %[[A_32]], %[[B_32]] |
| 815 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 816 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 817 | define i16 @and_i16(i16 %a, i16 %b) { |
| 818 | %r = and i16 %a, %b |
| 819 | ret i16 %r |
| 820 | } |
| 821 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 822 | ; GCN-LABEL: @or_i16( |
| 823 | ; SI: %r = or i16 %a, %b |
| 824 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 825 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 826 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 827 | ; VI-NEXT: %[[R_32:[0-9]+]] = or i32 %[[A_32]], %[[B_32]] |
| 828 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 829 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 830 | define i16 @or_i16(i16 %a, i16 %b) { |
| 831 | %r = or i16 %a, %b |
| 832 | ret i16 %r |
| 833 | } |
| 834 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 835 | ; GCN-LABEL: @xor_i16( |
| 836 | ; SI: %r = xor i16 %a, %b |
| 837 | ; SI-NEXT: ret i16 %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 838 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 839 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext i16 %b to i32 |
| 840 | ; VI-NEXT: %[[R_32:[0-9]+]] = xor i32 %[[A_32]], %[[B_32]] |
| 841 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[R_32]] to i16 |
| 842 | ; VI-NEXT: ret i16 %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 843 | define i16 @xor_i16(i16 %a, i16 %b) { |
| 844 | %r = xor i16 %a, %b |
| 845 | ret i16 %r |
| 846 | } |
| 847 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 848 | ; GCN-LABEL: @select_eq_i16( |
| 849 | ; SI: %cmp = icmp eq i16 %a, %b |
| 850 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 851 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 852 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 853 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 854 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp eq i32 %[[A_32_0]], %[[B_32_0]] |
| 855 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 856 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 857 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 858 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 859 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 860 | define i16 @select_eq_i16(i16 %a, i16 %b) { |
| 861 | %cmp = icmp eq i16 %a, %b |
| 862 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 863 | ret i16 %sel |
| 864 | } |
| 865 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 866 | ; GCN-LABEL: @select_ne_i16( |
| 867 | ; SI: %cmp = icmp ne i16 %a, %b |
| 868 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 869 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 870 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 871 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 872 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ne i32 %[[A_32_0]], %[[B_32_0]] |
| 873 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 874 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 875 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 876 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 877 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 878 | define i16 @select_ne_i16(i16 %a, i16 %b) { |
| 879 | %cmp = icmp ne i16 %a, %b |
| 880 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 881 | ret i16 %sel |
| 882 | } |
| 883 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 884 | ; GCN-LABEL: @select_ugt_i16( |
| 885 | ; SI: %cmp = icmp ugt i16 %a, %b |
| 886 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 887 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 888 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 889 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 890 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ugt i32 %[[A_32_0]], %[[B_32_0]] |
| 891 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 892 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 893 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 894 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 895 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 896 | define i16 @select_ugt_i16(i16 %a, i16 %b) { |
| 897 | %cmp = icmp ugt i16 %a, %b |
| 898 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 899 | ret i16 %sel |
| 900 | } |
| 901 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 902 | ; GCN-LABEL: @select_uge_i16( |
| 903 | ; SI: %cmp = icmp uge i16 %a, %b |
| 904 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 905 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 906 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 907 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 908 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp uge i32 %[[A_32_0]], %[[B_32_0]] |
| 909 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 910 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 911 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 912 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 913 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 914 | define i16 @select_uge_i16(i16 %a, i16 %b) { |
| 915 | %cmp = icmp uge i16 %a, %b |
| 916 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 917 | ret i16 %sel |
| 918 | } |
| 919 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 920 | ; GCN-LABEL: @select_ult_i16( |
| 921 | ; SI: %cmp = icmp ult i16 %a, %b |
| 922 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 923 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 924 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 925 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 926 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ult i32 %[[A_32_0]], %[[B_32_0]] |
| 927 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 928 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 929 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 930 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 931 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 932 | define i16 @select_ult_i16(i16 %a, i16 %b) { |
| 933 | %cmp = icmp ult i16 %a, %b |
| 934 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 935 | ret i16 %sel |
| 936 | } |
| 937 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 938 | ; GCN-LABEL: @select_ule_i16( |
| 939 | ; SI: %cmp = icmp ule i16 %a, %b |
| 940 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 941 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 942 | ; VI: %[[A_32_0:[0-9]+]] = zext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 943 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext i16 %b to i32 |
| 944 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ule i32 %[[A_32_0]], %[[B_32_0]] |
| 945 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext i16 %a to i32 |
| 946 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext i16 %b to i32 |
| 947 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 948 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 949 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 950 | define i16 @select_ule_i16(i16 %a, i16 %b) { |
| 951 | %cmp = icmp ule i16 %a, %b |
| 952 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 953 | ret i16 %sel |
| 954 | } |
| 955 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 956 | ; GCN-LABEL: @select_sgt_i16( |
| 957 | ; SI: %cmp = icmp sgt i16 %a, %b |
| 958 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 959 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 960 | ; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 961 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i16 %b to i32 |
| 962 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sgt i32 %[[A_32_0]], %[[B_32_0]] |
| 963 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i16 %a to i32 |
| 964 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i16 %b to i32 |
| 965 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 966 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 967 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 968 | define i16 @select_sgt_i16(i16 %a, i16 %b) { |
| 969 | %cmp = icmp sgt i16 %a, %b |
| 970 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 971 | ret i16 %sel |
| 972 | } |
| 973 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 974 | ; GCN-LABEL: @select_sge_i16( |
| 975 | ; SI: %cmp = icmp sge i16 %a, %b |
| 976 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 977 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 978 | ; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 979 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i16 %b to i32 |
| 980 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sge i32 %[[A_32_0]], %[[B_32_0]] |
| 981 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i16 %a to i32 |
| 982 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i16 %b to i32 |
| 983 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 984 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 985 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 986 | define i16 @select_sge_i16(i16 %a, i16 %b) { |
| 987 | %cmp = icmp sge i16 %a, %b |
| 988 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 989 | ret i16 %sel |
| 990 | } |
| 991 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 992 | ; GCN-LABEL: @select_slt_i16( |
| 993 | ; SI: %cmp = icmp slt i16 %a, %b |
| 994 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 995 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 996 | ; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 997 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i16 %b to i32 |
| 998 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp slt i32 %[[A_32_0]], %[[B_32_0]] |
| 999 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i16 %a to i32 |
| 1000 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i16 %b to i32 |
| 1001 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 1002 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 1003 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1004 | define i16 @select_slt_i16(i16 %a, i16 %b) { |
| 1005 | %cmp = icmp slt i16 %a, %b |
| 1006 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 1007 | ret i16 %sel |
| 1008 | } |
| 1009 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1010 | ; GCN-LABEL: @select_sle_i16( |
| 1011 | ; SI: %cmp = icmp sle i16 %a, %b |
| 1012 | ; SI-NEXT: %sel = select i1 %cmp, i16 %a, i16 %b |
| 1013 | ; SI-NEXT: ret i16 %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1014 | ; VI: %[[A_32_0:[0-9]+]] = sext i16 %a to i32 |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1015 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext i16 %b to i32 |
| 1016 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sle i32 %[[A_32_0]], %[[B_32_0]] |
| 1017 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext i16 %a to i32 |
| 1018 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext i16 %b to i32 |
| 1019 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select i1 %[[CMP]], i32 %[[A_32_1]], i32 %[[B_32_1]] |
| 1020 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc i32 %[[SEL_32]] to i16 |
| 1021 | ; VI-NEXT: ret i16 %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1022 | define i16 @select_sle_i16(i16 %a, i16 %b) { |
| 1023 | %cmp = icmp sle i16 %a, %b |
| 1024 | %sel = select i1 %cmp, i16 %a, i16 %b |
| 1025 | ret i16 %sel |
| 1026 | } |
| 1027 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1028 | declare i16 @llvm.bitreverse.i16(i16) |
| 1029 | ; GCN-LABEL: @bitreverse_i16( |
| 1030 | ; SI: %brev = call i16 @llvm.bitreverse.i16(i16 %a) |
| 1031 | ; SI-NEXT: ret i16 %brev |
| 1032 | ; VI: %[[A_32:[0-9]+]] = zext i16 %a to i32 |
| 1033 | ; VI-NEXT: %[[R_32:[0-9]+]] = call i32 @llvm.bitreverse.i32(i32 %[[A_32]]) |
| 1034 | ; VI-NEXT: %[[S_32:[0-9]+]] = lshr i32 %[[R_32]], 16 |
| 1035 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc i32 %[[S_32]] to i16 |
| 1036 | ; VI-NEXT: ret i16 %[[R_16]] |
| 1037 | define i16 @bitreverse_i16(i16 %a) { |
| 1038 | %brev = call i16 @llvm.bitreverse.i16(i16 %a) |
| 1039 | ret i16 %brev |
| 1040 | } |
| 1041 | |
Konstantin Zhuravlyov | f74fc60 | 2016-10-07 14:22:58 +0000 | [diff] [blame] | 1042 | ; GCN-LABEL: @add_3xi15( |
| 1043 | ; SI: %r = add <3 x i15> %a, %b |
| 1044 | ; SI-NEXT: ret <3 x i15> %r |
| 1045 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1046 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1047 | ; VI-NEXT: %[[R_32:[0-9]+]] = add <3 x i32> %[[A_32]], %[[B_32]] |
| 1048 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1049 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1050 | define <3 x i15> @add_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1051 | %r = add <3 x i15> %a, %b |
| 1052 | ret <3 x i15> %r |
| 1053 | } |
| 1054 | |
| 1055 | ; GCN-LABEL: @add_nsw_3xi15( |
| 1056 | ; SI: %r = add nsw <3 x i15> %a, %b |
| 1057 | ; SI-NEXT: ret <3 x i15> %r |
| 1058 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1059 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1060 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1061 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1062 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1063 | define <3 x i15> @add_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1064 | %r = add nsw <3 x i15> %a, %b |
| 1065 | ret <3 x i15> %r |
| 1066 | } |
| 1067 | |
| 1068 | ; GCN-LABEL: @add_nuw_3xi15( |
| 1069 | ; SI: %r = add nuw <3 x i15> %a, %b |
| 1070 | ; SI-NEXT: ret <3 x i15> %r |
| 1071 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1072 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1073 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1074 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1075 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1076 | define <3 x i15> @add_nuw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1077 | %r = add nuw <3 x i15> %a, %b |
| 1078 | ret <3 x i15> %r |
| 1079 | } |
| 1080 | |
| 1081 | ; GCN-LABEL: @add_nuw_nsw_3xi15( |
| 1082 | ; SI: %r = add nuw nsw <3 x i15> %a, %b |
| 1083 | ; SI-NEXT: ret <3 x i15> %r |
| 1084 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1085 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1086 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1087 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1088 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1089 | define <3 x i15> @add_nuw_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1090 | %r = add nuw nsw <3 x i15> %a, %b |
| 1091 | ret <3 x i15> %r |
| 1092 | } |
| 1093 | |
| 1094 | ; GCN-LABEL: @sub_3xi15( |
| 1095 | ; SI: %r = sub <3 x i15> %a, %b |
| 1096 | ; SI-NEXT: ret <3 x i15> %r |
| 1097 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1098 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1099 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub <3 x i32> %[[A_32]], %[[B_32]] |
| 1100 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1101 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1102 | define <3 x i15> @sub_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1103 | %r = sub <3 x i15> %a, %b |
| 1104 | ret <3 x i15> %r |
| 1105 | } |
| 1106 | |
| 1107 | ; GCN-LABEL: @sub_nsw_3xi15( |
| 1108 | ; SI: %r = sub nsw <3 x i15> %a, %b |
| 1109 | ; SI-NEXT: ret <3 x i15> %r |
| 1110 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1111 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1112 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1113 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1114 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1115 | define <3 x i15> @sub_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1116 | %r = sub nsw <3 x i15> %a, %b |
| 1117 | ret <3 x i15> %r |
| 1118 | } |
| 1119 | |
| 1120 | ; GCN-LABEL: @sub_nuw_3xi15( |
| 1121 | ; SI: %r = sub nuw <3 x i15> %a, %b |
| 1122 | ; SI-NEXT: ret <3 x i15> %r |
| 1123 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1124 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1125 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1126 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1127 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1128 | define <3 x i15> @sub_nuw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1129 | %r = sub nuw <3 x i15> %a, %b |
| 1130 | ret <3 x i15> %r |
| 1131 | } |
| 1132 | |
| 1133 | ; GCN-LABEL: @sub_nuw_nsw_3xi15( |
| 1134 | ; SI: %r = sub nuw nsw <3 x i15> %a, %b |
| 1135 | ; SI-NEXT: ret <3 x i15> %r |
| 1136 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1137 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1138 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1139 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1140 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1141 | define <3 x i15> @sub_nuw_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1142 | %r = sub nuw nsw <3 x i15> %a, %b |
| 1143 | ret <3 x i15> %r |
| 1144 | } |
| 1145 | |
| 1146 | ; GCN-LABEL: @mul_3xi15( |
| 1147 | ; SI: %r = mul <3 x i15> %a, %b |
| 1148 | ; SI-NEXT: ret <3 x i15> %r |
| 1149 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1150 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1151 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul <3 x i32> %[[A_32]], %[[B_32]] |
| 1152 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1153 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1154 | define <3 x i15> @mul_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1155 | %r = mul <3 x i15> %a, %b |
| 1156 | ret <3 x i15> %r |
| 1157 | } |
| 1158 | |
| 1159 | ; GCN-LABEL: @mul_nsw_3xi15( |
| 1160 | ; SI: %r = mul nsw <3 x i15> %a, %b |
| 1161 | ; SI-NEXT: ret <3 x i15> %r |
| 1162 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1163 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1164 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1165 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1166 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1167 | define <3 x i15> @mul_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1168 | %r = mul nsw <3 x i15> %a, %b |
| 1169 | ret <3 x i15> %r |
| 1170 | } |
| 1171 | |
| 1172 | ; GCN-LABEL: @mul_nuw_3xi15( |
| 1173 | ; SI: %r = mul nuw <3 x i15> %a, %b |
| 1174 | ; SI-NEXT: ret <3 x i15> %r |
| 1175 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1176 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1177 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1178 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1179 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1180 | define <3 x i15> @mul_nuw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1181 | %r = mul nuw <3 x i15> %a, %b |
| 1182 | ret <3 x i15> %r |
| 1183 | } |
| 1184 | |
| 1185 | ; GCN-LABEL: @mul_nuw_nsw_3xi15( |
| 1186 | ; SI: %r = mul nuw nsw <3 x i15> %a, %b |
| 1187 | ; SI-NEXT: ret <3 x i15> %r |
| 1188 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1189 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1190 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1191 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1192 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1193 | define <3 x i15> @mul_nuw_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1194 | %r = mul nuw nsw <3 x i15> %a, %b |
| 1195 | ret <3 x i15> %r |
| 1196 | } |
| 1197 | |
| 1198 | ; GCN-LABEL: @urem_3xi15( |
| 1199 | ; SI: %r = urem <3 x i15> %a, %b |
| 1200 | ; SI-NEXT: ret <3 x i15> %r |
| 1201 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1202 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1203 | ; VI-NEXT: %[[R_32:[0-9]+]] = urem <3 x i32> %[[A_32]], %[[B_32]] |
| 1204 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1205 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1206 | define <3 x i15> @urem_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1207 | %r = urem <3 x i15> %a, %b |
| 1208 | ret <3 x i15> %r |
| 1209 | } |
| 1210 | |
| 1211 | ; GCN-LABEL: @srem_3xi15( |
| 1212 | ; SI: %r = srem <3 x i15> %a, %b |
| 1213 | ; SI-NEXT: ret <3 x i15> %r |
| 1214 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1215 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1216 | ; VI-NEXT: %[[R_32:[0-9]+]] = srem <3 x i32> %[[A_32]], %[[B_32]] |
| 1217 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1218 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1219 | define <3 x i15> @srem_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1220 | %r = srem <3 x i15> %a, %b |
| 1221 | ret <3 x i15> %r |
| 1222 | } |
| 1223 | |
| 1224 | ; GCN-LABEL: @shl_3xi15( |
| 1225 | ; SI: %r = shl <3 x i15> %a, %b |
| 1226 | ; SI-NEXT: ret <3 x i15> %r |
| 1227 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1228 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1229 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl <3 x i32> %[[A_32]], %[[B_32]] |
| 1230 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1231 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1232 | define <3 x i15> @shl_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1233 | %r = shl <3 x i15> %a, %b |
| 1234 | ret <3 x i15> %r |
| 1235 | } |
| 1236 | |
| 1237 | ; GCN-LABEL: @shl_nsw_3xi15( |
| 1238 | ; SI: %r = shl nsw <3 x i15> %a, %b |
| 1239 | ; SI-NEXT: ret <3 x i15> %r |
| 1240 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1241 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1242 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1243 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1244 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1245 | define <3 x i15> @shl_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1246 | %r = shl nsw <3 x i15> %a, %b |
| 1247 | ret <3 x i15> %r |
| 1248 | } |
| 1249 | |
| 1250 | ; GCN-LABEL: @shl_nuw_3xi15( |
| 1251 | ; SI: %r = shl nuw <3 x i15> %a, %b |
| 1252 | ; SI-NEXT: ret <3 x i15> %r |
| 1253 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1254 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1255 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1256 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1257 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1258 | define <3 x i15> @shl_nuw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1259 | %r = shl nuw <3 x i15> %a, %b |
| 1260 | ret <3 x i15> %r |
| 1261 | } |
| 1262 | |
| 1263 | ; GCN-LABEL: @shl_nuw_nsw_3xi15( |
| 1264 | ; SI: %r = shl nuw nsw <3 x i15> %a, %b |
| 1265 | ; SI-NEXT: ret <3 x i15> %r |
| 1266 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1267 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1268 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1269 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1270 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1271 | define <3 x i15> @shl_nuw_nsw_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1272 | %r = shl nuw nsw <3 x i15> %a, %b |
| 1273 | ret <3 x i15> %r |
| 1274 | } |
| 1275 | |
| 1276 | ; GCN-LABEL: @lshr_3xi15( |
| 1277 | ; SI: %r = lshr <3 x i15> %a, %b |
| 1278 | ; SI-NEXT: ret <3 x i15> %r |
| 1279 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1280 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1281 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr <3 x i32> %[[A_32]], %[[B_32]] |
| 1282 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1283 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1284 | define <3 x i15> @lshr_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1285 | %r = lshr <3 x i15> %a, %b |
| 1286 | ret <3 x i15> %r |
| 1287 | } |
| 1288 | |
| 1289 | ; GCN-LABEL: @lshr_exact_3xi15( |
| 1290 | ; SI: %r = lshr exact <3 x i15> %a, %b |
| 1291 | ; SI-NEXT: ret <3 x i15> %r |
| 1292 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1293 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1294 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr exact <3 x i32> %[[A_32]], %[[B_32]] |
| 1295 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1296 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1297 | define <3 x i15> @lshr_exact_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1298 | %r = lshr exact <3 x i15> %a, %b |
| 1299 | ret <3 x i15> %r |
| 1300 | } |
| 1301 | |
| 1302 | ; GCN-LABEL: @ashr_3xi15( |
| 1303 | ; SI: %r = ashr <3 x i15> %a, %b |
| 1304 | ; SI-NEXT: ret <3 x i15> %r |
| 1305 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1306 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1307 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]] |
| 1308 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1309 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1310 | define <3 x i15> @ashr_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1311 | %r = ashr <3 x i15> %a, %b |
| 1312 | ret <3 x i15> %r |
| 1313 | } |
| 1314 | |
| 1315 | ; GCN-LABEL: @ashr_exact_3xi15( |
| 1316 | ; SI: %r = ashr exact <3 x i15> %a, %b |
| 1317 | ; SI-NEXT: ret <3 x i15> %r |
| 1318 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1319 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1320 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]] |
| 1321 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1322 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1323 | define <3 x i15> @ashr_exact_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1324 | %r = ashr exact <3 x i15> %a, %b |
| 1325 | ret <3 x i15> %r |
| 1326 | } |
| 1327 | |
| 1328 | ; GCN-LABEL: @and_3xi15( |
| 1329 | ; SI: %r = and <3 x i15> %a, %b |
| 1330 | ; SI-NEXT: ret <3 x i15> %r |
| 1331 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1332 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1333 | ; VI-NEXT: %[[R_32:[0-9]+]] = and <3 x i32> %[[A_32]], %[[B_32]] |
| 1334 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1335 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1336 | define <3 x i15> @and_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1337 | %r = and <3 x i15> %a, %b |
| 1338 | ret <3 x i15> %r |
| 1339 | } |
| 1340 | |
| 1341 | ; GCN-LABEL: @or_3xi15( |
| 1342 | ; SI: %r = or <3 x i15> %a, %b |
| 1343 | ; SI-NEXT: ret <3 x i15> %r |
| 1344 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1345 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1346 | ; VI-NEXT: %[[R_32:[0-9]+]] = or <3 x i32> %[[A_32]], %[[B_32]] |
| 1347 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1348 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1349 | define <3 x i15> @or_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1350 | %r = or <3 x i15> %a, %b |
| 1351 | ret <3 x i15> %r |
| 1352 | } |
| 1353 | |
| 1354 | ; GCN-LABEL: @xor_3xi15( |
| 1355 | ; SI: %r = xor <3 x i15> %a, %b |
| 1356 | ; SI-NEXT: ret <3 x i15> %r |
| 1357 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1358 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1359 | ; VI-NEXT: %[[R_32:[0-9]+]] = xor <3 x i32> %[[A_32]], %[[B_32]] |
| 1360 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i15> |
| 1361 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1362 | define <3 x i15> @xor_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1363 | %r = xor <3 x i15> %a, %b |
| 1364 | ret <3 x i15> %r |
| 1365 | } |
| 1366 | |
| 1367 | ; GCN-LABEL: @select_eq_3xi15( |
| 1368 | ; SI: %cmp = icmp eq <3 x i15> %a, %b |
| 1369 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1370 | ; SI-NEXT: ret <3 x i15> %sel |
| 1371 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1372 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1373 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp eq <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1374 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1375 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1376 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1377 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1378 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1379 | define <3 x i15> @select_eq_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1380 | %cmp = icmp eq <3 x i15> %a, %b |
| 1381 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1382 | ret <3 x i15> %sel |
| 1383 | } |
| 1384 | |
| 1385 | ; GCN-LABEL: @select_ne_3xi15( |
| 1386 | ; SI: %cmp = icmp ne <3 x i15> %a, %b |
| 1387 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1388 | ; SI-NEXT: ret <3 x i15> %sel |
| 1389 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1390 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1391 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ne <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1392 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1393 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1394 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1395 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1396 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1397 | define <3 x i15> @select_ne_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1398 | %cmp = icmp ne <3 x i15> %a, %b |
| 1399 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1400 | ret <3 x i15> %sel |
| 1401 | } |
| 1402 | |
| 1403 | ; GCN-LABEL: @select_ugt_3xi15( |
| 1404 | ; SI: %cmp = icmp ugt <3 x i15> %a, %b |
| 1405 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1406 | ; SI-NEXT: ret <3 x i15> %sel |
| 1407 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1408 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1409 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ugt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1410 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1411 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1412 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1413 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1414 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1415 | define <3 x i15> @select_ugt_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1416 | %cmp = icmp ugt <3 x i15> %a, %b |
| 1417 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1418 | ret <3 x i15> %sel |
| 1419 | } |
| 1420 | |
| 1421 | ; GCN-LABEL: @select_uge_3xi15( |
| 1422 | ; SI: %cmp = icmp uge <3 x i15> %a, %b |
| 1423 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1424 | ; SI-NEXT: ret <3 x i15> %sel |
| 1425 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1426 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1427 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp uge <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1428 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1429 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1430 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1431 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1432 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1433 | define <3 x i15> @select_uge_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1434 | %cmp = icmp uge <3 x i15> %a, %b |
| 1435 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1436 | ret <3 x i15> %sel |
| 1437 | } |
| 1438 | |
| 1439 | ; GCN-LABEL: @select_ult_3xi15( |
| 1440 | ; SI: %cmp = icmp ult <3 x i15> %a, %b |
| 1441 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1442 | ; SI-NEXT: ret <3 x i15> %sel |
| 1443 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1444 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1445 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ult <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1446 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1447 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1448 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1449 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1450 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1451 | define <3 x i15> @select_ult_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1452 | %cmp = icmp ult <3 x i15> %a, %b |
| 1453 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1454 | ret <3 x i15> %sel |
| 1455 | } |
| 1456 | |
| 1457 | ; GCN-LABEL: @select_ule_3xi15( |
| 1458 | ; SI: %cmp = icmp ule <3 x i15> %a, %b |
| 1459 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1460 | ; SI-NEXT: ret <3 x i15> %sel |
| 1461 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1462 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1463 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ule <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1464 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1465 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i15> %b to <3 x i32> |
| 1466 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1467 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1468 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1469 | define <3 x i15> @select_ule_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1470 | %cmp = icmp ule <3 x i15> %a, %b |
| 1471 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1472 | ret <3 x i15> %sel |
| 1473 | } |
| 1474 | |
| 1475 | ; GCN-LABEL: @select_sgt_3xi15( |
| 1476 | ; SI: %cmp = icmp sgt <3 x i15> %a, %b |
| 1477 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1478 | ; SI-NEXT: ret <3 x i15> %sel |
| 1479 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1480 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1481 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sgt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1482 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1483 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1484 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1485 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1486 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1487 | define <3 x i15> @select_sgt_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1488 | %cmp = icmp sgt <3 x i15> %a, %b |
| 1489 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1490 | ret <3 x i15> %sel |
| 1491 | } |
| 1492 | |
| 1493 | ; GCN-LABEL: @select_sge_3xi15( |
| 1494 | ; SI: %cmp = icmp sge <3 x i15> %a, %b |
| 1495 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1496 | ; SI-NEXT: ret <3 x i15> %sel |
| 1497 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1498 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1499 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sge <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1500 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1501 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1502 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1503 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1504 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1505 | define <3 x i15> @select_sge_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1506 | %cmp = icmp sge <3 x i15> %a, %b |
| 1507 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1508 | ret <3 x i15> %sel |
| 1509 | } |
| 1510 | |
| 1511 | ; GCN-LABEL: @select_slt_3xi15( |
| 1512 | ; SI: %cmp = icmp slt <3 x i15> %a, %b |
| 1513 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1514 | ; SI-NEXT: ret <3 x i15> %sel |
| 1515 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1516 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1517 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp slt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1518 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1519 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1520 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1521 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1522 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1523 | define <3 x i15> @select_slt_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1524 | %cmp = icmp slt <3 x i15> %a, %b |
| 1525 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1526 | ret <3 x i15> %sel |
| 1527 | } |
| 1528 | |
| 1529 | ; GCN-LABEL: @select_sle_3xi15( |
| 1530 | ; SI: %cmp = icmp sle <3 x i15> %a, %b |
| 1531 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1532 | ; SI-NEXT: ret <3 x i15> %sel |
| 1533 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1534 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1535 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sle <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1536 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i15> %a to <3 x i32> |
| 1537 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i15> %b to <3 x i32> |
| 1538 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1539 | ; VI-NEXT: %[[SEL_15:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i15> |
| 1540 | ; VI-NEXT: ret <3 x i15> %[[SEL_15]] |
| 1541 | define <3 x i15> @select_sle_3xi15(<3 x i15> %a, <3 x i15> %b) { |
| 1542 | %cmp = icmp sle <3 x i15> %a, %b |
| 1543 | %sel = select <3 x i1> %cmp, <3 x i15> %a, <3 x i15> %b |
| 1544 | ret <3 x i15> %sel |
| 1545 | } |
| 1546 | |
| 1547 | declare <3 x i15> @llvm.bitreverse.v3i15(<3 x i15>) |
| 1548 | ; GCN-LABEL: @bitreverse_3xi15( |
| 1549 | ; SI: %brev = call <3 x i15> @llvm.bitreverse.v3i15(<3 x i15> %a) |
| 1550 | ; SI-NEXT: ret <3 x i15> %brev |
| 1551 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i15> %a to <3 x i32> |
| 1552 | ; VI-NEXT: %[[R_32:[0-9]+]] = call <3 x i32> @llvm.bitreverse.v3i32(<3 x i32> %[[A_32]]) |
| 1553 | ; VI-NEXT: %[[S_32:[0-9]+]] = lshr <3 x i32> %[[R_32]], <i32 17, i32 17, i32 17> |
| 1554 | ; VI-NEXT: %[[R_15:[0-9]+]] = trunc <3 x i32> %[[S_32]] to <3 x i15> |
| 1555 | ; VI-NEXT: ret <3 x i15> %[[R_15]] |
| 1556 | define <3 x i15> @bitreverse_3xi15(<3 x i15> %a) { |
| 1557 | %brev = call <3 x i15> @llvm.bitreverse.v3i15(<3 x i15> %a) |
| 1558 | ret <3 x i15> %brev |
| 1559 | } |
| 1560 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1561 | ; GCN-LABEL: @add_3xi16( |
| 1562 | ; SI: %r = add <3 x i16> %a, %b |
| 1563 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1564 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1565 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1566 | ; VI-NEXT: %[[R_32:[0-9]+]] = add <3 x i32> %[[A_32]], %[[B_32]] |
| 1567 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1568 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1569 | define <3 x i16> @add_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1570 | %r = add <3 x i16> %a, %b |
| 1571 | ret <3 x i16> %r |
| 1572 | } |
| 1573 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1574 | ; GCN-LABEL: @add_nsw_3xi16( |
| 1575 | ; SI: %r = add nsw <3 x i16> %a, %b |
| 1576 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1577 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1578 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1579 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1580 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1581 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1582 | define <3 x i16> @add_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1583 | %r = add nsw <3 x i16> %a, %b |
| 1584 | ret <3 x i16> %r |
| 1585 | } |
| 1586 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1587 | ; GCN-LABEL: @add_nuw_3xi16( |
| 1588 | ; SI: %r = add nuw <3 x i16> %a, %b |
| 1589 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1590 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1591 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1592 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1593 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1594 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1595 | define <3 x i16> @add_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1596 | %r = add nuw <3 x i16> %a, %b |
| 1597 | ret <3 x i16> %r |
| 1598 | } |
| 1599 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1600 | ; GCN-LABEL: @add_nuw_nsw_3xi16( |
| 1601 | ; SI: %r = add nuw nsw <3 x i16> %a, %b |
| 1602 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1603 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1604 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1605 | ; VI-NEXT: %[[R_32:[0-9]+]] = add nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1606 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1607 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1608 | define <3 x i16> @add_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1609 | %r = add nuw nsw <3 x i16> %a, %b |
| 1610 | ret <3 x i16> %r |
| 1611 | } |
| 1612 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1613 | ; GCN-LABEL: @sub_3xi16( |
| 1614 | ; SI: %r = sub <3 x i16> %a, %b |
| 1615 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1616 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1617 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1618 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub <3 x i32> %[[A_32]], %[[B_32]] |
| 1619 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1620 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1621 | define <3 x i16> @sub_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1622 | %r = sub <3 x i16> %a, %b |
| 1623 | ret <3 x i16> %r |
| 1624 | } |
| 1625 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1626 | ; GCN-LABEL: @sub_nsw_3xi16( |
| 1627 | ; SI: %r = sub nsw <3 x i16> %a, %b |
| 1628 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1629 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1630 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1631 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1632 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1633 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1634 | define <3 x i16> @sub_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1635 | %r = sub nsw <3 x i16> %a, %b |
| 1636 | ret <3 x i16> %r |
| 1637 | } |
| 1638 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1639 | ; GCN-LABEL: @sub_nuw_3xi16( |
| 1640 | ; SI: %r = sub nuw <3 x i16> %a, %b |
| 1641 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1642 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1643 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1644 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1645 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1646 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1647 | define <3 x i16> @sub_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1648 | %r = sub nuw <3 x i16> %a, %b |
| 1649 | ret <3 x i16> %r |
| 1650 | } |
| 1651 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1652 | ; GCN-LABEL: @sub_nuw_nsw_3xi16( |
| 1653 | ; SI: %r = sub nuw nsw <3 x i16> %a, %b |
| 1654 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1655 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1656 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1657 | ; VI-NEXT: %[[R_32:[0-9]+]] = sub nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1658 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1659 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1660 | define <3 x i16> @sub_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1661 | %r = sub nuw nsw <3 x i16> %a, %b |
| 1662 | ret <3 x i16> %r |
| 1663 | } |
| 1664 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1665 | ; GCN-LABEL: @mul_3xi16( |
| 1666 | ; SI: %r = mul <3 x i16> %a, %b |
| 1667 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1668 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1669 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1670 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul <3 x i32> %[[A_32]], %[[B_32]] |
| 1671 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1672 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1673 | define <3 x i16> @mul_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1674 | %r = mul <3 x i16> %a, %b |
| 1675 | ret <3 x i16> %r |
| 1676 | } |
| 1677 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1678 | ; GCN-LABEL: @mul_nsw_3xi16( |
| 1679 | ; SI: %r = mul nsw <3 x i16> %a, %b |
| 1680 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1681 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1682 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1683 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1684 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1685 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1686 | define <3 x i16> @mul_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1687 | %r = mul nsw <3 x i16> %a, %b |
| 1688 | ret <3 x i16> %r |
| 1689 | } |
| 1690 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1691 | ; GCN-LABEL: @mul_nuw_3xi16( |
| 1692 | ; SI: %r = mul nuw <3 x i16> %a, %b |
| 1693 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1694 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1695 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1696 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1697 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1698 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1699 | define <3 x i16> @mul_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1700 | %r = mul nuw <3 x i16> %a, %b |
| 1701 | ret <3 x i16> %r |
| 1702 | } |
| 1703 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1704 | ; GCN-LABEL: @mul_nuw_nsw_3xi16( |
| 1705 | ; SI: %r = mul nuw nsw <3 x i16> %a, %b |
| 1706 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1707 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1708 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1709 | ; VI-NEXT: %[[R_32:[0-9]+]] = mul nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1710 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1711 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1712 | define <3 x i16> @mul_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1713 | %r = mul nuw nsw <3 x i16> %a, %b |
| 1714 | ret <3 x i16> %r |
| 1715 | } |
| 1716 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1717 | ; GCN-LABEL: @urem_3xi16( |
| 1718 | ; SI: %r = urem <3 x i16> %a, %b |
| 1719 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1720 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1721 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1722 | ; VI-NEXT: %[[R_32:[0-9]+]] = urem <3 x i32> %[[A_32]], %[[B_32]] |
| 1723 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1724 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1725 | define <3 x i16> @urem_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1726 | %r = urem <3 x i16> %a, %b |
| 1727 | ret <3 x i16> %r |
| 1728 | } |
| 1729 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1730 | ; GCN-LABEL: @srem_3xi16( |
| 1731 | ; SI: %r = srem <3 x i16> %a, %b |
| 1732 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1733 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1734 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 1735 | ; VI-NEXT: %[[R_32:[0-9]+]] = srem <3 x i32> %[[A_32]], %[[B_32]] |
| 1736 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1737 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1738 | define <3 x i16> @srem_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1739 | %r = srem <3 x i16> %a, %b |
| 1740 | ret <3 x i16> %r |
| 1741 | } |
| 1742 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1743 | ; GCN-LABEL: @shl_3xi16( |
| 1744 | ; SI: %r = shl <3 x i16> %a, %b |
| 1745 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1746 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1747 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1748 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl <3 x i32> %[[A_32]], %[[B_32]] |
| 1749 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1750 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1751 | define <3 x i16> @shl_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1752 | %r = shl <3 x i16> %a, %b |
| 1753 | ret <3 x i16> %r |
| 1754 | } |
| 1755 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1756 | ; GCN-LABEL: @shl_nsw_3xi16( |
| 1757 | ; SI: %r = shl nsw <3 x i16> %a, %b |
| 1758 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1759 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1760 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1761 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1762 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1763 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1764 | define <3 x i16> @shl_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1765 | %r = shl nsw <3 x i16> %a, %b |
| 1766 | ret <3 x i16> %r |
| 1767 | } |
| 1768 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1769 | ; GCN-LABEL: @shl_nuw_3xi16( |
| 1770 | ; SI: %r = shl nuw <3 x i16> %a, %b |
| 1771 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1772 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1773 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1774 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw <3 x i32> %[[A_32]], %[[B_32]] |
| 1775 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1776 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1777 | define <3 x i16> @shl_nuw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1778 | %r = shl nuw <3 x i16> %a, %b |
| 1779 | ret <3 x i16> %r |
| 1780 | } |
| 1781 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1782 | ; GCN-LABEL: @shl_nuw_nsw_3xi16( |
| 1783 | ; SI: %r = shl nuw nsw <3 x i16> %a, %b |
| 1784 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1785 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1786 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1787 | ; VI-NEXT: %[[R_32:[0-9]+]] = shl nuw nsw <3 x i32> %[[A_32]], %[[B_32]] |
| 1788 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1789 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1790 | define <3 x i16> @shl_nuw_nsw_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1791 | %r = shl nuw nsw <3 x i16> %a, %b |
| 1792 | ret <3 x i16> %r |
| 1793 | } |
| 1794 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1795 | ; GCN-LABEL: @lshr_3xi16( |
| 1796 | ; SI: %r = lshr <3 x i16> %a, %b |
| 1797 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1798 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1799 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1800 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr <3 x i32> %[[A_32]], %[[B_32]] |
| 1801 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1802 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1803 | define <3 x i16> @lshr_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1804 | %r = lshr <3 x i16> %a, %b |
| 1805 | ret <3 x i16> %r |
| 1806 | } |
| 1807 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1808 | ; GCN-LABEL: @lshr_exact_3xi16( |
| 1809 | ; SI: %r = lshr exact <3 x i16> %a, %b |
| 1810 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1811 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1812 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1813 | ; VI-NEXT: %[[R_32:[0-9]+]] = lshr exact <3 x i32> %[[A_32]], %[[B_32]] |
| 1814 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1815 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1816 | define <3 x i16> @lshr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1817 | %r = lshr exact <3 x i16> %a, %b |
| 1818 | ret <3 x i16> %r |
| 1819 | } |
| 1820 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1821 | ; GCN-LABEL: @ashr_3xi16( |
| 1822 | ; SI: %r = ashr <3 x i16> %a, %b |
| 1823 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | 691e2e0 | 2016-10-03 18:29:01 +0000 | [diff] [blame] | 1824 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1825 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 1826 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr <3 x i32> %[[A_32]], %[[B_32]] |
| 1827 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1828 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1829 | define <3 x i16> @ashr_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1830 | %r = ashr <3 x i16> %a, %b |
| 1831 | ret <3 x i16> %r |
| 1832 | } |
| 1833 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1834 | ; GCN-LABEL: @ashr_exact_3xi16( |
| 1835 | ; SI: %r = ashr exact <3 x i16> %a, %b |
| 1836 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | 691e2e0 | 2016-10-03 18:29:01 +0000 | [diff] [blame] | 1837 | ; VI: %[[A_32:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1838 | ; VI-NEXT: %[[B_32:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 1839 | ; VI-NEXT: %[[R_32:[0-9]+]] = ashr exact <3 x i32> %[[A_32]], %[[B_32]] |
| 1840 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1841 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1842 | define <3 x i16> @ashr_exact_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1843 | %r = ashr exact <3 x i16> %a, %b |
| 1844 | ret <3 x i16> %r |
| 1845 | } |
| 1846 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1847 | ; GCN-LABEL: @and_3xi16( |
| 1848 | ; SI: %r = and <3 x i16> %a, %b |
| 1849 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1850 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1851 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1852 | ; VI-NEXT: %[[R_32:[0-9]+]] = and <3 x i32> %[[A_32]], %[[B_32]] |
| 1853 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1854 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1855 | define <3 x i16> @and_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1856 | %r = and <3 x i16> %a, %b |
| 1857 | ret <3 x i16> %r |
| 1858 | } |
| 1859 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1860 | ; GCN-LABEL: @or_3xi16( |
| 1861 | ; SI: %r = or <3 x i16> %a, %b |
| 1862 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1863 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1864 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1865 | ; VI-NEXT: %[[R_32:[0-9]+]] = or <3 x i32> %[[A_32]], %[[B_32]] |
| 1866 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1867 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1868 | define <3 x i16> @or_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1869 | %r = or <3 x i16> %a, %b |
| 1870 | ret <3 x i16> %r |
| 1871 | } |
| 1872 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1873 | ; GCN-LABEL: @xor_3xi16( |
| 1874 | ; SI: %r = xor <3 x i16> %a, %b |
| 1875 | ; SI-NEXT: ret <3 x i16> %r |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1876 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1877 | ; VI-NEXT: %[[B_32:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1878 | ; VI-NEXT: %[[R_32:[0-9]+]] = xor <3 x i32> %[[A_32]], %[[B_32]] |
| 1879 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[R_32]] to <3 x i16> |
| 1880 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1881 | define <3 x i16> @xor_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1882 | %r = xor <3 x i16> %a, %b |
| 1883 | ret <3 x i16> %r |
| 1884 | } |
| 1885 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1886 | ; GCN-LABEL: @select_eq_3xi16( |
| 1887 | ; SI: %cmp = icmp eq <3 x i16> %a, %b |
| 1888 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1889 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1890 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1891 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1892 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp eq <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1893 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1894 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1895 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1896 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1897 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1898 | define <3 x i16> @select_eq_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1899 | %cmp = icmp eq <3 x i16> %a, %b |
| 1900 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1901 | ret <3 x i16> %sel |
| 1902 | } |
| 1903 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1904 | ; GCN-LABEL: @select_ne_3xi16( |
| 1905 | ; SI: %cmp = icmp ne <3 x i16> %a, %b |
| 1906 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1907 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1908 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1909 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1910 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ne <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1911 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1912 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1913 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1914 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1915 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1916 | define <3 x i16> @select_ne_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1917 | %cmp = icmp ne <3 x i16> %a, %b |
| 1918 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1919 | ret <3 x i16> %sel |
| 1920 | } |
| 1921 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1922 | ; GCN-LABEL: @select_ugt_3xi16( |
| 1923 | ; SI: %cmp = icmp ugt <3 x i16> %a, %b |
| 1924 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1925 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1926 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1927 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1928 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ugt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1929 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1930 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1931 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1932 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1933 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1934 | define <3 x i16> @select_ugt_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1935 | %cmp = icmp ugt <3 x i16> %a, %b |
| 1936 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1937 | ret <3 x i16> %sel |
| 1938 | } |
| 1939 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1940 | ; GCN-LABEL: @select_uge_3xi16( |
| 1941 | ; SI: %cmp = icmp uge <3 x i16> %a, %b |
| 1942 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1943 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1944 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1945 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1946 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp uge <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1947 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1948 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1949 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1950 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1951 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1952 | define <3 x i16> @select_uge_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1953 | %cmp = icmp uge <3 x i16> %a, %b |
| 1954 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1955 | ret <3 x i16> %sel |
| 1956 | } |
| 1957 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1958 | ; GCN-LABEL: @select_ult_3xi16( |
| 1959 | ; SI: %cmp = icmp ult <3 x i16> %a, %b |
| 1960 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1961 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1962 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1963 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1964 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ult <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1965 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1966 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1967 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1968 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1969 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1970 | define <3 x i16> @select_ult_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1971 | %cmp = icmp ult <3 x i16> %a, %b |
| 1972 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1973 | ret <3 x i16> %sel |
| 1974 | } |
| 1975 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1976 | ; GCN-LABEL: @select_ule_3xi16( |
| 1977 | ; SI: %cmp = icmp ule <3 x i16> %a, %b |
| 1978 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1979 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1980 | ; VI: %[[A_32_0:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1981 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1982 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp ule <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 1983 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 1984 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = zext <3 x i16> %b to <3 x i32> |
| 1985 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 1986 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 1987 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1988 | define <3 x i16> @select_ule_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 1989 | %cmp = icmp ule <3 x i16> %a, %b |
| 1990 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1991 | ret <3 x i16> %sel |
| 1992 | } |
| 1993 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1994 | ; GCN-LABEL: @select_sgt_3xi16( |
| 1995 | ; SI: %cmp = icmp sgt <3 x i16> %a, %b |
| 1996 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 1997 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 1998 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 1999 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2000 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sgt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 2001 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
| 2002 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2003 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 2004 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 2005 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2006 | define <3 x i16> @select_sgt_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 2007 | %cmp = icmp sgt <3 x i16> %a, %b |
| 2008 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2009 | ret <3 x i16> %sel |
| 2010 | } |
| 2011 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2012 | ; GCN-LABEL: @select_sge_3xi16( |
| 2013 | ; SI: %cmp = icmp sge <3 x i16> %a, %b |
| 2014 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2015 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2016 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2017 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2018 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sge <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 2019 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
| 2020 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2021 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 2022 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 2023 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2024 | define <3 x i16> @select_sge_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 2025 | %cmp = icmp sge <3 x i16> %a, %b |
| 2026 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2027 | ret <3 x i16> %sel |
| 2028 | } |
| 2029 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2030 | ; GCN-LABEL: @select_slt_3xi16( |
| 2031 | ; SI: %cmp = icmp slt <3 x i16> %a, %b |
| 2032 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2033 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2034 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2035 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2036 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp slt <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 2037 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
| 2038 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2039 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 2040 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 2041 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2042 | define <3 x i16> @select_slt_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 2043 | %cmp = icmp slt <3 x i16> %a, %b |
| 2044 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2045 | ret <3 x i16> %sel |
| 2046 | } |
| 2047 | |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2048 | ; GCN-LABEL: @select_sle_3xi16( |
| 2049 | ; SI: %cmp = icmp sle <3 x i16> %a, %b |
| 2050 | ; SI-NEXT: %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2051 | ; SI-NEXT: ret <3 x i16> %sel |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2052 | ; VI: %[[A_32_0:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2053 | ; VI-NEXT: %[[B_32_0:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2054 | ; VI-NEXT: %[[CMP:[0-9]+]] = icmp sle <3 x i32> %[[A_32_0]], %[[B_32_0]] |
| 2055 | ; VI-NEXT: %[[A_32_1:[0-9]+]] = sext <3 x i16> %a to <3 x i32> |
| 2056 | ; VI-NEXT: %[[B_32_1:[0-9]+]] = sext <3 x i16> %b to <3 x i32> |
| 2057 | ; VI-NEXT: %[[SEL_32:[0-9]+]] = select <3 x i1> %[[CMP]], <3 x i32> %[[A_32_1]], <3 x i32> %[[B_32_1]] |
| 2058 | ; VI-NEXT: %[[SEL_16:[0-9]+]] = trunc <3 x i32> %[[SEL_32]] to <3 x i16> |
| 2059 | ; VI-NEXT: ret <3 x i16> %[[SEL_16]] |
Konstantin Zhuravlyov | e14df4b | 2016-09-28 20:05:39 +0000 | [diff] [blame] | 2060 | define <3 x i16> @select_sle_3xi16(<3 x i16> %a, <3 x i16> %b) { |
| 2061 | %cmp = icmp sle <3 x i16> %a, %b |
| 2062 | %sel = select <3 x i1> %cmp, <3 x i16> %a, <3 x i16> %b |
| 2063 | ret <3 x i16> %sel |
| 2064 | } |
Konstantin Zhuravlyov | b4eb5d5 | 2016-10-06 02:20:46 +0000 | [diff] [blame] | 2065 | |
| 2066 | declare <3 x i16> @llvm.bitreverse.v3i16(<3 x i16>) |
| 2067 | ; GCN-LABEL: @bitreverse_3xi16( |
| 2068 | ; SI: %brev = call <3 x i16> @llvm.bitreverse.v3i16(<3 x i16> %a) |
| 2069 | ; SI-NEXT: ret <3 x i16> %brev |
| 2070 | ; VI: %[[A_32:[0-9]+]] = zext <3 x i16> %a to <3 x i32> |
| 2071 | ; VI-NEXT: %[[R_32:[0-9]+]] = call <3 x i32> @llvm.bitreverse.v3i32(<3 x i32> %[[A_32]]) |
| 2072 | ; VI-NEXT: %[[S_32:[0-9]+]] = lshr <3 x i32> %[[R_32]], <i32 16, i32 16, i32 16> |
| 2073 | ; VI-NEXT: %[[R_16:[0-9]+]] = trunc <3 x i32> %[[S_32]] to <3 x i16> |
| 2074 | ; VI-NEXT: ret <3 x i16> %[[R_16]] |
| 2075 | define <3 x i16> @bitreverse_3xi16(<3 x i16> %a) { |
| 2076 | %brev = call <3 x i16> @llvm.bitreverse.v3i16(<3 x i16> %a) |
| 2077 | ret <3 x i16> %brev |
| 2078 | } |