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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- R600InstrInfo.h - R600 Instruction Info Interface -------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Interface definition for R600InstrInfo
12//
13//===----------------------------------------------------------------------===//
14
15#ifndef R600INSTRUCTIONINFO_H_
16#define R600INSTRUCTIONINFO_H_
17
Tom Stellard75aadc22012-12-11 21:25:42 +000018#include "AMDGPUInstrInfo.h"
19#include "R600Defines.h"
20#include "R600RegisterInfo.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000021#include <map>
22
23namespace llvm {
24
25 class AMDGPUTargetMachine;
26 class DFAPacketizer;
27 class ScheduleDAG;
28 class MachineFunction;
29 class MachineInstr;
30 class MachineInstrBuilder;
31
32 class R600InstrInfo : public AMDGPUInstrInfo {
33 private:
34 const R600RegisterInfo RI;
Vincent Lejeunec2991642013-04-30 00:13:39 +000035 const AMDGPUSubtarget &ST;
Tom Stellard75aadc22012-12-11 21:25:42 +000036
37 int getBranchInstr(const MachineOperand &op) const;
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000038 std::vector<std::pair<int, unsigned> >
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000039 ExtractSrcs(MachineInstr *MI, const DenseMap<unsigned, unsigned> &PV, unsigned &ConstCount) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000040
41 public:
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000042 enum BankSwizzle {
Vincent Lejeunebb8a87212013-06-29 19:32:29 +000043 ALU_VEC_012_SCL_210 = 0,
44 ALU_VEC_021_SCL_122,
45 ALU_VEC_120_SCL_212,
46 ALU_VEC_102_SCL_221,
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000047 ALU_VEC_201,
48 ALU_VEC_210
49 };
50
Tom Stellard75aadc22012-12-11 21:25:42 +000051 explicit R600InstrInfo(AMDGPUTargetMachine &tm);
52
53 const R600RegisterInfo &getRegisterInfo() const;
54 virtual void copyPhysReg(MachineBasicBlock &MBB,
55 MachineBasicBlock::iterator MI, DebugLoc DL,
56 unsigned DestReg, unsigned SrcReg,
57 bool KillSrc) const;
58
59 bool isTrig(const MachineInstr &MI) const;
60 bool isPlaceHolderOpcode(unsigned opcode) const;
61 bool isReductionOp(unsigned opcode) const;
62 bool isCubeOp(unsigned opcode) const;
63
64 /// \returns true if this \p Opcode represents an ALU instruction.
65 bool isALUInstr(unsigned Opcode) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +000066 bool hasInstrModifiers(unsigned Opcode) const;
67 bool isLDSInstr(unsigned Opcode) const;
Tom Stellard75aadc22012-12-11 21:25:42 +000068
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000069 /// \returns true if this \p Opcode represents an ALU instruction or an
70 /// instruction that will be lowered in ExpandSpecialInstrs Pass.
71 bool canBeConsideredALU(const MachineInstr *MI) const;
72
Vincent Lejeune076c0b22013-04-30 00:14:17 +000073 bool isTransOnly(unsigned Opcode) const;
74 bool isTransOnly(const MachineInstr *MI) const;
Vincent Lejeune4d5c5e52013-09-04 19:53:30 +000075 bool isVectorOnly(unsigned Opcode) const;
76 bool isVectorOnly(const MachineInstr *MI) const;
Tom Stellard676c16d2013-08-16 01:11:51 +000077 bool isExport(unsigned Opcode) const;
Vincent Lejeune076c0b22013-04-30 00:14:17 +000078
Vincent Lejeunec2991642013-04-30 00:13:39 +000079 bool usesVertexCache(unsigned Opcode) const;
80 bool usesVertexCache(const MachineInstr *MI) const;
81 bool usesTextureCache(unsigned Opcode) const;
82 bool usesTextureCache(const MachineInstr *MI) const;
83
Tom Stellardce540332013-06-28 15:46:59 +000084 bool mustBeLastInClause(unsigned Opcode) const;
Tom Stellard26a3b672013-10-22 18:19:10 +000085 bool usesAddressRegister(MachineInstr *MI) const;
86 bool definesAddressRegister(MachineInstr *MI) const;
Tom Stellard7f6fa4c2013-09-12 02:55:06 +000087 bool readsLDSSrcReg(const MachineInstr *MI) const;
Tom Stellardce540332013-06-28 15:46:59 +000088
Tom Stellard84021442013-07-23 01:48:24 +000089 /// \returns The operand index for the given source number. Legal values
90 /// for SrcNum are 0, 1, and 2.
91 int getSrcIdx(unsigned Opcode, unsigned SrcNum) const;
92 /// \returns The operand Index for the Sel operand given an index to one
93 /// of the instruction's src operands.
94 int getSelIdx(unsigned Opcode, unsigned SrcIdx) const;
95
Vincent Lejeune0fca91d2013-05-17 16:50:02 +000096 /// \returns a pair for each src of an ALU instructions.
97 /// The first member of a pair is the register id.
98 /// If register is ALU_CONST, second member is SEL.
99 /// If register is ALU_LITERAL, second member is IMM.
100 /// Otherwise, second member value is undefined.
101 SmallVector<std::pair<MachineOperand *, int64_t>, 3>
102 getSrcs(MachineInstr *MI) const;
103
Vincent Lejeune77a83522013-06-29 19:32:43 +0000104 unsigned isLegalUpTo(
105 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
106 const std::vector<R600InstrInfo::BankSwizzle> &Swz,
107 const std::vector<std::pair<int, unsigned> > &TransSrcs,
108 R600InstrInfo::BankSwizzle TransSwz) const;
109
110 bool FindSwizzleForVectorSlot(
111 const std::vector<std::vector<std::pair<int, unsigned> > > &IGSrcs,
112 std::vector<R600InstrInfo::BankSwizzle> &SwzCandidate,
113 const std::vector<std::pair<int, unsigned> > &TransSrcs,
114 R600InstrInfo::BankSwizzle TransSwz) const;
Tom Stellardc026e8b2013-06-28 15:47:08 +0000115
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000116 /// Given the order VEC_012 < VEC_021 < VEC_120 < VEC_102 < VEC_201 < VEC_210
117 /// returns true and the first (in lexical order) BankSwizzle affectation
118 /// starting from the one already provided in the Instruction Group MIs that
119 /// fits Read Port limitations in BS if available. Otherwise returns false
120 /// and undefined content in BS.
Vincent Lejeune77a83522013-06-29 19:32:43 +0000121 /// isLastAluTrans should be set if the last Alu of MIs will be executed on
122 /// Trans ALU. In this case, ValidTSwizzle returns the BankSwizzle value to
123 /// apply to the last instruction.
Vincent Lejeune0fca91d2013-05-17 16:50:02 +0000124 /// PV holds GPR to PV registers in the Instruction Group MIs.
125 bool fitsReadPortLimitations(const std::vector<MachineInstr *> &MIs,
126 const DenseMap<unsigned, unsigned> &PV,
Vincent Lejeune77a83522013-06-29 19:32:43 +0000127 std::vector<BankSwizzle> &BS,
128 bool isLastAluTrans) const;
129
130 /// An instruction group can only access 2 channel pair (either [XY] or [ZW])
131 /// from KCache bank on R700+. This function check if MI set in input meet
132 /// this limitations
133 bool fitsConstReadLimitations(const std::vector<MachineInstr *> &) const;
134 /// Same but using const index set instead of MI set.
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000135 bool fitsConstReadLimitations(const std::vector<unsigned>&) const;
Vincent Lejeune0a22bc42013-03-14 15:50:45 +0000136
Tom Stellard75aadc22012-12-11 21:25:42 +0000137 /// \breif Vector instructions are instructions that must fill all
138 /// instruction slots within an instruction group.
139 bool isVector(const MachineInstr &MI) const;
140
Tom Stellard75aadc22012-12-11 21:25:42 +0000141 virtual unsigned getIEQOpcode() const;
142 virtual bool isMov(unsigned Opcode) const;
143
144 DFAPacketizer *CreateTargetScheduleState(const TargetMachine *TM,
145 const ScheduleDAG *DAG) const;
146
147 bool ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const;
148
149 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
150 SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const;
151
152 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB, const SmallVectorImpl<MachineOperand> &Cond, DebugLoc DL) const;
153
154 unsigned RemoveBranch(MachineBasicBlock &MBB) const;
155
156 bool isPredicated(const MachineInstr *MI) const;
157
158 bool isPredicable(MachineInstr *MI) const;
159
160 bool
161 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
162 const BranchProbability &Probability) const;
163
164 bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCyles,
165 unsigned ExtraPredCycles,
166 const BranchProbability &Probability) const ;
167
168 bool
169 isProfitableToIfCvt(MachineBasicBlock &TMBB,
170 unsigned NumTCycles, unsigned ExtraTCycles,
171 MachineBasicBlock &FMBB,
172 unsigned NumFCycles, unsigned ExtraFCycles,
173 const BranchProbability &Probability) const;
174
175 bool DefinesPredicate(MachineInstr *MI,
176 std::vector<MachineOperand> &Pred) const;
177
178 bool SubsumesPredicate(const SmallVectorImpl<MachineOperand> &Pred1,
179 const SmallVectorImpl<MachineOperand> &Pred2) const;
180
181 bool isProfitableToUnpredicate(MachineBasicBlock &TMBB,
182 MachineBasicBlock &FMBB) const;
183
184 bool PredicateInstruction(MachineInstr *MI,
185 const SmallVectorImpl<MachineOperand> &Pred) const;
186
Arnold Schwaighoferd2f96b92013-09-30 15:28:56 +0000187 unsigned int getPredicationCost(const MachineInstr *) const;
188
Tom Stellard75aadc22012-12-11 21:25:42 +0000189 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
190 const MachineInstr *MI,
191 unsigned *PredCost = 0) const;
192
193 virtual int getInstrLatency(const InstrItineraryData *ItinData,
194 SDNode *Node) const { return 1;}
195
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000196 /// \returns a list of all the registers that may be accesed using indirect
197 /// addressing.
198 std::vector<unsigned> getIndirectReservedRegs(const MachineFunction &MF) const;
199
200 virtual int getIndirectIndexBegin(const MachineFunction &MF) const;
201
202 virtual int getIndirectIndexEnd(const MachineFunction &MF) const;
203
204
205 virtual unsigned calculateIndirectAddress(unsigned RegIndex,
206 unsigned Channel) const;
207
Tom Stellard26a3b672013-10-22 18:19:10 +0000208 virtual const TargetRegisterClass *getIndirectAddrRegClass() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000209
210 virtual MachineInstrBuilder buildIndirectWrite(MachineBasicBlock *MBB,
211 MachineBasicBlock::iterator I,
212 unsigned ValueReg, unsigned Address,
213 unsigned OffsetReg) const;
214
215 virtual MachineInstrBuilder buildIndirectRead(MachineBasicBlock *MBB,
216 MachineBasicBlock::iterator I,
217 unsigned ValueReg, unsigned Address,
218 unsigned OffsetReg) const;
219
Vincent Lejeune80031d9f2013-04-03 16:49:34 +0000220 unsigned getMaxAlusPerClause() const;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000221
222 ///buildDefaultInstruction - This function returns a MachineInstr with
223 /// all the instruction modifiers initialized to their default values.
Tom Stellard75aadc22012-12-11 21:25:42 +0000224 /// You can use this function to avoid manually specifying each instruction
225 /// modifier operand when building a new instruction.
226 ///
227 /// \returns a MachineInstr with all the instruction modifiers initialized
228 /// to their default values.
229 MachineInstrBuilder buildDefaultInstruction(MachineBasicBlock &MBB,
230 MachineBasicBlock::iterator I,
231 unsigned Opcode,
232 unsigned DstReg,
233 unsigned Src0Reg,
234 unsigned Src1Reg = 0) const;
235
Vincent Lejeune519f21e2013-05-17 16:50:32 +0000236 MachineInstr *buildSlotOfVectorInstruction(MachineBasicBlock &MBB,
237 MachineInstr *MI,
238 unsigned Slot,
239 unsigned DstReg) const;
240
Tom Stellard75aadc22012-12-11 21:25:42 +0000241 MachineInstr *buildMovImm(MachineBasicBlock &BB,
242 MachineBasicBlock::iterator I,
243 unsigned DstReg,
244 uint64_t Imm) const;
245
Tom Stellard26a3b672013-10-22 18:19:10 +0000246 MachineInstr *buildMovInstr(MachineBasicBlock *MBB,
247 MachineBasicBlock::iterator I,
248 unsigned DstReg, unsigned SrcReg) const;
249
Tom Stellard75aadc22012-12-11 21:25:42 +0000250 /// \brief Get the index of Op in the MachineInstr.
251 ///
252 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000253 int getOperandIdx(const MachineInstr &MI, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000254
255 /// \brief Get the index of \p Op for the given Opcode.
256 ///
257 /// \returns -1 if the Instruction does not contain the specified \p Op.
Tom Stellard02661d92013-06-25 21:22:18 +0000258 int getOperandIdx(unsigned Opcode, unsigned Op) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000259
260 /// \brief Helper function for setting instruction flag values.
Tom Stellard02661d92013-06-25 21:22:18 +0000261 void setImmOperand(MachineInstr *MI, unsigned Op, int64_t Imm) const;
Tom Stellard75aadc22012-12-11 21:25:42 +0000262
263 /// \returns true if this instruction has an operand for storing target flags.
264 bool hasFlagOperand(const MachineInstr &MI) const;
265
266 ///\brief Add one of the MO_FLAG* flags to the specified \p Operand.
267 void addFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
268
269 ///\brief Determine if the specified \p Flag is set on this \p Operand.
270 bool isFlagSet(const MachineInstr &MI, unsigned Operand, unsigned Flag) const;
271
272 /// \param SrcIdx The register source to set the flag on (e.g src0, src1, src2)
273 /// \param Flag The flag being set.
274 ///
275 /// \returns the operand containing the flags for this instruction.
276 MachineOperand &getFlagOp(MachineInstr *MI, unsigned SrcIdx = 0,
277 unsigned Flag = 0) const;
278
279 /// \brief Clear the specified flag on the instruction.
280 void clearFlag(MachineInstr *MI, unsigned Operand, unsigned Flag) const;
281};
282
Tom Stellard13c68ef2013-09-05 18:38:09 +0000283namespace AMDGPU {
284
285int getLDSNoRetOp(uint16_t Opcode);
286
287} //End namespace AMDGPU
288
Tom Stellard75aadc22012-12-11 21:25:42 +0000289} // End llvm namespace
290
291#endif // R600INSTRINFO_H_