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Jim Grosbach00351b72010-10-08 17:28:40 +00001//===-- ARM/ARMCodeEmitter.cpp - Convert ARM code to machine code ---------===//
Evan Cheng9546a5c2007-07-05 21:15:40 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng9546a5c2007-07-05 21:15:40 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the pass that transforms the ARM machine instructions into
11// relocatable machine code.
12//
13//===----------------------------------------------------------------------===//
14
Evan Cheng19d64ba2008-10-29 23:55:43 +000015#define DEBUG_TYPE "jit"
Evan Cheng3be5b722008-09-02 06:52:38 +000016#include "ARM.h"
17#include "ARMAddressingModes.h"
Evan Cheng19d64ba2008-10-29 23:55:43 +000018#include "ARMConstantPoolValue.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000019#include "ARMInstrInfo.h"
Evan Cheng3be5b722008-09-02 06:52:38 +000020#include "ARMRelocations.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000021#include "ARMSubtarget.h"
22#include "ARMTargetMachine.h"
Jim Grosbachff2b4942008-10-28 18:25:49 +000023#include "llvm/Constants.h"
24#include "llvm/DerivedTypes.h"
Evan Cheng25a39092008-09-13 01:15:21 +000025#include "llvm/Function.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000026#include "llvm/PassManager.h"
Bruno Cardoso Lopesa194c3a2009-05-30 20:51:52 +000027#include "llvm/CodeGen/JITCodeEmitter.h"
Evan Cheng933b3922008-09-18 07:28:19 +000028#include "llvm/CodeGen/MachineConstantPool.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000029#include "llvm/CodeGen/MachineFunctionPass.h"
30#include "llvm/CodeGen/MachineInstr.h"
Evan Cheng7095cd22008-11-07 09:06:08 +000031#include "llvm/CodeGen/MachineJumpTableInfo.h"
Daniel Dunbarbc528b12009-09-21 05:58:35 +000032#include "llvm/CodeGen/MachineModuleInfo.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000033#include "llvm/CodeGen/Passes.h"
Evan Cheng9546a5c2007-07-05 21:15:40 +000034#include "llvm/ADT/Statistic.h"
Evan Cheng25a39092008-09-13 01:15:21 +000035#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +000036#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Cheng7095cd22008-11-07 09:06:08 +000038#ifndef NDEBUG
39#include <iomanip>
40#endif
Evan Cheng9546a5c2007-07-05 21:15:40 +000041using namespace llvm;
42
43STATISTIC(NumEmitted, "Number of machine instructions emitted");
44
45namespace {
Bruno Cardoso Lopesa194c3a2009-05-30 20:51:52 +000046
Chris Lattner8d806872010-02-02 21:48:51 +000047 class ARMCodeEmitter : public MachineFunctionPass {
Evan Cheng933b3922008-09-18 07:28:19 +000048 ARMJITInfo *JTI;
49 const ARMInstrInfo *II;
50 const TargetData *TD;
Evan Chengf6b24042009-09-10 01:23:53 +000051 const ARMSubtarget *Subtarget;
Evan Cheng933b3922008-09-18 07:28:19 +000052 TargetMachine &TM;
Chris Lattner8d806872010-02-02 21:48:51 +000053 JITCodeEmitter &MCE;
Chris Lattner34adc8d2010-03-14 01:41:15 +000054 MachineModuleInfo *MMI;
Evan Cheng20dbb3b2008-10-31 19:55:13 +000055 const std::vector<MachineConstantPoolEntry> *MCPEs;
Evan Cheng7095cd22008-11-07 09:06:08 +000056 const std::vector<MachineJumpTableEntry> *MJTEs;
57 bool IsPIC;
Bob Wilson4469a892010-06-28 22:23:17 +000058 bool IsThumb;
Bob Wilsona6fe21a2010-03-17 21:16:45 +000059
Daniel Dunbarbc528b12009-09-21 05:58:35 +000060 void getAnalysisUsage(AnalysisUsage &AU) const {
61 AU.addRequired<MachineModuleInfo>();
62 MachineFunctionPass::getAnalysisUsage(AU);
63 }
Bob Wilsona6fe21a2010-03-17 21:16:45 +000064
Evan Cheng9546a5c2007-07-05 21:15:40 +000065 static char ID;
Chris Lattner8d806872010-02-02 21:48:51 +000066 public:
67 ARMCodeEmitter(TargetMachine &tm, JITCodeEmitter &mce)
Owen Andersona7aed182010-08-06 18:33:48 +000068 : MachineFunctionPass(ID), JTI(0),
Dan Gohman1f0f2142010-04-17 17:42:52 +000069 II((const ARMInstrInfo *)tm.getInstrInfo()),
Chris Lattner8d806872010-02-02 21:48:51 +000070 TD(tm.getTargetData()), TM(tm),
Bob Wilson4469a892010-06-28 22:23:17 +000071 MCE(mce), MCPEs(0), MJTEs(0),
72 IsPIC(TM.getRelocationModel() == Reloc::PIC_), IsThumb(false) {}
Bob Wilsona6fe21a2010-03-17 21:16:45 +000073
Chris Lattner8d806872010-02-02 21:48:51 +000074 /// getBinaryCodeForInstr - This function, generated by the
75 /// CodeEmitterGenerator using TableGen, produces the binary encoding for
76 /// machine instructions.
Jim Grosbacha7b6d582010-10-08 00:21:28 +000077 unsigned getBinaryCodeForInstr(const MachineInstr &MI) const;
Evan Cheng9546a5c2007-07-05 21:15:40 +000078
79 bool runOnMachineFunction(MachineFunction &MF);
80
81 virtual const char *getPassName() const {
82 return "ARM Machine Code Emitter";
83 }
84
85 void emitInstruction(const MachineInstr &MI);
Evan Cheng3be5b722008-09-02 06:52:38 +000086
87 private:
Evan Cheng933b3922008-09-18 07:28:19 +000088
Evan Chengfd2adbf2008-11-05 23:22:34 +000089 void emitWordLE(unsigned Binary);
Evan Chengad519bb2008-11-11 22:19:31 +000090 void emitDWordLE(uint64_t Binary);
Evan Cheng933b3922008-09-18 07:28:19 +000091 void emitConstPoolInstruction(const MachineInstr &MI);
Zonr Chang2da5aa12010-05-25 08:42:45 +000092 void emitMOVi32immInstruction(const MachineInstr &MI);
Evan Chengb870fd82008-11-06 02:25:39 +000093 void emitMOVi2piecesInstruction(const MachineInstr &MI);
Evan Cheng7095cd22008-11-07 09:06:08 +000094 void emitLEApcrelJTInstruction(const MachineInstr &MI);
Evan Cheng30f6f8f2008-11-14 20:09:11 +000095 void emitPseudoMoveInstruction(const MachineInstr &MI);
Evan Chengfd2adbf2008-11-05 23:22:34 +000096 void addPCLabel(unsigned LabelID);
Evan Cheng933b3922008-09-18 07:28:19 +000097 void emitPseudoInstruction(const MachineInstr &MI);
Evan Cheng33fa89c6f2008-09-12 22:01:15 +000098 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
Evan Chengd1424c42008-09-12 22:45:55 +000099 const TargetInstrDesc &TID,
Evan Cheng467e6e82008-10-31 19:10:44 +0000100 const MachineOperand &MO,
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000101 unsigned OpIdx);
102
Evan Chengb870fd82008-11-06 02:25:39 +0000103 unsigned getMachineSoImmOpValue(unsigned SoImm);
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000104 unsigned getAddrModeSBit(const MachineInstr &MI,
105 const TargetInstrDesc &TID) const;
Evan Chengd1424c42008-09-12 22:45:55 +0000106
Evan Chengfd2adbf2008-11-05 23:22:34 +0000107 void emitDataProcessingInstruction(const MachineInstr &MI,
Evan Cheng8467e242008-11-07 22:30:53 +0000108 unsigned ImplicitRd = 0,
Evan Chengfd2adbf2008-11-05 23:22:34 +0000109 unsigned ImplicitRn = 0);
Evan Cheng3be5b722008-09-02 06:52:38 +0000110
Evan Chengfd2adbf2008-11-05 23:22:34 +0000111 void emitLoadStoreInstruction(const MachineInstr &MI,
Evan Cheng7095cd22008-11-07 09:06:08 +0000112 unsigned ImplicitRd = 0,
Evan Chengfd2adbf2008-11-05 23:22:34 +0000113 unsigned ImplicitRn = 0);
Evan Cheng81889d012008-11-05 18:35:52 +0000114
Evan Chengfd2adbf2008-11-05 23:22:34 +0000115 void emitMiscLoadStoreInstruction(const MachineInstr &MI,
116 unsigned ImplicitRn = 0);
Evan Cheng81889d012008-11-05 18:35:52 +0000117
118 void emitLoadStoreMultipleInstruction(const MachineInstr &MI);
119
Evan Cheng2686c8f2008-11-06 01:21:28 +0000120 void emitMulFrmInstruction(const MachineInstr &MI);
Evan Cheng81889d012008-11-05 18:35:52 +0000121
Evan Cheng49d66522008-11-06 22:15:19 +0000122 void emitExtendInstruction(const MachineInstr &MI);
123
Evan Cheng98dc53e2008-11-07 01:41:35 +0000124 void emitMiscArithInstruction(const MachineInstr &MI);
125
Bob Wilson96649842010-08-11 00:01:18 +0000126 void emitSaturateInstruction(const MachineInstr &MI);
127
Evan Cheng81889d012008-11-05 18:35:52 +0000128 void emitBranchInstruction(const MachineInstr &MI);
129
Evan Cheng8467e242008-11-07 22:30:53 +0000130 void emitInlineJumpTable(unsigned JTIndex);
Evan Cheng7095cd22008-11-07 09:06:08 +0000131
Evan Cheng81889d012008-11-05 18:35:52 +0000132 void emitMiscBranchInstruction(const MachineInstr &MI);
Evan Cheng3be5b722008-09-02 06:52:38 +0000133
Evan Chengac2af2f2008-11-11 02:11:05 +0000134 void emitVFPArithInstruction(const MachineInstr &MI);
135
Evan Cheng38c9a142008-11-11 19:40:26 +0000136 void emitVFPConversionInstruction(const MachineInstr &MI);
137
Evan Cheng8cbbcb12008-11-11 21:48:44 +0000138 void emitVFPLoadStoreInstruction(const MachineInstr &MI);
139
140 void emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI);
141
Bob Wilsonab0819e2010-06-29 17:34:07 +0000142 void emitNEONLaneInstruction(const MachineInstr &MI);
Bob Wilsonbe157b02010-06-29 20:13:29 +0000143 void emitNEONDupInstruction(const MachineInstr &MI);
Bob Wilsone70c8b12010-06-25 21:17:19 +0000144 void emitNEON1RegModImmInstruction(const MachineInstr &MI);
145 void emitNEON2RegInstruction(const MachineInstr &MI);
Bob Wilson2530ca02010-06-25 22:40:46 +0000146 void emitNEON3RegInstruction(const MachineInstr &MI);
Bob Wilson6eae5202010-06-11 21:34:50 +0000147
Evan Cheng3be5b722008-09-02 06:52:38 +0000148 /// getMachineOpValue - Return binary encoding of operand. If the machine
149 /// operand requires relocation, record the relocation and return zero.
Jim Grosbachb770c002010-10-08 17:45:54 +0000150 unsigned getMachineOpValue(const MachineInstr &MI,
151 const MachineOperand &MO) const;
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const {
Evan Cheng3be5b722008-09-02 06:52:38 +0000153 return getMachineOpValue(MI, MI.getOperand(OpIdx));
154 }
Evan Cheng3be5b722008-09-02 06:52:38 +0000155
Jim Grosbachd9d31da2010-10-12 23:00:24 +0000156 // FIXME: The legacy JIT ARMCodeEmitter doesn't rely on the the
157 // TableGen'erated getBinaryCodeForInstr() function to encode any
158 // operand values, instead querying getMachineOpValue() directly for
159 // each operand it needs to encode. Thus, any of the new encoder
160 // helper functions can simply return 0 as the values the return
161 // are already handled elsewhere. They are placeholders to allow this
162 // encoder to continue to function until the MC encoder is sufficiently
163 // far along that this one can be eliminated entirely.
Owen Anderson7ffe3b32010-11-11 19:07:48 +0000164 unsigned NEONThumb2DataIPostEncoder(const MachineInstr &MI, unsigned Val)
165 const { return 0; }
Owen Anderson99a8cb42010-11-11 21:36:43 +0000166 unsigned NEONThumb2LoadStorePostEncoder(const MachineInstr &MI,unsigned Val)
167 const { return 0; }
Owen Andersonce2250f2010-11-11 23:12:55 +0000168 unsigned NEONThumb2DupPostEncoder(const MachineInstr &MI,unsigned Val)
169 const { return 0; }
Jim Grosbach9d6d77a2010-11-11 18:04:49 +0000170 unsigned getBranchTargetOpValue(const MachineInstr &MI, unsigned Op)
171 const { return 0; }
Jim Grosbachd9d31da2010-10-12 23:00:24 +0000172 unsigned getCCOutOpValue(const MachineInstr &MI, unsigned Op)
173 const { return 0; }
Jim Grosbach12e493a2010-10-12 23:18:08 +0000174 unsigned getSOImmOpValue(const MachineInstr &MI, unsigned Op)
175 const { return 0; }
Owen Anderson8fdd1722010-11-12 21:12:40 +0000176 unsigned getT2SOImmOpValue(const MachineInstr &MI, unsigned Op)
177 const { return 0; }
Jim Grosbachefd53692010-10-12 23:53:58 +0000178 unsigned getSORegOpValue(const MachineInstr &MI, unsigned Op)
179 const { return 0; }
Owen Anderson50d662b2010-11-29 22:44:32 +0000180 unsigned getT2AddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
181 const { return 0; }
182 unsigned getT2AddrModeImm8OpValue(const MachineInstr &MI, unsigned Op)
183 const { return 0; }
Owen Andersone22c7322010-11-30 00:14:31 +0000184 unsigned getT2AddrModeImm8OffsetOpValue(const MachineInstr &MI, unsigned Op)
185 const { return 0; }
Owen Anderson50d662b2010-11-29 22:44:32 +0000186 unsigned getT2AddrModeSORegOpValue(const MachineInstr &MI, unsigned Op)
187 const { return 0; }
Owen Anderson8fdd1722010-11-12 21:12:40 +0000188 unsigned getT2SORegOpValue(const MachineInstr &MI, unsigned Op)
189 const { return 0; }
Jim Grosbach1e7db682010-10-13 19:56:10 +0000190 unsigned getRotImmOpValue(const MachineInstr &MI, unsigned Op)
191 const { return 0; }
Jim Grosbach68a335e2010-10-15 17:15:16 +0000192 unsigned getImmMinusOneOpValue(const MachineInstr &MI, unsigned Op)
193 const { return 0; }
Owen Andersona4b63e12010-11-02 22:28:01 +0000194 unsigned getAddrMode6AddressOpValue(const MachineInstr &MI, unsigned Op)
Owen Andersonad402342010-11-02 00:05:05 +0000195 const { return 0; }
Bob Wilson318ce7c2010-11-30 00:00:42 +0000196 unsigned getAddrMode6DupAddressOpValue(const MachineInstr &MI, unsigned Op)
197 const { return 0; }
Owen Andersona4b63e12010-11-02 22:28:01 +0000198 unsigned getAddrMode6OffsetOpValue(const MachineInstr &MI, unsigned Op)
Owen Anderson526ffd52010-11-02 01:24:55 +0000199 const { return 0; }
Jim Grosbach5edb03e2010-10-21 22:03:21 +0000200 unsigned getBitfieldInvertedMaskOpValue(const MachineInstr &MI,
201 unsigned Op) const { return 0; }
Jim Grosbachcc4a4912010-11-10 23:38:36 +0000202 uint32_t getLdStmModeOpValue(const MachineInstr &MI, unsigned OpIdx)
203 const {return 0; }
Jim Grosbachdbfb5ed2010-11-09 17:20:53 +0000204 uint32_t getLdStSORegOpValue(const MachineInstr &MI, unsigned OpIdx)
205 const { return 0; }
Bill Wendlinge84eb992010-11-03 01:49:29 +0000206
207 unsigned getAddrModeImm12OpValue(const MachineInstr &MI, unsigned Op)
208 const {
209 // {17-13} = reg
210 // {12} = (U)nsigned (add == '1', sub == '0')
211 // {11-0} = imm12
Bill Wendling603bd8f2010-11-02 22:31:46 +0000212 const MachineOperand &MO = MI.getOperand(Op);
213 const MachineOperand &MO1 = MI.getOperand(Op + 1);
214 if (!MO.isReg()) {
215 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
216 return 0;
Jim Grosbach333b0a92010-10-27 19:55:59 +0000217 }
Bill Wendling603bd8f2010-11-02 22:31:46 +0000218 unsigned Reg = getARMRegisterNumbering(MO.getReg());
Bill Wendlinge84eb992010-11-03 01:49:29 +0000219 int32_t Imm12 = MO1.getImm();
Bill Wendling603bd8f2010-11-02 22:31:46 +0000220 uint32_t Binary;
Bill Wendlinge84eb992010-11-03 01:49:29 +0000221 Binary = Imm12 & 0xfff;
222 if (Imm12 >= 0)
223 Binary |= (1 << 12);
224 Binary |= (Reg << 13);
225 return Binary;
226 }
Jason W Kim5a97bd82010-11-18 23:37:15 +0000227
228 unsigned getMovtImmOpValue(const MachineInstr &MI, unsigned Op) const {
229 return 0;
230 }
231
Jim Grosbach38b469e2010-11-15 20:47:07 +0000232 uint32_t getAddrMode2OpValue(const MachineInstr &MI, unsigned OpIdx)
233 const { return 0;}
234 uint32_t getAddrMode2OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
235 const { return 0;}
Jim Grosbach68685e62010-11-11 16:55:29 +0000236 uint32_t getAddrMode3OffsetOpValue(const MachineInstr &MI, unsigned OpIdx)
237 const { return 0;}
Bill Wendling811c9362010-11-30 07:44:32 +0000238 uint32_t getAddrMode3OpValue(const MachineInstr &MI, unsigned Op)
239 const { return 0; }
240 uint32_t getAddrModeS4OpValue(const MachineInstr &MI, unsigned Op)
241 const { return 0; }
Bill Wendlinge84eb992010-11-03 01:49:29 +0000242 uint32_t getAddrMode5OpValue(const MachineInstr &MI, unsigned Op) const {
Bill Wendling0914d442010-11-20 00:26:37 +0000243 // {17-13} = reg
244 // {12} = (U)nsigned (add == '1', sub == '0')
245 // {11-0} = imm12
Bill Wendlinge84eb992010-11-03 01:49:29 +0000246 const MachineOperand &MO = MI.getOperand(Op);
247 const MachineOperand &MO1 = MI.getOperand(Op + 1);
248 if (!MO.isReg()) {
249 emitConstPoolAddress(MO.getIndex(), ARM::reloc_arm_cp_entry);
250 return 0;
251 }
252 unsigned Reg = getARMRegisterNumbering(MO.getReg());
Bill Wendling0914d442010-11-20 00:26:37 +0000253 int32_t Imm12 = MO1.getImm();
254
255 // Special value for #-0
256 if (Imm12 == INT32_MIN)
257 Imm12 = 0;
258
259 // Immediate is always encoded as positive. The 'U' bit controls add vs
260 // sub.
261 bool isAdd = true;
262 if (Imm12 < 0) {
263 Imm12 = -Imm12;
264 isAdd = false;
265 }
266
267 uint32_t Binary = Imm12 & 0xfff;
268 if (isAdd)
269 Binary |= (1 << 12);
270 Binary |= (Reg << 13);
Bill Wendling603bd8f2010-11-02 22:31:46 +0000271 return Binary;
272 }
Jim Grosbach5f0d6162010-10-29 23:21:57 +0000273 unsigned getNEONVcvtImm32OpValue(const MachineInstr &MI, unsigned Op)
274 const { return 0; }
Jim Grosbachd9d31da2010-10-12 23:00:24 +0000275
Jim Grosbach74ef9e12010-10-30 00:37:59 +0000276 unsigned getRegisterListOpValue(const MachineInstr &MI, unsigned Op)
277 const { return 0; }
278
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +0000279 /// getMovi32Value - Return binary encoding of operand for movw/movt. If the
Jim Grosbach84511e12010-06-02 21:53:11 +0000280 /// machine operand requires relocation, record the relocation and return
281 /// zero.
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +0000282 unsigned getMovi32Value(const MachineInstr &MI,const MachineOperand &MO,
Zonr Chang2da5aa12010-05-25 08:42:45 +0000283 unsigned Reloc);
Zonr Chang2da5aa12010-05-25 08:42:45 +0000284
Evan Chengfd2adbf2008-11-05 23:22:34 +0000285 /// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
Evan Cheng3be5b722008-09-02 06:52:38 +0000286 ///
Evan Chengfd2adbf2008-11-05 23:22:34 +0000287 unsigned getShiftOp(unsigned Imm) const ;
Evan Cheng3be5b722008-09-02 06:52:38 +0000288
289 /// Routines that handle operands which add machine relocations which are
Evan Cheng8467e242008-11-07 22:30:53 +0000290 /// fixed up by the relocation stage.
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000291 void emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
Jeffrey Yasskindb5f24c2009-11-07 08:51:52 +0000292 bool MayNeedFarStub, bool Indirect,
Jim Grosbachb770c002010-10-08 17:45:54 +0000293 intptr_t ACPV = 0) const;
294 void emitExternalSymbolAddress(const char *ES, unsigned Reloc) const;
295 void emitConstPoolAddress(unsigned CPI, unsigned Reloc) const;
296 void emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const;
Evan Cheng8467e242008-11-07 22:30:53 +0000297 void emitMachineBasicBlock(MachineBasicBlock *BB, unsigned Reloc,
Jim Grosbachb770c002010-10-08 17:45:54 +0000298 intptr_t JTBase = 0) const;
Evan Cheng9546a5c2007-07-05 21:15:40 +0000299 };
Evan Cheng9546a5c2007-07-05 21:15:40 +0000300}
301
Chris Lattner8d806872010-02-02 21:48:51 +0000302char ARMCodeEmitter::ID = 0;
303
Bob Wilsona6fe21a2010-03-17 21:16:45 +0000304/// createARMJITCodeEmitterPass - Return a pass that emits the collected ARM
Chris Lattnerc83cfb9d2010-02-02 21:38:59 +0000305/// code to the specified MCE object.
Bruno Cardoso Lopes5661ea62009-07-06 05:09:34 +0000306FunctionPass *llvm::createARMJITCodeEmitterPass(ARMBaseTargetMachine &TM,
307 JITCodeEmitter &JCE) {
Chris Lattner8d806872010-02-02 21:48:51 +0000308 return new ARMCodeEmitter(TM, JCE);
Evan Cheng9546a5c2007-07-05 21:15:40 +0000309}
Bruno Cardoso Lopesa194c3a2009-05-30 20:51:52 +0000310
Chris Lattner8d806872010-02-02 21:48:51 +0000311bool ARMCodeEmitter::runOnMachineFunction(MachineFunction &MF) {
Evan Cheng9546a5c2007-07-05 21:15:40 +0000312 assert((MF.getTarget().getRelocationModel() != Reloc::Default ||
313 MF.getTarget().getRelocationModel() != Reloc::Static) &&
314 "JIT relocation model must be set to static or default!");
Dan Gohman1f0f2142010-04-17 17:42:52 +0000315 JTI = ((ARMTargetMachine &)MF.getTarget()).getJITInfo();
316 II = ((const ARMTargetMachine &)MF.getTarget()).getInstrInfo();
317 TD = ((const ARMTargetMachine &)MF.getTarget()).getTargetData();
Evan Chengf6b24042009-09-10 01:23:53 +0000318 Subtarget = &TM.getSubtarget<ARMSubtarget>();
Evan Cheng20dbb3b2008-10-31 19:55:13 +0000319 MCPEs = &MF.getConstantPool()->getConstants();
Chris Lattnera14ac3fd2010-01-25 23:22:00 +0000320 MJTEs = 0;
321 if (MF.getJumpTableInfo()) MJTEs = &MF.getJumpTableInfo()->getJumpTables();
Evan Cheng7095cd22008-11-07 09:06:08 +0000322 IsPIC = TM.getRelocationModel() == Reloc::PIC_;
Bob Wilson4469a892010-06-28 22:23:17 +0000323 IsThumb = MF.getInfo<ARMFunctionInfo>()->isThumbFunction();
Evan Cheng98161f52008-11-08 07:38:22 +0000324 JTI->Initialize(MF, IsPIC);
Chris Lattner34adc8d2010-03-14 01:41:15 +0000325 MMI = &getAnalysis<MachineModuleInfo>();
326 MCE.setModuleInfo(MMI);
Evan Cheng9546a5c2007-07-05 21:15:40 +0000327
328 do {
Jim Grosbachf24f9d92009-08-11 15:33:49 +0000329 DEBUG(errs() << "JITTing function '"
Daniel Dunbar0dd5e1e2009-07-25 00:23:56 +0000330 << MF.getFunction()->getName() << "'\n");
Evan Cheng9546a5c2007-07-05 21:15:40 +0000331 MCE.startFunction(MF);
Jim Grosbachf24f9d92009-08-11 15:33:49 +0000332 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
Evan Cheng9546a5c2007-07-05 21:15:40 +0000333 MBB != E; ++MBB) {
334 MCE.StartMachineBasicBlock(MBB);
335 for (MachineBasicBlock::const_iterator I = MBB->begin(), E = MBB->end();
336 I != E; ++I)
337 emitInstruction(*I);
338 }
339 } while (MCE.finishFunction(MF));
340
341 return false;
342}
343
Evan Chengfd2adbf2008-11-05 23:22:34 +0000344/// getShiftOp - Return the shift opcode (bit[6:5]) of the immediate value.
Evan Cheng3be5b722008-09-02 06:52:38 +0000345///
Chris Lattner8d806872010-02-02 21:48:51 +0000346unsigned ARMCodeEmitter::getShiftOp(unsigned Imm) const {
Evan Chengfd2adbf2008-11-05 23:22:34 +0000347 switch (ARM_AM::getAM2ShiftOpc(Imm)) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000348 default: llvm_unreachable("Unknown shift opc!");
Evan Cheng3be5b722008-09-02 06:52:38 +0000349 case ARM_AM::asr: return 2;
350 case ARM_AM::lsl: return 0;
351 case ARM_AM::lsr: return 1;
Evan Chengf7c6eff2007-08-07 01:37:15 +0000352 case ARM_AM::ror:
Evan Cheng3be5b722008-09-02 06:52:38 +0000353 case ARM_AM::rrx: return 3;
Evan Chengf7c6eff2007-08-07 01:37:15 +0000354 }
Evan Cheng3be5b722008-09-02 06:52:38 +0000355 return 0;
Evan Chengf7c6eff2007-08-07 01:37:15 +0000356}
357
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +0000358/// getMovi32Value - Return binary encoding of operand for movw/movt. If the
Zonr Chang2da5aa12010-05-25 08:42:45 +0000359/// machine operand requires relocation, record the relocation and return zero.
360unsigned ARMCodeEmitter::getMovi32Value(const MachineInstr &MI,
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +0000361 const MachineOperand &MO,
Zonr Chang2da5aa12010-05-25 08:42:45 +0000362 unsigned Reloc) {
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +0000363 assert(((Reloc == ARM::reloc_arm_movt) || (Reloc == ARM::reloc_arm_movw))
Zonr Chang2da5aa12010-05-25 08:42:45 +0000364 && "Relocation to this function should be for movt or movw");
365
366 if (MO.isImm())
367 return static_cast<unsigned>(MO.getImm());
368 else if (MO.isGlobal())
369 emitGlobalAddress(MO.getGlobal(), Reloc, true, false);
370 else if (MO.isSymbol())
371 emitExternalSymbolAddress(MO.getSymbolName(), Reloc);
372 else if (MO.isMBB())
373 emitMachineBasicBlock(MO.getMBB(), Reloc);
374 else {
375#ifndef NDEBUG
376 errs() << MO;
377#endif
378 llvm_unreachable("Unsupported operand type for movw/movt");
379 }
380 return 0;
381}
382
Evan Cheng3be5b722008-09-02 06:52:38 +0000383/// getMachineOpValue - Return binary encoding of operand. If the machine
384/// operand requires relocation, record the relocation and return zero.
Chris Lattner8d806872010-02-02 21:48:51 +0000385unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI,
Jim Grosbachb770c002010-10-08 17:45:54 +0000386 const MachineOperand &MO) const {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000387 if (MO.isReg())
Jim Grosbach40e85fb2010-09-15 20:26:25 +0000388 return getARMRegisterNumbering(MO.getReg());
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000389 else if (MO.isImm())
Evan Cheng3be5b722008-09-02 06:52:38 +0000390 return static_cast<unsigned>(MO.getImm());
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000391 else if (MO.isGlobal())
Evan Chengf6b24042009-09-10 01:23:53 +0000392 emitGlobalAddress(MO.getGlobal(), ARM::reloc_arm_branch, true, false);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000393 else if (MO.isSymbol())
Evan Chengbb373c42008-11-08 07:22:33 +0000394 emitExternalSymbolAddress(MO.getSymbolName(), ARM::reloc_arm_branch);
Evan Chengbfcee5b2008-11-12 01:02:24 +0000395 else if (MO.isCPI()) {
396 const TargetInstrDesc &TID = MI.getDesc();
397 // For VFP load, the immediate offset is multiplied by 4.
398 unsigned Reloc = ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm)
399 ? ARM::reloc_arm_vfp_cp_entry : ARM::reloc_arm_cp_entry;
400 emitConstPoolAddress(MO.getIndex(), Reloc);
401 } else if (MO.isJTI())
Chris Lattnera5bb3702007-12-30 23:10:15 +0000402 emitJumpTableAddress(MO.getIndex(), ARM::reloc_arm_relative);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000403 else if (MO.isMBB())
Evan Cheng7095cd22008-11-07 09:06:08 +0000404 emitMachineBasicBlock(MO.getMBB(), ARM::reloc_arm_branch);
Jim Grosbach2aeb8b92010-11-19 00:27:09 +0000405 else
406 llvm_unreachable("Unable to encode MachineOperand!");
Evan Cheng3be5b722008-09-02 06:52:38 +0000407 return 0;
Evan Chengf7c6eff2007-08-07 01:37:15 +0000408}
409
Evan Cheng933b3922008-09-18 07:28:19 +0000410/// emitGlobalAddress - Emit the specified address to the code stream.
Evan Chengf7c6eff2007-08-07 01:37:15 +0000411///
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000412void ARMCodeEmitter::emitGlobalAddress(const GlobalValue *GV, unsigned Reloc,
Chris Lattner8d806872010-02-02 21:48:51 +0000413 bool MayNeedFarStub, bool Indirect,
Jim Grosbachb770c002010-10-08 17:45:54 +0000414 intptr_t ACPV) const {
Evan Chengf6b24042009-09-10 01:23:53 +0000415 MachineRelocation MR = Indirect
416 ? MachineRelocation::getIndirectSymbol(MCE.getCurrentPCOffset(), Reloc,
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000417 const_cast<GlobalValue *>(GV),
418 ACPV, MayNeedFarStub)
Evan Chengf6b24042009-09-10 01:23:53 +0000419 : MachineRelocation::getGV(MCE.getCurrentPCOffset(), Reloc,
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000420 const_cast<GlobalValue *>(GV), ACPV,
421 MayNeedFarStub);
Evan Chengf6b24042009-09-10 01:23:53 +0000422 MCE.addRelocation(MR);
Evan Chengf7c6eff2007-08-07 01:37:15 +0000423}
424
425/// emitExternalSymbolAddress - Arrange for the address of an external symbol to
426/// be emitted to the current location in the function, and allow it to be PC
427/// relative.
Jim Grosbachb770c002010-10-08 17:45:54 +0000428void ARMCodeEmitter::
429emitExternalSymbolAddress(const char *ES, unsigned Reloc) const {
Evan Chengf7c6eff2007-08-07 01:37:15 +0000430 MCE.addRelocation(MachineRelocation::getExtSym(MCE.getCurrentPCOffset(),
431 Reloc, ES));
432}
433
434/// emitConstPoolAddress - Arrange for the address of an constant pool
435/// to be emitted to the current location in the function, and allow it to be PC
436/// relative.
Jim Grosbachb770c002010-10-08 17:45:54 +0000437void ARMCodeEmitter::emitConstPoolAddress(unsigned CPI, unsigned Reloc) const {
Evan Cheng19d64ba2008-10-29 23:55:43 +0000438 // Tell JIT emitter we'll resolve the address.
Evan Chengf7c6eff2007-08-07 01:37:15 +0000439 MCE.addRelocation(MachineRelocation::getConstPool(MCE.getCurrentPCOffset(),
Evan Cheng8467e242008-11-07 22:30:53 +0000440 Reloc, CPI, 0, true));
Evan Chengf7c6eff2007-08-07 01:37:15 +0000441}
442
443/// emitJumpTableAddress - Arrange for the address of a jump table to
444/// be emitted to the current location in the function, and allow it to be PC
445/// relative.
Jim Grosbachb770c002010-10-08 17:45:54 +0000446void ARMCodeEmitter::
447emitJumpTableAddress(unsigned JTIndex, unsigned Reloc) const {
Evan Chengf7c6eff2007-08-07 01:37:15 +0000448 MCE.addRelocation(MachineRelocation::getJumpTable(MCE.getCurrentPCOffset(),
Evan Cheng8467e242008-11-07 22:30:53 +0000449 Reloc, JTIndex, 0, true));
Evan Chengf7c6eff2007-08-07 01:37:15 +0000450}
451
Raul Herbster1457b2b2007-08-30 23:29:26 +0000452/// emitMachineBasicBlock - Emit the specified address basic block.
Chris Lattner8d806872010-02-02 21:48:51 +0000453void ARMCodeEmitter::emitMachineBasicBlock(MachineBasicBlock *BB,
Jim Grosbachb770c002010-10-08 17:45:54 +0000454 unsigned Reloc,
455 intptr_t JTBase) const {
Raul Herbster1457b2b2007-08-30 23:29:26 +0000456 MCE.addRelocation(MachineRelocation::getBB(MCE.getCurrentPCOffset(),
Evan Cheng8467e242008-11-07 22:30:53 +0000457 Reloc, BB, JTBase));
Raul Herbster1457b2b2007-08-30 23:29:26 +0000458}
Evan Chengf7c6eff2007-08-07 01:37:15 +0000459
Chris Lattner8d806872010-02-02 21:48:51 +0000460void ARMCodeEmitter::emitWordLE(unsigned Binary) {
Chris Lattneraf29ea62009-08-23 06:49:22 +0000461 DEBUG(errs() << " 0x";
462 errs().write_hex(Binary) << "\n");
Evan Chengfd2adbf2008-11-05 23:22:34 +0000463 MCE.emitWordLE(Binary);
464}
465
Chris Lattner8d806872010-02-02 21:48:51 +0000466void ARMCodeEmitter::emitDWordLE(uint64_t Binary) {
Chris Lattneraf29ea62009-08-23 06:49:22 +0000467 DEBUG(errs() << " 0x";
468 errs().write_hex(Binary) << "\n");
Evan Chengad519bb2008-11-11 22:19:31 +0000469 MCE.emitDWordLE(Binary);
470}
471
Chris Lattner8d806872010-02-02 21:48:51 +0000472void ARMCodeEmitter::emitInstruction(const MachineInstr &MI) {
Chris Lattnera6f074f2009-08-23 03:41:05 +0000473 DEBUG(errs() << "JIT: " << (void*)MCE.getCurrentPCValue() << ":\t" << MI);
Evan Cheng25a39092008-09-13 01:15:21 +0000474
Devang Patel051454a2009-10-06 02:19:11 +0000475 MCE.processDebugLoc(MI.getDebugLoc(), true);
Jeffrey Yasskin15d54b92009-07-17 18:49:39 +0000476
Dan Gohmand2d1ae12010-06-22 15:08:57 +0000477 ++NumEmitted; // Keep track of the # of mi's emitted
Evan Cheng81889d012008-11-05 18:35:52 +0000478 switch (MI.getDesc().TSFlags & ARMII::FormMask) {
Evan Chengfabdcce2008-11-13 23:36:57 +0000479 default: {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000480 llvm_unreachable("Unhandled instruction encoding format!");
Evan Cheng81889d012008-11-05 18:35:52 +0000481 break;
Evan Chengfabdcce2008-11-13 23:36:57 +0000482 }
Jim Grosbach56f47172010-11-17 23:33:14 +0000483 case ARMII::MiscFrm:
484 if (MI.getOpcode() == ARM::LEApcrelJT) {
485 // Materialize jumptable address.
486 emitLEApcrelJTInstruction(MI);
487 break;
488 }
489 llvm_unreachable("Unhandled instruction encoding!");
490 break;
Evan Cheng81889d012008-11-05 18:35:52 +0000491 case ARMII::Pseudo:
Evan Cheng933b3922008-09-18 07:28:19 +0000492 emitPseudoInstruction(MI);
Evan Cheng81889d012008-11-05 18:35:52 +0000493 break;
494 case ARMII::DPFrm:
495 case ARMII::DPSoRegFrm:
496 emitDataProcessingInstruction(MI);
497 break;
Evan Cheng2666f592008-11-13 07:34:59 +0000498 case ARMII::LdFrm:
499 case ARMII::StFrm:
Evan Cheng81889d012008-11-05 18:35:52 +0000500 emitLoadStoreInstruction(MI);
501 break;
Evan Cheng2666f592008-11-13 07:34:59 +0000502 case ARMII::LdMiscFrm:
503 case ARMII::StMiscFrm:
Evan Cheng81889d012008-11-05 18:35:52 +0000504 emitMiscLoadStoreInstruction(MI);
505 break;
Evan Chengaf644b52008-11-12 07:18:38 +0000506 case ARMII::LdStMulFrm:
Evan Cheng81889d012008-11-05 18:35:52 +0000507 emitLoadStoreMultipleInstruction(MI);
508 break;
Evan Cheng2686c8f2008-11-06 01:21:28 +0000509 case ARMII::MulFrm:
510 emitMulFrmInstruction(MI);
Evan Cheng81889d012008-11-05 18:35:52 +0000511 break;
Evan Cheng49d66522008-11-06 22:15:19 +0000512 case ARMII::ExtFrm:
513 emitExtendInstruction(MI);
514 break;
Evan Cheng98dc53e2008-11-07 01:41:35 +0000515 case ARMII::ArithMiscFrm:
516 emitMiscArithInstruction(MI);
517 break;
Bob Wilson96649842010-08-11 00:01:18 +0000518 case ARMII::SatFrm:
519 emitSaturateInstruction(MI);
520 break;
Evan Chengaa03cd32008-11-06 17:48:05 +0000521 case ARMII::BrFrm:
Evan Cheng81889d012008-11-05 18:35:52 +0000522 emitBranchInstruction(MI);
523 break;
Evan Chengaa03cd32008-11-06 17:48:05 +0000524 case ARMII::BrMiscFrm:
Evan Cheng81889d012008-11-05 18:35:52 +0000525 emitMiscBranchInstruction(MI);
526 break;
Evan Chengac2af2f2008-11-11 02:11:05 +0000527 // VFP instructions.
528 case ARMII::VFPUnaryFrm:
529 case ARMII::VFPBinaryFrm:
530 emitVFPArithInstruction(MI);
531 break;
Evan Cheng38c9a142008-11-11 19:40:26 +0000532 case ARMII::VFPConv1Frm:
533 case ARMII::VFPConv2Frm:
Evan Cheng97ccab82008-11-11 22:46:12 +0000534 case ARMII::VFPConv3Frm:
Evan Cheng4b6c7ef2008-11-12 06:41:41 +0000535 case ARMII::VFPConv4Frm:
536 case ARMII::VFPConv5Frm:
Evan Cheng38c9a142008-11-11 19:40:26 +0000537 emitVFPConversionInstruction(MI);
538 break;
Evan Cheng8cbbcb12008-11-11 21:48:44 +0000539 case ARMII::VFPLdStFrm:
540 emitVFPLoadStoreInstruction(MI);
541 break;
542 case ARMII::VFPLdStMulFrm:
543 emitVFPLoadStoreMultipleInstruction(MI);
544 break;
Bill Wendling5f5b9222010-10-15 23:35:12 +0000545
Bob Wilson6eae5202010-06-11 21:34:50 +0000546 // NEON instructions.
Bob Wilson0248da92010-06-26 04:07:15 +0000547 case ARMII::NGetLnFrm:
Bob Wilsonab0819e2010-06-29 17:34:07 +0000548 case ARMII::NSetLnFrm:
549 emitNEONLaneInstruction(MI);
Bob Wilson0248da92010-06-26 04:07:15 +0000550 break;
Bob Wilsonbe157b02010-06-29 20:13:29 +0000551 case ARMII::NDupFrm:
552 emitNEONDupInstruction(MI);
553 break;
Bob Wilson6eae5202010-06-11 21:34:50 +0000554 case ARMII::N1RegModImmFrm:
Bob Wilsone70c8b12010-06-25 21:17:19 +0000555 emitNEON1RegModImmInstruction(MI);
556 break;
557 case ARMII::N2RegFrm:
558 emitNEON2RegInstruction(MI);
Bob Wilson6eae5202010-06-11 21:34:50 +0000559 break;
Bob Wilson2530ca02010-06-25 22:40:46 +0000560 case ARMII::N3RegFrm:
561 emitNEON3RegInstruction(MI);
562 break;
Evan Cheng81889d012008-11-05 18:35:52 +0000563 }
Devang Patel051454a2009-10-06 02:19:11 +0000564 MCE.processDebugLoc(MI.getDebugLoc(), false);
Evan Chengf7c6eff2007-08-07 01:37:15 +0000565}
566
Chris Lattner8d806872010-02-02 21:48:51 +0000567void ARMCodeEmitter::emitConstPoolInstruction(const MachineInstr &MI) {
Evan Cheng8467e242008-11-07 22:30:53 +0000568 unsigned CPI = MI.getOperand(0).getImm(); // CP instruction index.
569 unsigned CPIndex = MI.getOperand(1).getIndex(); // Actual cp entry index.
Evan Cheng20dbb3b2008-10-31 19:55:13 +0000570 const MachineConstantPoolEntry &MCPE = (*MCPEs)[CPIndex];
Jim Grosbachf24f9d92009-08-11 15:33:49 +0000571
Evan Cheng467e6e82008-10-31 19:10:44 +0000572 // Remember the CONSTPOOL_ENTRY address for later relocation.
573 JTI->addConstantPoolEntryAddr(CPI, MCE.getCurrentPCValue());
574
575 // Emit constpool island entry. In most cases, the actual values will be
576 // resolved and relocated after code emission.
577 if (MCPE.isMachineConstantPoolEntry()) {
578 ARMConstantPoolValue *ACPV =
579 static_cast<ARMConstantPoolValue*>(MCPE.Val.MachineCPVal);
580
Chris Lattnera6f074f2009-08-23 03:41:05 +0000581 DEBUG(errs() << " ** ARM constant pool #" << CPI << " @ "
582 << (void*)MCE.getCurrentPCValue() << " " << *ACPV << '\n');
Evan Cheng467e6e82008-10-31 19:10:44 +0000583
Bob Wilson433ab092009-11-02 16:59:06 +0000584 assert(ACPV->isGlobalValue() && "unsupported constant pool value");
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000585 const GlobalValue *GV = ACPV->getGV();
Evan Cheng467e6e82008-10-31 19:10:44 +0000586 if (GV) {
Evan Chengf6b24042009-09-10 01:23:53 +0000587 Reloc::Model RelocM = TM.getRelocationModel();
Evan Cheng43b9ca62009-08-28 23:18:09 +0000588 emitGlobalAddress(GV, ARM::reloc_arm_machine_cp_entry,
Evan Chengf6b24042009-09-10 01:23:53 +0000589 isa<Function>(GV),
590 Subtarget->GVIsIndirectSymbol(GV, RelocM),
591 (intptr_t)ACPV);
Evan Cheng6dd08b62008-11-04 00:50:32 +0000592 } else {
Evan Cheng467e6e82008-10-31 19:10:44 +0000593 emitExternalSymbolAddress(ACPV->getSymbol(), ARM::reloc_arm_absolute);
594 }
Evan Chengfd2adbf2008-11-05 23:22:34 +0000595 emitWordLE(0);
Evan Cheng467e6e82008-10-31 19:10:44 +0000596 } else {
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000597 const Constant *CV = MCPE.Val.ConstVal;
Evan Cheng467e6e82008-10-31 19:10:44 +0000598
Daniel Dunbar0dd5e1e2009-07-25 00:23:56 +0000599 DEBUG({
600 errs() << " ** Constant pool #" << CPI << " @ "
601 << (void*)MCE.getCurrentPCValue() << " ";
602 if (const Function *F = dyn_cast<Function>(CV))
603 errs() << F->getName();
604 else
605 errs() << *CV;
606 errs() << '\n';
607 });
Evan Cheng467e6e82008-10-31 19:10:44 +0000608
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000609 if (const GlobalValue *GV = dyn_cast<GlobalValue>(CV)) {
Evan Chengf6b24042009-09-10 01:23:53 +0000610 emitGlobalAddress(GV, ARM::reloc_arm_absolute, isa<Function>(GV), false);
Evan Chengfd2adbf2008-11-05 23:22:34 +0000611 emitWordLE(0);
Evan Chengad519bb2008-11-11 22:19:31 +0000612 } else if (const ConstantInt *CI = dyn_cast<ConstantInt>(CV)) {
Gabor Greifb171ca02010-10-22 23:16:11 +0000613 uint32_t Val = uint32_t(*CI->getValue().getRawData());
Evan Chengfd2adbf2008-11-05 23:22:34 +0000614 emitWordLE(Val);
Evan Chengad519bb2008-11-11 22:19:31 +0000615 } else if (const ConstantFP *CFP = dyn_cast<ConstantFP>(CV)) {
Chris Lattnerfdd87902009-10-05 05:54:46 +0000616 if (CFP->getType()->isFloatTy())
Evan Chengad519bb2008-11-11 22:19:31 +0000617 emitWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
Chris Lattnerfdd87902009-10-05 05:54:46 +0000618 else if (CFP->getType()->isDoubleTy())
Evan Chengad519bb2008-11-11 22:19:31 +0000619 emitDWordLE(CFP->getValueAPF().bitcastToAPInt().getZExtValue());
620 else {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000621 llvm_unreachable("Unable to handle this constantpool entry!");
Evan Chengad519bb2008-11-11 22:19:31 +0000622 }
623 } else {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000624 llvm_unreachable("Unable to handle this constantpool entry!");
Evan Cheng467e6e82008-10-31 19:10:44 +0000625 }
626 }
627}
628
Zonr Chang2da5aa12010-05-25 08:42:45 +0000629void ARMCodeEmitter::emitMOVi32immInstruction(const MachineInstr &MI) {
630 const MachineOperand &MO0 = MI.getOperand(0);
631 const MachineOperand &MO1 = MI.getOperand(1);
632
633 // Emit the 'movw' instruction.
634 unsigned Binary = 0x30 << 20; // mov: Insts{27-20} = 0b00110000
635
636 unsigned Lo16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movw) & 0xFFFF;
637
638 // Set the conditional execution predicate.
639 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
640
641 // Encode Rd.
642 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
643
644 // Encode imm16 as imm4:imm12
645 Binary |= Lo16 & 0xFFF; // Insts{11-0} = imm12
646 Binary |= ((Lo16 >> 12) & 0xF) << 16; // Insts{19-16} = imm4
647 emitWordLE(Binary);
648
649 unsigned Hi16 = getMovi32Value(MI, MO1, ARM::reloc_arm_movt) >> 16;
650 // Emit the 'movt' instruction.
651 Binary = 0x34 << 20; // movt: Insts{27-20} = 0b00110100
652
653 // Set the conditional execution predicate.
654 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
655
656 // Encode Rd.
657 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
658
659 // Encode imm16 as imm4:imm1, same as movw above.
660 Binary |= Hi16 & 0xFFF;
661 Binary |= ((Hi16 >> 12) & 0xF) << 16;
662 emitWordLE(Binary);
663}
664
Chris Lattner8d806872010-02-02 21:48:51 +0000665void ARMCodeEmitter::emitMOVi2piecesInstruction(const MachineInstr &MI) {
Evan Chengb870fd82008-11-06 02:25:39 +0000666 const MachineOperand &MO0 = MI.getOperand(0);
667 const MachineOperand &MO1 = MI.getOperand(1);
Bob Wilson1b0e6142010-03-11 00:46:22 +0000668 assert(MO1.isImm() && ARM_AM::isSOImmTwoPartVal(MO1.getImm()) &&
669 "Not a valid so_imm value!");
Evan Chengb870fd82008-11-06 02:25:39 +0000670 unsigned V1 = ARM_AM::getSOImmTwoPartFirst(MO1.getImm());
671 unsigned V2 = ARM_AM::getSOImmTwoPartSecond(MO1.getImm());
672
673 // Emit the 'mov' instruction.
674 unsigned Binary = 0xd << 21; // mov: Insts{24-21} = 0b1101
675
676 // Set the conditional execution predicate.
Evan Cheng49d66522008-11-06 22:15:19 +0000677 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Chengb870fd82008-11-06 02:25:39 +0000678
679 // Encode Rd.
680 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
681
682 // Encode so_imm.
683 // Set bit I(25) to identify this is the immediate form of <shifter_op>
684 Binary |= 1 << ARMII::I_BitShift;
Evan Chenge3a53c42009-07-08 21:03:57 +0000685 Binary |= getMachineSoImmOpValue(V1);
Evan Chengb870fd82008-11-06 02:25:39 +0000686 emitWordLE(Binary);
687
688 // Now the 'orr' instruction.
689 Binary = 0xc << 21; // orr: Insts{24-21} = 0b1100
690
691 // Set the conditional execution predicate.
Evan Cheng49d66522008-11-06 22:15:19 +0000692 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Chengb870fd82008-11-06 02:25:39 +0000693
694 // Encode Rd.
695 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift;
696
697 // Encode Rn.
698 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift;
699
700 // Encode so_imm.
701 // Set bit I(25) to identify this is the immediate form of <shifter_op>
702 Binary |= 1 << ARMII::I_BitShift;
Evan Chenge3a53c42009-07-08 21:03:57 +0000703 Binary |= getMachineSoImmOpValue(V2);
Evan Chengb870fd82008-11-06 02:25:39 +0000704 emitWordLE(Binary);
705}
706
Chris Lattner8d806872010-02-02 21:48:51 +0000707void ARMCodeEmitter::emitLEApcrelJTInstruction(const MachineInstr &MI) {
Evan Cheng7095cd22008-11-07 09:06:08 +0000708 // It's basically add r, pc, (LJTI - $+8)
Jim Grosbachf24f9d92009-08-11 15:33:49 +0000709
Evan Cheng7095cd22008-11-07 09:06:08 +0000710 const TargetInstrDesc &TID = MI.getDesc();
711
712 // Emit the 'add' instruction.
Jim Grosbach4ded8f22010-11-17 21:57:51 +0000713 unsigned Binary = 0x4 << 21; // add: Insts{24-21} = 0b0100
Evan Cheng7095cd22008-11-07 09:06:08 +0000714
715 // Set the conditional execution predicate
716 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
717
718 // Encode S bit if MI modifies CPSR.
719 Binary |= getAddrModeSBit(MI, TID);
720
721 // Encode Rd.
722 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
723
724 // Encode Rn which is PC.
Jim Grosbach40e85fb2010-09-15 20:26:25 +0000725 Binary |= getARMRegisterNumbering(ARM::PC) << ARMII::RegRnShift;
Evan Cheng7095cd22008-11-07 09:06:08 +0000726
727 // Encode the displacement.
Evan Cheng7095cd22008-11-07 09:06:08 +0000728 Binary |= 1 << ARMII::I_BitShift;
729 emitJumpTableAddress(MI.getOperand(1).getIndex(), ARM::reloc_arm_jt_base);
730
731 emitWordLE(Binary);
732}
733
Chris Lattner8d806872010-02-02 21:48:51 +0000734void ARMCodeEmitter::emitPseudoMoveInstruction(const MachineInstr &MI) {
Evan Cheng30f6f8f2008-11-14 20:09:11 +0000735 unsigned Opcode = MI.getDesc().Opcode;
736
737 // Part of binary is determined by TableGn.
738 unsigned Binary = getBinaryCodeForInstr(MI);
739
740 // Set the conditional execution predicate
741 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
742
743 // Encode S bit if MI modifies CPSR.
744 if (Opcode == ARM::MOVsrl_flag || Opcode == ARM::MOVsra_flag)
745 Binary |= 1 << ARMII::S_BitShift;
746
747 // Encode register def if there is one.
748 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
749
750 // Encode the shift operation.
751 switch (Opcode) {
752 default: break;
Jim Grosbach062749c2010-10-14 20:43:44 +0000753 case ARM::RRX:
Evan Cheng30f6f8f2008-11-14 20:09:11 +0000754 // rrx
755 Binary |= 0x6 << 4;
756 break;
757 case ARM::MOVsrl_flag:
758 // lsr #1
759 Binary |= (0x2 << 4) | (1 << 7);
760 break;
761 case ARM::MOVsra_flag:
762 // asr #1
763 Binary |= (0x4 << 4) | (1 << 7);
764 break;
765 }
766
767 // Encode register Rm.
768 Binary |= getMachineOpValue(MI, 1);
769
770 emitWordLE(Binary);
771}
772
Chris Lattner8d806872010-02-02 21:48:51 +0000773void ARMCodeEmitter::addPCLabel(unsigned LabelID) {
Chris Lattneraf29ea62009-08-23 06:49:22 +0000774 DEBUG(errs() << " ** LPC" << LabelID << " @ "
775 << (void*)MCE.getCurrentPCValue() << '\n');
Evan Chengfd2adbf2008-11-05 23:22:34 +0000776 JTI->addPCLabelAddr(LabelID, MCE.getCurrentPCValue());
777}
778
Chris Lattner8d806872010-02-02 21:48:51 +0000779void ARMCodeEmitter::emitPseudoInstruction(const MachineInstr &MI) {
Evan Cheng467e6e82008-10-31 19:10:44 +0000780 unsigned Opcode = MI.getDesc().Opcode;
781 switch (Opcode) {
782 default:
Evan Cheng83e0d482009-09-28 09:14:39 +0000783 llvm_unreachable("ARMCodeEmitter::emitPseudoInstruction");
Jim Grosbach027bd472010-11-30 00:24:05 +0000784 case ARM::BX_CALL:
785 case ARM::BMOVPCRX_CALL:
786 case ARM::BXr9_CALL:
787 case ARM::BMOVPCRXr9_CALL: {
Xerxes Ranbyff66cd42010-07-22 17:28:34 +0000788 // First emit mov lr, pc
789 unsigned Binary = 0x01a0e00f;
790 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
791 emitWordLE(Binary);
792
793 // and then emit the branch.
794 emitMiscBranchInstruction(MI);
795 break;
796 }
Chris Lattnerb06015a2010-02-09 19:54:29 +0000797 case TargetOpcode::INLINEASM: {
Evan Cheng59213d62008-11-19 23:21:33 +0000798 // We allow inline assembler nodes with empty bodies - they can
799 // implicitly define registers, which is ok for JIT.
800 if (MI.getOperand(0).getSymbolName()[0]) {
Chris Lattner2104b8d2010-04-07 22:58:41 +0000801 report_fatal_error("JIT does not support inline asm!");
Evan Cheng59213d62008-11-19 23:21:33 +0000802 }
Evan Chengfabdcce2008-11-13 23:36:57 +0000803 break;
804 }
Bill Wendling499f7972010-07-16 22:20:36 +0000805 case TargetOpcode::PROLOG_LABEL:
Chris Lattneree2fbbc2010-03-14 02:33:54 +0000806 case TargetOpcode::EH_LABEL:
807 MCE.emitLabel(MI.getOperand(0).getMCSymbol());
808 break;
Chris Lattnerb06015a2010-02-09 19:54:29 +0000809 case TargetOpcode::IMPLICIT_DEF:
810 case TargetOpcode::KILL:
Evan Chengfabdcce2008-11-13 23:36:57 +0000811 // Do nothing.
812 break;
Evan Cheng467e6e82008-10-31 19:10:44 +0000813 case ARM::CONSTPOOL_ENTRY:
814 emitConstPoolInstruction(MI);
815 break;
816 case ARM::PICADD: {
Evan Cheng6dd08b62008-11-04 00:50:32 +0000817 // Remember of the address of the PC label for relocation later.
Evan Chengfd2adbf2008-11-05 23:22:34 +0000818 addPCLabel(MI.getOperand(2).getImm());
Evan Cheng467e6e82008-10-31 19:10:44 +0000819 // PICADD is just an add instruction that implicitly read pc.
Evan Cheng8467e242008-11-07 22:30:53 +0000820 emitDataProcessingInstruction(MI, 0, ARM::PC);
Evan Chengfd2adbf2008-11-05 23:22:34 +0000821 break;
822 }
823 case ARM::PICLDR:
824 case ARM::PICLDRB:
825 case ARM::PICSTR:
826 case ARM::PICSTRB: {
827 // Remember of the address of the PC label for relocation later.
828 addPCLabel(MI.getOperand(2).getImm());
829 // These are just load / store instructions that implicitly read pc.
Evan Cheng7095cd22008-11-07 09:06:08 +0000830 emitLoadStoreInstruction(MI, 0, ARM::PC);
Evan Chengfd2adbf2008-11-05 23:22:34 +0000831 break;
832 }
833 case ARM::PICLDRH:
834 case ARM::PICLDRSH:
835 case ARM::PICLDRSB:
836 case ARM::PICSTRH: {
837 // Remember of the address of the PC label for relocation later.
838 addPCLabel(MI.getOperand(2).getImm());
839 // These are just load / store instructions that implicitly read pc.
840 emitMiscLoadStoreInstruction(MI, ARM::PC);
Evan Cheng467e6e82008-10-31 19:10:44 +0000841 break;
842 }
Zonr Chang2da5aa12010-05-25 08:42:45 +0000843
844 case ARM::MOVi32imm:
Evan Chengf478cf92010-11-12 23:03:38 +0000845 // Two instructions to materialize a constant.
846 if (Subtarget->hasV6T2Ops())
847 emitMOVi32immInstruction(MI);
848 else
849 emitMOVi2piecesInstruction(MI);
Zonr Chang2da5aa12010-05-25 08:42:45 +0000850 break;
851
Evan Cheng7095cd22008-11-07 09:06:08 +0000852 case ARM::LEApcrelJT:
853 // Materialize jumptable address.
854 emitLEApcrelJTInstruction(MI);
855 break;
Jim Grosbach062749c2010-10-14 20:43:44 +0000856 case ARM::RRX:
Evan Cheng30f6f8f2008-11-14 20:09:11 +0000857 case ARM::MOVsrl_flag:
858 case ARM::MOVsra_flag:
859 emitPseudoMoveInstruction(MI);
860 break;
Evan Cheng467e6e82008-10-31 19:10:44 +0000861 }
862}
863
Bob Wilsona6fe21a2010-03-17 21:16:45 +0000864unsigned ARMCodeEmitter::getMachineSoRegOpValue(const MachineInstr &MI,
Evan Chengd1424c42008-09-12 22:45:55 +0000865 const TargetInstrDesc &TID,
Evan Cheng467e6e82008-10-31 19:10:44 +0000866 const MachineOperand &MO,
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000867 unsigned OpIdx) {
Evan Cheng467e6e82008-10-31 19:10:44 +0000868 unsigned Binary = getMachineOpValue(MI, MO);
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000869
870 const MachineOperand &MO1 = MI.getOperand(OpIdx + 1);
871 const MachineOperand &MO2 = MI.getOperand(OpIdx + 2);
872 ARM_AM::ShiftOpc SOpc = ARM_AM::getSORegShOp(MO2.getImm());
873
874 // Encode the shift opcode.
875 unsigned SBits = 0;
876 unsigned Rs = MO1.getReg();
877 if (Rs) {
878 // Set shift operand (bit[7:4]).
879 // LSL - 0001
880 // LSR - 0011
881 // ASR - 0101
882 // ROR - 0111
883 // RRX - 0110 and bit[11:8] clear.
884 switch (SOpc) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000885 default: llvm_unreachable("Unknown shift opc!");
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000886 case ARM_AM::lsl: SBits = 0x1; break;
887 case ARM_AM::lsr: SBits = 0x3; break;
888 case ARM_AM::asr: SBits = 0x5; break;
889 case ARM_AM::ror: SBits = 0x7; break;
890 case ARM_AM::rrx: SBits = 0x6; break;
891 }
892 } else {
893 // Set shift operand (bit[6:4]).
894 // LSL - 000
895 // LSR - 010
896 // ASR - 100
897 // ROR - 110
898 switch (SOpc) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000899 default: llvm_unreachable("Unknown shift opc!");
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000900 case ARM_AM::lsl: SBits = 0x0; break;
901 case ARM_AM::lsr: SBits = 0x2; break;
902 case ARM_AM::asr: SBits = 0x4; break;
903 case ARM_AM::ror: SBits = 0x6; break;
904 }
905 }
906 Binary |= SBits << 4;
907 if (SOpc == ARM_AM::rrx)
908 return Binary;
909
910 // Encode the shift operation Rs or shift_imm (except rrx).
911 if (Rs) {
912 // Encode Rs bit[11:8].
913 assert(ARM_AM::getSORegOffset(MO2.getImm()) == 0);
Jim Grosbach40e85fb2010-09-15 20:26:25 +0000914 return Binary | (getARMRegisterNumbering(Rs) << ARMII::RegRsShift);
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000915 }
916
917 // Encode shift_imm bit[11:7].
918 return Binary | ARM_AM::getSORegOffset(MO2.getImm()) << 7;
919}
920
Chris Lattner8d806872010-02-02 21:48:51 +0000921unsigned ARMCodeEmitter::getMachineSoImmOpValue(unsigned SoImm) {
Evan Chenge3a53c42009-07-08 21:03:57 +0000922 int SoImmVal = ARM_AM::getSOImmVal(SoImm);
923 assert(SoImmVal != -1 && "Not a valid so_imm value!");
924
Evan Cheng467e6e82008-10-31 19:10:44 +0000925 // Encode rotate_imm.
Evan Chenge3a53c42009-07-08 21:03:57 +0000926 unsigned Binary = (ARM_AM::getSOImmValRot((unsigned)SoImmVal) >> 1)
Evan Cheng49d66522008-11-06 22:15:19 +0000927 << ARMII::SoRotImmShift;
928
Evan Cheng467e6e82008-10-31 19:10:44 +0000929 // Encode immed_8.
Evan Chenge3a53c42009-07-08 21:03:57 +0000930 Binary |= ARM_AM::getSOImmValImm((unsigned)SoImmVal);
Evan Cheng467e6e82008-10-31 19:10:44 +0000931 return Binary;
932}
933
Chris Lattner8d806872010-02-02 21:48:51 +0000934unsigned ARMCodeEmitter::getAddrModeSBit(const MachineInstr &MI,
Bob Wilsona6fe21a2010-03-17 21:16:45 +0000935 const TargetInstrDesc &TID) const {
Evan Cheng5f23e9f2008-11-20 02:25:51 +0000936 for (unsigned i = MI.getNumOperands(), e = TID.getNumOperands(); i != e; --i){
Evan Chengd1424c42008-09-12 22:45:55 +0000937 const MachineOperand &MO = MI.getOperand(i-1);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000938 if (MO.isReg() && MO.isDef() && MO.getReg() == ARM::CPSR)
Evan Chengd1424c42008-09-12 22:45:55 +0000939 return 1 << ARMII::S_BitShift;
940 }
941 return 0;
942}
943
Bob Wilsona6fe21a2010-03-17 21:16:45 +0000944void ARMCodeEmitter::emitDataProcessingInstruction(const MachineInstr &MI,
Evan Cheng8467e242008-11-07 22:30:53 +0000945 unsigned ImplicitRd,
Evan Chengfd2adbf2008-11-05 23:22:34 +0000946 unsigned ImplicitRn) {
Evan Cheng81889d012008-11-05 18:35:52 +0000947 const TargetInstrDesc &TID = MI.getDesc();
Evan Cheng81889d012008-11-05 18:35:52 +0000948
949 // Part of binary is determined by TableGn.
950 unsigned Binary = getBinaryCodeForInstr(MI);
951
Jim Grosbachc084e842008-10-07 19:05:35 +0000952 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +0000953 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000954
Evan Chengd1424c42008-09-12 22:45:55 +0000955 // Encode S bit if MI modifies CPSR.
Jim Grosbach4d0549e2008-11-03 18:38:31 +0000956 Binary |= getAddrModeSBit(MI, TID);
Evan Chengd1424c42008-09-12 22:45:55 +0000957
Evan Cheng33fa89c6f2008-09-12 22:01:15 +0000958 // Encode register def if there is one.
Evan Chengd1424c42008-09-12 22:45:55 +0000959 unsigned NumDefs = TID.getNumDefs();
Evan Chengc5c74f32008-09-12 23:15:39 +0000960 unsigned OpIdx = 0;
Evan Cheng8467e242008-11-07 22:30:53 +0000961 if (NumDefs)
962 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
963 else if (ImplicitRd)
964 // Special handling for implicit use (e.g. PC).
Jim Grosbach40e85fb2010-09-15 20:26:25 +0000965 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
Evan Cheng3be5b722008-09-02 06:52:38 +0000966
Zonr Chang2da5aa12010-05-25 08:42:45 +0000967 if (TID.Opcode == ARM::MOVi16) {
968 // Get immediate from MI.
969 unsigned Lo16 = getMovi32Value(MI, MI.getOperand(OpIdx),
970 ARM::reloc_arm_movw);
971 // Encode imm which is the same as in emitMOVi32immInstruction().
972 Binary |= Lo16 & 0xFFF;
973 Binary |= ((Lo16 >> 12) & 0xF) << 16;
974 emitWordLE(Binary);
975 return;
976 } else if(TID.Opcode == ARM::MOVTi16) {
977 unsigned Hi16 = (getMovi32Value(MI, MI.getOperand(OpIdx),
978 ARM::reloc_arm_movt) >> 16);
979 Binary |= Hi16 & 0xFFF;
980 Binary |= ((Hi16 >> 12) & 0xF) << 16;
981 emitWordLE(Binary);
982 return;
Shih-wei Liaoc4376b92010-05-26 04:46:50 +0000983 } else if ((TID.Opcode == ARM::BFC) || (TID.Opcode == ARM::BFI)) {
Shih-wei Liaob6e0bc92010-05-26 00:25:05 +0000984 uint32_t v = ~MI.getOperand(2).getImm();
985 int32_t lsb = CountTrailingZeros_32(v);
986 int32_t msb = (32 - CountLeadingZeros_32(v)) - 1;
Shih-wei Liao0568ca02010-05-26 03:21:39 +0000987 // Instr{20-16} = msb, Instr{11-7} = lsb
Shih-wei Liaob6e0bc92010-05-26 00:25:05 +0000988 Binary |= (msb & 0x1F) << 16;
989 Binary |= (lsb & 0x1F) << 7;
990 emitWordLE(Binary);
991 return;
Shih-wei Liao0568ca02010-05-26 03:21:39 +0000992 } else if ((TID.Opcode == ARM::UBFX) || (TID.Opcode == ARM::SBFX)) {
993 // Encode Rn in Instr{0-3}
994 Binary |= getMachineOpValue(MI, OpIdx++);
995
996 uint32_t lsb = MI.getOperand(OpIdx++).getImm();
997 uint32_t widthm1 = MI.getOperand(OpIdx++).getImm() - 1;
998
999 // Instr{20-16} = widthm1, Instr{11-7} = lsb
1000 Binary |= (widthm1 & 0x1F) << 16;
1001 Binary |= (lsb & 0x1F) << 7;
1002 emitWordLE(Binary);
1003 return;
Zonr Chang2da5aa12010-05-25 08:42:45 +00001004 }
1005
Evan Cheng47b546d2008-11-06 08:47:38 +00001006 // If this is a two-address operand, skip it. e.g. MOVCCr operand 1.
1007 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1008 ++OpIdx;
1009
Jim Grosbach3dc0a3b2008-10-01 18:16:49 +00001010 // Encode first non-shifter register operand if there is one.
Evan Cheng81889d012008-11-05 18:35:52 +00001011 bool isUnary = TID.TSFlags & ARMII::UnaryDP;
1012 if (!isUnary) {
Evan Chengfd2adbf2008-11-05 23:22:34 +00001013 if (ImplicitRn)
1014 // Special handling for implicit use (e.g. PC).
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001015 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
Evan Cheng467e6e82008-10-31 19:10:44 +00001016 else {
1017 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRnShift;
1018 ++OpIdx;
1019 }
Evan Cheng3be5b722008-09-02 06:52:38 +00001020 }
1021
Evan Cheng33fa89c6f2008-09-12 22:01:15 +00001022 // Encode shifter operand.
Evan Cheng33fa89c6f2008-09-12 22:01:15 +00001023 const MachineOperand &MO = MI.getOperand(OpIdx);
Evan Cheng81889d012008-11-05 18:35:52 +00001024 if ((TID.TSFlags & ARMII::FormMask) == ARMII::DPSoRegFrm) {
Evan Cheng467e6e82008-10-31 19:10:44 +00001025 // Encode SoReg.
Evan Chengfd2adbf2008-11-05 23:22:34 +00001026 emitWordLE(Binary | getMachineSoRegOpValue(MI, TID, MO, OpIdx));
Evan Cheng81889d012008-11-05 18:35:52 +00001027 return;
1028 }
Evan Cheng467e6e82008-10-31 19:10:44 +00001029
Evan Cheng81889d012008-11-05 18:35:52 +00001030 if (MO.isReg()) {
Evan Cheng33fa89c6f2008-09-12 22:01:15 +00001031 // Encode register Rm.
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001032 emitWordLE(Binary | getARMRegisterNumbering(MO.getReg()));
Evan Cheng81889d012008-11-05 18:35:52 +00001033 return;
1034 }
Evan Cheng3be5b722008-09-02 06:52:38 +00001035
Evan Cheng33fa89c6f2008-09-12 22:01:15 +00001036 // Encode so_imm.
Evan Chenge3a53c42009-07-08 21:03:57 +00001037 Binary |= getMachineSoImmOpValue((unsigned)MO.getImm());
Evan Cheng81889d012008-11-05 18:35:52 +00001038
Evan Chengfd2adbf2008-11-05 23:22:34 +00001039 emitWordLE(Binary);
Evan Cheng3be5b722008-09-02 06:52:38 +00001040}
1041
Bob Wilsona6fe21a2010-03-17 21:16:45 +00001042void ARMCodeEmitter::emitLoadStoreInstruction(const MachineInstr &MI,
Evan Cheng7095cd22008-11-07 09:06:08 +00001043 unsigned ImplicitRd,
Evan Chengfd2adbf2008-11-05 23:22:34 +00001044 unsigned ImplicitRn) {
Evan Cheng077c8f82008-11-08 01:44:13 +00001045 const TargetInstrDesc &TID = MI.getDesc();
Evan Cheng2666f592008-11-13 07:34:59 +00001046 unsigned Form = TID.TSFlags & ARMII::FormMask;
1047 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
Evan Cheng077c8f82008-11-08 01:44:13 +00001048
Evan Cheng81889d012008-11-05 18:35:52 +00001049 // Part of binary is determined by TableGn.
1050 unsigned Binary = getBinaryCodeForInstr(MI);
1051
Jim Grosbach338de3e2010-10-27 23:12:14 +00001052 // If this is an LDRi12, STRi12 or LDRcp, nothing more needs be done.
1053 if (MI.getOpcode() == ARM::LDRi12 || MI.getOpcode() == ARM::LDRcp ||
1054 MI.getOpcode() == ARM::STRi12) {
Jim Grosbachba1c6cd2010-10-27 17:52:51 +00001055 emitWordLE(Binary);
1056 return;
1057 }
1058
Jim Grosbachc084e842008-10-07 19:05:35 +00001059 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +00001060 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Cheng933b3922008-09-18 07:28:19 +00001061
Evan Cheng7095cd22008-11-07 09:06:08 +00001062 unsigned OpIdx = 0;
Evan Cheng2666f592008-11-13 07:34:59 +00001063
1064 // Operand 0 of a pre- and post-indexed store is the address base
1065 // writeback. Skip it.
1066 bool Skipped = false;
1067 if (IsPrePost && Form == ARMII::StFrm) {
1068 ++OpIdx;
1069 Skipped = true;
1070 }
1071
1072 // Set first operand
Evan Cheng7095cd22008-11-07 09:06:08 +00001073 if (ImplicitRd)
1074 // Special handling for implicit use (e.g. PC).
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001075 Binary |= (getARMRegisterNumbering(ImplicitRd) << ARMII::RegRdShift);
Evan Cheng7095cd22008-11-07 09:06:08 +00001076 else
1077 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
Evan Cheng3be5b722008-09-02 06:52:38 +00001078
1079 // Set second operand
Evan Chengfd2adbf2008-11-05 23:22:34 +00001080 if (ImplicitRn)
1081 // Special handling for implicit use (e.g. PC).
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001082 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
Evan Cheng7095cd22008-11-07 09:06:08 +00001083 else
1084 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
Evan Cheng3be5b722008-09-02 06:52:38 +00001085
Evan Cheng077c8f82008-11-08 01:44:13 +00001086 // If this is a two-address operand, skip it. e.g. LDR_PRE.
Evan Cheng2666f592008-11-13 07:34:59 +00001087 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
Evan Cheng077c8f82008-11-08 01:44:13 +00001088 ++OpIdx;
1089
Evan Chengfd2adbf2008-11-05 23:22:34 +00001090 const MachineOperand &MO2 = MI.getOperand(OpIdx);
Evan Cheng47b546d2008-11-06 08:47:38 +00001091 unsigned AM2Opc = (ImplicitRn == ARM::PC)
Evan Chengfd2adbf2008-11-05 23:22:34 +00001092 ? 0 : MI.getOperand(OpIdx+1).getImm();
Evan Cheng3be5b722008-09-02 06:52:38 +00001093
Evan Cheng380482a2008-09-13 01:44:01 +00001094 // Set bit U(23) according to sign of immed value (positive or negative).
Evan Chengfd2adbf2008-11-05 23:22:34 +00001095 Binary |= ((ARM_AM::getAM2Op(AM2Opc) == ARM_AM::add ? 1 : 0) <<
Evan Cheng380482a2008-09-13 01:44:01 +00001096 ARMII::U_BitShift);
Evan Cheng3be5b722008-09-02 06:52:38 +00001097 if (!MO2.getReg()) { // is immediate
Evan Chengfd2adbf2008-11-05 23:22:34 +00001098 if (ARM_AM::getAM2Offset(AM2Opc))
Evan Cheng3be5b722008-09-02 06:52:38 +00001099 // Set the value of offset_12 field
Evan Chengfd2adbf2008-11-05 23:22:34 +00001100 Binary |= ARM_AM::getAM2Offset(AM2Opc);
1101 emitWordLE(Binary);
Evan Cheng81889d012008-11-05 18:35:52 +00001102 return;
Evan Cheng3be5b722008-09-02 06:52:38 +00001103 }
1104
Bill Wendling05819052010-10-20 22:44:54 +00001105 // Set bit I(25), because this is not in immediate encoding.
Evan Cheng3be5b722008-09-02 06:52:38 +00001106 Binary |= 1 << ARMII::I_BitShift;
1107 assert(TargetRegisterInfo::isPhysicalRegister(MO2.getReg()));
1108 // Set bit[3:0] to the corresponding Rm register
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001109 Binary |= getARMRegisterNumbering(MO2.getReg());
Evan Cheng3be5b722008-09-02 06:52:38 +00001110
Evan Cheng2836d912008-11-12 07:34:37 +00001111 // If this instr is in scaled register offset/index instruction, set
Evan Cheng3be5b722008-09-02 06:52:38 +00001112 // shift_immed(bit[11:7]) and shift(bit[6:5]) fields.
Evan Chengfd2adbf2008-11-05 23:22:34 +00001113 if (unsigned ShImm = ARM_AM::getAM2Offset(AM2Opc)) {
Evan Cheng2836d912008-11-12 07:34:37 +00001114 Binary |= getShiftOp(AM2Opc) << ARMII::ShiftImmShift; // shift
1115 Binary |= ShImm << ARMII::ShiftShift; // shift_immed
Evan Cheng3be5b722008-09-02 06:52:38 +00001116 }
1117
Evan Chengfd2adbf2008-11-05 23:22:34 +00001118 emitWordLE(Binary);
Evan Cheng3be5b722008-09-02 06:52:38 +00001119}
1120
Chris Lattner8d806872010-02-02 21:48:51 +00001121void ARMCodeEmitter::emitMiscLoadStoreInstruction(const MachineInstr &MI,
Bob Wilsona6fe21a2010-03-17 21:16:45 +00001122 unsigned ImplicitRn) {
Evan Cheng077c8f82008-11-08 01:44:13 +00001123 const TargetInstrDesc &TID = MI.getDesc();
Evan Cheng2666f592008-11-13 07:34:59 +00001124 unsigned Form = TID.TSFlags & ARMII::FormMask;
1125 bool IsPrePost = (TID.TSFlags & ARMII::IndexModeMask) != 0;
Evan Cheng077c8f82008-11-08 01:44:13 +00001126
Evan Cheng81889d012008-11-05 18:35:52 +00001127 // Part of binary is determined by TableGn.
1128 unsigned Binary = getBinaryCodeForInstr(MI);
1129
Jim Grosbachc084e842008-10-07 19:05:35 +00001130 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +00001131 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Cheng933b3922008-09-18 07:28:19 +00001132
Evan Cheng2666f592008-11-13 07:34:59 +00001133 unsigned OpIdx = 0;
1134
1135 // Operand 0 of a pre- and post-indexed store is the address base
1136 // writeback. Skip it.
1137 bool Skipped = false;
1138 if (IsPrePost && Form == ARMII::StMiscFrm) {
1139 ++OpIdx;
1140 Skipped = true;
1141 }
1142
Evan Cheng3be5b722008-09-02 06:52:38 +00001143 // Set first operand
Evan Cheng2666f592008-11-13 07:34:59 +00001144 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
Evan Cheng3be5b722008-09-02 06:52:38 +00001145
Evan Cheng1283c6a2009-06-15 08:28:29 +00001146 // Skip LDRD and STRD's second operand.
1147 if (TID.Opcode == ARM::LDRD || TID.Opcode == ARM::STRD)
1148 ++OpIdx;
1149
Evan Cheng3be5b722008-09-02 06:52:38 +00001150 // Set second operand
Evan Chengfd2adbf2008-11-05 23:22:34 +00001151 if (ImplicitRn)
1152 // Special handling for implicit use (e.g. PC).
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001153 Binary |= (getARMRegisterNumbering(ImplicitRn) << ARMII::RegRnShift);
Evan Cheng7095cd22008-11-07 09:06:08 +00001154 else
1155 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
Evan Cheng3be5b722008-09-02 06:52:38 +00001156
Evan Cheng077c8f82008-11-08 01:44:13 +00001157 // If this is a two-address operand, skip it. e.g. LDRH_POST.
Evan Cheng2666f592008-11-13 07:34:59 +00001158 if (!Skipped && TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
Evan Cheng077c8f82008-11-08 01:44:13 +00001159 ++OpIdx;
1160
Evan Chengfd2adbf2008-11-05 23:22:34 +00001161 const MachineOperand &MO2 = MI.getOperand(OpIdx);
Evan Cheng47b546d2008-11-06 08:47:38 +00001162 unsigned AM3Opc = (ImplicitRn == ARM::PC)
Evan Chengfd2adbf2008-11-05 23:22:34 +00001163 ? 0 : MI.getOperand(OpIdx+1).getImm();
Evan Cheng3be5b722008-09-02 06:52:38 +00001164
Evan Cheng380482a2008-09-13 01:44:01 +00001165 // Set bit U(23) according to sign of immed value (positive or negative)
Evan Chengfd2adbf2008-11-05 23:22:34 +00001166 Binary |= ((ARM_AM::getAM3Op(AM3Opc) == ARM_AM::add ? 1 : 0) <<
Evan Cheng3be5b722008-09-02 06:52:38 +00001167 ARMII::U_BitShift);
1168
1169 // If this instr is in register offset/index encoding, set bit[3:0]
1170 // to the corresponding Rm register.
1171 if (MO2.getReg()) {
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001172 Binary |= getARMRegisterNumbering(MO2.getReg());
Evan Chengfd2adbf2008-11-05 23:22:34 +00001173 emitWordLE(Binary);
Evan Cheng81889d012008-11-05 18:35:52 +00001174 return;
Evan Cheng3be5b722008-09-02 06:52:38 +00001175 }
1176
Evan Cheng47b546d2008-11-06 08:47:38 +00001177 // This instr is in immediate offset/index encoding, set bit 22 to 1.
Evan Cheng49d66522008-11-06 22:15:19 +00001178 Binary |= 1 << ARMII::AM3_I_BitShift;
Evan Chengfd2adbf2008-11-05 23:22:34 +00001179 if (unsigned ImmOffs = ARM_AM::getAM3Offset(AM3Opc)) {
Evan Cheng3be5b722008-09-02 06:52:38 +00001180 // Set operands
Evan Cheng2836d912008-11-12 07:34:37 +00001181 Binary |= (ImmOffs >> 4) << ARMII::ImmHiShift; // immedH
1182 Binary |= (ImmOffs & 0xF); // immedL
Evan Cheng3be5b722008-09-02 06:52:38 +00001183 }
1184
Evan Chengfd2adbf2008-11-05 23:22:34 +00001185 emitWordLE(Binary);
Evan Cheng3be5b722008-09-02 06:52:38 +00001186}
1187
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001188static unsigned getAddrModeUPBits(unsigned Mode) {
1189 unsigned Binary = 0;
Evan Cheng3be5b722008-09-02 06:52:38 +00001190
1191 // Set addressing mode by modifying bits U(23) and P(24)
1192 // IA - Increment after - bit U = 1 and bit P = 0
1193 // IB - Increment before - bit U = 1 and bit P = 1
1194 // DA - Decrement after - bit U = 0 and bit P = 0
1195 // DB - Decrement before - bit U = 0 and bit P = 1
Evan Cheng3be5b722008-09-02 06:52:38 +00001196 switch (Mode) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001197 default: llvm_unreachable("Unknown addressing sub-mode!");
Evan Cheng71140342009-09-09 23:55:03 +00001198 case ARM_AM::da: break;
Evan Cheng49d66522008-11-06 22:15:19 +00001199 case ARM_AM::db: Binary |= 0x1 << ARMII::P_BitShift; break;
1200 case ARM_AM::ia: Binary |= 0x1 << ARMII::U_BitShift; break;
1201 case ARM_AM::ib: Binary |= 0x3 << ARMII::U_BitShift; break;
Evan Cheng3be5b722008-09-02 06:52:38 +00001202 }
1203
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001204 return Binary;
1205}
1206
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001207void ARMCodeEmitter::emitLoadStoreMultipleInstruction(const MachineInstr &MI) {
1208 const TargetInstrDesc &TID = MI.getDesc();
1209 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1210
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001211 // Part of binary is determined by TableGn.
1212 unsigned Binary = getBinaryCodeForInstr(MI);
1213
1214 // Set the conditional execution predicate
1215 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1216
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001217 // Skip operand 0 of an instruction with base register update.
1218 unsigned OpIdx = 0;
1219 if (IsUpdating)
1220 ++OpIdx;
1221
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001222 // Set base address operand
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001223 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001224
1225 // Set addressing mode by modifying bits U(23) and P(24)
Bill Wendlingb100f912010-11-17 05:31:09 +00001226 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1227 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001228
Evan Cheng3be5b722008-09-02 06:52:38 +00001229 // Set bit W(21)
Bob Wilsond6243b42010-03-16 17:46:45 +00001230 if (IsUpdating)
Evan Cheng49d66522008-11-06 22:15:19 +00001231 Binary |= 0x1 << ARMII::W_BitShift;
Evan Cheng3be5b722008-09-02 06:52:38 +00001232
1233 // Set registers
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001234 for (unsigned i = OpIdx+2, e = MI.getNumOperands(); i != e; ++i) {
Evan Cheng3be5b722008-09-02 06:52:38 +00001235 const MachineOperand &MO = MI.getOperand(i);
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001236 if (!MO.isReg() || MO.isImplicit())
1237 break;
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001238 unsigned RegNum = getARMRegisterNumbering(MO.getReg());
Evan Cheng3be5b722008-09-02 06:52:38 +00001239 assert(TargetRegisterInfo::isPhysicalRegister(MO.getReg()) &&
1240 RegNum < 16);
1241 Binary |= 0x1 << RegNum;
1242 }
1243
Evan Chengfd2adbf2008-11-05 23:22:34 +00001244 emitWordLE(Binary);
Evan Cheng3be5b722008-09-02 06:52:38 +00001245}
1246
Chris Lattner8d806872010-02-02 21:48:51 +00001247void ARMCodeEmitter::emitMulFrmInstruction(const MachineInstr &MI) {
Evan Cheng81889d012008-11-05 18:35:52 +00001248 const TargetInstrDesc &TID = MI.getDesc();
1249
1250 // Part of binary is determined by TableGn.
1251 unsigned Binary = getBinaryCodeForInstr(MI);
1252
Jim Grosbach4d0549e2008-11-03 18:38:31 +00001253 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +00001254 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Jim Grosbach4d0549e2008-11-03 18:38:31 +00001255
1256 // Encode S bit if MI modifies CPSR.
1257 Binary |= getAddrModeSBit(MI, TID);
1258
1259 // 32x32->64bit operations have two destination registers. The number
1260 // of register definitions will tell us if that's what we're dealing with.
Evan Cheng49d66522008-11-06 22:15:19 +00001261 unsigned OpIdx = 0;
Jim Grosbach4d0549e2008-11-03 18:38:31 +00001262 if (TID.getNumDefs() == 2)
1263 Binary |= getMachineOpValue (MI, OpIdx++) << ARMII::RegRdLoShift;
1264
1265 // Encode Rd
1266 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdHiShift;
1267
1268 // Encode Rm
1269 Binary |= getMachineOpValue(MI, OpIdx++);
1270
1271 // Encode Rs
1272 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRsShift;
1273
Evan Cheng2686c8f2008-11-06 01:21:28 +00001274 // Many multiple instructions (e.g. MLA) have three src operands. Encode
1275 // it as Rn (for multiply, that's in the same offset as RdLo.
Evan Cheng49d66522008-11-06 22:15:19 +00001276 if (TID.getNumOperands() > OpIdx &&
1277 !TID.OpInfo[OpIdx].isPredicate() &&
1278 !TID.OpInfo[OpIdx].isOptionalDef())
1279 Binary |= getMachineOpValue(MI, OpIdx) << ARMII::RegRdLoShift;
1280
1281 emitWordLE(Binary);
1282}
1283
Chris Lattner8d806872010-02-02 21:48:51 +00001284void ARMCodeEmitter::emitExtendInstruction(const MachineInstr &MI) {
Evan Cheng49d66522008-11-06 22:15:19 +00001285 const TargetInstrDesc &TID = MI.getDesc();
1286
1287 // Part of binary is determined by TableGn.
1288 unsigned Binary = getBinaryCodeForInstr(MI);
1289
1290 // Set the conditional execution predicate
1291 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1292
1293 unsigned OpIdx = 0;
1294
1295 // Encode Rd
1296 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1297
1298 const MachineOperand &MO1 = MI.getOperand(OpIdx++);
1299 const MachineOperand &MO2 = MI.getOperand(OpIdx);
1300 if (MO2.isReg()) {
1301 // Two register operand form.
1302 // Encode Rn.
1303 Binary |= getMachineOpValue(MI, MO1) << ARMII::RegRnShift;
1304
1305 // Encode Rm.
1306 Binary |= getMachineOpValue(MI, MO2);
1307 ++OpIdx;
1308 } else {
1309 Binary |= getMachineOpValue(MI, MO1);
1310 }
1311
1312 // Encode rot imm (0, 8, 16, or 24) if it has a rotate immediate operand.
1313 if (MI.getOperand(OpIdx).isImm() &&
1314 !TID.OpInfo[OpIdx].isPredicate() &&
1315 !TID.OpInfo[OpIdx].isOptionalDef())
1316 Binary |= (getMachineOpValue(MI, OpIdx) / 8) << ARMII::ExtRotImmShift;
Evan Cheng2686c8f2008-11-06 01:21:28 +00001317
Evan Chengfd2adbf2008-11-05 23:22:34 +00001318 emitWordLE(Binary);
Jim Grosbach4d0549e2008-11-03 18:38:31 +00001319}
1320
Chris Lattner8d806872010-02-02 21:48:51 +00001321void ARMCodeEmitter::emitMiscArithInstruction(const MachineInstr &MI) {
Evan Cheng98dc53e2008-11-07 01:41:35 +00001322 const TargetInstrDesc &TID = MI.getDesc();
1323
1324 // Part of binary is determined by TableGn.
1325 unsigned Binary = getBinaryCodeForInstr(MI);
1326
1327 // Set the conditional execution predicate
1328 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1329
1330 unsigned OpIdx = 0;
1331
1332 // Encode Rd
1333 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRdShift;
1334
1335 const MachineOperand &MO = MI.getOperand(OpIdx++);
1336 if (OpIdx == TID.getNumOperands() ||
1337 TID.OpInfo[OpIdx].isPredicate() ||
1338 TID.OpInfo[OpIdx].isOptionalDef()) {
1339 // Encode Rm and it's done.
1340 Binary |= getMachineOpValue(MI, MO);
1341 emitWordLE(Binary);
1342 return;
1343 }
1344
1345 // Encode Rn.
1346 Binary |= getMachineOpValue(MI, MO) << ARMII::RegRnShift;
1347
1348 // Encode Rm.
1349 Binary |= getMachineOpValue(MI, OpIdx++);
1350
1351 // Encode shift_imm.
1352 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
Bob Wilson942b10f2010-08-17 17:23:19 +00001353 if (TID.Opcode == ARM::PKHTB) {
1354 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1355 if (ShiftAmt == 32)
1356 ShiftAmt = 0;
1357 }
Evan Cheng98dc53e2008-11-07 01:41:35 +00001358 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1359 Binary |= ShiftAmt << ARMII::ShiftShift;
Jim Grosbachf24f9d92009-08-11 15:33:49 +00001360
Evan Cheng98dc53e2008-11-07 01:41:35 +00001361 emitWordLE(Binary);
1362}
1363
Bob Wilson96649842010-08-11 00:01:18 +00001364void ARMCodeEmitter::emitSaturateInstruction(const MachineInstr &MI) {
1365 const TargetInstrDesc &TID = MI.getDesc();
1366
1367 // Part of binary is determined by TableGen.
1368 unsigned Binary = getBinaryCodeForInstr(MI);
1369
1370 // Set the conditional execution predicate
1371 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1372
1373 // Encode Rd
1374 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift;
1375
1376 // Encode saturate bit position.
1377 unsigned Pos = MI.getOperand(1).getImm();
Bob Wilsonadd513112010-08-11 23:10:46 +00001378 if (TID.Opcode == ARM::SSAT || TID.Opcode == ARM::SSAT16)
Bob Wilson96649842010-08-11 00:01:18 +00001379 Pos -= 1;
1380 assert((Pos < 16 || (Pos < 32 &&
1381 TID.Opcode != ARM::SSAT16 &&
1382 TID.Opcode != ARM::USAT16)) &&
1383 "saturate bit position out of range");
1384 Binary |= Pos << 16;
1385
1386 // Encode Rm
1387 Binary |= getMachineOpValue(MI, 2);
1388
1389 // Encode shift_imm.
1390 if (TID.getNumOperands() == 4) {
Bob Wilsonadd513112010-08-11 23:10:46 +00001391 unsigned ShiftOp = MI.getOperand(3).getImm();
1392 ARM_AM::ShiftOpc Opc = ARM_AM::getSORegShOp(ShiftOp);
1393 if (Opc == ARM_AM::asr)
1394 Binary |= (1 << 6);
Bob Wilson96649842010-08-11 00:01:18 +00001395 unsigned ShiftAmt = MI.getOperand(3).getImm();
Bob Wilsonadd513112010-08-11 23:10:46 +00001396 if (ShiftAmt == 32 && Opc == ARM_AM::asr)
Bob Wilson96649842010-08-11 00:01:18 +00001397 ShiftAmt = 0;
1398 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
1399 Binary |= ShiftAmt << ARMII::ShiftShift;
1400 }
1401
1402 emitWordLE(Binary);
1403}
1404
Chris Lattner8d806872010-02-02 21:48:51 +00001405void ARMCodeEmitter::emitBranchInstruction(const MachineInstr &MI) {
Evan Cheng81889d012008-11-05 18:35:52 +00001406 const TargetInstrDesc &TID = MI.getDesc();
1407
Torok Edwinfb8d6d52009-07-08 20:53:28 +00001408 if (TID.Opcode == ARM::TPsoft) {
Torok Edwinfbcc6632009-07-14 16:55:14 +00001409 llvm_unreachable("ARM::TPsoft FIXME"); // FIXME
Torok Edwinfb8d6d52009-07-08 20:53:28 +00001410 }
Evan Chengaa03cd32008-11-06 17:48:05 +00001411
Evan Cheng3be5b722008-09-02 06:52:38 +00001412 // Part of binary is determined by TableGn.
1413 unsigned Binary = getBinaryCodeForInstr(MI);
1414
Evan Cheng81889d012008-11-05 18:35:52 +00001415 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +00001416 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Cheng81889d012008-11-05 18:35:52 +00001417
1418 // Set signed_immed_24 field
1419 Binary |= getMachineOpValue(MI, 0);
1420
Evan Chengfd2adbf2008-11-05 23:22:34 +00001421 emitWordLE(Binary);
Evan Cheng81889d012008-11-05 18:35:52 +00001422}
1423
Chris Lattner8d806872010-02-02 21:48:51 +00001424void ARMCodeEmitter::emitInlineJumpTable(unsigned JTIndex) {
Evan Cheng7095cd22008-11-07 09:06:08 +00001425 // Remember the base address of the inline jump table.
Evan Cheng0b773192008-12-10 02:32:19 +00001426 uintptr_t JTBase = MCE.getCurrentPCValue();
Evan Cheng8467e242008-11-07 22:30:53 +00001427 JTI->addJumpTableBaseAddr(JTIndex, JTBase);
Chris Lattneraf29ea62009-08-23 06:49:22 +00001428 DEBUG(errs() << " ** Jump Table #" << JTIndex << " @ " << (void*)JTBase
1429 << '\n');
Evan Cheng7095cd22008-11-07 09:06:08 +00001430
1431 // Now emit the jump table entries.
1432 const std::vector<MachineBasicBlock*> &MBBs = (*MJTEs)[JTIndex].MBBs;
1433 for (unsigned i = 0, e = MBBs.size(); i != e; ++i) {
1434 if (IsPIC)
1435 // DestBB address - JT base.
Evan Cheng8467e242008-11-07 22:30:53 +00001436 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_pic_jt, JTBase);
Evan Cheng7095cd22008-11-07 09:06:08 +00001437 else
1438 // Absolute DestBB address.
1439 emitMachineBasicBlock(MBBs[i], ARM::reloc_arm_absolute);
1440 emitWordLE(0);
1441 }
1442}
1443
Chris Lattner8d806872010-02-02 21:48:51 +00001444void ARMCodeEmitter::emitMiscBranchInstruction(const MachineInstr &MI) {
Evan Cheng81889d012008-11-05 18:35:52 +00001445 const TargetInstrDesc &TID = MI.getDesc();
Evan Cheng81889d012008-11-05 18:35:52 +00001446
Evan Cheng8467e242008-11-07 22:30:53 +00001447 // Handle jump tables.
Evan Chengf2972562009-07-25 00:13:11 +00001448 if (TID.Opcode == ARM::BR_JTr || TID.Opcode == ARM::BR_JTadd) {
Evan Cheng8467e242008-11-07 22:30:53 +00001449 // First emit a ldr pc, [] instruction.
1450 emitDataProcessingInstruction(MI, ARM::PC);
1451
1452 // Then emit the inline jump table.
Evan Chengb61e3a82009-07-08 00:05:05 +00001453 unsigned JTIndex =
Evan Chengf2972562009-07-25 00:13:11 +00001454 (TID.Opcode == ARM::BR_JTr)
Evan Cheng8467e242008-11-07 22:30:53 +00001455 ? MI.getOperand(1).getIndex() : MI.getOperand(2).getIndex();
1456 emitInlineJumpTable(JTIndex);
1457 return;
Evan Chengf2972562009-07-25 00:13:11 +00001458 } else if (TID.Opcode == ARM::BR_JTm) {
Evan Cheng7095cd22008-11-07 09:06:08 +00001459 // First emit a ldr pc, [] instruction.
1460 emitLoadStoreInstruction(MI, ARM::PC);
1461
1462 // Then emit the inline jump table.
Evan Cheng8467e242008-11-07 22:30:53 +00001463 emitInlineJumpTable(MI.getOperand(3).getIndex());
Evan Cheng7095cd22008-11-07 09:06:08 +00001464 return;
1465 }
1466
Evan Cheng81889d012008-11-05 18:35:52 +00001467 // Part of binary is determined by TableGn.
1468 unsigned Binary = getBinaryCodeForInstr(MI);
1469
1470 // Set the conditional execution predicate
Evan Cheng49d66522008-11-06 22:15:19 +00001471 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
Evan Cheng81889d012008-11-05 18:35:52 +00001472
Anton Korobeynikovbf16a172010-03-06 19:39:36 +00001473 if (TID.Opcode == ARM::BX_RET || TID.Opcode == ARM::MOVPCLR)
Evan Cheng81889d012008-11-05 18:35:52 +00001474 // The return register is LR.
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001475 Binary |= getARMRegisterNumbering(ARM::LR);
Jim Grosbachf24f9d92009-08-11 15:33:49 +00001476 else
Evan Cheng81889d012008-11-05 18:35:52 +00001477 // otherwise, set the return register
1478 Binary |= getMachineOpValue(MI, 0);
1479
Evan Chengfd2adbf2008-11-05 23:22:34 +00001480 emitWordLE(Binary);
Evan Cheng9546a5c2007-07-05 21:15:40 +00001481}
Evan Cheng3be5b722008-09-02 06:52:38 +00001482
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001483static unsigned encodeVFPRd(const MachineInstr &MI, unsigned OpIdx) {
Evan Chenga0e2f262008-11-12 02:19:38 +00001484 unsigned RegD = MI.getOperand(OpIdx).getReg();
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001485 unsigned Binary = 0;
Jim Grosbach789ca9a2010-09-15 19:44:57 +00001486 bool isSPVFP = ARM::SPRRegisterClass->contains(RegD);
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001487 RegD = getARMRegisterNumbering(RegD);
Evan Chenga0e2f262008-11-12 02:19:38 +00001488 if (!isSPVFP)
1489 Binary |= RegD << ARMII::RegRdShift;
1490 else {
1491 Binary |= ((RegD & 0x1E) >> 1) << ARMII::RegRdShift;
1492 Binary |= (RegD & 0x01) << ARMII::D_BitShift;
1493 }
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001494 return Binary;
1495}
Evan Cheng38c9a142008-11-11 19:40:26 +00001496
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001497static unsigned encodeVFPRn(const MachineInstr &MI, unsigned OpIdx) {
Evan Chenga0e2f262008-11-12 02:19:38 +00001498 unsigned RegN = MI.getOperand(OpIdx).getReg();
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001499 unsigned Binary = 0;
Jim Grosbach789ca9a2010-09-15 19:44:57 +00001500 bool isSPVFP = ARM::SPRRegisterClass->contains(RegN);
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001501 RegN = getARMRegisterNumbering(RegN);
Evan Chenga0e2f262008-11-12 02:19:38 +00001502 if (!isSPVFP)
1503 Binary |= RegN << ARMII::RegRnShift;
1504 else {
1505 Binary |= ((RegN & 0x1E) >> 1) << ARMII::RegRnShift;
1506 Binary |= (RegN & 0x01) << ARMII::N_BitShift;
1507 }
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001508 return Binary;
1509}
Evan Chenga0e2f262008-11-12 02:19:38 +00001510
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001511static unsigned encodeVFPRm(const MachineInstr &MI, unsigned OpIdx) {
1512 unsigned RegM = MI.getOperand(OpIdx).getReg();
1513 unsigned Binary = 0;
Jim Grosbach789ca9a2010-09-15 19:44:57 +00001514 bool isSPVFP = ARM::SPRRegisterClass->contains(RegM);
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001515 RegM = getARMRegisterNumbering(RegM);
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001516 if (!isSPVFP)
1517 Binary |= RegM;
1518 else {
1519 Binary |= ((RegM & 0x1E) >> 1);
1520 Binary |= (RegM & 0x01) << ARMII::M_BitShift;
Evan Cheng38c9a142008-11-11 19:40:26 +00001521 }
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001522 return Binary;
1523}
1524
Chris Lattner8d806872010-02-02 21:48:51 +00001525void ARMCodeEmitter::emitVFPArithInstruction(const MachineInstr &MI) {
Evan Chengaf644b52008-11-12 07:18:38 +00001526 const TargetInstrDesc &TID = MI.getDesc();
1527
1528 // Part of binary is determined by TableGn.
1529 unsigned Binary = getBinaryCodeForInstr(MI);
1530
1531 // Set the conditional execution predicate
1532 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1533
1534 unsigned OpIdx = 0;
1535 assert((Binary & ARMII::D_BitShift) == 0 &&
1536 (Binary & ARMII::N_BitShift) == 0 &&
1537 (Binary & ARMII::M_BitShift) == 0 && "VFP encoding bug!");
1538
1539 // Encode Dd / Sd.
1540 Binary |= encodeVFPRd(MI, OpIdx++);
1541
1542 // If this is a two-address operand, skip it, e.g. FMACD.
1543 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1544 ++OpIdx;
1545
1546 // Encode Dn / Sn.
1547 if ((TID.TSFlags & ARMII::FormMask) == ARMII::VFPBinaryFrm)
Evan Cheng052f20d2008-11-12 08:14:21 +00001548 Binary |= encodeVFPRn(MI, OpIdx++);
Evan Chengaf644b52008-11-12 07:18:38 +00001549
1550 if (OpIdx == TID.getNumOperands() ||
1551 TID.OpInfo[OpIdx].isPredicate() ||
1552 TID.OpInfo[OpIdx].isOptionalDef()) {
1553 // FCMPEZD etc. has only one operand.
1554 emitWordLE(Binary);
1555 return;
1556 }
1557
1558 // Encode Dm / Sm.
1559 Binary |= encodeVFPRm(MI, OpIdx);
Jim Grosbachf24f9d92009-08-11 15:33:49 +00001560
Evan Chengaf644b52008-11-12 07:18:38 +00001561 emitWordLE(Binary);
1562}
1563
Bob Wilsona6fe21a2010-03-17 21:16:45 +00001564void ARMCodeEmitter::emitVFPConversionInstruction(const MachineInstr &MI) {
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001565 const TargetInstrDesc &TID = MI.getDesc();
1566 unsigned Form = TID.TSFlags & ARMII::FormMask;
1567
1568 // Part of binary is determined by TableGn.
1569 unsigned Binary = getBinaryCodeForInstr(MI);
1570
1571 // Set the conditional execution predicate
1572 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1573
1574 switch (Form) {
1575 default: break;
1576 case ARMII::VFPConv1Frm:
1577 case ARMII::VFPConv2Frm:
1578 case ARMII::VFPConv3Frm:
1579 // Encode Dd / Sd.
1580 Binary |= encodeVFPRd(MI, 0);
1581 break;
1582 case ARMII::VFPConv4Frm:
1583 // Encode Dn / Sn.
1584 Binary |= encodeVFPRn(MI, 0);
1585 break;
1586 case ARMII::VFPConv5Frm:
1587 // Encode Dm / Sm.
1588 Binary |= encodeVFPRm(MI, 0);
1589 break;
1590 }
1591
1592 switch (Form) {
1593 default: break;
1594 case ARMII::VFPConv1Frm:
1595 // Encode Dm / Sm.
1596 Binary |= encodeVFPRm(MI, 1);
Evan Cheng4af89f72008-11-13 07:46:59 +00001597 break;
Evan Cheng4b6c7ef2008-11-12 06:41:41 +00001598 case ARMII::VFPConv2Frm:
1599 case ARMII::VFPConv3Frm:
1600 // Encode Dn / Sn.
1601 Binary |= encodeVFPRn(MI, 1);
1602 break;
1603 case ARMII::VFPConv4Frm:
1604 case ARMII::VFPConv5Frm:
1605 // Encode Dd / Sd.
1606 Binary |= encodeVFPRd(MI, 1);
1607 break;
1608 }
1609
1610 if (Form == ARMII::VFPConv5Frm)
1611 // Encode Dn / Sn.
1612 Binary |= encodeVFPRn(MI, 2);
1613 else if (Form == ARMII::VFPConv3Frm)
1614 // Encode Dm / Sm.
1615 Binary |= encodeVFPRm(MI, 2);
Evan Cheng38c9a142008-11-11 19:40:26 +00001616
1617 emitWordLE(Binary);
1618}
1619
Chris Lattner8d806872010-02-02 21:48:51 +00001620void ARMCodeEmitter::emitVFPLoadStoreInstruction(const MachineInstr &MI) {
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001621 // Part of binary is determined by TableGn.
1622 unsigned Binary = getBinaryCodeForInstr(MI);
1623
1624 // Set the conditional execution predicate
1625 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1626
1627 unsigned OpIdx = 0;
1628
1629 // Encode Dd / Sd.
Evan Chengaf644b52008-11-12 07:18:38 +00001630 Binary |= encodeVFPRd(MI, OpIdx++);
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001631
1632 // Encode address base.
1633 const MachineOperand &Base = MI.getOperand(OpIdx++);
1634 Binary |= getMachineOpValue(MI, Base) << ARMII::RegRnShift;
1635
1636 // If there is a non-zero immediate offset, encode it.
1637 if (Base.isReg()) {
1638 const MachineOperand &Offset = MI.getOperand(OpIdx);
1639 if (unsigned ImmOffs = ARM_AM::getAM5Offset(Offset.getImm())) {
1640 if (ARM_AM::getAM5Op(Offset.getImm()) == ARM_AM::add)
1641 Binary |= 1 << ARMII::U_BitShift;
Evan Cheng45d030a2008-11-12 08:21:12 +00001642 Binary |= ImmOffs;
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001643 emitWordLE(Binary);
1644 return;
1645 }
1646 }
1647
1648 // If immediate offset is omitted, default to +0.
1649 Binary |= 1 << ARMII::U_BitShift;
1650
1651 emitWordLE(Binary);
1652}
1653
Bob Wilsona6fe21a2010-03-17 21:16:45 +00001654void
1655ARMCodeEmitter::emitVFPLoadStoreMultipleInstruction(const MachineInstr &MI) {
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001656 const TargetInstrDesc &TID = MI.getDesc();
1657 bool IsUpdating = (TID.TSFlags & ARMII::IndexModeMask) != 0;
1658
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001659 // Part of binary is determined by TableGn.
1660 unsigned Binary = getBinaryCodeForInstr(MI);
1661
1662 // Set the conditional execution predicate
1663 Binary |= II->getPredicate(&MI) << ARMII::CondShift;
1664
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001665 // Skip operand 0 of an instruction with base register update.
1666 unsigned OpIdx = 0;
1667 if (IsUpdating)
1668 ++OpIdx;
1669
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001670 // Set base address operand
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001671 Binary |= getMachineOpValue(MI, OpIdx++) << ARMII::RegRnShift;
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001672
1673 // Set addressing mode by modifying bits U(23) and P(24)
Bill Wendlingb100f912010-11-17 05:31:09 +00001674 ARM_AM::AMSubMode Mode = ARM_AM::getLoadStoreMultipleSubMode(MI.getOpcode());
1675 Binary |= getAddrModeUPBits(ARM_AM::getAM4SubMode(Mode));
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001676
1677 // Set bit W(21)
Bob Wilson466d1e32010-03-16 18:38:09 +00001678 if (IsUpdating)
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001679 Binary |= 0x1 << ARMII::W_BitShift;
1680
1681 // First register is encoded in Dd.
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001682 Binary |= encodeVFPRd(MI, OpIdx+2);
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001683
Bob Wilson13ce07f2010-08-27 23:18:17 +00001684 // Count the number of registers.
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001685 unsigned NumRegs = 1;
Bob Wilsonf1e8f7f2010-03-13 07:34:35 +00001686 for (unsigned i = OpIdx+3, e = MI.getNumOperands(); i != e; ++i) {
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001687 const MachineOperand &MO = MI.getOperand(i);
1688 if (!MO.isReg() || MO.isImplicit())
1689 break;
1690 ++NumRegs;
1691 }
Shih-wei Liaoe22abfa2010-05-26 00:02:28 +00001692 // Bit 8 will be set if <list> is consecutive 64-bit registers (e.g., D0)
1693 // Otherwise, it will be 0, in the case of 32-bit registers.
1694 if(Binary & 0x100)
1695 Binary |= NumRegs * 2;
1696 else
1697 Binary |= NumRegs;
Evan Cheng8cbbcb12008-11-11 21:48:44 +00001698
1699 emitWordLE(Binary);
1700}
1701
Bob Wilson6eae5202010-06-11 21:34:50 +00001702static unsigned encodeNEONRd(const MachineInstr &MI, unsigned OpIdx) {
1703 unsigned RegD = MI.getOperand(OpIdx).getReg();
1704 unsigned Binary = 0;
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001705 RegD = getARMRegisterNumbering(RegD);
Bob Wilson6eae5202010-06-11 21:34:50 +00001706 Binary |= (RegD & 0xf) << ARMII::RegRdShift;
1707 Binary |= ((RegD >> 4) & 1) << ARMII::D_BitShift;
1708 return Binary;
1709}
1710
Bob Wilson2530ca02010-06-25 22:40:46 +00001711static unsigned encodeNEONRn(const MachineInstr &MI, unsigned OpIdx) {
1712 unsigned RegN = MI.getOperand(OpIdx).getReg();
1713 unsigned Binary = 0;
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001714 RegN = getARMRegisterNumbering(RegN);
Bob Wilson2530ca02010-06-25 22:40:46 +00001715 Binary |= (RegN & 0xf) << ARMII::RegRnShift;
1716 Binary |= ((RegN >> 4) & 1) << ARMII::N_BitShift;
1717 return Binary;
1718}
1719
Bob Wilsone70c8b12010-06-25 21:17:19 +00001720static unsigned encodeNEONRm(const MachineInstr &MI, unsigned OpIdx) {
1721 unsigned RegM = MI.getOperand(OpIdx).getReg();
1722 unsigned Binary = 0;
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001723 RegM = getARMRegisterNumbering(RegM);
Bob Wilsone70c8b12010-06-25 21:17:19 +00001724 Binary |= (RegM & 0xf);
1725 Binary |= ((RegM >> 4) & 1) << ARMII::M_BitShift;
1726 return Binary;
1727}
1728
Bob Wilson584387d2010-06-28 21:12:19 +00001729/// convertNEONDataProcToThumb - Convert the ARM mode encoding for a NEON
1730/// data-processing instruction to the corresponding Thumb encoding.
1731static unsigned convertNEONDataProcToThumb(unsigned Binary) {
1732 assert((Binary & 0xfe000000) == 0xf2000000 &&
1733 "not an ARM NEON data-processing instruction");
1734 unsigned UBit = (Binary >> 24) & 1;
1735 return 0xef000000 | (UBit << 28) | (Binary & 0xffffff);
1736}
1737
Bob Wilsonab0819e2010-06-29 17:34:07 +00001738void ARMCodeEmitter::emitNEONLaneInstruction(const MachineInstr &MI) {
Bob Wilson0248da92010-06-26 04:07:15 +00001739 unsigned Binary = getBinaryCodeForInstr(MI);
1740
Bob Wilsonab0819e2010-06-29 17:34:07 +00001741 unsigned RegTOpIdx, RegNOpIdx, LnOpIdx;
1742 const TargetInstrDesc &TID = MI.getDesc();
1743 if ((TID.TSFlags & ARMII::FormMask) == ARMII::NGetLnFrm) {
1744 RegTOpIdx = 0;
1745 RegNOpIdx = 1;
1746 LnOpIdx = 2;
1747 } else { // ARMII::NSetLnFrm
1748 RegTOpIdx = 2;
1749 RegNOpIdx = 0;
1750 LnOpIdx = 3;
1751 }
1752
Bob Wilson0248da92010-06-26 04:07:15 +00001753 // Set the conditional execution predicate
Bob Wilson3d12ff72010-06-29 00:26:13 +00001754 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
Bob Wilson0248da92010-06-26 04:07:15 +00001755
Bob Wilsonab0819e2010-06-29 17:34:07 +00001756 unsigned RegT = MI.getOperand(RegTOpIdx).getReg();
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001757 RegT = getARMRegisterNumbering(RegT);
Bob Wilson0248da92010-06-26 04:07:15 +00001758 Binary |= (RegT << ARMII::RegRdShift);
Bob Wilsonab0819e2010-06-29 17:34:07 +00001759 Binary |= encodeNEONRn(MI, RegNOpIdx);
Bob Wilson0248da92010-06-26 04:07:15 +00001760
1761 unsigned LaneShift;
1762 if ((Binary & (1 << 22)) != 0)
1763 LaneShift = 0; // 8-bit elements
1764 else if ((Binary & (1 << 5)) != 0)
1765 LaneShift = 1; // 16-bit elements
1766 else
1767 LaneShift = 2; // 32-bit elements
1768
Bob Wilsonab0819e2010-06-29 17:34:07 +00001769 unsigned Lane = MI.getOperand(LnOpIdx).getImm() << LaneShift;
Bob Wilson0248da92010-06-26 04:07:15 +00001770 unsigned Opc1 = Lane >> 2;
1771 unsigned Opc2 = Lane & 3;
1772 assert((Opc1 & 3) == 0 && "out-of-range lane number operand");
1773 Binary |= (Opc1 << 21);
1774 Binary |= (Opc2 << 5);
1775
1776 emitWordLE(Binary);
1777}
1778
Bob Wilsonbe157b02010-06-29 20:13:29 +00001779void ARMCodeEmitter::emitNEONDupInstruction(const MachineInstr &MI) {
1780 unsigned Binary = getBinaryCodeForInstr(MI);
1781
1782 // Set the conditional execution predicate
1783 Binary |= (IsThumb ? ARMCC::AL : II->getPredicate(&MI)) << ARMII::CondShift;
1784
1785 unsigned RegT = MI.getOperand(1).getReg();
Jim Grosbach40e85fb2010-09-15 20:26:25 +00001786 RegT = getARMRegisterNumbering(RegT);
Bob Wilsonbe157b02010-06-29 20:13:29 +00001787 Binary |= (RegT << ARMII::RegRdShift);
1788 Binary |= encodeNEONRn(MI, 0);
1789 emitWordLE(Binary);
1790}
1791
Bob Wilsone70c8b12010-06-25 21:17:19 +00001792void ARMCodeEmitter::emitNEON1RegModImmInstruction(const MachineInstr &MI) {
Bob Wilson6eae5202010-06-11 21:34:50 +00001793 unsigned Binary = getBinaryCodeForInstr(MI);
1794 // Destination register is encoded in Dd.
1795 Binary |= encodeNEONRd(MI, 0);
1796 // Immediate fields: Op, Cmode, I, Imm3, Imm4
1797 unsigned Imm = MI.getOperand(1).getImm();
1798 unsigned Op = (Imm >> 12) & 1;
Bob Wilson6eae5202010-06-11 21:34:50 +00001799 unsigned Cmode = (Imm >> 8) & 0xf;
Bob Wilson6eae5202010-06-11 21:34:50 +00001800 unsigned I = (Imm >> 7) & 1;
Bob Wilson6eae5202010-06-11 21:34:50 +00001801 unsigned Imm3 = (Imm >> 4) & 0x7;
Bob Wilson6eae5202010-06-11 21:34:50 +00001802 unsigned Imm4 = Imm & 0xf;
Bob Wilson544317d2010-06-28 21:16:30 +00001803 Binary |= (I << 24) | (Imm3 << 16) | (Cmode << 8) | (Op << 5) | Imm4;
Bob Wilson4469a892010-06-28 22:23:17 +00001804 if (IsThumb)
Bob Wilson584387d2010-06-28 21:12:19 +00001805 Binary = convertNEONDataProcToThumb(Binary);
Bob Wilson6eae5202010-06-11 21:34:50 +00001806 emitWordLE(Binary);
1807}
1808
Bob Wilsone70c8b12010-06-25 21:17:19 +00001809void ARMCodeEmitter::emitNEON2RegInstruction(const MachineInstr &MI) {
Bob Wilson2530ca02010-06-25 22:40:46 +00001810 const TargetInstrDesc &TID = MI.getDesc();
Bob Wilsone70c8b12010-06-25 21:17:19 +00001811 unsigned Binary = getBinaryCodeForInstr(MI);
Bob Wilson2530ca02010-06-25 22:40:46 +00001812 // Destination register is encoded in Dd; source register in Dm.
1813 unsigned OpIdx = 0;
1814 Binary |= encodeNEONRd(MI, OpIdx++);
1815 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1816 ++OpIdx;
1817 Binary |= encodeNEONRm(MI, OpIdx);
Bob Wilson4469a892010-06-28 22:23:17 +00001818 if (IsThumb)
Bob Wilson584387d2010-06-28 21:12:19 +00001819 Binary = convertNEONDataProcToThumb(Binary);
Bob Wilsone70c8b12010-06-25 21:17:19 +00001820 // FIXME: This does not handle VDUPfdf or VDUPfqf.
1821 emitWordLE(Binary);
1822}
1823
Bob Wilson2530ca02010-06-25 22:40:46 +00001824void ARMCodeEmitter::emitNEON3RegInstruction(const MachineInstr &MI) {
1825 const TargetInstrDesc &TID = MI.getDesc();
1826 unsigned Binary = getBinaryCodeForInstr(MI);
1827 // Destination register is encoded in Dd; source registers in Dn and Dm.
1828 unsigned OpIdx = 0;
1829 Binary |= encodeNEONRd(MI, OpIdx++);
1830 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1831 ++OpIdx;
1832 Binary |= encodeNEONRn(MI, OpIdx++);
1833 if (TID.getOperandConstraint(OpIdx, TOI::TIED_TO) != -1)
1834 ++OpIdx;
1835 Binary |= encodeNEONRm(MI, OpIdx);
Bob Wilson4469a892010-06-28 22:23:17 +00001836 if (IsThumb)
Bob Wilson584387d2010-06-28 21:12:19 +00001837 Binary = convertNEONDataProcToThumb(Binary);
Bob Wilson2530ca02010-06-25 22:40:46 +00001838 // FIXME: This does not handle VMOVDneon or VMOVQ.
1839 emitWordLE(Binary);
1840}
1841
Evan Cheng3be5b722008-09-02 06:52:38 +00001842#include "ARMGenCodeEmitter.inc"