blob: f5b5bcb9d108ff323e059a8f26dc814fa5123291 [file] [log] [blame]
Sanjay Pateleb504762016-07-16 18:08:22 +00001; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
2; RUN: opt < %s -instcombine -S | FileCheck %s
3
4; Tests for Integer BitWidth <= 64 && BitWidth % 8 != 0.
5
6;; Flip sign bit then add INT_MIN -> nop.
7define i1 @test1(i1 %x) {
8; CHECK-LABEL: @test1(
9; CHECK-NEXT: ret i1 %x
10;
11 %tmp.2 = xor i1 %x, 1
12 %tmp.4 = add i1 %tmp.2, 1
13 ret i1 %tmp.4
14}
15
16;; Flip sign bit then add INT_MIN -> nop.
17define i47 @test2(i47 %x) {
18; CHECK-LABEL: @test2(
19; CHECK-NEXT: ret i47 %x
20;
21 %tmp.2 = xor i47 %x, 70368744177664
22 %tmp.4 = add i47 %tmp.2, 70368744177664
23 ret i47 %tmp.4
24}
25
26;; Flip sign bit then add INT_MIN -> nop.
27define i15 @test3(i15 %x) {
28; CHECK-LABEL: @test3(
29; CHECK-NEXT: ret i15 %x
30;
31 %tmp.2 = xor i15 %x, 16384
32 %tmp.4 = add i15 %tmp.2, 16384
33 ret i15 %tmp.4
34}
35
Sanjay Patel040bd162016-07-16 18:24:18 +000036; X + signbit --> X ^ signbit
37define <2 x i5> @test3vec(<2 x i5> %x) {
38; CHECK-LABEL: @test3vec(
Sanjay Patel79acd2a2016-07-16 18:29:26 +000039; CHECK-NEXT: [[Y:%.*]] = xor <2 x i5> %x, <i5 -16, i5 -16>
Sanjay Patel040bd162016-07-16 18:24:18 +000040; CHECK-NEXT: ret <2 x i5> [[Y]]
41;
42 %y = add <2 x i5> %x, <i5 16, i5 16>
43 ret <2 x i5> %y
44}
45
Sanjay Pateleb504762016-07-16 18:08:22 +000046;; (x & 0b1111..0) + 1 -> x | 1
47define i49 @test4(i49 %x) {
48; CHECK-LABEL: @test4(
49; CHECK-NEXT: [[TMP_4:%.*]] = or i49 %x, 1
50; CHECK-NEXT: ret i49 [[TMP_4]]
51;
52 %tmp.2 = and i49 %x, 562949953421310
53 %tmp.4 = add i49 %tmp.2, 1
54 ret i49 %tmp.4
55}
56
Sanjay Pateldbf44f52016-07-18 20:37:51 +000057define i7 @sext(i4 %x) {
58; CHECK-LABEL: @sext(
59; CHECK-NEXT: [[XOR:%.*]] = xor i4 %x, -8
60; CHECK-NEXT: [[ZEXT:%.*]] = zext i4 [[XOR]] to i7
61; CHECK-NEXT: [[ADD:%.*]] = add nsw i7 [[ZEXT]], -8
62; CHECK-NEXT: ret i7 [[ADD]]
63;
64 %xor = xor i4 %x, -8
65 %zext = zext i4 %xor to i7
66 %add = add nsw i7 %zext, -8
67 ret i7 %add
68}
69
70define <2 x i10> @sext_vec(<2 x i3> %x) {
71; CHECK-LABEL: @sext_vec(
72; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i3> %x, <i3 -4, i3 -4>
73; CHECK-NEXT: [[ZEXT:%.*]] = zext <2 x i3> [[XOR]] to <2 x i10>
74; CHECK-NEXT: [[ADD:%.*]] = add nsw <2 x i10> [[ZEXT]], <i10 -4, i10 -4>
75; CHECK-NEXT: ret <2 x i10> [[ADD]]
76;
77 %xor = xor <2 x i3> %x, <i3 -4, i3 -4>
78 %zext = zext <2 x i3> %xor to <2 x i10>
79 %add = add nsw <2 x i10> %zext, <i10 -4, i10 -4>
80 ret <2 x i10> %add
81}
82
Sanjay Pateleb504762016-07-16 18:08:22 +000083; Tests for Integer BitWidth > 64 && BitWidth <= 1024.
84
85;; Flip sign bit then add INT_MIN -> nop.
86define i111 @test5(i111 %x) {
87; CHECK-LABEL: @test5(
88; CHECK-NEXT: ret i111 %x
89;
90 %tmp.2 = shl i111 1, 110
91 %tmp.4 = xor i111 %x, %tmp.2
92 %tmp.6 = add i111 %tmp.4, %tmp.2
93 ret i111 %tmp.6
94}
95
96;; Flip sign bit then add INT_MIN -> nop.
97define i65 @test6(i65 %x) {
98; CHECK-LABEL: @test6(
99; CHECK-NEXT: ret i65 %x
100;
101 %tmp.0 = shl i65 1, 64
102 %tmp.2 = xor i65 %x, %tmp.0
103 %tmp.4 = add i65 %tmp.2, %tmp.0
104 ret i65 %tmp.4
105}
106
107;; Flip sign bit then add INT_MIN -> nop.
108define i1024 @test7(i1024 %x) {
109; CHECK-LABEL: @test7(
110; CHECK-NEXT: ret i1024 %x
111;
112 %tmp.0 = shl i1024 1, 1023
113 %tmp.2 = xor i1024 %x, %tmp.0
114 %tmp.4 = add i1024 %tmp.2, %tmp.0
115 ret i1024 %tmp.4
116}
117
118;; If we have add(xor(X, 0xF..F80..), 0x80..), it's an xor.
119define i128 @test8(i128 %x) {
120; CHECK-LABEL: @test8(
121; CHECK-NEXT: [[TMP_4:%.*]] = xor i128 %x, 170141183460469231731687303715884105600
122; CHECK-NEXT: ret i128 [[TMP_4]]
123;
124 %tmp.5 = shl i128 1, 127
125 %tmp.1 = ashr i128 %tmp.5, 120
126 %tmp.2 = xor i128 %x, %tmp.1
127 %tmp.4 = add i128 %tmp.2, %tmp.5
128 ret i128 %tmp.4
129}
130
131;; (x & 254)+1 -> (x & 254)|1
132define i77 @test9(i77 %x) {
133; CHECK-LABEL: @test9(
134; CHECK-NEXT: [[TMP_2:%.*]] = and i77 %x, 562949953421310
135; CHECK-NEXT: [[TMP_4:%.*]] = or i77 [[TMP_2]], 1
136; CHECK-NEXT: ret i77 [[TMP_4]]
137;
138 %tmp.2 = and i77 %x, 562949953421310
139 %tmp.4 = add i77 %tmp.2, 1
140 ret i77 %tmp.4
141}
142