Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 1 | //===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the MachineIRBuidler class. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | #include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h" |
| 13 | |
| 14 | #include "llvm/CodeGen/MachineFunction.h" |
| 15 | #include "llvm/CodeGen/MachineInstr.h" |
| 16 | #include "llvm/CodeGen/MachineInstrBuilder.h" |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 17 | #include "llvm/CodeGen/MachineRegisterInfo.h" |
David Blaikie | 3f833ed | 2017-11-08 01:01:31 +0000 | [diff] [blame] | 18 | #include "llvm/CodeGen/TargetInstrInfo.h" |
David Blaikie | b3bde2e | 2017-11-17 01:07:10 +0000 | [diff] [blame] | 19 | #include "llvm/CodeGen/TargetOpcodes.h" |
| 20 | #include "llvm/CodeGen/TargetSubtargetInfo.h" |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 21 | #include "llvm/IR/DebugInfo.h" |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 22 | |
| 23 | using namespace llvm; |
| 24 | |
Quentin Colombet | 000b580 | 2016-03-11 17:27:51 +0000 | [diff] [blame] | 25 | void MachineIRBuilder::setMF(MachineFunction &MF) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 26 | this->MF = &MF; |
| 27 | this->MBB = nullptr; |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 28 | this->MRI = &MF.getRegInfo(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 29 | this->TII = MF.getSubtarget().getInstrInfo(); |
| 30 | this->DL = DebugLoc(); |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 31 | this->II = MachineBasicBlock::iterator(); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 32 | this->InsertedInstr = nullptr; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 33 | } |
| 34 | |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 35 | void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 36 | this->MBB = &MBB; |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 37 | this->II = MBB.end(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 38 | assert(&getMF() == MBB.getParent() && |
| 39 | "Basic block is in a different function"); |
| 40 | } |
| 41 | |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 42 | void MachineIRBuilder::setInstr(MachineInstr &MI) { |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 43 | assert(MI.getParent() && "Instruction is not part of a basic block"); |
Quentin Colombet | 91ebd71 | 2016-03-11 17:27:47 +0000 | [diff] [blame] | 44 | setMBB(*MI.getParent()); |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 45 | this->II = MI.getIterator(); |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 46 | } |
| 47 | |
Tim Northover | 05cc485 | 2016-12-07 21:05:38 +0000 | [diff] [blame] | 48 | void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB, |
| 49 | MachineBasicBlock::iterator II) { |
| 50 | assert(MBB.getParent() == &getMF() && |
| 51 | "Basic block is in a different function"); |
| 52 | this->MBB = &MBB; |
| 53 | this->II = II; |
Quentin Colombet | 2ad1f85 | 2016-02-11 17:44:59 +0000 | [diff] [blame] | 54 | } |
| 55 | |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 56 | void MachineIRBuilder::recordInsertions( |
| 57 | std::function<void(MachineInstr *)> Inserted) { |
Benjamin Kramer | 061f4a5 | 2017-01-13 14:39:03 +0000 | [diff] [blame] | 58 | InsertedInstr = std::move(Inserted); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 59 | } |
| 60 | |
| 61 | void MachineIRBuilder::stopRecordingInsertions() { |
| 62 | InsertedInstr = nullptr; |
| 63 | } |
| 64 | |
Quentin Colombet | f9b4934 | 2016-03-11 17:27:58 +0000 | [diff] [blame] | 65 | //------------------------------------------------------------------------------ |
| 66 | // Build instruction variants. |
| 67 | //------------------------------------------------------------------------------ |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 68 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 69 | MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) { |
Tim Northover | a5e38fa | 2016-09-22 13:49:25 +0000 | [diff] [blame] | 70 | return insertInstr(buildInstrNoInsert(Opcode)); |
| 71 | } |
| 72 | |
| 73 | MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 74 | MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode)); |
Tim Northover | a5e38fa | 2016-09-22 13:49:25 +0000 | [diff] [blame] | 75 | return MIB; |
| 76 | } |
| 77 | |
| 78 | |
| 79 | MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 80 | getMBB().insert(getInsertPt(), MIB); |
Tim Northover | 438c77c | 2016-08-25 17:37:32 +0000 | [diff] [blame] | 81 | if (InsertedInstr) |
| 82 | InsertedInstr(MIB); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 83 | return MIB; |
Quentin Colombet | 74d7d2f | 2016-02-11 18:53:28 +0000 | [diff] [blame] | 84 | } |
| 85 | |
Adrian Prantl | aac78ce | 2017-08-01 22:37:35 +0000 | [diff] [blame] | 86 | MachineInstrBuilder |
| 87 | MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable, |
| 88 | const MDNode *Expr) { |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 89 | assert(isa<DILocalVariable>(Variable) && "not a variable"); |
| 90 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); |
| 91 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
| 92 | "Expected inlined-at fields to agree"); |
Adrian Prantl | aac78ce | 2017-08-01 22:37:35 +0000 | [diff] [blame] | 93 | return insertInstr(BuildMI(getMF(), DL, getTII().get(TargetOpcode::DBG_VALUE), |
| 94 | /*IsIndirect*/ false, Reg, Variable, Expr)); |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 95 | } |
| 96 | |
Adrian Prantl | d92ac5a | 2017-07-28 22:46:20 +0000 | [diff] [blame] | 97 | MachineInstrBuilder |
| 98 | MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable, |
| 99 | const MDNode *Expr) { |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 100 | assert(isa<DILocalVariable>(Variable) && "not a variable"); |
| 101 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); |
| 102 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
| 103 | "Expected inlined-at fields to agree"); |
Adrian Prantl | aac78ce | 2017-08-01 22:37:35 +0000 | [diff] [blame] | 104 | return insertInstr(BuildMI(getMF(), DL, getTII().get(TargetOpcode::DBG_VALUE), |
| 105 | /*IsIndirect*/ true, Reg, Variable, Expr)); |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 106 | } |
| 107 | |
| 108 | MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI, |
| 109 | const MDNode *Variable, |
| 110 | const MDNode *Expr) { |
| 111 | assert(isa<DILocalVariable>(Variable) && "not a variable"); |
| 112 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); |
| 113 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
| 114 | "Expected inlined-at fields to agree"); |
| 115 | return buildInstr(TargetOpcode::DBG_VALUE) |
| 116 | .addFrameIndex(FI) |
| 117 | .addImm(0) |
| 118 | .addMetadata(Variable) |
| 119 | .addMetadata(Expr); |
| 120 | } |
| 121 | |
| 122 | MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C, |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 123 | const MDNode *Variable, |
| 124 | const MDNode *Expr) { |
| 125 | assert(isa<DILocalVariable>(Variable) && "not a variable"); |
| 126 | assert(cast<DIExpression>(Expr)->isValid() && "not an expression"); |
| 127 | assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) && |
| 128 | "Expected inlined-at fields to agree"); |
| 129 | auto MIB = buildInstr(TargetOpcode::DBG_VALUE); |
| 130 | if (auto *CI = dyn_cast<ConstantInt>(&C)) { |
| 131 | if (CI->getBitWidth() > 64) |
| 132 | MIB.addCImm(CI); |
| 133 | else |
| 134 | MIB.addImm(CI->getZExtValue()); |
Ahmed Bougacha | 4826bae | 2017-03-07 20:34:20 +0000 | [diff] [blame] | 135 | } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) { |
Ahmed Bougacha | adce3ee | 2017-03-07 20:52:57 +0000 | [diff] [blame] | 136 | MIB.addFPImm(CFP); |
Ahmed Bougacha | 4826bae | 2017-03-07 20:34:20 +0000 | [diff] [blame] | 137 | } else { |
| 138 | // Insert %noreg if we didn't find a usable constant and had to drop it. |
| 139 | MIB.addReg(0U); |
| 140 | } |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 141 | |
Adrian Prantl | d92ac5a | 2017-07-28 22:46:20 +0000 | [diff] [blame] | 142 | return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr); |
Tim Northover | 09aac4a | 2017-01-26 23:39:14 +0000 | [diff] [blame] | 143 | } |
| 144 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 145 | MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 146 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 147 | return buildInstr(TargetOpcode::G_FRAME_INDEX) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 148 | .addDef(Res) |
| 149 | .addFrameIndex(Idx); |
Tim Northover | bd50546 | 2016-07-22 16:59:52 +0000 | [diff] [blame] | 150 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 151 | |
Tim Northover | 032548f | 2016-09-12 12:10:41 +0000 | [diff] [blame] | 152 | MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res, |
| 153 | const GlobalValue *GV) { |
| 154 | assert(MRI->getType(Res).isPointer() && "invalid operand type"); |
| 155 | assert(MRI->getType(Res).getAddressSpace() == |
| 156 | GV->getType()->getAddressSpace() && |
| 157 | "address space mismatch"); |
| 158 | |
| 159 | return buildInstr(TargetOpcode::G_GLOBAL_VALUE) |
| 160 | .addDef(Res) |
| 161 | .addGlobalAddress(GV); |
| 162 | } |
| 163 | |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 164 | MachineInstrBuilder MachineIRBuilder::buildBinaryOp(unsigned Opcode, unsigned Res, unsigned Op0, |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 165 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 166 | assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) && |
| 167 | "invalid operand type"); |
| 168 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 169 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 170 | |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 171 | return buildInstr(Opcode) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 172 | .addDef(Res) |
| 173 | .addUse(Op0) |
| 174 | .addUse(Op1); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 175 | } |
| 176 | |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 177 | MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0, |
| 178 | unsigned Op1) { |
| 179 | return buildBinaryOp(TargetOpcode::G_ADD, Res, Op0, Op1); |
| 180 | } |
| 181 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 182 | MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0, |
| 183 | unsigned Op1) { |
| 184 | assert(MRI->getType(Res).isPointer() && |
| 185 | MRI->getType(Res) == MRI->getType(Op0) && "type mismatch"); |
| 186 | assert(MRI->getType(Op1).isScalar() && "invalid offset type"); |
| 187 | |
| 188 | return buildInstr(TargetOpcode::G_GEP) |
| 189 | .addDef(Res) |
| 190 | .addUse(Op0) |
| 191 | .addUse(Op1); |
| 192 | } |
| 193 | |
Daniel Sanders | 4e52366 | 2017-06-13 23:42:32 +0000 | [diff] [blame] | 194 | Optional<MachineInstrBuilder> |
| 195 | MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0, |
| 196 | const LLT &ValueTy, uint64_t Value) { |
| 197 | assert(Res == 0 && "Res is a result argument"); |
| 198 | assert(ValueTy.isScalar() && "invalid offset type"); |
| 199 | |
| 200 | if (Value == 0) { |
| 201 | Res = Op0; |
| 202 | return None; |
| 203 | } |
| 204 | |
| 205 | Res = MRI->createGenericVirtualRegister(MRI->getType(Op0)); |
| 206 | unsigned TmpReg = MRI->createGenericVirtualRegister(ValueTy); |
| 207 | |
| 208 | buildConstant(TmpReg, Value); |
| 209 | return buildGEP(Res, Op0, TmpReg); |
| 210 | } |
| 211 | |
Tim Northover | c2f8956 | 2017-02-14 20:56:18 +0000 | [diff] [blame] | 212 | MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0, |
| 213 | uint32_t NumBits) { |
| 214 | assert(MRI->getType(Res).isPointer() && |
| 215 | MRI->getType(Res) == MRI->getType(Op0) && "type mismatch"); |
| 216 | |
| 217 | return buildInstr(TargetOpcode::G_PTR_MASK) |
| 218 | .addDef(Res) |
| 219 | .addUse(Op0) |
| 220 | .addImm(NumBits); |
| 221 | } |
| 222 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 223 | MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0, |
| 224 | unsigned Op1) { |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 225 | return buildBinaryOp(TargetOpcode::G_SUB, Res, Op0, Op1); |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 226 | } |
| 227 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 228 | MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0, |
| 229 | unsigned Op1) { |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 230 | return buildBinaryOp(TargetOpcode::G_MUL, Res, Op0, Op1); |
Tim Northover | cecee56 | 2016-08-26 17:46:13 +0000 | [diff] [blame] | 231 | } |
| 232 | |
Tim Northover | c3e3f59 | 2017-02-03 18:22:45 +0000 | [diff] [blame] | 233 | MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0, |
| 234 | unsigned Op1) { |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 235 | return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1); |
Tim Northover | c3e3f59 | 2017-02-03 18:22:45 +0000 | [diff] [blame] | 236 | } |
| 237 | |
Diana Picus | 3e40b46 | 2017-07-05 11:32:12 +0000 | [diff] [blame] | 238 | MachineInstrBuilder MachineIRBuilder::buildOr(unsigned Res, unsigned Op0, |
Diana Picus | 97a5d9b | 2017-07-05 11:47:23 +0000 | [diff] [blame] | 239 | unsigned Op1) { |
Diana Picus | 3e40b46 | 2017-07-05 11:32:12 +0000 | [diff] [blame] | 240 | return buildBinaryOp(TargetOpcode::G_OR, Res, Op0, Op1); |
| 241 | } |
Diana Picus | 05e704f | 2017-07-05 11:02:31 +0000 | [diff] [blame] | 242 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 243 | MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) { |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 244 | return buildInstr(TargetOpcode::G_BR).addMBB(&Dest); |
Tim Northover | cc5f762 | 2016-07-26 16:45:26 +0000 | [diff] [blame] | 245 | } |
| 246 | |
Kristof Beyls | 65a12c0 | 2017-01-30 09:13:18 +0000 | [diff] [blame] | 247 | MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) { |
Tim Northover | c990236 | 2017-06-27 22:45:35 +0000 | [diff] [blame] | 248 | assert(MRI->getType(Tgt).isPointer() && "invalid branch destination"); |
Kristof Beyls | 65a12c0 | 2017-01-30 09:13:18 +0000 | [diff] [blame] | 249 | return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt); |
| 250 | } |
| 251 | |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 252 | MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) { |
Tim Northover | 849fcca | 2017-06-27 21:41:40 +0000 | [diff] [blame] | 253 | assert(MRI->getType(Res) == LLT() || MRI->getType(Op) == LLT() || |
| 254 | MRI->getType(Res) == MRI->getType(Op)); |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 255 | return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); |
Tim Northover | 756eca3 | 2016-07-26 16:45:30 +0000 | [diff] [blame] | 256 | } |
| 257 | |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 258 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, |
| 259 | const ConstantInt &Val) { |
| 260 | LLT Ty = MRI->getType(Res); |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 261 | |
Sam McCall | 03435f5 | 2016-12-06 10:14:36 +0000 | [diff] [blame] | 262 | assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type"); |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 263 | |
| 264 | const ConstantInt *NewVal = &Val; |
| 265 | if (Ty.getSizeInBits() != Val.getBitWidth()) |
Matthias Braun | f1caa28 | 2017-12-15 22:22:58 +0000 | [diff] [blame] | 266 | NewVal = ConstantInt::get(MF->getFunction().getContext(), |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 267 | Val.getValue().sextOrTrunc(Ty.getSizeInBits())); |
| 268 | |
| 269 | return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal); |
| 270 | } |
| 271 | |
| 272 | MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res, |
| 273 | int64_t Val) { |
Matthias Braun | f1caa28 | 2017-12-15 22:22:58 +0000 | [diff] [blame] | 274 | auto IntN = IntegerType::get(MF->getFunction().getContext(), |
Tim Northover | 9267ac5 | 2016-12-05 21:47:07 +0000 | [diff] [blame] | 275 | MRI->getType(Res).getSizeInBits()); |
| 276 | ConstantInt *CI = ConstantInt::get(IntN, Val, true); |
| 277 | return buildConstant(Res, *CI); |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 278 | } |
| 279 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 280 | MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res, |
| 281 | const ConstantFP &Val) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 282 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 283 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 284 | return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); |
Tim Northover | b16734f | 2016-08-19 20:09:15 +0000 | [diff] [blame] | 285 | } |
| 286 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 287 | MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst, |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 288 | MachineBasicBlock &Dest) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 289 | assert(MRI->getType(Tst).isScalar() && "invalid operand type"); |
| 290 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 291 | return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest); |
Tim Northover | 69c2ba5 | 2016-07-29 17:58:00 +0000 | [diff] [blame] | 292 | } |
| 293 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 294 | MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr, |
| 295 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 296 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 297 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 298 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 299 | return buildInstr(TargetOpcode::G_LOAD) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 300 | .addDef(Res) |
| 301 | .addUse(Addr) |
| 302 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 303 | } |
| 304 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 305 | MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr, |
| 306 | MachineMemOperand &MMO) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 307 | assert(MRI->getType(Val).isValid() && "invalid operand type"); |
| 308 | assert(MRI->getType(Addr).isPointer() && "invalid operand type"); |
| 309 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 310 | return buildInstr(TargetOpcode::G_STORE) |
Tim Northover | a51575f | 2016-07-29 17:43:52 +0000 | [diff] [blame] | 311 | .addUse(Val) |
| 312 | .addUse(Addr) |
| 313 | .addMemOperand(&MMO); |
Tim Northover | ad2b717 | 2016-07-26 20:23:26 +0000 | [diff] [blame] | 314 | } |
| 315 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 316 | MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res, |
| 317 | unsigned CarryOut, |
| 318 | unsigned Op0, unsigned Op1, |
| 319 | unsigned CarryIn) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 320 | assert(MRI->getType(Res).isScalar() && "invalid operand type"); |
| 321 | assert(MRI->getType(Res) == MRI->getType(Op0) && |
| 322 | MRI->getType(Res) == MRI->getType(Op1) && "type mismatch"); |
| 323 | assert(MRI->getType(CarryOut).isScalar() && "invalid operand type"); |
| 324 | assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch"); |
| 325 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 326 | return buildInstr(TargetOpcode::G_UADDE) |
Tim Northover | 9656f14 | 2016-08-04 20:54:13 +0000 | [diff] [blame] | 327 | .addDef(Res) |
| 328 | .addDef(CarryOut) |
| 329 | .addUse(Op0) |
| 330 | .addUse(Op1) |
| 331 | .addUse(CarryIn); |
| 332 | } |
| 333 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 334 | MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) { |
| 335 | validateTruncExt(Res, Op, true); |
| 336 | return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 337 | } |
| 338 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 339 | MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) { |
| 340 | validateTruncExt(Res, Op, true); |
| 341 | return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 342 | } |
| 343 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 344 | MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) { |
| 345 | validateTruncExt(Res, Op, true); |
| 346 | return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op); |
Tim Northover | 6cd4b23 | 2016-08-23 21:01:26 +0000 | [diff] [blame] | 347 | } |
| 348 | |
Aditya Nandakumar | 892979e | 2017-08-25 04:57:27 +0000 | [diff] [blame] | 349 | MachineInstrBuilder |
| 350 | MachineIRBuilder::buildExtOrTrunc(unsigned ExtOpc, unsigned Res, unsigned Op) { |
| 351 | assert((TargetOpcode::G_ANYEXT == ExtOpc || TargetOpcode::G_ZEXT == ExtOpc || |
| 352 | TargetOpcode::G_SEXT == ExtOpc) && |
| 353 | "Expecting Extending Opc"); |
Tim Northover | c990236 | 2017-06-27 22:45:35 +0000 | [diff] [blame] | 354 | assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()); |
| 355 | assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar()); |
| 356 | |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 357 | unsigned Opcode = TargetOpcode::COPY; |
| 358 | if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits()) |
Aditya Nandakumar | 892979e | 2017-08-25 04:57:27 +0000 | [diff] [blame] | 359 | Opcode = ExtOpc; |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 360 | else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits()) |
| 361 | Opcode = TargetOpcode::G_TRUNC; |
Tim Northover | c990236 | 2017-06-27 22:45:35 +0000 | [diff] [blame] | 362 | else |
| 363 | assert(MRI->getType(Res) == MRI->getType(Op)); |
Tim Northover | a7653b3 | 2016-09-12 11:20:22 +0000 | [diff] [blame] | 364 | |
| 365 | return buildInstr(Opcode).addDef(Res).addUse(Op); |
| 366 | } |
| 367 | |
Aditya Nandakumar | 892979e | 2017-08-25 04:57:27 +0000 | [diff] [blame] | 368 | MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res, |
| 369 | unsigned Op) { |
| 370 | return buildExtOrTrunc(TargetOpcode::G_SEXT, Res, Op); |
| 371 | } |
| 372 | |
Tim Northover | c3e3f59 | 2017-02-03 18:22:45 +0000 | [diff] [blame] | 373 | MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res, |
| 374 | unsigned Op) { |
Aditya Nandakumar | 892979e | 2017-08-25 04:57:27 +0000 | [diff] [blame] | 375 | return buildExtOrTrunc(TargetOpcode::G_ZEXT, Res, Op); |
| 376 | } |
Tim Northover | c990236 | 2017-06-27 22:45:35 +0000 | [diff] [blame] | 377 | |
Aditya Nandakumar | 892979e | 2017-08-25 04:57:27 +0000 | [diff] [blame] | 378 | MachineInstrBuilder MachineIRBuilder::buildAnyExtOrTrunc(unsigned Res, |
| 379 | unsigned Op) { |
| 380 | return buildExtOrTrunc(TargetOpcode::G_ANYEXT, Res, Op); |
Tim Northover | c3e3f59 | 2017-02-03 18:22:45 +0000 | [diff] [blame] | 381 | } |
| 382 | |
Tim Northover | 95b6d5f | 2017-03-06 19:04:17 +0000 | [diff] [blame] | 383 | MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) { |
| 384 | LLT SrcTy = MRI->getType(Src); |
| 385 | LLT DstTy = MRI->getType(Dst); |
| 386 | if (SrcTy == DstTy) |
| 387 | return buildCopy(Dst, Src); |
| 388 | |
| 389 | unsigned Opcode; |
| 390 | if (SrcTy.isPointer() && DstTy.isScalar()) |
| 391 | Opcode = TargetOpcode::G_PTRTOINT; |
| 392 | else if (DstTy.isPointer() && SrcTy.isScalar()) |
| 393 | Opcode = TargetOpcode::G_INTTOPTR; |
| 394 | else { |
| 395 | assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet"); |
| 396 | Opcode = TargetOpcode::G_BITCAST; |
| 397 | } |
| 398 | |
| 399 | return buildInstr(Opcode).addDef(Dst).addUse(Src); |
| 400 | } |
| 401 | |
Tim Northover | c2c545b | 2017-03-06 23:50:28 +0000 | [diff] [blame] | 402 | MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src, |
| 403 | uint64_t Index) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 404 | #ifndef NDEBUG |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 405 | assert(MRI->getType(Src).isValid() && "invalid operand type"); |
Tim Northover | c2c545b | 2017-03-06 23:50:28 +0000 | [diff] [blame] | 406 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 407 | assert(Index + MRI->getType(Res).getSizeInBits() <= |
| 408 | MRI->getType(Src).getSizeInBits() && |
| 409 | "extracting off end of register"); |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 410 | #endif |
| 411 | |
Tim Northover | c2c545b | 2017-03-06 23:50:28 +0000 | [diff] [blame] | 412 | if (MRI->getType(Res).getSizeInBits() == MRI->getType(Src).getSizeInBits()) { |
| 413 | assert(Index == 0 && "insertion past the end of a register"); |
| 414 | return buildCast(Res, Src); |
| 415 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 416 | |
Tim Northover | c2c545b | 2017-03-06 23:50:28 +0000 | [diff] [blame] | 417 | return buildInstr(TargetOpcode::G_EXTRACT) |
| 418 | .addDef(Res) |
| 419 | .addUse(Src) |
| 420 | .addImm(Index); |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 421 | } |
| 422 | |
Tim Northover | b57bf2a | 2017-06-23 16:15:37 +0000 | [diff] [blame] | 423 | void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops, |
| 424 | ArrayRef<uint64_t> Indices) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 425 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 426 | assert(Ops.size() == Indices.size() && "incompatible args"); |
Tim Northover | 26b76f2 | 2016-08-19 18:32:14 +0000 | [diff] [blame] | 427 | assert(!Ops.empty() && "invalid trivial sequence"); |
Tim Northover | 991b12b | 2016-08-30 20:51:25 +0000 | [diff] [blame] | 428 | assert(std::is_sorted(Indices.begin(), Indices.end()) && |
| 429 | "sequence offsets must be in ascending order"); |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 430 | |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 431 | assert(MRI->getType(Res).isValid() && "invalid operand type"); |
| 432 | for (auto Op : Ops) |
| 433 | assert(MRI->getType(Op).isValid() && "invalid operand type"); |
| 434 | #endif |
| 435 | |
Tim Northover | b57bf2a | 2017-06-23 16:15:37 +0000 | [diff] [blame] | 436 | LLT ResTy = MRI->getType(Res); |
| 437 | LLT OpTy = MRI->getType(Ops[0]); |
| 438 | unsigned OpSize = OpTy.getSizeInBits(); |
| 439 | bool MaybeMerge = true; |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 440 | for (unsigned i = 0; i < Ops.size(); ++i) { |
Tim Northover | b57bf2a | 2017-06-23 16:15:37 +0000 | [diff] [blame] | 441 | if (MRI->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) { |
| 442 | MaybeMerge = false; |
| 443 | break; |
| 444 | } |
Tim Northover | 91c8173 | 2016-08-19 17:17:06 +0000 | [diff] [blame] | 445 | } |
Tim Northover | b57bf2a | 2017-06-23 16:15:37 +0000 | [diff] [blame] | 446 | |
| 447 | if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) { |
| 448 | buildMerge(Res, Ops); |
| 449 | return; |
| 450 | } |
| 451 | |
| 452 | unsigned ResIn = MRI->createGenericVirtualRegister(ResTy); |
| 453 | buildUndef(ResIn); |
| 454 | |
| 455 | for (unsigned i = 0; i < Ops.size(); ++i) { |
| 456 | unsigned ResOut = |
| 457 | i + 1 == Ops.size() ? Res : MRI->createGenericVirtualRegister(ResTy); |
| 458 | buildInsert(ResOut, ResIn, Ops[i], Indices[i]); |
| 459 | ResIn = ResOut; |
| 460 | } |
Tim Northover | 33b07d6 | 2016-07-22 20:03:43 +0000 | [diff] [blame] | 461 | } |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 462 | |
Tim Northover | 81dafc1 | 2017-03-06 18:36:40 +0000 | [diff] [blame] | 463 | MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) { |
Tim Northover | ff5e7e1 | 2017-06-30 20:27:36 +0000 | [diff] [blame] | 464 | return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res); |
Tim Northover | 81dafc1 | 2017-03-06 18:36:40 +0000 | [diff] [blame] | 465 | } |
| 466 | |
Tim Northover | bf01729 | 2017-03-03 22:46:09 +0000 | [diff] [blame] | 467 | MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res, |
| 468 | ArrayRef<unsigned> Ops) { |
| 469 | |
| 470 | #ifndef NDEBUG |
| 471 | assert(!Ops.empty() && "invalid trivial sequence"); |
| 472 | LLT Ty = MRI->getType(Ops[0]); |
| 473 | for (auto Reg : Ops) |
| 474 | assert(MRI->getType(Reg) == Ty && "type mismatch in input list"); |
| 475 | assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() == |
| 476 | MRI->getType(Res).getSizeInBits() && |
| 477 | "input operands do not cover output register"); |
| 478 | #endif |
| 479 | |
Tim Northover | c2d5e6d | 2017-06-26 20:34:13 +0000 | [diff] [blame] | 480 | if (Ops.size() == 1) |
Tim Northover | 849fcca | 2017-06-27 21:41:40 +0000 | [diff] [blame] | 481 | return buildCast(Res, Ops[0]); |
Tim Northover | c2d5e6d | 2017-06-26 20:34:13 +0000 | [diff] [blame] | 482 | |
Tim Northover | bf01729 | 2017-03-03 22:46:09 +0000 | [diff] [blame] | 483 | MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES); |
| 484 | MIB.addDef(Res); |
| 485 | for (unsigned i = 0; i < Ops.size(); ++i) |
| 486 | MIB.addUse(Ops[i]); |
| 487 | return MIB; |
| 488 | } |
| 489 | |
| 490 | MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res, |
| 491 | unsigned Op) { |
| 492 | |
| 493 | #ifndef NDEBUG |
| 494 | assert(!Res.empty() && "invalid trivial sequence"); |
| 495 | LLT Ty = MRI->getType(Res[0]); |
| 496 | for (auto Reg : Res) |
| 497 | assert(MRI->getType(Reg) == Ty && "type mismatch in input list"); |
| 498 | assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() == |
| 499 | MRI->getType(Op).getSizeInBits() && |
| 500 | "input operands do not cover output register"); |
| 501 | #endif |
| 502 | |
| 503 | MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES); |
| 504 | for (unsigned i = 0; i < Res.size(); ++i) |
| 505 | MIB.addDef(Res[i]); |
| 506 | MIB.addUse(Op); |
| 507 | return MIB; |
| 508 | } |
| 509 | |
Tim Northover | 3e6a7af | 2017-03-03 23:05:47 +0000 | [diff] [blame] | 510 | MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src, |
| 511 | unsigned Op, unsigned Index) { |
Tim Northover | c990236 | 2017-06-27 22:45:35 +0000 | [diff] [blame] | 512 | assert(Index + MRI->getType(Op).getSizeInBits() <= |
| 513 | MRI->getType(Res).getSizeInBits() && |
| 514 | "insertion past the end of a register"); |
| 515 | |
Tim Northover | 95b6d5f | 2017-03-06 19:04:17 +0000 | [diff] [blame] | 516 | if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) { |
Tim Northover | 95b6d5f | 2017-03-06 19:04:17 +0000 | [diff] [blame] | 517 | return buildCast(Res, Op); |
| 518 | } |
| 519 | |
Tim Northover | 3e6a7af | 2017-03-03 23:05:47 +0000 | [diff] [blame] | 520 | return buildInstr(TargetOpcode::G_INSERT) |
| 521 | .addDef(Res) |
| 522 | .addUse(Src) |
| 523 | .addUse(Op) |
| 524 | .addImm(Index); |
| 525 | } |
| 526 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 527 | MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID, |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 528 | unsigned Res, |
| 529 | bool HasSideEffects) { |
| 530 | auto MIB = |
| 531 | buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 532 | : TargetOpcode::G_INTRINSIC); |
Tim Northover | 5fb414d | 2016-07-29 22:32:36 +0000 | [diff] [blame] | 533 | if (Res) |
| 534 | MIB.addDef(Res); |
| 535 | MIB.addIntrinsicID(ID); |
| 536 | return MIB; |
| 537 | } |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 538 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 539 | MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) { |
| 540 | validateTruncExt(Res, Op, false); |
| 541 | return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op); |
Tim Northover | 3233581 | 2016-08-04 18:35:11 +0000 | [diff] [blame] | 542 | } |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 543 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 544 | MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) { |
| 545 | validateTruncExt(Res, Op, false); |
| 546 | return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op); |
Tim Northover | a11be04 | 2016-08-19 22:40:08 +0000 | [diff] [blame] | 547 | } |
| 548 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 549 | MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred, |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 550 | unsigned Res, unsigned Op0, |
| 551 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 552 | #ifndef NDEBUG |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 553 | assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch"); |
| 554 | assert(CmpInst::isIntPredicate(Pred) && "invalid predicate"); |
Tim Northover | 4cf0a48 | 2016-09-15 10:40:38 +0000 | [diff] [blame] | 555 | if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer()) |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 556 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 557 | else |
| 558 | assert(MRI->getType(Res).isVector() && |
| 559 | MRI->getType(Res).getNumElements() == |
| 560 | MRI->getType(Op0).getNumElements() && |
| 561 | "type mismatch"); |
| 562 | #endif |
| 563 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 564 | return buildInstr(TargetOpcode::G_ICMP) |
Tim Northover | de3aea041 | 2016-08-17 20:25:25 +0000 | [diff] [blame] | 565 | .addDef(Res) |
| 566 | .addPredicate(Pred) |
| 567 | .addUse(Op0) |
| 568 | .addUse(Op1); |
| 569 | } |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 570 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 571 | MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred, |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 572 | unsigned Res, unsigned Op0, |
| 573 | unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 574 | #ifndef NDEBUG |
| 575 | assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) && |
| 576 | "invalid operand type"); |
| 577 | assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch"); |
| 578 | assert(CmpInst::isFPPredicate(Pred) && "invalid predicate"); |
| 579 | if (MRI->getType(Op0).isScalar()) |
| 580 | assert(MRI->getType(Res).isScalar() && "type mismatch"); |
| 581 | else |
| 582 | assert(MRI->getType(Res).isVector() && |
| 583 | MRI->getType(Res).getNumElements() == |
| 584 | MRI->getType(Op0).getNumElements() && |
| 585 | "type mismatch"); |
| 586 | #endif |
| 587 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 588 | return buildInstr(TargetOpcode::G_FCMP) |
Tim Northover | d5c23bc | 2016-08-19 20:48:16 +0000 | [diff] [blame] | 589 | .addDef(Res) |
| 590 | .addPredicate(Pred) |
| 591 | .addUse(Op0) |
| 592 | .addUse(Op1); |
| 593 | } |
| 594 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 595 | MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst, |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 596 | unsigned Op0, unsigned Op1) { |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 597 | #ifndef NDEBUG |
Tim Northover | f50f2f3 | 2016-12-06 18:38:34 +0000 | [diff] [blame] | 598 | LLT ResTy = MRI->getType(Res); |
| 599 | assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) && |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 600 | "invalid operand type"); |
Tim Northover | f50f2f3 | 2016-12-06 18:38:34 +0000 | [diff] [blame] | 601 | assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) && |
| 602 | "type mismatch"); |
| 603 | if (ResTy.isScalar() || ResTy.isPointer()) |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 604 | assert(MRI->getType(Tst).isScalar() && "type mismatch"); |
| 605 | else |
Ahmed Bougacha | 38455ea | 2017-03-07 20:53:03 +0000 | [diff] [blame] | 606 | assert((MRI->getType(Tst).isScalar() || |
| 607 | (MRI->getType(Tst).isVector() && |
| 608 | MRI->getType(Tst).getNumElements() == |
| 609 | MRI->getType(Op0).getNumElements())) && |
Tim Northover | 1f8b1db | 2016-09-09 11:46:58 +0000 | [diff] [blame] | 610 | "type mismatch"); |
| 611 | #endif |
| 612 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 613 | return buildInstr(TargetOpcode::G_SELECT) |
Tim Northover | 5a28c36 | 2016-08-19 20:09:07 +0000 | [diff] [blame] | 614 | .addDef(Res) |
| 615 | .addUse(Tst) |
| 616 | .addUse(Op0) |
| 617 | .addUse(Op1); |
| 618 | } |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 619 | |
Volkan Keles | 04cb08c | 2017-03-10 19:08:28 +0000 | [diff] [blame] | 620 | MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement(unsigned Res, |
| 621 | unsigned Val, |
| 622 | unsigned Elt, |
| 623 | unsigned Idx) { |
| 624 | #ifndef NDEBUG |
| 625 | LLT ResTy = MRI->getType(Res); |
| 626 | LLT ValTy = MRI->getType(Val); |
| 627 | LLT EltTy = MRI->getType(Elt); |
| 628 | LLT IdxTy = MRI->getType(Idx); |
| 629 | assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type"); |
Kristof Beyls | 0f36e68 | 2017-04-19 07:23:57 +0000 | [diff] [blame] | 630 | assert(IdxTy.isScalar() && "invalid operand type"); |
Volkan Keles | 04cb08c | 2017-03-10 19:08:28 +0000 | [diff] [blame] | 631 | assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch"); |
| 632 | assert(ResTy.getElementType() == EltTy && "type mismatch"); |
| 633 | #endif |
| 634 | |
| 635 | return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT) |
| 636 | .addDef(Res) |
| 637 | .addUse(Val) |
| 638 | .addUse(Elt) |
| 639 | .addUse(Idx); |
| 640 | } |
| 641 | |
| 642 | MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res, |
| 643 | unsigned Val, |
| 644 | unsigned Idx) { |
| 645 | #ifndef NDEBUG |
| 646 | LLT ResTy = MRI->getType(Res); |
| 647 | LLT ValTy = MRI->getType(Val); |
| 648 | LLT IdxTy = MRI->getType(Idx); |
| 649 | assert(ValTy.isVector() && "invalid operand type"); |
Kristof Beyls | 0f36e68 | 2017-04-19 07:23:57 +0000 | [diff] [blame] | 650 | assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type"); |
| 651 | assert(IdxTy.isScalar() && "invalid operand type"); |
Volkan Keles | 04cb08c | 2017-03-10 19:08:28 +0000 | [diff] [blame] | 652 | assert(ValTy.getElementType() == ResTy && "type mismatch"); |
| 653 | #endif |
| 654 | |
| 655 | return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT) |
| 656 | .addDef(Res) |
| 657 | .addUse(Val) |
| 658 | .addUse(Idx); |
| 659 | } |
| 660 | |
Daniel Sanders | aef1dfc | 2017-11-30 20:11:42 +0000 | [diff] [blame] | 661 | MachineInstrBuilder |
| 662 | MachineIRBuilder::buildAtomicCmpXchg(unsigned OldValRes, unsigned Addr, |
| 663 | unsigned CmpVal, unsigned NewVal, |
| 664 | MachineMemOperand &MMO) { |
| 665 | #ifndef NDEBUG |
| 666 | LLT OldValResTy = MRI->getType(OldValRes); |
| 667 | LLT AddrTy = MRI->getType(Addr); |
| 668 | LLT CmpValTy = MRI->getType(CmpVal); |
| 669 | LLT NewValTy = MRI->getType(NewVal); |
| 670 | assert(OldValResTy.isScalar() && "invalid operand type"); |
| 671 | assert(AddrTy.isPointer() && "invalid operand type"); |
| 672 | assert(CmpValTy.isValid() && "invalid operand type"); |
| 673 | assert(NewValTy.isValid() && "invalid operand type"); |
| 674 | assert(OldValResTy == CmpValTy && "type mismatch"); |
| 675 | assert(OldValResTy == NewValTy && "type mismatch"); |
| 676 | #endif |
| 677 | |
| 678 | return buildInstr(TargetOpcode::G_ATOMIC_CMPXCHG) |
| 679 | .addDef(OldValRes) |
| 680 | .addUse(Addr) |
| 681 | .addUse(CmpVal) |
| 682 | .addUse(NewVal) |
| 683 | .addMemOperand(&MMO); |
| 684 | } |
| 685 | |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 686 | void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src, |
| 687 | bool IsExtend) { |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 688 | #ifndef NDEBUG |
Tim Northover | 0f140c7 | 2016-09-09 11:46:34 +0000 | [diff] [blame] | 689 | LLT SrcTy = MRI->getType(Src); |
| 690 | LLT DstTy = MRI->getType(Dst); |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 691 | |
| 692 | if (DstTy.isVector()) { |
| 693 | assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector"); |
| 694 | assert(SrcTy.getNumElements() == DstTy.getNumElements() && |
| 695 | "different number of elements in a trunc/ext"); |
| 696 | } else |
| 697 | assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc"); |
| 698 | |
| 699 | if (IsExtend) |
| 700 | assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() && |
| 701 | "invalid narrowing extend"); |
| 702 | else |
| 703 | assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() && |
| 704 | "invalid widening trunc"); |
Richard Smith | 418237b | 2016-08-23 22:14:15 +0000 | [diff] [blame] | 705 | #endif |
Tim Northover | bdf67c9 | 2016-08-23 21:01:33 +0000 | [diff] [blame] | 706 | } |