| Thomas Lively | 9510ada | 2019-01-31 00:35:37 +0000 | [diff] [blame] | 1 | ; RUN: llc < %s -asm-verbose=false -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers |
| 2 | |
| 3 | ; Regression test for PR40267. Tests that invalid indices in |
| 4 | ; extract_vector_elt can be handled when vectors ops are split. Notice |
| 5 | ; that SIMD is not enabled for this test. Check only that llc does not |
| 6 | ; crash, since it would previously trigger an assertion. |
| 7 | |
| 8 | target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128" |
| 9 | target triple = "wasm32-unknown-unknown" |
| 10 | |
| 11 | define void @foo() { |
| 12 | %L6 = load i32, i32* undef |
| 13 | br label %BB1 |
| 14 | |
| 15 | BB1: ; preds = %BB1, %0 |
| 16 | %bj = select <4 x i1> <i1 true, i1 true, i1 false, i1 false>, <4 x i32> <i32 55, i32 21, i32 92, i32 68>, <4 x i32> <i32 51, i32 61, i32 62, i32 39> |
| 17 | %E1 = extractelement <4 x i32> %bj, i32 0 |
| 18 | %E23 = extractelement <4 x i32> zeroinitializer, i32 %E1 |
| 19 | %I33 = insertelement <4 x i32> undef, i32 %E23, i1 undef |
| 20 | store <4 x i32> %I33, <4 x i32>* undef |
| 21 | br label %BB1 |
| 22 | } |