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Tom Stellard45bb48e2015-06-13 03:28:10 +00001//===-- AMDGPUMCTargetDesc.cpp - AMDGPU Target Descriptions ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief This file provides AMDGPU specific target descriptions.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AMDGPUMCTargetDesc.h"
Tom Stellarde135ffd2015-09-25 21:41:28 +000016#include "AMDGPUELFStreamer.h"
Tom Stellard45bb48e2015-06-13 03:28:10 +000017#include "AMDGPUMCAsmInfo.h"
Tom Stellard347ac792015-06-26 21:15:07 +000018#include "AMDGPUTargetStreamer.h"
Tom Stellard45bb48e2015-06-13 03:28:10 +000019#include "InstPrinter/AMDGPUInstPrinter.h"
20#include "SIDefines.h"
Tom Stellard45bb48e2015-06-13 03:28:10 +000021#include "llvm/MC/MCContext.h"
22#include "llvm/MC/MCInstrInfo.h"
23#include "llvm/MC/MCRegisterInfo.h"
24#include "llvm/MC/MCStreamer.h"
25#include "llvm/MC/MCSubtargetInfo.h"
26#include "llvm/MC/MachineLocation.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/TargetRegistry.h"
29
30using namespace llvm;
31
32#define GET_INSTRINFO_MC_DESC
33#include "AMDGPUGenInstrInfo.inc"
34
35#define GET_SUBTARGETINFO_MC_DESC
36#include "AMDGPUGenSubtargetInfo.inc"
37
38#define GET_REGINFO_MC_DESC
39#include "AMDGPUGenRegisterInfo.inc"
40
41static MCInstrInfo *createAMDGPUMCInstrInfo() {
42 MCInstrInfo *X = new MCInstrInfo();
43 InitAMDGPUMCInstrInfo(X);
44 return X;
45}
46
Daniel Sanders50f17232015-09-15 16:17:27 +000047static MCRegisterInfo *createAMDGPUMCRegisterInfo(const Triple &TT) {
Tom Stellard45bb48e2015-06-13 03:28:10 +000048 MCRegisterInfo *X = new MCRegisterInfo();
49 InitAMDGPUMCRegisterInfo(X, 0);
50 return X;
51}
52
Daniel Sanders50f17232015-09-15 16:17:27 +000053static MCSubtargetInfo *
54createAMDGPUMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) {
Duncan P. N. Exon Smith754e21f2015-07-10 22:43:42 +000055 return createAMDGPUMCSubtargetInfoImpl(TT, CPU, FS);
Tom Stellard45bb48e2015-06-13 03:28:10 +000056}
57
Daniel Sanders50f17232015-09-15 16:17:27 +000058static MCInstPrinter *createAMDGPUMCInstPrinter(const Triple &T,
Tom Stellard45bb48e2015-06-13 03:28:10 +000059 unsigned SyntaxVariant,
60 const MCAsmInfo &MAI,
61 const MCInstrInfo &MII,
62 const MCRegisterInfo &MRI) {
63 return new AMDGPUInstPrinter(MAI, MII, MRI);
64}
65
Tom Stellard347ac792015-06-26 21:15:07 +000066static MCTargetStreamer *createAMDGPUAsmTargetStreamer(MCStreamer &S,
67 formatted_raw_ostream &OS,
68 MCInstPrinter *InstPrint,
69 bool isVerboseAsm) {
70 return new AMDGPUTargetAsmStreamer(S, OS);
71}
72
73static MCTargetStreamer * createAMDGPUObjectTargetStreamer(
74 MCStreamer &S,
75 const MCSubtargetInfo &STI) {
76 return new AMDGPUTargetELFStreamer(S);
77}
78
Tom Stellarde135ffd2015-09-25 21:41:28 +000079static MCStreamer *createMCStreamer(const Triple &T, MCContext &Context,
80 MCAsmBackend &MAB, raw_pwrite_stream &OS,
81 MCCodeEmitter *Emitter, bool RelaxAll) {
82 if (T.getOS() == Triple::AMDHSA)
83 return createAMDGPUELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
84
85 return createELFStreamer(Context, MAB, OS, Emitter, RelaxAll);
86}
87
Tom Stellard45bb48e2015-06-13 03:28:10 +000088extern "C" void LLVMInitializeAMDGPUTargetMC() {
Mehdi Aminif42454b2016-10-09 23:00:34 +000089 for (Target *T : {&getTheAMDGPUTarget(), &getTheGCNTarget()}) {
Tom Stellard45bb48e2015-06-13 03:28:10 +000090 RegisterMCAsmInfo<AMDGPUMCAsmInfo> X(*T);
91
Tom Stellard45bb48e2015-06-13 03:28:10 +000092 TargetRegistry::RegisterMCInstrInfo(*T, createAMDGPUMCInstrInfo);
93 TargetRegistry::RegisterMCRegInfo(*T, createAMDGPUMCRegisterInfo);
94 TargetRegistry::RegisterMCSubtargetInfo(*T, createAMDGPUMCSubtargetInfo);
95 TargetRegistry::RegisterMCInstPrinter(*T, createAMDGPUMCInstPrinter);
96 TargetRegistry::RegisterMCAsmBackend(*T, createAMDGPUAsmBackend);
Tom Stellarde135ffd2015-09-25 21:41:28 +000097 TargetRegistry::RegisterELFStreamer(*T, createMCStreamer);
Tom Stellard45bb48e2015-06-13 03:28:10 +000098 }
99
Tom Stellard347ac792015-06-26 21:15:07 +0000100 // R600 specific registration
Mehdi Aminif42454b2016-10-09 23:00:34 +0000101 TargetRegistry::RegisterMCCodeEmitter(getTheAMDGPUTarget(),
Tom Stellard45bb48e2015-06-13 03:28:10 +0000102 createR600MCCodeEmitter);
Tom Stellard347ac792015-06-26 21:15:07 +0000103
104 // GCN specific registration
Mehdi Aminif42454b2016-10-09 23:00:34 +0000105 TargetRegistry::RegisterMCCodeEmitter(getTheGCNTarget(),
106 createSIMCCodeEmitter);
Tom Stellard347ac792015-06-26 21:15:07 +0000107
Mehdi Aminif42454b2016-10-09 23:00:34 +0000108 TargetRegistry::RegisterAsmTargetStreamer(getTheGCNTarget(),
Tom Stellard347ac792015-06-26 21:15:07 +0000109 createAMDGPUAsmTargetStreamer);
Mehdi Aminif42454b2016-10-09 23:00:34 +0000110 TargetRegistry::RegisterObjectTargetStreamer(
111 getTheGCNTarget(), createAMDGPUObjectTargetStreamer);
Tom Stellard45bb48e2015-06-13 03:28:10 +0000112}