Matt Arsenault | c3a73c3 | 2014-05-22 03:20:30 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI %s |
Matt Arsenault | c996175 | 2014-10-03 23:54:56 +0000 | [diff] [blame] | 2 | ; RUN: llc -march=r600 -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -check-prefix=CI -check-prefix=FUNC %s |
| 3 | |
| 4 | declare i32 @llvm.r600.read.tidig.x() nounwind readnone |
Matt Arsenault | c3a73c3 | 2014-05-22 03:20:30 +0000 | [diff] [blame] | 5 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 6 | ; SI-LABEL: {{^}}fp_to_uint_i32_f64: |
Matt Arsenault | c3a73c3 | 2014-05-22 03:20:30 +0000 | [diff] [blame] | 7 | ; SI: V_CVT_U32_F64_e32 |
| 8 | define void @fp_to_uint_i32_f64(i32 addrspace(1)* %out, double %in) { |
| 9 | %cast = fptoui double %in to i32 |
| 10 | store i32 %cast, i32 addrspace(1)* %out, align 4 |
| 11 | ret void |
| 12 | } |
Matt Arsenault | c996175 | 2014-10-03 23:54:56 +0000 | [diff] [blame] | 13 | |
| 14 | ; SI-LABEL: @fp_to_uint_v2i32_v2f64 |
| 15 | ; SI: V_CVT_U32_F64_e32 |
| 16 | ; SI: V_CVT_U32_F64_e32 |
| 17 | define void @fp_to_uint_v2i32_v2f64(<2 x i32> addrspace(1)* %out, <2 x double> %in) { |
| 18 | %cast = fptoui <2 x double> %in to <2 x i32> |
| 19 | store <2 x i32> %cast, <2 x i32> addrspace(1)* %out, align 8 |
| 20 | ret void |
| 21 | } |
| 22 | |
| 23 | ; SI-LABEL: @fp_to_uint_v4i32_v4f64 |
| 24 | ; SI: V_CVT_U32_F64_e32 |
| 25 | ; SI: V_CVT_U32_F64_e32 |
| 26 | ; SI: V_CVT_U32_F64_e32 |
| 27 | ; SI: V_CVT_U32_F64_e32 |
| 28 | define void @fp_to_uint_v4i32_v4f64(<4 x i32> addrspace(1)* %out, <4 x double> %in) { |
| 29 | %cast = fptoui <4 x double> %in to <4 x i32> |
| 30 | store <4 x i32> %cast, <4 x i32> addrspace(1)* %out, align 8 |
| 31 | ret void |
| 32 | } |
| 33 | |
| 34 | ; FUNC-LABEL: @fp_to_uint_i64_f64 |
| 35 | ; CI-DAG: BUFFER_LOAD_DWORDX2 [[VAL:v\[[0-9]+:[0-9]+\]]] |
| 36 | ; CI-DAG: V_TRUNC_F64_e32 [[TRUNC:v\[[0-9]+:[0-9]+\]]], [[VAL]] |
| 37 | ; CI-DAG: S_MOV_B32 s[[K0_LO:[0-9]+]], 0{{$}} |
| 38 | ; CI-DAG: S_MOV_B32 s[[K0_HI:[0-9]+]], 0x3df00000 |
| 39 | |
| 40 | ; CI-DAG: V_MUL_F64 [[MUL:v\[[0-9]+:[0-9]+\]]], [[VAL]], s{{\[}}[[K0_LO]]:[[K0_HI]]{{\]}} |
| 41 | ; CI-DAG: V_FLOOR_F64_e32 [[FLOOR:v\[[0-9]+:[0-9]+\]]], [[MUL]] |
| 42 | |
| 43 | ; CI-DAG: S_MOV_B32 s[[K1_HI:[0-9]+]], 0xc1f00000 |
| 44 | |
| 45 | ; CI-DAG: V_FMA_F64 [[FMA:v\[[0-9]+:[0-9]+\]]], [[FLOOR]], s{{\[[0-9]+}}:[[K1_HI]]{{\]}}, [[TRUNC]] |
| 46 | ; CI-DAG: V_CVT_U32_F64_e32 v[[LO:[0-9]+]], [[FMA]] |
| 47 | ; CI-DAG: V_CVT_U32_F64_e32 v[[HI:[0-9]+]], [[FLOOR]] |
| 48 | ; CI: BUFFER_STORE_DWORDX2 v{{\[}}[[LO]]:[[HI]]{{\]}} |
| 49 | define void @fp_to_uint_i64_f64(i64 addrspace(1)* %out, double addrspace(1)* %in) { |
| 50 | %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone |
| 51 | %gep = getelementptr double addrspace(1)* %in, i32 %tid |
| 52 | %val = load double addrspace(1)* %gep, align 8 |
| 53 | %cast = fptoui double %val to i64 |
| 54 | store i64 %cast, i64 addrspace(1)* %out, align 4 |
| 55 | ret void |
| 56 | } |
| 57 | |
| 58 | ; SI-LABEL: @fp_to_uint_v2i64_v2f64 |
| 59 | define void @fp_to_uint_v2i64_v2f64(<2 x i64> addrspace(1)* %out, <2 x double> %in) { |
| 60 | %cast = fptoui <2 x double> %in to <2 x i64> |
| 61 | store <2 x i64> %cast, <2 x i64> addrspace(1)* %out, align 16 |
| 62 | ret void |
| 63 | } |
| 64 | |
| 65 | ; SI-LABEL: @fp_to_uint_v4i64_v4f64 |
| 66 | define void @fp_to_uint_v4i64_v4f64(<4 x i64> addrspace(1)* %out, <4 x double> %in) { |
| 67 | %cast = fptoui <4 x double> %in to <4 x i64> |
| 68 | store <4 x i64> %cast, <4 x i64> addrspace(1)* %out, align 32 |
| 69 | ret void |
| 70 | } |