Blame - llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp - toolchain/llvm-project

blob: 7f53240f21afa9670f863a5093ac6fa9cc1a7cb9 [file] [log] [blame]

Jia Liu	b22310f	2012-02-18 12:03:15 +0000	[diff] [blame]	1	//===-- ARMDisassembler.cpp - Disassembler for ARM/Thumb ISA --------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	2	//
				3	// The LLVM Compiler Infrastructure
				4	//
				5	// This file is distributed under the University of Illinois Open Source
				6	// License. See LICENSE.TXT for details.
				7	//
				8	//===----------------------------------------------------------------------===//
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	9
				10	#define DEBUG_TYPE "arm-disassembler"
				11
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	12	#include "llvm/MC/MCDisassembler.h"
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	13	#include "MCTargetDesc/ARMAddressingModes.h"
				14	#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	15	#include "MCTargetDesc/ARMMCExpr.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	16	#include "llvm/MC/MCContext.h"
				17	#include "llvm/MC/MCExpr.h"
				18	#include "llvm/MC/MCFixedLenDisassembler.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	19	#include "llvm/MC/MCInst.h"
Benjamin Kramer	48b5bbf	2011-11-11 12:39:41 +0000	[diff] [blame]	20	#include "llvm/MC/MCInstrDesc.h"
Dylan Noblesmith	7a3973d	2012-04-03 15:48:14 +0000	[diff] [blame]	21	#include "llvm/MC/MCSubtargetInfo.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	22	#include "llvm/Support/Debug.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	23	#include "llvm/Support/ErrorHandling.h"
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	24	#include "llvm/Support/LEB128.h"
Chandler Carruth	ed0881b	2012-12-03 16:50:05 +0000	[diff] [blame]	25	#include "llvm/Support/MemoryObject.h"
Evan Cheng	2bb4035	2011-08-24 18:08:43 +0000	[diff] [blame]	26	#include "llvm/Support/TargetRegistry.h"
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	27	#include "llvm/Support/raw_ostream.h"
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	28	#include <vector>
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	29
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	30	using namespace llvm;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	31
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	32	typedef MCDisassembler::DecodeStatus DecodeStatus;
				33
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	34	namespace {
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	35	// Handles the condition code status of instructions in IT blocks
				36	class ITStatus
				37	{
				38	public:
				39	// Returns the condition code for instruction in IT block
				40	unsigned getITCC() {
				41	unsigned CC = ARMCC::AL;
				42	if (instrInITBlock())
				43	CC = ITStates.back();
				44	return CC;
				45	}
				46
				47	// Advances the IT block state to the next T or E
				48	void advanceITState() {
				49	ITStates.pop_back();
				50	}
				51
				52	// Returns true if the current instruction is in an IT block
				53	bool instrInITBlock() {
				54	return !ITStates.empty();
				55	}
				56
				57	// Returns true if current instruction is the last instruction in an IT block
				58	bool instrLastInITBlock() {
				59	return ITStates.size() == 1;
				60	}
				61
				62	// Called when decoding an IT instruction. Sets the IT state for the following
				63	// instructions that for the IT block. Firstcond and Mask correspond to the
				64	// fields in the IT instruction encoding.
				65	void setITState(char Firstcond, char Mask) {
				66	// (3 - the number of trailing zeros) is the number of then / else.
Richard Barton	f435b09	2012-04-27 08:42:59 +0000	[diff] [blame]	67	unsigned CondBit0 = Firstcond & 1;
Michael J. Spencer	df1ecbd7	2013-05-24 22:23:49 +0000	[diff] [blame]	68	unsigned NumTZ = countTrailingZeros<uint8_t>(Mask);
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	69	unsigned char CCBits = static_cast<unsigned char>(Firstcond & 0xf);
				70	assert(NumTZ <= 3 && "Invalid IT mask!");
				71	// push condition codes onto the stack the correct order for the pops
				72	for (unsigned Pos = NumTZ+1; Pos <= 3; ++Pos) {
				73	bool T = ((Mask >> Pos) & 1) == CondBit0;
				74	if (T)
				75	ITStates.push_back(CCBits);
				76	else
				77	ITStates.push_back(CCBits ^ 1);
				78	}
				79	ITStates.push_back(CCBits);
				80	}
				81
				82	private:
				83	std::vector<unsigned char> ITStates;
				84	};
				85	}
				86
				87	namespace {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	88	/// ARMDisassembler - ARM disassembler for all ARM platforms.
				89	class ARMDisassembler : public MCDisassembler {
				90	public:
				91	/// Constructor - Initializes the disassembler.
				92	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	93	ARMDisassembler(const MCSubtargetInfo &STI) :
				94	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	95	}
				96
				97	~ARMDisassembler() {
				98	}
				99
				100	/// getInstruction - See MCDisassembler.
				101	DecodeStatus getInstruction(MCInst &instr,
				102	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	103	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	104	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	105	raw_ostream &vStream,
				106	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	107	};
				108
				109	/// ThumbDisassembler - Thumb disassembler for all Thumb platforms.
				110	class ThumbDisassembler : public MCDisassembler {
				111	public:
				112	/// Constructor - Initializes the disassembler.
				113	///
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	114	ThumbDisassembler(const MCSubtargetInfo &STI) :
				115	MCDisassembler(STI) {
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	116	}
				117
				118	~ThumbDisassembler() {
				119	}
				120
				121	/// getInstruction - See MCDisassembler.
				122	DecodeStatus getInstruction(MCInst &instr,
				123	uint64_t &size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	124	const MemoryObject &region,
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	125	uint64_t address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	126	raw_ostream &vStream,
				127	raw_ostream &cStream) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	128
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	129	private:
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	130	mutable ITStatus ITBlock;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	131	DecodeStatus AddThumbPredicate(MCInst&) const;
Owen Anderson	ed96b58	2011-09-01 23:35:51 +0000	[diff] [blame]	132	void UpdateThumbVFPPredicate(MCInst&) const;
				133	};
				134	}
				135
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	136	static bool Check(DecodeStatus &Out, DecodeStatus In) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	137	switch (In) {
				138	case MCDisassembler::Success:
				139	// Out stays the same.
				140	return true;
				141	case MCDisassembler::SoftFail:
				142	Out = In;
				143	return true;
				144	case MCDisassembler::Fail:
				145	Out = In;
				146	return false;
				147	}
David Blaikie	46a9f01	2012-01-20 21:51:11 +0000	[diff] [blame]	148	llvm_unreachable("Invalid DecodeStatus!");
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	149	}
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	150
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	151
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	152	// Forward declare these because the autogenerated code will reference them.
				153	// Definitions are further down.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	154	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	155	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	156	static DecodeStatus DecodeGPRnopcRegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	157	unsigned RegNo, uint64_t Address,
				158	const void *Decoder);
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	159	static DecodeStatus DecodeGPRwithAPSRRegisterClass(MCInst &Inst,
				160	unsigned RegNo, uint64_t Address,
				161	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	162	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	163	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	164	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	165	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	166	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	167	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	168	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				169	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	170	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	171	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	172	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	173	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	174	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	175	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	176	static DecodeStatus DecodeDPR_VFP2RegisterClass(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	177	unsigned RegNo,
				178	uint64_t Address,
				179	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	180	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	181	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	182	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	183	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	184	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	185	unsigned RegNo, uint64_t Address,
				186	const void *Decoder);
Johnny Chen	74491bb	2010-08-12 01:40:54 +0000	[diff] [blame]	187
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	188	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	189	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	190	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	191	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	192	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	193	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	194	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	195	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	196	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	197	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	198	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	199	uint64_t Address, const void *Decoder);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	200
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	201	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	202	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	203	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	204	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	205	static DecodeStatus DecodeAddrMode2IdxInstruction(MCInst &Inst,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	206	unsigned Insn,
				207	uint64_t Address,
				208	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	209	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	210	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	211	static DecodeStatus DecodeAddrMode3Instruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	212	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	213	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	214	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	215	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	216	uint64_t Address, const void *Decoder);
				217
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	218	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst & Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	219	unsigned Insn,
				220	uint64_t Adddress,
				221	const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	222	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	223	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	224	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	225	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	226	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	227	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	228	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	229	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	230	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	231	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	232	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	233	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	234	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	235	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	236	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	237	uint64_t Address, const void *Decoder);
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	238	static DecodeStatus DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				239	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	240	static DecodeStatus DecodeBranchImmInstruction(MCInst &Inst,unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	241	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	242	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	243	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	244	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Val,
				245	uint64_t Address, const void *Decoder);
				246	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Val,
				247	uint64_t Address, const void *Decoder);
				248	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Val,
				249	uint64_t Address, const void *Decoder);
				250	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Val,
				251	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	252	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	253	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	254	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	255	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	256	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	257	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	258	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	259	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	260	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	261	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	262	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	263	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	264	static DecodeStatus DecodeNEONModImmInstruction(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	265	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	266	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	267	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	268	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	269	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	270	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	271	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	272	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	273	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	274	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	275	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	276	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	277	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	278	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	279	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	280	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	281	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	282	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Insn,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	283	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	284	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Insn,
				285	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	286	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Insn,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	287	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	288	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	289	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	290	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	291	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	292	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	293	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	294	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	295	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	296	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	297	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	298	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	299	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	300	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	301	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	302	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	303	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	304	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	305	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	306	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	307	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	308	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	309	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	310	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	311	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	312	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	313	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	314	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	315	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	316	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	317	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	318	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	319	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	320	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	321	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	322	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	323	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	324	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	325	uint64_t Address, const void *Decoder);
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	326	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				327	const void *Decoder);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	328
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	329
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	330	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	331	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	332	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	333	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	334	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	335	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	336	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	337	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	338	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	339	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	340	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	341	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	342	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	343	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	344	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	345	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	346	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	347	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	348	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	349	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	350	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				351	uint64_t Address, const void* Decoder);
				352	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				353	uint64_t Address, const void* Decoder);
				354	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				355	uint64_t Address, const void* Decoder);
				356	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				357	uint64_t Address, const void* Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	358	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	359	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	360	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	361	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	362	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	363	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	364	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	365	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	366	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	367	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	368	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	369	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	370	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	371	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	372	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	373	uint64_t Address, const void *Decoder);
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	374	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				375	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	376	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	377	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	378	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	379	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	380	static DecodeStatus DecodeThumbTableBranch(MCInst &Inst, unsigned Val,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	381	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	382	static DecodeStatus DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	383	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	384	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	385	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	386	static DecodeStatus DecodeThumbBCCTargetOperand(MCInst &Inst,unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	387	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	388	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	389	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	390	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Val,
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	391	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	392	static DecodeStatus DecodeT2LDRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	393	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	394	static DecodeStatus DecodeT2STRDPreInstruction(MCInst &Inst,unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	395	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	396	static DecodeStatus DecodeT2Adr(MCInst &Inst, unsigned Val,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	397	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	398	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Val,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	399	uint64_t Address, const void *Decoder);
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	400	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	401	uint64_t Address, const void *Decoder);
				402
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	403	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	404	uint64_t Address, const void *Decoder);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	405	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				406	uint64_t Address, const void *Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	407	#include "ARMGenDisassemblerTables.inc"
Sean Callanan	814e69b	2010-04-13 21:21:57 +0000	[diff] [blame]	408
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	409	static MCDisassembler *createARMDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				410	return new ARMDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	411	}
				412
James Molloy	4c493e8	2011-09-07 17:24:38 +0000	[diff] [blame]	413	static MCDisassembler *createThumbDisassembler(const Target &T, const MCSubtargetInfo &STI) {
				414	return new ThumbDisassembler(STI);
Johnny Chen	7b999ea	2010-04-02 22:27:38 +0000	[diff] [blame]	415	}
				416
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	417	DecodeStatus ARMDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	418	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	419	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	420	raw_ostream &os,
				421	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	422	CommentStream = &cs;
				423
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	424	uint8_t bytes[4];
				425
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	426	assert(!(STI.getFeatureBits() & ARM::ModeThumb) &&
				427	"Asked to disassemble an ARM instruction but Subtarget is in Thumb mode!");
				428
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	429	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	430	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	431	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	432	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	433	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	434
				435	// Encoded as a small-endian 32-bit word in the stream.
				436	uint32_t insn = (bytes[3] << 24) \|
				437	(bytes[2] << 16) \|
				438	(bytes[1] << 8) \|
				439	(bytes[0] << 0);
				440
				441	// Calling the auto-generated decoder function.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	442	DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
				443	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	444	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	445	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	446	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	447	}
				448
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	449	// VFP and NEON instructions, similarly, are shared between ARM
				450	// and Thumb modes.
				451	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	452	result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	453	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	454	Size = 4;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	455	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	456	}
				457
				458	MI.clear();
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	459	result = decodeInstruction(DecoderTableVFPV832, MI, insn, Address, this, STI);
				460	if (result != MCDisassembler::Fail) {
				461	Size = 4;
				462	return result;
				463	}
				464
				465	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	466	result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
				467	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	468	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	469	Size = 4;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	470	// Add a fake predicate operand, because we share these instruction
				471	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	472	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				473	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	474	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	475	}
				476
				477	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	478	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
				479	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	480	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	481	Size = 4;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	482	// Add a fake predicate operand, because we share these instruction
				483	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	484	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				485	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	486	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	487	}
				488
				489	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	490	result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
				491	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	492	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	493	Size = 4;
				494	// Add a fake predicate operand, because we share these instruction
				495	// definitions with Thumb2 where these instructions are predicable.
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	496	if (!DecodePredicateOperand(MI, 0xE, Address, this))
				497	return MCDisassembler::Fail;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	498	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	499	}
				500
				501	MI.clear();
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	502	result = decodeInstruction(DecoderTablev8NEON32, MI, insn, Address,
				503	this, STI);
				504	if (result != MCDisassembler::Fail) {
				505	Size = 4;
				506	return result;
				507	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	508
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	509	MI.clear();
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame^]	510	result = decodeInstruction(DecoderTablev8Crypto32, MI, insn, Address,
				511	this, STI);
				512	if (result != MCDisassembler::Fail) {
				513	Size = 4;
				514	return result;
				515	}
				516
				517	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	518	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	519	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	520	}
				521
				522	namespace llvm {
Benjamin Kramer	0d6d098	2011-10-22 16:50:00 +0000	[diff] [blame]	523	extern const MCInstrDesc ARMInsts[];
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	524	}
				525
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	526	/// tryAddingSymbolicOperand - trys to add a symbolic operand in place of the
				527	/// immediate Value in the MCInst. The immediate Value has had any PC
				528	/// adjustment made by the caller. If the instruction is a branch instruction
				529	/// then isBranch is true, else false. If the getOpInfo() function was set as
				530	/// part of the setupForSymbolicDisassembly() call then that function is called
				531	/// to get any symbolic information at the Address for this instruction. If
				532	/// that returns non-zero then the symbolic information it returns is used to
				533	/// create an MCExpr and that is added as an operand to the MCInst. If
				534	/// getOpInfo() returns zero and isBranch is true then a symbol look up for
				535	/// Value is done and if a symbol is found an MCExpr is created with that, else
				536	/// an MCExpr with Value is created. This function returns true if it adds an
				537	/// operand to the MCInst and false otherwise.
				538	static bool tryAddingSymbolicOperand(uint64_t Address, int32_t Value,
				539	bool isBranch, uint64_t InstSize,
				540	MCInst &MI, const void *Decoder) {
				541	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	542	// FIXME: Does it make sense for value to be negative?
				543	return Dis->tryAddingSymbolicOperand(MI, (uint32_t)Value, Address, isBranch,
				544	/* Offset */ 0, InstSize);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	545	}
				546
				547	/// tryAddingPcLoadReferenceComment - trys to add a comment as to what is being
				548	/// referenced by a load instruction with the base register that is the Pc.
				549	/// These can often be values in a literal pool near the Address of the
				550	/// instruction. The Address of the instruction and its immediate Value are
				551	/// used as a possible literal pool entry. The SymbolLookUp call back will
Sylvestre Ledru	35521e2	2012-07-23 08:51:15 +0000	[diff] [blame]	552	/// return the name of a symbol referenced by the literal pool's entry if
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	553	/// the referenced address is that of a symbol. Or it will return a pointer to
				554	/// a literal 'C' string if the referenced address of the literal pool's entry
				555	/// is an address into a section with 'C' string literals.
				556	static void tryAddingPcLoadReferenceComment(uint64_t Address, int Value,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	557	const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	558	const MCDisassembler Dis = static_cast<const MCDisassembler>(Decoder);
Ahmed Bougacha	ad1084d	2013-05-24 00:39:57 +0000	[diff] [blame]	559	Dis->tryAddingPcLoadReferenceComment(Value, Address);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	560	}
				561
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	562	// Thumb1 instructions don't have explicit S bits. Rather, they
				563	// implicitly set CPSR. Since it's not represented in the encoding, the
				564	// auto-generated decoder won't inject the CPSR operand. We need to fix
				565	// that as a post-pass.
				566	static void AddThumb1SBit(MCInst &MI, bool InITBlock) {
				567	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	568	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	569	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	570	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				571	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	572	if (OpInfo[i].isOptionalDef() && OpInfo[i].RegClass == ARM::CCRRegClassID) {
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	573	if (i > 0 && OpInfo[i-1].isPredicate()) continue;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	574	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
				575	return;
				576	}
				577	}
				578
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	579	MI.insert(I, MCOperand::CreateReg(InITBlock ? 0 : ARM::CPSR));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	580	}
				581
				582	// Most Thumb instructions don't have explicit predicates in the
				583	// encoding, but rather get their predicates from IT context. We need
				584	// to fix up the predicate operands using this context information as a
				585	// post-pass.
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	586	MCDisassembler::DecodeStatus
				587	ThumbDisassembler::AddThumbPredicate(MCInst &MI) const {
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	588	MCDisassembler::DecodeStatus S = Success;
				589
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	590	// A few instructions actually have predicates encoded in them. Don't
				591	// try to overwrite it if we're seeing one of those.
				592	switch (MI.getOpcode()) {
				593	case ARM::tBcc:
				594	case ARM::t2Bcc:
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	595	case ARM::tCBZ:
				596	case ARM::tCBNZ:
Owen Anderson	61e4604	2011-09-19 23:47:10 +0000	[diff] [blame]	597	case ARM::tCPS:
				598	case ARM::t2CPS3p:
				599	case ARM::t2CPS2p:
				600	case ARM::t2CPS1p:
Owen Anderson	163be01	2011-09-19 23:57:20 +0000	[diff] [blame]	601	case ARM::tMOVSr:
Owen Anderson	44f76ea	2011-10-13 17:58:39 +0000	[diff] [blame]	602	case ARM::tSETEND:
Owen Anderson	33d3953	2011-09-08 22:48:37 +0000	[diff] [blame]	603	// Some instructions (mostly conditional branches) are not
				604	// allowed in IT blocks.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	605	if (ITBlock.instrInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	606	S = SoftFail;
				607	else
				608	return Success;
				609	break;
				610	case ARM::tB:
				611	case ARM::t2B:
Owen Anderson	f902d92	2011-09-19 22:34:23 +0000	[diff] [blame]	612	case ARM::t2TBB:
				613	case ARM::t2TBH:
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	614	// Some instructions (mostly unconditional branches) can
				615	// only appears at the end of, or outside of, an IT.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	616	if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	617	S = SoftFail;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	618	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	619	default:
				620	break;
				621	}
				622
				623	// If we're in an IT block, base the predicate on that. Otherwise,
				624	// assume a predicate of AL.
				625	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	626	CC = ITBlock.getITCC();
				627	if (CC == 0xF)
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	628	CC = ARMCC::AL;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	629	if (ITBlock.instrInITBlock())
				630	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	631
				632	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	633	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	634	MCInst::iterator I = MI.begin();
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	635	for (unsigned i = 0; i < NumOps; ++i, ++I) {
				636	if (I == MI.end()) break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	637	if (OpInfo[i].isPredicate()) {
				638	I = MI.insert(I, MCOperand::CreateImm(CC));
				639	++I;
				640	if (CC == ARMCC::AL)
				641	MI.insert(I, MCOperand::CreateReg(0));
				642	else
				643	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	644	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	645	}
				646	}
				647
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	648	I = MI.insert(I, MCOperand::CreateImm(CC));
				649	++I;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	650	if (CC == ARMCC::AL)
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	651	MI.insert(I, MCOperand::CreateReg(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	652	else
Owen Anderson	187e1e4	2011-08-17 18:14:48 +0000	[diff] [blame]	653	MI.insert(I, MCOperand::CreateReg(ARM::CPSR));
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	654
Owen Anderson	29cfe6c	2011-09-09 21:48:23 +0000	[diff] [blame]	655	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	656	}
				657
				658	// Thumb VFP instructions are a special case. Because we share their
				659	// encodings between ARM and Thumb modes, and they are predicable in ARM
				660	// mode, the auto-generated decoder will give them an (incorrect)
				661	// predicate operand. We need to rewrite these operands based on the IT
				662	// context as a post-pass.
				663	void ThumbDisassembler::UpdateThumbVFPPredicate(MCInst &MI) const {
				664	unsigned CC;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	665	CC = ITBlock.getITCC();
				666	if (ITBlock.instrInITBlock())
				667	ITBlock.advanceITState();
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	668
				669	const MCOperandInfo *OpInfo = ARMInsts[MI.getOpcode()].OpInfo;
				670	MCInst::iterator I = MI.begin();
Owen Anderson	216cfaa	2011-08-24 21:35:46 +0000	[diff] [blame]	671	unsigned short NumOps = ARMInsts[MI.getOpcode()].NumOperands;
				672	for (unsigned i = 0; i < NumOps; ++i, ++I) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	673	if (OpInfo[i].isPredicate() ) {
				674	I->setImm(CC);
				675	++I;
				676	if (CC == ARMCC::AL)
				677	I->setReg(0);
				678	else
				679	I->setReg(ARM::CPSR);
				680	return;
				681	}
				682	}
				683	}
				684
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	685	DecodeStatus ThumbDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
Derek Schuff	56b662c	2012-02-29 01:09:06 +0000	[diff] [blame]	686	const MemoryObject &Region,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	687	uint64_t Address,
Owen Anderson	a0c3b97	2011-09-15 23:38:46 +0000	[diff] [blame]	688	raw_ostream &os,
				689	raw_ostream &cs) const {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	690	CommentStream = &cs;
				691
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	692	uint8_t bytes[4];
				693
James Molloy	8067df9	2011-09-07 19:42:28 +0000	[diff] [blame]	694	assert((STI.getFeatureBits() & ARM::ModeThumb) &&
				695	"Asked to disassemble in Thumb mode but Subtarget is in ARM mode!");
				696
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	697	// We want to read exactly 2 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	698	if (Region.readBytes(Address, 2, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	699	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	700	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	701	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	702
				703	uint16_t insn16 = (bytes[1] << 8) \| bytes[0];
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	704	DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
				705	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	706	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	707	Size = 2;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	708	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	709	return result;
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	710	}
				711
				712	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	713	result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
				714	Address, this, STI);
Owen Anderson	91a8f9b	2011-08-16 23:45:44 +0000	[diff] [blame]	715	if (result) {
				716	Size = 2;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	717	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	718	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	719	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	720	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	721	}
				722
				723	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	724	result = decodeInstruction(DecoderTableThumb216, MI, insn16,
				725	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	726	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	727	Size = 2;
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	728
				729	// Nested IT blocks are UNPREDICTABLE. Must be checked before we add
				730	// the Thumb predicate.
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	731	if (MI.getOpcode() == ARM::t2IT && ITBlock.instrInITBlock())
Owen Anderson	6a5c150	2011-10-06 23:33:11 +0000	[diff] [blame]	732	result = MCDisassembler::SoftFail;
				733
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	734	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	735
				736	// If we find an IT instruction, we need to parse its condition
				737	// code and mask operands so that we can apply them correctly
				738	// to the subsequent instructions.
				739	if (MI.getOpcode() == ARM::t2IT) {
Owen Anderson	f1e3844	2011-09-14 21:06:21 +0000	[diff] [blame]	740
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	741	unsigned Firstcond = MI.getOperand(0).getImm();
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	742	unsigned Mask = MI.getOperand(1).getImm();
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	743	ITBlock.setITState(Firstcond, Mask);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	744	}
				745
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	746	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	747	}
				748
				749	// We want to read exactly 4 bytes of data.
Benjamin Kramer	534d3a4	2013-05-24 10:54:58 +0000	[diff] [blame]	750	if (Region.readBytes(Address, 4, bytes) == -1) {
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	751	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	752	return MCDisassembler::Fail;
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	753	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	754
				755	uint32_t insn32 = (bytes[3] << 8) \|
				756	(bytes[2] << 0) \|
				757	(bytes[1] << 24) \|
				758	(bytes[0] << 16);
				759	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	760	result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
				761	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	762	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	763	Size = 4;
Richard Barton	e960000	2012-04-24 11:13:20 +0000	[diff] [blame]	764	bool InITBlock = ITBlock.instrInITBlock();
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	765	Check(result, AddThumbPredicate(MI));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	766	AddThumb1SBit(MI, InITBlock);
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	767	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	768	}
				769
				770	MI.clear();
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	771	result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
				772	this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	773	if (result != MCDisassembler::Fail) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	774	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	775	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	776	return result;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	777	}
				778
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	779	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				780	MI.clear();
				781	result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
				782	if (result != MCDisassembler::Fail) {
				783	Size = 4;
				784	UpdateThumbVFPPredicate(MI);
				785	return result;
				786	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	787	}
				788
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	789	MI.clear();
				790	result = decodeInstruction(DecoderTableVFPV832, MI, insn32, Address, this, STI);
				791	if (result != MCDisassembler::Fail) {
				792	Size = 4;
Joey Gouly	cc4ff9e	2013-07-04 14:57:20 +0000	[diff] [blame]	793	return result;
				794	}
				795
Amaury de la Vieuville	8449c0d	2013-06-24 09:15:01 +0000	[diff] [blame]	796	if (fieldFromInstruction(insn32, 28, 4) == 0xE) {
				797	MI.clear();
				798	result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
				799	this, STI);
				800	if (result != MCDisassembler::Fail) {
				801	Size = 4;
				802	Check(result, AddThumbPredicate(MI));
				803	return result;
				804	}
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	805	}
				806
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	807	if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	808	MI.clear();
				809	uint32_t NEONLdStInsn = insn32;
				810	NEONLdStInsn &= 0xF0FFFFFF;
				811	NEONLdStInsn \|= 0x04000000;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	812	result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
				813	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	814	if (result != MCDisassembler::Fail) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	815	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	816	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	817	return result;
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	818	}
				819	}
				820
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	821	if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
Owen Anderson	a6201f0	2011-08-15 23:38:54 +0000	[diff] [blame]	822	MI.clear();
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	823	uint32_t NEONDataInsn = insn32;
				824	NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
				825	NEONDataInsn \|= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				826	NEONDataInsn \|= 0x12000000; // Set bits 28 and 25
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	827	result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
				828	Address, this, STI);
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	829	if (result != MCDisassembler::Fail) {
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	830	Size = 4;
Owen Anderson	2fefa42	2011-09-08 22:42:49 +0000	[diff] [blame]	831	Check(result, AddThumbPredicate(MI));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	832	return result;
Owen Anderson	c86a5bd	2011-08-10 19:01:10 +0000	[diff] [blame]	833	}
				834	}
				835
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	836	MI.clear();
Amara Emerson	3308909	2013-09-19 11:59:01 +0000	[diff] [blame^]	837	uint32_t NEONCryptoInsn = insn32;
				838	NEONCryptoInsn &= 0xF0FFFFFF; // Clear bits 27-24
				839	NEONCryptoInsn \|= (NEONCryptoInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
				840	NEONCryptoInsn \|= 0x12000000; // Set bits 28 and 25
				841	result = decodeInstruction(DecoderTablev8Crypto32, MI, NEONCryptoInsn,
				842	Address, this, STI);
				843	if (result != MCDisassembler::Fail) {
				844	Size = 4;
				845	return result;
				846	}
				847
				848	MI.clear();
Joey Gouly	df68600	2013-07-17 13:59:38 +0000	[diff] [blame]	849	uint32_t NEONv8Insn = insn32;
				850	NEONv8Insn &= 0xF3FFFFFF; // Clear bits 27-26
				851	result = decodeInstruction(DecoderTablev8NEON32, MI, NEONv8Insn, Address,
				852	this, STI);
				853	if (result != MCDisassembler::Fail) {
				854	Size = 4;
				855	return result;
				856	}
				857
				858	MI.clear();
Benjamin Kramer	aa38dba	2011-08-26 18:21:36 +0000	[diff] [blame]	859	Size = 0;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	860	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	861	}
				862
				863
				864	extern "C" void LLVMInitializeARMDisassembler() {
				865	TargetRegistry::RegisterMCDisassembler(TheARMTarget,
				866	createARMDisassembler);
				867	TargetRegistry::RegisterMCDisassembler(TheThumbTarget,
				868	createThumbDisassembler);
				869	}
				870
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	871	static const uint16_t GPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	872	ARM::R0, ARM::R1, ARM::R2, ARM::R3,
				873	ARM::R4, ARM::R5, ARM::R6, ARM::R7,
				874	ARM::R8, ARM::R9, ARM::R10, ARM::R11,
				875	ARM::R12, ARM::SP, ARM::LR, ARM::PC
				876	};
				877
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	878	static DecodeStatus DecodeGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	879	uint64_t Address, const void *Decoder) {
				880	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	881	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	882
				883	unsigned Register = GPRDecoderTable[RegNo];
				884	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	885	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	886	}
				887
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	888	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	889	DecodeGPRnopcRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	890	uint64_t Address, const void *Decoder) {
Silviu Baranga	32a4933	2012-03-20 15:54:56 +0000	[diff] [blame]	891	DecodeStatus S = MCDisassembler::Success;
				892
				893	if (RegNo == 15)
				894	S = MCDisassembler::SoftFail;
				895
				896	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				897
				898	return S;
Owen Anderson	042619f	2011-08-09 22:48:45 +0000	[diff] [blame]	899	}
				900
Mihai Popa	dc1764c5	2013-05-13 14:10:04 +0000	[diff] [blame]	901	static DecodeStatus
				902	DecodeGPRwithAPSRRegisterClass(MCInst &Inst, unsigned RegNo,
				903	uint64_t Address, const void *Decoder) {
				904	DecodeStatus S = MCDisassembler::Success;
				905
				906	if (RegNo == 15)
				907	{
				908	Inst.addOperand(MCOperand::CreateReg(ARM::APSR_NZCV));
				909	return MCDisassembler::Success;
				910	}
				911
				912	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				913	return S;
				914	}
				915
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	916	static DecodeStatus DecodetGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	917	uint64_t Address, const void *Decoder) {
				918	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	919	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	920	return DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder);
				921	}
				922
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	923	static const uint16_t GPRPairDecoderTable[] = {
				924	ARM::R0_R1, ARM::R2_R3, ARM::R4_R5, ARM::R6_R7,
				925	ARM::R8_R9, ARM::R10_R11, ARM::R12_SP
				926	};
				927
				928	static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, unsigned RegNo,
				929	uint64_t Address, const void *Decoder) {
				930	DecodeStatus S = MCDisassembler::Success;
				931
				932	if (RegNo > 13)
				933	return MCDisassembler::Fail;
				934
				935	if ((RegNo & 1) \|\| RegNo == 0xe)
				936	S = MCDisassembler::SoftFail;
				937
				938	unsigned RegisterPair = GPRPairDecoderTable[RegNo/2];
				939	Inst.addOperand(MCOperand::CreateReg(RegisterPair));
				940	return S;
				941	}
				942
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	943	static DecodeStatus DecodetcGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	944	uint64_t Address, const void *Decoder) {
				945	unsigned Register = 0;
				946	switch (RegNo) {
				947	case 0:
				948	Register = ARM::R0;
				949	break;
				950	case 1:
				951	Register = ARM::R1;
				952	break;
				953	case 2:
				954	Register = ARM::R2;
				955	break;
				956	case 3:
				957	Register = ARM::R3;
				958	break;
				959	case 9:
				960	Register = ARM::R9;
				961	break;
				962	case 12:
				963	Register = ARM::R12;
				964	break;
				965	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	966	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	967	}
				968
				969	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	970	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	971	}
				972
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	973	static DecodeStatus DecoderGPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	974	uint64_t Address, const void *Decoder) {
Amaury de la Vieuville	8175bda	2013-06-24 09:14:54 +0000	[diff] [blame]	975	DecodeStatus S = MCDisassembler::Success;
				976	if (RegNo == 13 \|\| RegNo == 15)
				977	S = MCDisassembler::SoftFail;
				978	Check(S, DecodeGPRRegisterClass(Inst, RegNo, Address, Decoder));
				979	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	980	}
				981
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	982	static const uint16_t SPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	983	ARM::S0, ARM::S1, ARM::S2, ARM::S3,
				984	ARM::S4, ARM::S5, ARM::S6, ARM::S7,
				985	ARM::S8, ARM::S9, ARM::S10, ARM::S11,
				986	ARM::S12, ARM::S13, ARM::S14, ARM::S15,
				987	ARM::S16, ARM::S17, ARM::S18, ARM::S19,
				988	ARM::S20, ARM::S21, ARM::S22, ARM::S23,
				989	ARM::S24, ARM::S25, ARM::S26, ARM::S27,
				990	ARM::S28, ARM::S29, ARM::S30, ARM::S31
				991	};
				992
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	993	static DecodeStatus DecodeSPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	994	uint64_t Address, const void *Decoder) {
				995	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	996	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	997
				998	unsigned Register = SPRDecoderTable[RegNo];
				999	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1000	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1001	}
				1002
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1003	static const uint16_t DPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1004	ARM::D0, ARM::D1, ARM::D2, ARM::D3,
				1005	ARM::D4, ARM::D5, ARM::D6, ARM::D7,
				1006	ARM::D8, ARM::D9, ARM::D10, ARM::D11,
				1007	ARM::D12, ARM::D13, ARM::D14, ARM::D15,
				1008	ARM::D16, ARM::D17, ARM::D18, ARM::D19,
				1009	ARM::D20, ARM::D21, ARM::D22, ARM::D23,
				1010	ARM::D24, ARM::D25, ARM::D26, ARM::D27,
				1011	ARM::D28, ARM::D29, ARM::D30, ARM::D31
				1012	};
				1013
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1014	static DecodeStatus DecodeDPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1015	uint64_t Address, const void *Decoder) {
				1016	if (RegNo > 31)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1017	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1018
				1019	unsigned Register = DPRDecoderTable[RegNo];
				1020	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1021	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1022	}
				1023
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1024	static DecodeStatus DecodeDPR_8RegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1025	uint64_t Address, const void *Decoder) {
				1026	if (RegNo > 7)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1027	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1028	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1029	}
				1030
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1031	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1032	DecodeDPR_VFP2RegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1033	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1034	if (RegNo > 15)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1035	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1036	return DecodeDPRRegisterClass(Inst, RegNo, Address, Decoder);
				1037	}
				1038
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1039	static const uint16_t QPRDecoderTable[] = {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1040	ARM::Q0, ARM::Q1, ARM::Q2, ARM::Q3,
				1041	ARM::Q4, ARM::Q5, ARM::Q6, ARM::Q7,
				1042	ARM::Q8, ARM::Q9, ARM::Q10, ARM::Q11,
				1043	ARM::Q12, ARM::Q13, ARM::Q14, ARM::Q15
				1044	};
				1045
				1046
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1047	static DecodeStatus DecodeQPRRegisterClass(MCInst &Inst, unsigned RegNo,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1048	uint64_t Address, const void *Decoder) {
Mihai Popa	dcf0922	2013-05-20 14:42:43 +0000	[diff] [blame]	1049	if (RegNo > 31 \|\| (RegNo & 1) != 0)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1050	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1051	RegNo >>= 1;
				1052
				1053	unsigned Register = QPRDecoderTable[RegNo];
				1054	Inst.addOperand(MCOperand::CreateReg(Register));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1055	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1056	}
				1057
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1058	static const uint16_t DPairDecoderTable[] = {
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1059	ARM::Q0, ARM::D1_D2, ARM::Q1, ARM::D3_D4, ARM::Q2, ARM::D5_D6,
				1060	ARM::Q3, ARM::D7_D8, ARM::Q4, ARM::D9_D10, ARM::Q5, ARM::D11_D12,
				1061	ARM::Q6, ARM::D13_D14, ARM::Q7, ARM::D15_D16, ARM::Q8, ARM::D17_D18,
				1062	ARM::Q9, ARM::D19_D20, ARM::Q10, ARM::D21_D22, ARM::Q11, ARM::D23_D24,
				1063	ARM::Q12, ARM::D25_D26, ARM::Q13, ARM::D27_D28, ARM::Q14, ARM::D29_D30,
				1064	ARM::Q15
				1065	};
				1066
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1067	static DecodeStatus DecodeDPairRegisterClass(MCInst &Inst, unsigned RegNo,
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	1068	uint64_t Address, const void *Decoder) {
				1069	if (RegNo > 30)
				1070	return MCDisassembler::Fail;
				1071
				1072	unsigned Register = DPairDecoderTable[RegNo];
				1073	Inst.addOperand(MCOperand::CreateReg(Register));
				1074	return MCDisassembler::Success;
				1075	}
				1076
Craig Topper	ca658c2	2012-03-11 07:16:55 +0000	[diff] [blame]	1077	static const uint16_t DPairSpacedDecoderTable[] = {
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1078	ARM::D0_D2, ARM::D1_D3, ARM::D2_D4, ARM::D3_D5,
				1079	ARM::D4_D6, ARM::D5_D7, ARM::D6_D8, ARM::D7_D9,
				1080	ARM::D8_D10, ARM::D9_D11, ARM::D10_D12, ARM::D11_D13,
				1081	ARM::D12_D14, ARM::D13_D15, ARM::D14_D16, ARM::D15_D17,
				1082	ARM::D16_D18, ARM::D17_D19, ARM::D18_D20, ARM::D19_D21,
				1083	ARM::D20_D22, ARM::D21_D23, ARM::D22_D24, ARM::D23_D25,
				1084	ARM::D24_D26, ARM::D25_D27, ARM::D26_D28, ARM::D27_D29,
				1085	ARM::D28_D30, ARM::D29_D31
				1086	};
				1087
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1088	static DecodeStatus DecodeDPairSpacedRegisterClass(MCInst &Inst,
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	1089	unsigned RegNo,
				1090	uint64_t Address,
				1091	const void *Decoder) {
				1092	if (RegNo > 29)
				1093	return MCDisassembler::Fail;
				1094
				1095	unsigned Register = DPairSpacedDecoderTable[RegNo];
				1096	Inst.addOperand(MCOperand::CreateReg(Register));
				1097	return MCDisassembler::Success;
				1098	}
				1099
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1100	static DecodeStatus DecodePredicateOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1101	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1102	if (Val == 0xF) return MCDisassembler::Fail;
Owen Anderson	7a2401d	2011-08-09 21:07:45 +0000	[diff] [blame]	1103	// AL predicate is not allowed on Thumb1 branches.
				1104	if (Inst.getOpcode() == ARM::tBcc && Val == 0xE)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1105	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1106	Inst.addOperand(MCOperand::CreateImm(Val));
				1107	if (Val == ARMCC::AL) {
				1108	Inst.addOperand(MCOperand::CreateReg(0));
				1109	} else
				1110	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1111	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1112	}
				1113
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1114	static DecodeStatus DecodeCCOutOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1115	uint64_t Address, const void *Decoder) {
				1116	if (Val)
				1117	Inst.addOperand(MCOperand::CreateReg(ARM::CPSR));
				1118	else
				1119	Inst.addOperand(MCOperand::CreateReg(0));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1120	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1121	}
				1122
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1123	static DecodeStatus DecodeSOImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1124	uint64_t Address, const void *Decoder) {
				1125	uint32_t imm = Val & 0xFF;
				1126	uint32_t rot = (Val & 0xF00) >> 7;
Eli Friedman	a7ad9f3	2011-10-13 23:36:06 +0000	[diff] [blame]	1127	uint32_t rot_imm = (imm >> rot) \| (imm << ((32-rot) & 0x1F));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1128	Inst.addOperand(MCOperand::CreateImm(rot_imm));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1129	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1130	}
				1131
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1132	static DecodeStatus DecodeSORegImmOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1133	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1134	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1135
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1136	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1137	unsigned type = fieldFromInstruction(Val, 5, 2);
				1138	unsigned imm = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1139
				1140	// Register-immediate
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1141	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1142	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1143
				1144	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1145	switch (type) {
				1146	case 0:
				1147	Shift = ARM_AM::lsl;
				1148	break;
				1149	case 1:
				1150	Shift = ARM_AM::lsr;
				1151	break;
				1152	case 2:
				1153	Shift = ARM_AM::asr;
				1154	break;
				1155	case 3:
				1156	Shift = ARM_AM::ror;
				1157	break;
				1158	}
				1159
				1160	if (Shift == ARM_AM::ror && imm == 0)
				1161	Shift = ARM_AM::rrx;
				1162
				1163	unsigned Op = Shift \| (imm << 3);
				1164	Inst.addOperand(MCOperand::CreateImm(Op));
				1165
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1166	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1167	}
				1168
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1169	static DecodeStatus DecodeSORegRegOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1170	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1171	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1172
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1173	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1174	unsigned type = fieldFromInstruction(Val, 5, 2);
				1175	unsigned Rs = fieldFromInstruction(Val, 8, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1176
				1177	// Register-register
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1178	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1179	return MCDisassembler::Fail;
				1180	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rs, Address, Decoder)))
				1181	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1182
				1183	ARM_AM::ShiftOpc Shift = ARM_AM::lsl;
				1184	switch (type) {
				1185	case 0:
				1186	Shift = ARM_AM::lsl;
				1187	break;
				1188	case 1:
				1189	Shift = ARM_AM::lsr;
				1190	break;
				1191	case 2:
				1192	Shift = ARM_AM::asr;
				1193	break;
				1194	case 3:
				1195	Shift = ARM_AM::ror;
				1196	break;
				1197	}
				1198
				1199	Inst.addOperand(MCOperand::CreateImm(Shift));
				1200
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1201	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1202	}
				1203
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1204	static DecodeStatus DecodeRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1205	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1206	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1207
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1208	bool writebackLoad = false;
				1209	unsigned writebackReg = 0;
				1210	switch (Inst.getOpcode()) {
				1211	default:
				1212	break;
				1213	case ARM::LDMIA_UPD:
				1214	case ARM::LDMDB_UPD:
				1215	case ARM::LDMIB_UPD:
				1216	case ARM::LDMDA_UPD:
				1217	case ARM::t2LDMIA_UPD:
				1218	case ARM::t2LDMDB_UPD:
				1219	writebackLoad = true;
				1220	writebackReg = Inst.getOperand(0).getReg();
				1221	break;
				1222	}
				1223
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	1224	// Empty register lists are not allowed.
Benjamin Kramer	8bad66e	2013-05-19 22:01:57 +0000	[diff] [blame]	1225	if (Val == 0) return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1226	for (unsigned i = 0; i < 16; ++i) {
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1227	if (Val & (1 << i)) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1228	if (!Check(S, DecodeGPRRegisterClass(Inst, i, Address, Decoder)))
				1229	return MCDisassembler::Fail;
Owen Anderson	53db43b	2011-09-09 23:13:33 +0000	[diff] [blame]	1230	// Writeback not allowed if Rn is in the target list.
				1231	if (writebackLoad && writebackReg == Inst.end()[-1].getReg())
				1232	Check(S, MCDisassembler::SoftFail);
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1233	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1234	}
				1235
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1236	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1237	}
				1238
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1239	static DecodeStatus DecodeSPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1240	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1241	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1242
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1243	unsigned Vd = fieldFromInstruction(Val, 8, 5);
				1244	unsigned regs = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1245
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1246	// In case of unpredictable encoding, tweak the operands.
				1247	if (regs == 0 \|\| (Vd + regs) > 32) {
				1248	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1249	regs = std::max( 1u, regs);
				1250	S = MCDisassembler::SoftFail;
				1251	}
				1252
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1253	if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
				1254	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1255	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1256	if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1257	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1258	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1259
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1260	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1261	}
				1262
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1263	static DecodeStatus DecodeDPRRegListOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1264	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1265	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1266
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1267	unsigned Vd = fieldFromInstruction(Val, 8, 5);
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1268	unsigned regs = fieldFromInstruction(Val, 1, 7);
Silviu Baranga	9560af8	2012-05-03 16:38:40 +0000	[diff] [blame]	1269
Tim Northover	4173e29	2013-05-31 15:55:51 +0000	[diff] [blame]	1270	// In case of unpredictable encoding, tweak the operands.
				1271	if (regs == 0 \|\| regs > 16 \|\| (Vd + regs) > 32) {
				1272	regs = Vd + regs > 32 ? 32 - Vd : regs;
				1273	regs = std::max( 1u, regs);
				1274	regs = std::min(16u, regs);
				1275	S = MCDisassembler::SoftFail;
				1276	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1277
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1278	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				1279	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1280	for (unsigned i = 0; i < (regs - 1); ++i) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1281	if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder)))
				1282	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	1283	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1284
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1285	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1286	}
				1287
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1288	static DecodeStatus DecodeBitfieldMaskOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1289	uint64_t Address, const void *Decoder) {
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1290	// This operand encodes a mask of contiguous zeros between a specified MSB
				1291	// and LSB. To decode it, we create the mask of all bits MSB-and-lower,
				1292	// the mask of all bits LSB-and-lower, and then xor them to create
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1293	// the mask of that's all ones on [msb, lsb]. Finally we not it to
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	1294	// create the final mask.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1295	unsigned msb = fieldFromInstruction(Val, 5, 5);
				1296	unsigned lsb = fieldFromInstruction(Val, 0, 5);
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1297
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1298	DecodeStatus S = MCDisassembler::Success;
Kevin Enderby	136d674	2012-11-29 23:47:11 +0000	[diff] [blame]	1299	if (lsb > msb) {
				1300	Check(S, MCDisassembler::SoftFail);
				1301	// The check above will cause the warning for the "potentially undefined
				1302	// instruction encoding" but we can't build a bad MCOperand value here
				1303	// with a lsb > msb or else printing the MCInst will cause a crash.
				1304	lsb = msb;
				1305	}
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1306
Owen Anderson	b925e93	2011-09-16 23:04:48 +0000	[diff] [blame]	1307	uint32_t msb_mask = 0xFFFFFFFF;
				1308	if (msb != 31) msb_mask = (1U << (msb+1)) - 1;
				1309	uint32_t lsb_mask = (1U << lsb) - 1;
Owen Anderson	3ca958c	2011-09-16 22:29:48 +0000	[diff] [blame]	1310
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1311	Inst.addOperand(MCOperand::CreateImm(~(msb_mask ^ lsb_mask)));
Owen Anderson	502cd9d	2011-09-16 23:30:01 +0000	[diff] [blame]	1312	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1313	}
				1314
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1315	static DecodeStatus DecodeCopMemInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1316	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1317	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1318
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1319	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1320	unsigned CRd = fieldFromInstruction(Insn, 12, 4);
				1321	unsigned coproc = fieldFromInstruction(Insn, 8, 4);
				1322	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				1323	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1324	unsigned U = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1325
				1326	switch (Inst.getOpcode()) {
				1327	case ARM::LDC_OFFSET:
				1328	case ARM::LDC_PRE:
				1329	case ARM::LDC_POST:
				1330	case ARM::LDC_OPTION:
				1331	case ARM::LDCL_OFFSET:
				1332	case ARM::LDCL_PRE:
				1333	case ARM::LDCL_POST:
				1334	case ARM::LDCL_OPTION:
				1335	case ARM::STC_OFFSET:
				1336	case ARM::STC_PRE:
				1337	case ARM::STC_POST:
				1338	case ARM::STC_OPTION:
				1339	case ARM::STCL_OFFSET:
				1340	case ARM::STCL_PRE:
				1341	case ARM::STCL_POST:
				1342	case ARM::STCL_OPTION:
Owen Anderson	18d17aa	2011-09-07 21:10:42 +0000	[diff] [blame]	1343	case ARM::t2LDC_OFFSET:
				1344	case ARM::t2LDC_PRE:
				1345	case ARM::t2LDC_POST:
				1346	case ARM::t2LDC_OPTION:
				1347	case ARM::t2LDCL_OFFSET:
				1348	case ARM::t2LDCL_PRE:
				1349	case ARM::t2LDCL_POST:
				1350	case ARM::t2LDCL_OPTION:
				1351	case ARM::t2STC_OFFSET:
				1352	case ARM::t2STC_PRE:
				1353	case ARM::t2STC_POST:
				1354	case ARM::t2STC_OPTION:
				1355	case ARM::t2STCL_OFFSET:
				1356	case ARM::t2STCL_PRE:
				1357	case ARM::t2STCL_POST:
				1358	case ARM::t2STCL_OPTION:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1359	if (coproc == 0xA \|\| coproc == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1360	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1361	break;
				1362	default:
				1363	break;
				1364	}
				1365
				1366	Inst.addOperand(MCOperand::CreateImm(coproc));
				1367	Inst.addOperand(MCOperand::CreateImm(CRd));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1368	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1369	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1370
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1371	switch (Inst.getOpcode()) {
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1372	case ARM::t2LDC2_OFFSET:
				1373	case ARM::t2LDC2L_OFFSET:
				1374	case ARM::t2LDC2_PRE:
				1375	case ARM::t2LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1376	case ARM::t2STC2_OFFSET:
				1377	case ARM::t2STC2L_OFFSET:
				1378	case ARM::t2STC2_PRE:
				1379	case ARM::t2STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1380	case ARM::LDC2_OFFSET:
				1381	case ARM::LDC2L_OFFSET:
				1382	case ARM::LDC2_PRE:
				1383	case ARM::LDC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1384	case ARM::STC2_OFFSET:
				1385	case ARM::STC2L_OFFSET:
				1386	case ARM::STC2_PRE:
				1387	case ARM::STC2L_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1388	case ARM::t2LDC_OFFSET:
				1389	case ARM::t2LDCL_OFFSET:
				1390	case ARM::t2LDC_PRE:
				1391	case ARM::t2LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1392	case ARM::t2STC_OFFSET:
				1393	case ARM::t2STCL_OFFSET:
				1394	case ARM::t2STC_PRE:
				1395	case ARM::t2STCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1396	case ARM::LDC_OFFSET:
				1397	case ARM::LDCL_OFFSET:
				1398	case ARM::LDC_PRE:
				1399	case ARM::LDCL_PRE:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1400	case ARM::STC_OFFSET:
				1401	case ARM::STCL_OFFSET:
				1402	case ARM::STC_PRE:
				1403	case ARM::STCL_PRE:
Jim Grosbach	a098a89	2011-10-12 21:59:02 +0000	[diff] [blame]	1404	imm = ARM_AM::getAM5Opc(U ? ARM_AM::add : ARM_AM::sub, imm);
				1405	Inst.addOperand(MCOperand::CreateImm(imm));
				1406	break;
				1407	case ARM::t2LDC2_POST:
				1408	case ARM::t2LDC2L_POST:
				1409	case ARM::t2STC2_POST:
				1410	case ARM::t2STC2L_POST:
				1411	case ARM::LDC2_POST:
				1412	case ARM::LDC2L_POST:
				1413	case ARM::STC2_POST:
				1414	case ARM::STC2L_POST:
				1415	case ARM::t2LDC_POST:
				1416	case ARM::t2LDCL_POST:
				1417	case ARM::t2STC_POST:
				1418	case ARM::t2STCL_POST:
				1419	case ARM::LDC_POST:
				1420	case ARM::LDCL_POST:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1421	case ARM::STC_POST:
				1422	case ARM::STCL_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1423	imm \|= U << 8;
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1424	// fall through.
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1425	default:
Jim Grosbach	54a20ed	2011-10-12 20:54:17 +0000	[diff] [blame]	1426	// The 'option' variant doesn't encode 'U' in the immediate since
				1427	// the immediate is unsigned [0,255].
				1428	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1429	break;
				1430	}
				1431
				1432	switch (Inst.getOpcode()) {
				1433	case ARM::LDC_OFFSET:
				1434	case ARM::LDC_PRE:
				1435	case ARM::LDC_POST:
				1436	case ARM::LDC_OPTION:
				1437	case ARM::LDCL_OFFSET:
				1438	case ARM::LDCL_PRE:
				1439	case ARM::LDCL_POST:
				1440	case ARM::LDCL_OPTION:
				1441	case ARM::STC_OFFSET:
				1442	case ARM::STC_PRE:
				1443	case ARM::STC_POST:
				1444	case ARM::STC_OPTION:
				1445	case ARM::STCL_OFFSET:
				1446	case ARM::STCL_PRE:
				1447	case ARM::STCL_POST:
				1448	case ARM::STCL_OPTION:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1449	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1450	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1451	break;
				1452	default:
				1453	break;
				1454	}
				1455
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1456	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1457	}
				1458
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1459	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1460	DecodeAddrMode2IdxInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1461	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1462	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1463
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1464	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1465	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1466	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1467	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				1468	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1469	unsigned reg = fieldFromInstruction(Insn, 25, 1);
				1470	unsigned P = fieldFromInstruction(Insn, 24, 1);
				1471	unsigned W = fieldFromInstruction(Insn, 21, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1472
				1473	// On stores, the writeback operand precedes Rt.
				1474	switch (Inst.getOpcode()) {
				1475	case ARM::STR_POST_IMM:
				1476	case ARM::STR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1477	case ARM::STRB_POST_IMM:
				1478	case ARM::STRB_POST_REG:
Jim Grosbach	e259421	2011-08-11 22:18:00 +0000	[diff] [blame]	1479	case ARM::STRT_POST_REG:
				1480	case ARM::STRT_POST_IMM:
Jim Grosbach	2a50260	2011-08-11 20:04:56 +0000	[diff] [blame]	1481	case ARM::STRBT_POST_REG:
				1482	case ARM::STRBT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1483	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1484	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1485	break;
				1486	default:
				1487	break;
				1488	}
				1489
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1490	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1491	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1492
				1493	// On loads, the writeback operand comes after Rt.
				1494	switch (Inst.getOpcode()) {
				1495	case ARM::LDR_POST_IMM:
				1496	case ARM::LDR_POST_REG:
Owen Anderson	3a850f2	2011-08-11 20:47:56 +0000	[diff] [blame]	1497	case ARM::LDRB_POST_IMM:
				1498	case ARM::LDRB_POST_REG:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1499	case ARM::LDRBT_POST_REG:
				1500	case ARM::LDRBT_POST_IMM:
Jim Grosbach	d5d6359	2011-08-10 23:43:54 +0000	[diff] [blame]	1501	case ARM::LDRT_POST_REG:
				1502	case ARM::LDRT_POST_IMM:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1503	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1504	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1505	break;
				1506	default:
				1507	break;
				1508	}
				1509
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1510	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1511	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1512
				1513	ARM_AM::AddrOpc Op = ARM_AM::add;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1514	if (!fieldFromInstruction(Insn, 23, 1))
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1515	Op = ARM_AM::sub;
				1516
				1517	bool writeback = (P == 0) \|\| (W == 1);
				1518	unsigned idx_mode = 0;
				1519	if (P && writeback)
				1520	idx_mode = ARMII::IndexModePre;
				1521	else if (!P && writeback)
				1522	idx_mode = ARMII::IndexModePost;
				1523
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1524	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1525	S = MCDisassembler::SoftFail; // UNPREDICTABLE
Owen Anderson	3477f2c	2011-08-11 19:00:18 +0000	[diff] [blame]	1526
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1527	if (reg) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1528	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1529	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1530	ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1531	switch( fieldFromInstruction(Insn, 5, 2)) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1532	case 0:
				1533	Opc = ARM_AM::lsl;
				1534	break;
				1535	case 1:
				1536	Opc = ARM_AM::lsr;
				1537	break;
				1538	case 2:
				1539	Opc = ARM_AM::asr;
				1540	break;
				1541	case 3:
				1542	Opc = ARM_AM::ror;
				1543	break;
				1544	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1545	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1546	}
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1547	unsigned amt = fieldFromInstruction(Insn, 7, 5);
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1548	if (Opc == ARM_AM::ror && amt == 0)
				1549	Opc = ARM_AM::rrx;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1550	unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
				1551
				1552	Inst.addOperand(MCOperand::CreateImm(imm));
				1553	} else {
				1554	Inst.addOperand(MCOperand::CreateReg(0));
				1555	unsigned tmp = ARM_AM::getAM2Opc(Op, imm, ARM_AM::lsl, idx_mode);
				1556	Inst.addOperand(MCOperand::CreateImm(tmp));
				1557	}
				1558
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1559	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1560	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1561
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1562	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1563	}
				1564
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1565	static DecodeStatus DecodeSORegMemOperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1566	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1567	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1568
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1569	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				1570	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				1571	unsigned type = fieldFromInstruction(Val, 5, 2);
				1572	unsigned imm = fieldFromInstruction(Val, 7, 5);
				1573	unsigned U = fieldFromInstruction(Val, 12, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1574
Owen Anderson	d151b09	2011-08-09 21:38:14 +0000	[diff] [blame]	1575	ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1576	switch (type) {
				1577	case 0:
				1578	ShOp = ARM_AM::lsl;
				1579	break;
				1580	case 1:
				1581	ShOp = ARM_AM::lsr;
				1582	break;
				1583	case 2:
				1584	ShOp = ARM_AM::asr;
				1585	break;
				1586	case 3:
				1587	ShOp = ARM_AM::ror;
				1588	break;
				1589	}
				1590
Tim Northover	0c97e76	2012-09-22 11:18:12 +0000	[diff] [blame]	1591	if (ShOp == ARM_AM::ror && imm == 0)
				1592	ShOp = ARM_AM::rrx;
				1593
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1594	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1595	return MCDisassembler::Fail;
				1596	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1597	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1598	unsigned shift;
				1599	if (U)
				1600	shift = ARM_AM::getAM2Opc(ARM_AM::add, imm, ShOp);
				1601	else
				1602	shift = ARM_AM::getAM2Opc(ARM_AM::sub, imm, ShOp);
				1603	Inst.addOperand(MCOperand::CreateImm(shift));
				1604
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1605	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1606	}
				1607
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1608	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1609	DecodeAddrMode3Instruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	1610	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1611	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1612
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1613	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				1614	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1615	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1616	unsigned type = fieldFromInstruction(Insn, 22, 1);
				1617	unsigned imm = fieldFromInstruction(Insn, 8, 4);
				1618	unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
				1619	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1620	unsigned W = fieldFromInstruction(Insn, 21, 1);
				1621	unsigned P = fieldFromInstruction(Insn, 24, 1);
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1622	unsigned Rt2 = Rt + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1623
				1624	bool writeback = (W == 1) \| (P == 0);
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1625
				1626	// For {LD,ST}RD, Rt must be even, else undefined.
				1627	switch (Inst.getOpcode()) {
				1628	case ARM::STRD:
				1629	case ARM::STRD_PRE:
				1630	case ARM::STRD_POST:
				1631	case ARM::LDRD:
				1632	case ARM::LDRD_PRE:
				1633	case ARM::LDRD_POST:
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1634	if (Rt & 0x1) S = MCDisassembler::SoftFail;
				1635	break;
				1636	default:
				1637	break;
				1638	}
				1639	switch (Inst.getOpcode()) {
				1640	case ARM::STRD:
				1641	case ARM::STRD_PRE:
				1642	case ARM::STRD_POST:
				1643	if (P == 0 && W == 1)
				1644	S = MCDisassembler::SoftFail;
				1645
				1646	if (writeback && (Rn == 15 \|\| Rn == Rt \|\| Rn == Rt2))
				1647	S = MCDisassembler::SoftFail;
				1648	if (type && Rm == 15)
				1649	S = MCDisassembler::SoftFail;
				1650	if (Rt2 == 15)
				1651	S = MCDisassembler::SoftFail;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1652	if (!type && fieldFromInstruction(Insn, 8, 4))
Silviu Baranga	4afd7d2	2012-03-22 14:14:49 +0000	[diff] [blame]	1653	S = MCDisassembler::SoftFail;
				1654	break;
				1655	case ARM::STRH:
				1656	case ARM::STRH_PRE:
				1657	case ARM::STRH_POST:
				1658	if (Rt == 15)
				1659	S = MCDisassembler::SoftFail;
				1660	if (writeback && (Rn == 15 \|\| Rn == Rt))
				1661	S = MCDisassembler::SoftFail;
				1662	if (!type && Rm == 15)
				1663	S = MCDisassembler::SoftFail;
				1664	break;
				1665	case ARM::LDRD:
				1666	case ARM::LDRD_PRE:
				1667	case ARM::LDRD_POST:
				1668	if (type && Rn == 15){
				1669	if (Rt2 == 15)
				1670	S = MCDisassembler::SoftFail;
				1671	break;
				1672	}
				1673	if (P == 0 && W == 1)
				1674	S = MCDisassembler::SoftFail;
				1675	if (!type && (Rt2 == 15 \|\| Rm == 15 \|\| Rm == Rt \|\| Rm == Rt2))
				1676	S = MCDisassembler::SoftFail;
				1677	if (!type && writeback && Rn == 15)
				1678	S = MCDisassembler::SoftFail;
				1679	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				1680	S = MCDisassembler::SoftFail;
				1681	break;
				1682	case ARM::LDRH:
				1683	case ARM::LDRH_PRE:
				1684	case ARM::LDRH_POST:
				1685	if (type && Rn == 15){
				1686	if (Rt == 15)
				1687	S = MCDisassembler::SoftFail;
				1688	break;
				1689	}
				1690	if (Rt == 15)
				1691	S = MCDisassembler::SoftFail;
				1692	if (!type && Rm == 15)
				1693	S = MCDisassembler::SoftFail;
				1694	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1695	S = MCDisassembler::SoftFail;
				1696	break;
				1697	case ARM::LDRSH:
				1698	case ARM::LDRSH_PRE:
				1699	case ARM::LDRSH_POST:
				1700	case ARM::LDRSB:
				1701	case ARM::LDRSB_PRE:
				1702	case ARM::LDRSB_POST:
				1703	if (type && Rn == 15){
				1704	if (Rt == 15)
				1705	S = MCDisassembler::SoftFail;
				1706	break;
				1707	}
				1708	if (type && (Rt == 15 \|\| (writeback && Rn == Rt)))
				1709	S = MCDisassembler::SoftFail;
				1710	if (!type && (Rt == 15 \|\| Rm == 15))
				1711	S = MCDisassembler::SoftFail;
				1712	if (!type && writeback && (Rn == 15 \|\| Rn == Rt))
				1713	S = MCDisassembler::SoftFail;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1714	break;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1715	default:
				1716	break;
Owen Anderson	1d5d2ca	2011-08-15 20:51:32 +0000	[diff] [blame]	1717	}
				1718
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1719	if (writeback) { // Writeback
				1720	if (P)
				1721	U \|= ARMII::IndexModePre << 9;
				1722	else
				1723	U \|= ARMII::IndexModePost << 9;
				1724
				1725	// On stores, the writeback operand precedes Rt.
				1726	switch (Inst.getOpcode()) {
				1727	case ARM::STRD:
				1728	case ARM::STRD_PRE:
				1729	case ARM::STRD_POST:
Owen Anderson	60138ea	2011-08-12 20:02:50 +0000	[diff] [blame]	1730	case ARM::STRH:
				1731	case ARM::STRH_PRE:
				1732	case ARM::STRH_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1733	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1734	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1735	break;
				1736	default:
				1737	break;
				1738	}
				1739	}
				1740
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1741	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				1742	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1743	switch (Inst.getOpcode()) {
				1744	case ARM::STRD:
				1745	case ARM::STRD_PRE:
				1746	case ARM::STRD_POST:
				1747	case ARM::LDRD:
				1748	case ARM::LDRD_PRE:
				1749	case ARM::LDRD_POST:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1750	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt+1, Address, Decoder)))
				1751	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1752	break;
				1753	default:
				1754	break;
				1755	}
				1756
				1757	if (writeback) {
				1758	// On loads, the writeback operand comes after Rt.
				1759	switch (Inst.getOpcode()) {
				1760	case ARM::LDRD:
				1761	case ARM::LDRD_PRE:
				1762	case ARM::LDRD_POST:
Owen Anderson	2d1d7a1	2011-08-12 20:36:11 +0000	[diff] [blame]	1763	case ARM::LDRH:
				1764	case ARM::LDRH_PRE:
				1765	case ARM::LDRH_POST:
				1766	case ARM::LDRSH:
				1767	case ARM::LDRSH_PRE:
				1768	case ARM::LDRSH_POST:
				1769	case ARM::LDRSB:
				1770	case ARM::LDRSB_PRE:
				1771	case ARM::LDRSB_POST:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1772	case ARM::LDRHTr:
				1773	case ARM::LDRSBTr:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1774	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1775	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1776	break;
				1777	default:
				1778	break;
				1779	}
				1780	}
				1781
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1782	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1783	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1784
				1785	if (type) {
				1786	Inst.addOperand(MCOperand::CreateReg(0));
				1787	Inst.addOperand(MCOperand::CreateImm(U \| (imm << 4) \| Rm));
				1788	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1789	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				1790	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1791	Inst.addOperand(MCOperand::CreateImm(U));
				1792	}
				1793
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1794	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1795	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1796
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1797	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1798	}
				1799
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1800	static DecodeStatus DecodeRFEInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1801	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1802	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1803
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1804	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1805	unsigned mode = fieldFromInstruction(Insn, 23, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1806
				1807	switch (mode) {
				1808	case 0:
				1809	mode = ARM_AM::da;
				1810	break;
				1811	case 1:
				1812	mode = ARM_AM::ia;
				1813	break;
				1814	case 2:
				1815	mode = ARM_AM::db;
				1816	break;
				1817	case 3:
				1818	mode = ARM_AM::ib;
				1819	break;
				1820	}
				1821
				1822	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1823	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1824	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1825
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1826	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1827	}
				1828
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1829	static DecodeStatus DecodeQADDInstruction(MCInst &Inst, unsigned Insn,
				1830	uint64_t Address, const void *Decoder) {
				1831	DecodeStatus S = MCDisassembler::Success;
				1832
				1833	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				1834	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				1835	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1836	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1837
				1838	if (pred == 0xF)
				1839	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				1840
				1841	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				1842	return MCDisassembler::Fail;
				1843	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				1844	return MCDisassembler::Fail;
				1845	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				1846	return MCDisassembler::Fail;
				1847	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1848	return MCDisassembler::Fail;
				1849	return S;
				1850	}
				1851
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1852	static DecodeStatus DecodeMemMultipleWritebackInstruction(MCInst &Inst,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1853	unsigned Insn,
				1854	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1855	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1856
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1857	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				1858	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				1859	unsigned reglist = fieldFromInstruction(Insn, 0, 16);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1860
				1861	if (pred == 0xF) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1862	// Ambiguous with RFE and SRS
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1863	switch (Inst.getOpcode()) {
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1864	case ARM::LDMDA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1865	Inst.setOpcode(ARM::RFEDA);
				1866	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1867	case ARM::LDMDA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1868	Inst.setOpcode(ARM::RFEDA_UPD);
				1869	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1870	case ARM::LDMDB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1871	Inst.setOpcode(ARM::RFEDB);
				1872	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1873	case ARM::LDMDB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1874	Inst.setOpcode(ARM::RFEDB_UPD);
				1875	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1876	case ARM::LDMIA:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1877	Inst.setOpcode(ARM::RFEIA);
				1878	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1879	case ARM::LDMIA_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1880	Inst.setOpcode(ARM::RFEIA_UPD);
				1881	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1882	case ARM::LDMIB:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1883	Inst.setOpcode(ARM::RFEIB);
				1884	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1885	case ARM::LDMIB_UPD:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1886	Inst.setOpcode(ARM::RFEIB_UPD);
				1887	break;
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1888	case ARM::STMDA:
				1889	Inst.setOpcode(ARM::SRSDA);
				1890	break;
				1891	case ARM::STMDA_UPD:
				1892	Inst.setOpcode(ARM::SRSDA_UPD);
				1893	break;
				1894	case ARM::STMDB:
				1895	Inst.setOpcode(ARM::SRSDB);
				1896	break;
				1897	case ARM::STMDB_UPD:
				1898	Inst.setOpcode(ARM::SRSDB_UPD);
				1899	break;
				1900	case ARM::STMIA:
				1901	Inst.setOpcode(ARM::SRSIA);
				1902	break;
				1903	case ARM::STMIA_UPD:
				1904	Inst.setOpcode(ARM::SRSIA_UPD);
				1905	break;
				1906	case ARM::STMIB:
				1907	Inst.setOpcode(ARM::SRSIB);
				1908	break;
				1909	case ARM::STMIB_UPD:
				1910	Inst.setOpcode(ARM::SRSIB_UPD);
				1911	break;
				1912	default:
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1913	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1914	}
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1915
				1916	// For stores (which become SRS's, the only operand is the mode.
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1917	if (fieldFromInstruction(Insn, 20, 1) == 0) {
Amaury de la Vieuville	68bcd02	2013-06-08 13:43:59 +0000	[diff] [blame]	1918	// Check SRS encoding constraints
				1919	if (!(fieldFromInstruction(Insn, 22, 1) == 1 &&
				1920	fieldFromInstruction(Insn, 20, 1) == 0))
				1921	return MCDisassembler::Fail;
				1922
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1923	Inst.addOperand(
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1924	MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
Owen Anderson	192a760	2011-08-18 22:31:17 +0000	[diff] [blame]	1925	return S;
				1926	}
				1927
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1928	return DecodeRFEInstruction(Inst, Insn, Address, Decoder);
				1929	}
				1930
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1931	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1932	return MCDisassembler::Fail;
				1933	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				1934	return MCDisassembler::Fail; // Tied
				1935	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				1936	return MCDisassembler::Fail;
				1937	if (!Check(S, DecodeRegListOperand(Inst, reglist, Address, Decoder)))
				1938	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1939
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	1940	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1941	}
				1942
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1943	static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1944	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1945	unsigned imod = fieldFromInstruction(Insn, 18, 2);
				1946	unsigned M = fieldFromInstruction(Insn, 17, 1);
				1947	unsigned iflags = fieldFromInstruction(Insn, 6, 3);
				1948	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1949
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1950	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	3d2e0e9d	2011-08-09 23:05:39 +0000	[diff] [blame]	1951
Amaury de la Vieuville	631df63	2013-06-08 13:38:52 +0000	[diff] [blame]	1952	// This decoder is called from multiple location that do not check
				1953	// the full encoding is valid before they do.
				1954	if (fieldFromInstruction(Insn, 5, 1) != 0 \|\|
				1955	fieldFromInstruction(Insn, 16, 1) != 0 \|\|
				1956	fieldFromInstruction(Insn, 20, 8) != 0x10)
				1957	return MCDisassembler::Fail;
				1958
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1959	// imod == '01' --> UNPREDICTABLE
				1960	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				1961	// return failure here. The '01' imod value is unprintable, so there's
				1962	// nothing useful we could do even if we returned UNPREDICTABLE.
				1963
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1964	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1965
				1966	if (imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1967	Inst.setOpcode(ARM::CPS3p);
				1968	Inst.addOperand(MCOperand::CreateImm(imod));
				1969	Inst.addOperand(MCOperand::CreateImm(iflags));
				1970	Inst.addOperand(MCOperand::CreateImm(mode));
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1971	} else if (imod && !M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1972	Inst.setOpcode(ARM::CPS2p);
				1973	Inst.addOperand(MCOperand::CreateImm(imod));
				1974	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1975	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1976	} else if (!imod && M) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1977	Inst.setOpcode(ARM::CPS1p);
				1978	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1979	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1980	} else {
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1981	// imod == '00' && M == '0' --> UNPREDICTABLE
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1982	Inst.setOpcode(ARM::CPS1p);
				1983	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	1984	S = MCDisassembler::SoftFail;
Owen Anderson	5d2db89	2011-08-18 22:15:25 +0000	[diff] [blame]	1985	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1986
Owen Anderson	67d6f11	2011-08-18 22:11:02 +0000	[diff] [blame]	1987	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	1988	}
				1989
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	1990	static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1991	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	1992	unsigned imod = fieldFromInstruction(Insn, 9, 2);
				1993	unsigned M = fieldFromInstruction(Insn, 8, 1);
				1994	unsigned iflags = fieldFromInstruction(Insn, 5, 3);
				1995	unsigned mode = fieldFromInstruction(Insn, 0, 5);
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1996
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	1997	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	1998
				1999	// imod == '01' --> UNPREDICTABLE
				2000	// NOTE: Even though this is technically UNPREDICTABLE, we choose to
				2001	// return failure here. The '01' imod value is unprintable, so there's
				2002	// nothing useful we could do even if we returned UNPREDICTABLE.
				2003
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2004	if (imod == 1) return MCDisassembler::Fail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2005
				2006	if (imod && M) {
				2007	Inst.setOpcode(ARM::t2CPS3p);
				2008	Inst.addOperand(MCOperand::CreateImm(imod));
				2009	Inst.addOperand(MCOperand::CreateImm(iflags));
				2010	Inst.addOperand(MCOperand::CreateImm(mode));
				2011	} else if (imod && !M) {
				2012	Inst.setOpcode(ARM::t2CPS2p);
				2013	Inst.addOperand(MCOperand::CreateImm(imod));
				2014	Inst.addOperand(MCOperand::CreateImm(iflags));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2015	if (mode) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2016	} else if (!imod && M) {
				2017	Inst.setOpcode(ARM::t2CPS1p);
				2018	Inst.addOperand(MCOperand::CreateImm(mode));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	2019	if (iflags) S = MCDisassembler::SoftFail;
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2020	} else {
Quentin Colombet	a83d5e9	2013-04-26 17:54:54 +0000	[diff] [blame]	2021	// imod == '00' && M == '0' --> this is a HINT instruction
				2022	int imm = fieldFromInstruction(Insn, 0, 8);
				2023	// HINT are defined only for immediate in [0..4]
				2024	if(imm > 4) return MCDisassembler::Fail;
				2025	Inst.setOpcode(ARM::t2HINT);
				2026	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2027	}
				2028
				2029	return S;
				2030	}
				2031
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2032	static DecodeStatus DecodeT2MOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2033	uint64_t Address, const void *Decoder) {
				2034	DecodeStatus S = MCDisassembler::Success;
				2035
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2036	unsigned Rd = fieldFromInstruction(Insn, 8, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2037	unsigned imm = 0;
				2038
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2039	imm \|= (fieldFromInstruction(Insn, 0, 8) << 0);
				2040	imm \|= (fieldFromInstruction(Insn, 12, 3) << 8);
				2041	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
				2042	imm \|= (fieldFromInstruction(Insn, 26, 1) << 11);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2043
				2044	if (Inst.getOpcode() == ARM::t2MOVTi16)
				2045	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2046	return MCDisassembler::Fail;
				2047	if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
				2048	return MCDisassembler::Fail;
				2049
				2050	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2051	Inst.addOperand(MCOperand::CreateImm(imm));
				2052
				2053	return S;
				2054	}
				2055
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2056	static DecodeStatus DecodeArmMOVTWInstruction(MCInst &Inst, unsigned Insn,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2057	uint64_t Address, const void *Decoder) {
				2058	DecodeStatus S = MCDisassembler::Success;
				2059
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2060	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2061	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2062	unsigned imm = 0;
				2063
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2064	imm \|= (fieldFromInstruction(Insn, 0, 12) << 0);
				2065	imm \|= (fieldFromInstruction(Insn, 16, 4) << 12);
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2066
				2067	if (Inst.getOpcode() == ARM::MOVTi16)
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2068	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2069	return MCDisassembler::Fail;
Tim Northover	a155ab2	2013-04-19 09:58:09 +0000	[diff] [blame]	2070
				2071	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2072	return MCDisassembler::Fail;
				2073
				2074	if (!tryAddingSymbolicOperand(Address, imm, false, 4, Inst, Decoder))
				2075	Inst.addOperand(MCOperand::CreateImm(imm));
				2076
				2077	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2078	return MCDisassembler::Fail;
				2079
				2080	return S;
				2081	}
Owen Anderson	9b7bd15	2011-08-23 17:45:18 +0000	[diff] [blame]	2082
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2083	static DecodeStatus DecodeSMLAInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2084	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2085	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2086
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2087	unsigned Rd = fieldFromInstruction(Insn, 16, 4);
				2088	unsigned Rn = fieldFromInstruction(Insn, 0, 4);
				2089	unsigned Rm = fieldFromInstruction(Insn, 8, 4);
				2090	unsigned Ra = fieldFromInstruction(Insn, 12, 4);
				2091	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2092
				2093	if (pred == 0xF)
				2094	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				2095
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2096	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
				2097	return MCDisassembler::Fail;
				2098	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				2099	return MCDisassembler::Fail;
				2100	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
				2101	return MCDisassembler::Fail;
				2102	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Ra, Address, Decoder)))
				2103	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2104
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2105	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2106	return MCDisassembler::Fail;
Owen Anderson	2f7aa73	2011-08-11 22:05:38 +0000	[diff] [blame]	2107
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2108	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2109	}
				2110
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2111	static DecodeStatus DecodeAddrModeImm12Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2112	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2113	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2114
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2115	unsigned add = fieldFromInstruction(Val, 12, 1);
				2116	unsigned imm = fieldFromInstruction(Val, 0, 12);
				2117	unsigned Rn = fieldFromInstruction(Val, 13, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2118
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2119	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2120	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2121
				2122	if (!add) imm *= -1;
				2123	if (imm == 0 && !add) imm = INT32_MIN;
				2124	Inst.addOperand(MCOperand::CreateImm(imm));
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2125	if (Rn == 15)
				2126	tryAddingPcLoadReferenceComment(Address, Address + imm + 8, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2127
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2128	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2129	}
				2130
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2131	static DecodeStatus DecodeAddrMode5Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2132	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2133	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2134
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2135	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				2136	unsigned U = fieldFromInstruction(Val, 8, 1);
				2137	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2138
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2139	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2140	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2141
				2142	if (U)
				2143	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::add, imm)));
				2144	else
				2145	Inst.addOperand(MCOperand::CreateImm(ARM_AM::getAM5Opc(ARM_AM::sub, imm)));
				2146
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2147	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2148	}
				2149
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2150	static DecodeStatus DecodeAddrMode7Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2151	uint64_t Address, const void *Decoder) {
				2152	return DecodeGPRRegisterClass(Inst, Val, Address, Decoder);
				2153	}
				2154
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2155	static DecodeStatus
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2156	DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
				2157	uint64_t Address, const void *Decoder) {
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2158	DecodeStatus Status = MCDisassembler::Success;
				2159
				2160	// Note the J1 and J2 values are from the encoded instruction. So here
				2161	// change them to I1 and I2 values via as documented:
				2162	// I1 = NOT(J1 EOR S);
				2163	// I2 = NOT(J2 EOR S);
				2164	// and build the imm32 with one trailing zero as documented:
				2165	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
				2166	unsigned S = fieldFromInstruction(Insn, 26, 1);
				2167	unsigned J1 = fieldFromInstruction(Insn, 13, 1);
				2168	unsigned J2 = fieldFromInstruction(Insn, 11, 1);
				2169	unsigned I1 = !(J1 ^ S);
				2170	unsigned I2 = !(J2 ^ S);
				2171	unsigned imm10 = fieldFromInstruction(Insn, 16, 10);
				2172	unsigned imm11 = fieldFromInstruction(Insn, 0, 11);
				2173	unsigned tmp = (S << 23) \| (I1 << 22) \| (I2 << 21) \| (imm10 << 11) \| imm11;
Amaury de la Vieuville	bd2b610	2013-06-13 16:41:55 +0000	[diff] [blame]	2174	int imm32 = SignExtend32<25>(tmp << 1);
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2175	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2176	true, 4, Inst, Decoder))
Kevin Enderby	6fd9624	2012-10-29 23:27:20 +0000	[diff] [blame]	2177	Inst.addOperand(MCOperand::CreateImm(imm32));
				2178
				2179	return Status;
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	2180	}
				2181
				2182	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2183	DecodeBranchImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	2184	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2185	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2186
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2187	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				2188	unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2189
				2190	if (pred == 0xF) {
				2191	Inst.setOpcode(ARM::BLXi);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2192	imm \|= fieldFromInstruction(Insn, 24, 1) << 1;
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2193	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2194	true, 4, Inst, Decoder))
Benjamin Kramer	406dc17	2011-08-09 22:02:50 +0000	[diff] [blame]	2195	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2196	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2197	}
				2198
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	2199	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
				2200	true, 4, Inst, Decoder))
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	2201	Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2202	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				2203	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2205	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2206	}
				2207
				2208
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2209	static DecodeStatus DecodeAddrMode6Operand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2210	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2211	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2212
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2213	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				2214	unsigned align = fieldFromInstruction(Val, 4, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2215
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2216	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2217	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2218	if (!align)
				2219	Inst.addOperand(MCOperand::CreateImm(0));
				2220	else
				2221	Inst.addOperand(MCOperand::CreateImm(4 << align));
				2222
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2223	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2224	}
				2225
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2226	static DecodeStatus DecodeVLDInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2227	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2228	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2229
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2230	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2231	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2232	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2233	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2234	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2235	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2236
				2237	// First output register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2238	switch (Inst.getOpcode()) {
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2239	case ARM::VLD1q16: case ARM::VLD1q32: case ARM::VLD1q64: case ARM::VLD1q8:
				2240	case ARM::VLD1q16wb_fixed: case ARM::VLD1q16wb_register:
				2241	case ARM::VLD1q32wb_fixed: case ARM::VLD1q32wb_register:
				2242	case ARM::VLD1q64wb_fixed: case ARM::VLD1q64wb_register:
				2243	case ARM::VLD1q8wb_fixed: case ARM::VLD1q8wb_register:
				2244	case ARM::VLD2d16: case ARM::VLD2d32: case ARM::VLD2d8:
				2245	case ARM::VLD2d16wb_fixed: case ARM::VLD2d16wb_register:
				2246	case ARM::VLD2d32wb_fixed: case ARM::VLD2d32wb_register:
				2247	case ARM::VLD2d8wb_fixed: case ARM::VLD2d8wb_register:
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2248	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2249	return MCDisassembler::Fail;
				2250	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2251	case ARM::VLD2b16:
				2252	case ARM::VLD2b32:
				2253	case ARM::VLD2b8:
				2254	case ARM::VLD2b16wb_fixed:
				2255	case ARM::VLD2b16wb_register:
				2256	case ARM::VLD2b32wb_fixed:
				2257	case ARM::VLD2b32wb_register:
				2258	case ARM::VLD2b8wb_fixed:
				2259	case ARM::VLD2b8wb_register:
				2260	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2261	return MCDisassembler::Fail;
				2262	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2263	default:
				2264	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2265	return MCDisassembler::Fail;
				2266	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2267
				2268	// Second output register
				2269	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2270	case ARM::VLD3d8:
				2271	case ARM::VLD3d16:
				2272	case ARM::VLD3d32:
				2273	case ARM::VLD3d8_UPD:
				2274	case ARM::VLD3d16_UPD:
				2275	case ARM::VLD3d32_UPD:
				2276	case ARM::VLD4d8:
				2277	case ARM::VLD4d16:
				2278	case ARM::VLD4d32:
				2279	case ARM::VLD4d8_UPD:
				2280	case ARM::VLD4d16_UPD:
				2281	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2282	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2283	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2284	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2285	case ARM::VLD3q8:
				2286	case ARM::VLD3q16:
				2287	case ARM::VLD3q32:
				2288	case ARM::VLD3q8_UPD:
				2289	case ARM::VLD3q16_UPD:
				2290	case ARM::VLD3q32_UPD:
				2291	case ARM::VLD4q8:
				2292	case ARM::VLD4q16:
				2293	case ARM::VLD4q32:
				2294	case ARM::VLD4q8_UPD:
				2295	case ARM::VLD4q16_UPD:
				2296	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2297	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2298	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2299	default:
				2300	break;
				2301	}
				2302
				2303	// Third output register
				2304	switch(Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2305	case ARM::VLD3d8:
				2306	case ARM::VLD3d16:
				2307	case ARM::VLD3d32:
				2308	case ARM::VLD3d8_UPD:
				2309	case ARM::VLD3d16_UPD:
				2310	case ARM::VLD3d32_UPD:
				2311	case ARM::VLD4d8:
				2312	case ARM::VLD4d16:
				2313	case ARM::VLD4d32:
				2314	case ARM::VLD4d8_UPD:
				2315	case ARM::VLD4d16_UPD:
				2316	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2317	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2318	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2319	break;
				2320	case ARM::VLD3q8:
				2321	case ARM::VLD3q16:
				2322	case ARM::VLD3q32:
				2323	case ARM::VLD3q8_UPD:
				2324	case ARM::VLD3q16_UPD:
				2325	case ARM::VLD3q32_UPD:
				2326	case ARM::VLD4q8:
				2327	case ARM::VLD4q16:
				2328	case ARM::VLD4q32:
				2329	case ARM::VLD4q8_UPD:
				2330	case ARM::VLD4q16_UPD:
				2331	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2332	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2333	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2334	break;
				2335	default:
				2336	break;
				2337	}
				2338
				2339	// Fourth output register
				2340	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2341	case ARM::VLD4d8:
				2342	case ARM::VLD4d16:
				2343	case ARM::VLD4d32:
				2344	case ARM::VLD4d8_UPD:
				2345	case ARM::VLD4d16_UPD:
				2346	case ARM::VLD4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2347	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2348	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2349	break;
				2350	case ARM::VLD4q8:
				2351	case ARM::VLD4q16:
				2352	case ARM::VLD4q32:
				2353	case ARM::VLD4q8_UPD:
				2354	case ARM::VLD4q16_UPD:
				2355	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2356	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2357	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2358	break;
				2359	default:
				2360	break;
				2361	}
				2362
				2363	// Writeback operand
				2364	switch (Inst.getOpcode()) {
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2365	case ARM::VLD1d8wb_fixed:
				2366	case ARM::VLD1d16wb_fixed:
				2367	case ARM::VLD1d32wb_fixed:
				2368	case ARM::VLD1d64wb_fixed:
				2369	case ARM::VLD1d8wb_register:
				2370	case ARM::VLD1d16wb_register:
				2371	case ARM::VLD1d32wb_register:
				2372	case ARM::VLD1d64wb_register:
				2373	case ARM::VLD1q8wb_fixed:
				2374	case ARM::VLD1q16wb_fixed:
				2375	case ARM::VLD1q32wb_fixed:
				2376	case ARM::VLD1q64wb_fixed:
				2377	case ARM::VLD1q8wb_register:
				2378	case ARM::VLD1q16wb_register:
				2379	case ARM::VLD1q32wb_register:
				2380	case ARM::VLD1q64wb_register:
Jim Grosbach	92fd05e	2011-10-24 23:26:05 +0000	[diff] [blame]	2381	case ARM::VLD1d8Twb_fixed:
				2382	case ARM::VLD1d8Twb_register:
				2383	case ARM::VLD1d16Twb_fixed:
				2384	case ARM::VLD1d16Twb_register:
				2385	case ARM::VLD1d32Twb_fixed:
				2386	case ARM::VLD1d32Twb_register:
				2387	case ARM::VLD1d64Twb_fixed:
				2388	case ARM::VLD1d64Twb_register:
Jim Grosbach	17ec1a1	2011-10-25 00:14:01 +0000	[diff] [blame]	2389	case ARM::VLD1d8Qwb_fixed:
				2390	case ARM::VLD1d8Qwb_register:
				2391	case ARM::VLD1d16Qwb_fixed:
				2392	case ARM::VLD1d16Qwb_register:
				2393	case ARM::VLD1d32Qwb_fixed:
				2394	case ARM::VLD1d32Qwb_register:
				2395	case ARM::VLD1d64Qwb_fixed:
				2396	case ARM::VLD1d64Qwb_register:
Jim Grosbach	d146a02	2011-12-09 21:28:25 +0000	[diff] [blame]	2397	case ARM::VLD2d8wb_fixed:
				2398	case ARM::VLD2d16wb_fixed:
				2399	case ARM::VLD2d32wb_fixed:
				2400	case ARM::VLD2q8wb_fixed:
				2401	case ARM::VLD2q16wb_fixed:
				2402	case ARM::VLD2q32wb_fixed:
				2403	case ARM::VLD2d8wb_register:
				2404	case ARM::VLD2d16wb_register:
				2405	case ARM::VLD2d32wb_register:
				2406	case ARM::VLD2q8wb_register:
				2407	case ARM::VLD2q16wb_register:
				2408	case ARM::VLD2q32wb_register:
				2409	case ARM::VLD2b8wb_fixed:
				2410	case ARM::VLD2b16wb_fixed:
				2411	case ARM::VLD2b32wb_fixed:
				2412	case ARM::VLD2b8wb_register:
				2413	case ARM::VLD2b16wb_register:
				2414	case ARM::VLD2b32wb_register:
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2415	Inst.addOperand(MCOperand::CreateImm(0));
				2416	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2417	case ARM::VLD3d8_UPD:
				2418	case ARM::VLD3d16_UPD:
				2419	case ARM::VLD3d32_UPD:
				2420	case ARM::VLD3q8_UPD:
				2421	case ARM::VLD3q16_UPD:
				2422	case ARM::VLD3q32_UPD:
				2423	case ARM::VLD4d8_UPD:
				2424	case ARM::VLD4d16_UPD:
				2425	case ARM::VLD4d32_UPD:
				2426	case ARM::VLD4q8_UPD:
				2427	case ARM::VLD4q16_UPD:
				2428	case ARM::VLD4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2429	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2430	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2431	break;
				2432	default:
				2433	break;
				2434	}
				2435
				2436	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2437	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2438	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2439
				2440	// AddrMode6 Offset (register)
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2441	switch (Inst.getOpcode()) {
				2442	default:
				2443	// The below have been updated to have explicit am6offset split
				2444	// between fixed and register offset. For those instructions not
				2445	// yet updated, we need to add an additional reg0 operand for the
				2446	// fixed variant.
				2447	//
				2448	// The fixed offset encodes as Rm == 0xd, so we check for that.
				2449	if (Rm == 0xd) {
				2450	Inst.addOperand(MCOperand::CreateReg(0));
				2451	break;
				2452	}
				2453	// Fall through to handle the register offset variant.
				2454	case ARM::VLD1d8wb_fixed:
				2455	case ARM::VLD1d16wb_fixed:
				2456	case ARM::VLD1d32wb_fixed:
				2457	case ARM::VLD1d64wb_fixed:
Owen Anderson	8a6ebd0	2011-10-27 22:53:10 +0000	[diff] [blame]	2458	case ARM::VLD1d8Twb_fixed:
				2459	case ARM::VLD1d16Twb_fixed:
				2460	case ARM::VLD1d32Twb_fixed:
				2461	case ARM::VLD1d64Twb_fixed:
Owen Anderson	40703f4	2011-10-31 17:17:32 +0000	[diff] [blame]	2462	case ARM::VLD1d8Qwb_fixed:
				2463	case ARM::VLD1d16Qwb_fixed:
				2464	case ARM::VLD1d32Qwb_fixed:
				2465	case ARM::VLD1d64Qwb_fixed:
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2466	case ARM::VLD1d8wb_register:
				2467	case ARM::VLD1d16wb_register:
				2468	case ARM::VLD1d32wb_register:
				2469	case ARM::VLD1d64wb_register:
				2470	case ARM::VLD1q8wb_fixed:
				2471	case ARM::VLD1q16wb_fixed:
				2472	case ARM::VLD1q32wb_fixed:
				2473	case ARM::VLD1q64wb_fixed:
				2474	case ARM::VLD1q8wb_register:
				2475	case ARM::VLD1q16wb_register:
				2476	case ARM::VLD1q32wb_register:
				2477	case ARM::VLD1q64wb_register:
				2478	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2479	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2480	// increment and we need to add the register operand to the instruction.
				2481	if (Rm != 0xD && Rm != 0xF &&
				2482	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2483	return MCDisassembler::Fail;
Jim Grosbach	2098cb1	2011-10-24 21:45:13 +0000	[diff] [blame]	2484	break;
Kevin Enderby	d2980cd	2012-04-11 00:25:40 +0000	[diff] [blame]	2485	case ARM::VLD2d8wb_fixed:
				2486	case ARM::VLD2d16wb_fixed:
				2487	case ARM::VLD2d32wb_fixed:
				2488	case ARM::VLD2b8wb_fixed:
				2489	case ARM::VLD2b16wb_fixed:
				2490	case ARM::VLD2b32wb_fixed:
				2491	case ARM::VLD2q8wb_fixed:
				2492	case ARM::VLD2q16wb_fixed:
				2493	case ARM::VLD2q32wb_fixed:
				2494	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2495	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2496
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2497	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2498	}
				2499
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2500	static DecodeStatus DecodeVLDST1Instruction(MCInst &Inst, unsigned Insn,
				2501	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2502	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2503	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2504	if (type == 6 && (align & 2)) return MCDisassembler::Fail;
				2505	if (type == 7 && (align & 2)) return MCDisassembler::Fail;
				2506	if (type == 10 && align == 3) return MCDisassembler::Fail;
				2507
				2508	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2509	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2510	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2511	}
				2512
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2513	static DecodeStatus DecodeVLDST2Instruction(MCInst &Inst, unsigned Insn,
				2514	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2515	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2516	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2517
				2518	unsigned type = fieldFromInstruction(Insn, 8, 4);
				2519	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2520	if (type == 8 && align == 3) return MCDisassembler::Fail;
				2521	if (type == 9 && align == 3) return MCDisassembler::Fail;
				2522
				2523	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2524	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2525	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2526	}
				2527
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2528	static DecodeStatus DecodeVLDST3Instruction(MCInst &Inst, unsigned Insn,
				2529	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2530	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2531	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2532
				2533	unsigned align = fieldFromInstruction(Insn, 4, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2534	if (align & 2) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2535
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2536	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2537	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2538	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2539	}
				2540
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2541	static DecodeStatus DecodeVLDST4Instruction(MCInst &Inst, unsigned Insn,
				2542	uint64_t Address, const void *Decoder) {
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2543	unsigned size = fieldFromInstruction(Insn, 6, 2);
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2544	if (size == 3) return MCDisassembler::Fail;
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2545
Amaury de la Vieuville	064546c	2013-06-11 08:14:14 +0000	[diff] [blame]	2546	unsigned load = fieldFromInstruction(Insn, 21, 1);
				2547	return load ? DecodeVLDInstruction(Inst, Insn, Address, Decoder)
				2548	: DecodeVSTInstruction(Inst, Insn, Address, Decoder);
Mihai Popa	f41e3f5	2013-05-20 14:57:05 +0000	[diff] [blame]	2549	}
				2550
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2551	static DecodeStatus DecodeVSTInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2552	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2553	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2554
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2555	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2556	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2557	unsigned wb = fieldFromInstruction(Insn, 16, 4);
				2558	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2559	Rn \|= fieldFromInstruction(Insn, 4, 2) << 4;
				2560	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2561
				2562	// Writeback Operand
				2563	switch (Inst.getOpcode()) {
Jim Grosbach	05df460	2011-10-31 21:50:31 +0000	[diff] [blame]	2564	case ARM::VST1d8wb_fixed:
				2565	case ARM::VST1d16wb_fixed:
				2566	case ARM::VST1d32wb_fixed:
				2567	case ARM::VST1d64wb_fixed:
				2568	case ARM::VST1d8wb_register:
				2569	case ARM::VST1d16wb_register:
				2570	case ARM::VST1d32wb_register:
				2571	case ARM::VST1d64wb_register:
				2572	case ARM::VST1q8wb_fixed:
				2573	case ARM::VST1q16wb_fixed:
				2574	case ARM::VST1q32wb_fixed:
				2575	case ARM::VST1q64wb_fixed:
				2576	case ARM::VST1q8wb_register:
				2577	case ARM::VST1q16wb_register:
				2578	case ARM::VST1q32wb_register:
				2579	case ARM::VST1q64wb_register:
Jim Grosbach	98d032f	2011-11-29 22:38:04 +0000	[diff] [blame]	2580	case ARM::VST1d8Twb_fixed:
				2581	case ARM::VST1d16Twb_fixed:
				2582	case ARM::VST1d32Twb_fixed:
				2583	case ARM::VST1d64Twb_fixed:
				2584	case ARM::VST1d8Twb_register:
				2585	case ARM::VST1d16Twb_register:
				2586	case ARM::VST1d32Twb_register:
				2587	case ARM::VST1d64Twb_register:
Jim Grosbach	5ee209c	2011-11-29 22:58:48 +0000	[diff] [blame]	2588	case ARM::VST1d8Qwb_fixed:
				2589	case ARM::VST1d16Qwb_fixed:
				2590	case ARM::VST1d32Qwb_fixed:
				2591	case ARM::VST1d64Qwb_fixed:
				2592	case ARM::VST1d8Qwb_register:
				2593	case ARM::VST1d16Qwb_register:
				2594	case ARM::VST1d32Qwb_register:
				2595	case ARM::VST1d64Qwb_register:
Jim Grosbach	88ac761	2011-12-14 21:32:11 +0000	[diff] [blame]	2596	case ARM::VST2d8wb_fixed:
				2597	case ARM::VST2d16wb_fixed:
				2598	case ARM::VST2d32wb_fixed:
				2599	case ARM::VST2d8wb_register:
				2600	case ARM::VST2d16wb_register:
				2601	case ARM::VST2d32wb_register:
				2602	case ARM::VST2q8wb_fixed:
				2603	case ARM::VST2q16wb_fixed:
				2604	case ARM::VST2q32wb_fixed:
				2605	case ARM::VST2q8wb_register:
				2606	case ARM::VST2q16wb_register:
				2607	case ARM::VST2q32wb_register:
				2608	case ARM::VST2b8wb_fixed:
				2609	case ARM::VST2b16wb_fixed:
				2610	case ARM::VST2b32wb_fixed:
				2611	case ARM::VST2b8wb_register:
				2612	case ARM::VST2b16wb_register:
				2613	case ARM::VST2b32wb_register:
Kevin Enderby	72f18bb	2012-04-11 22:40:17 +0000	[diff] [blame]	2614	if (Rm == 0xF)
				2615	return MCDisassembler::Fail;
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2616	Inst.addOperand(MCOperand::CreateImm(0));
				2617	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2618	case ARM::VST3d8_UPD:
				2619	case ARM::VST3d16_UPD:
				2620	case ARM::VST3d32_UPD:
				2621	case ARM::VST3q8_UPD:
				2622	case ARM::VST3q16_UPD:
				2623	case ARM::VST3q32_UPD:
				2624	case ARM::VST4d8_UPD:
				2625	case ARM::VST4d16_UPD:
				2626	case ARM::VST4d32_UPD:
				2627	case ARM::VST4q8_UPD:
				2628	case ARM::VST4q16_UPD:
				2629	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2630	if (!Check(S, DecodeGPRRegisterClass(Inst, wb, Address, Decoder)))
				2631	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2632	break;
				2633	default:
				2634	break;
				2635	}
				2636
				2637	// AddrMode6 Base (register+alignment)
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2638	if (!Check(S, DecodeAddrMode6Operand(Inst, Rn, Address, Decoder)))
				2639	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2640
				2641	// AddrMode6 Offset (register)
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2642	switch (Inst.getOpcode()) {
				2643	default:
				2644	if (Rm == 0xD)
				2645	Inst.addOperand(MCOperand::CreateReg(0));
				2646	else if (Rm != 0xF) {
				2647	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2648	return MCDisassembler::Fail;
				2649	}
				2650	break;
				2651	case ARM::VST1d8wb_fixed:
				2652	case ARM::VST1d16wb_fixed:
				2653	case ARM::VST1d32wb_fixed:
				2654	case ARM::VST1d64wb_fixed:
				2655	case ARM::VST1q8wb_fixed:
				2656	case ARM::VST1q16wb_fixed:
				2657	case ARM::VST1q32wb_fixed:
				2658	case ARM::VST1q64wb_fixed:
Kevin Enderby	7e7d5ee	2012-03-21 20:54:32 +0000	[diff] [blame]	2659	case ARM::VST1d8Twb_fixed:
				2660	case ARM::VST1d16Twb_fixed:
				2661	case ARM::VST1d32Twb_fixed:
				2662	case ARM::VST1d64Twb_fixed:
				2663	case ARM::VST1d8Qwb_fixed:
				2664	case ARM::VST1d16Qwb_fixed:
				2665	case ARM::VST1d32Qwb_fixed:
				2666	case ARM::VST1d64Qwb_fixed:
				2667	case ARM::VST2d8wb_fixed:
				2668	case ARM::VST2d16wb_fixed:
				2669	case ARM::VST2d32wb_fixed:
				2670	case ARM::VST2q8wb_fixed:
				2671	case ARM::VST2q16wb_fixed:
				2672	case ARM::VST2q32wb_fixed:
				2673	case ARM::VST2b8wb_fixed:
				2674	case ARM::VST2b16wb_fixed:
				2675	case ARM::VST2b32wb_fixed:
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2676	break;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2677	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2678
Owen Anderson	69e54a7	2011-11-01 22:18:13 +0000	[diff] [blame]	2679
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2680	// First input register
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2681	switch (Inst.getOpcode()) {
				2682	case ARM::VST1q16:
				2683	case ARM::VST1q32:
				2684	case ARM::VST1q64:
				2685	case ARM::VST1q8:
				2686	case ARM::VST1q16wb_fixed:
				2687	case ARM::VST1q16wb_register:
				2688	case ARM::VST1q32wb_fixed:
				2689	case ARM::VST1q32wb_register:
				2690	case ARM::VST1q64wb_fixed:
				2691	case ARM::VST1q64wb_register:
				2692	case ARM::VST1q8wb_fixed:
				2693	case ARM::VST1q8wb_register:
				2694	case ARM::VST2d16:
				2695	case ARM::VST2d32:
				2696	case ARM::VST2d8:
				2697	case ARM::VST2d16wb_fixed:
				2698	case ARM::VST2d16wb_register:
				2699	case ARM::VST2d32wb_fixed:
				2700	case ARM::VST2d32wb_register:
				2701	case ARM::VST2d8wb_fixed:
				2702	case ARM::VST2d8wb_register:
				2703	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2704	return MCDisassembler::Fail;
				2705	break;
Jim Grosbach	e5307f9	2012-03-05 21:43:40 +0000	[diff] [blame]	2706	case ARM::VST2b16:
				2707	case ARM::VST2b32:
				2708	case ARM::VST2b8:
				2709	case ARM::VST2b16wb_fixed:
				2710	case ARM::VST2b16wb_register:
				2711	case ARM::VST2b32wb_fixed:
				2712	case ARM::VST2b32wb_register:
				2713	case ARM::VST2b8wb_fixed:
				2714	case ARM::VST2b8wb_register:
				2715	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2716	return MCDisassembler::Fail;
				2717	break;
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	2718	default:
				2719	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2720	return MCDisassembler::Fail;
				2721	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2722
				2723	// Second input register
				2724	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2725	case ARM::VST3d8:
				2726	case ARM::VST3d16:
				2727	case ARM::VST3d32:
				2728	case ARM::VST3d8_UPD:
				2729	case ARM::VST3d16_UPD:
				2730	case ARM::VST3d32_UPD:
				2731	case ARM::VST4d8:
				2732	case ARM::VST4d16:
				2733	case ARM::VST4d32:
				2734	case ARM::VST4d8_UPD:
				2735	case ARM::VST4d16_UPD:
				2736	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2737	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+1)%32, Address, Decoder)))
				2738	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2739	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2740	case ARM::VST3q8:
				2741	case ARM::VST3q16:
				2742	case ARM::VST3q32:
				2743	case ARM::VST3q8_UPD:
				2744	case ARM::VST3q16_UPD:
				2745	case ARM::VST3q32_UPD:
				2746	case ARM::VST4q8:
				2747	case ARM::VST4q16:
				2748	case ARM::VST4q32:
				2749	case ARM::VST4q8_UPD:
				2750	case ARM::VST4q16_UPD:
				2751	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2752	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2753	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2754	break;
				2755	default:
				2756	break;
				2757	}
				2758
				2759	// Third input register
				2760	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2761	case ARM::VST3d8:
				2762	case ARM::VST3d16:
				2763	case ARM::VST3d32:
				2764	case ARM::VST3d8_UPD:
				2765	case ARM::VST3d16_UPD:
				2766	case ARM::VST3d32_UPD:
				2767	case ARM::VST4d8:
				2768	case ARM::VST4d16:
				2769	case ARM::VST4d32:
				2770	case ARM::VST4d8_UPD:
				2771	case ARM::VST4d16_UPD:
				2772	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2773	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2)%32, Address, Decoder)))
				2774	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2775	break;
				2776	case ARM::VST3q8:
				2777	case ARM::VST3q16:
				2778	case ARM::VST3q32:
				2779	case ARM::VST3q8_UPD:
				2780	case ARM::VST3q16_UPD:
				2781	case ARM::VST3q32_UPD:
				2782	case ARM::VST4q8:
				2783	case ARM::VST4q16:
				2784	case ARM::VST4q32:
				2785	case ARM::VST4q8_UPD:
				2786	case ARM::VST4q16_UPD:
				2787	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2788	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+4)%32, Address, Decoder)))
				2789	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2790	break;
				2791	default:
				2792	break;
				2793	}
				2794
				2795	// Fourth input register
				2796	switch (Inst.getOpcode()) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2797	case ARM::VST4d8:
				2798	case ARM::VST4d16:
				2799	case ARM::VST4d32:
				2800	case ARM::VST4d8_UPD:
				2801	case ARM::VST4d16_UPD:
				2802	case ARM::VST4d32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2803	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3)%32, Address, Decoder)))
				2804	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2805	break;
				2806	case ARM::VST4q8:
				2807	case ARM::VST4q16:
				2808	case ARM::VST4q32:
				2809	case ARM::VST4q8_UPD:
				2810	case ARM::VST4q16_UPD:
				2811	case ARM::VST4q32_UPD:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2812	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+6)%32, Address, Decoder)))
				2813	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2814	break;
				2815	default:
				2816	break;
				2817	}
				2818
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2819	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2820	}
				2821
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2822	static DecodeStatus DecodeVLD1DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2823	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2824	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2825
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2826	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2827	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2828	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2829	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2830	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2831	unsigned size = fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2832
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2833	if (size == 0 && align == 1)
				2834	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2835	align *= (1 << size);
				2836
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2837	switch (Inst.getOpcode()) {
				2838	case ARM::VLD1DUPq16: case ARM::VLD1DUPq32: case ARM::VLD1DUPq8:
				2839	case ARM::VLD1DUPq16wb_fixed: case ARM::VLD1DUPq16wb_register:
				2840	case ARM::VLD1DUPq32wb_fixed: case ARM::VLD1DUPq32wb_register:
				2841	case ARM::VLD1DUPq8wb_fixed: case ARM::VLD1DUPq8wb_register:
				2842	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2843	return MCDisassembler::Fail;
				2844	break;
				2845	default:
				2846	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2847	return MCDisassembler::Fail;
				2848	break;
				2849	}
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2850	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2851	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2852	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2853	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2854
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2855	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2856	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2857	Inst.addOperand(MCOperand::CreateImm(align));
				2858
Jim Grosbach	a68c9a8	2011-11-30 19:35:44 +0000	[diff] [blame]	2859	// The fixed offset post-increment encodes Rm == 0xd. The no-writeback
				2860	// variant encodes Rm == 0xf. Anything else is a register offset post-
				2861	// increment and we need to add the register operand to the instruction.
				2862	if (Rm != 0xD && Rm != 0xF &&
				2863	!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2864	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2865
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2866	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2867	}
				2868
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2869	static DecodeStatus DecodeVLD2DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2870	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2871	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2872
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2873	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2874	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2875	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2876	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2877	unsigned align = fieldFromInstruction(Insn, 4, 1);
				2878	unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2879	align = 2size;
				2880
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2881	switch (Inst.getOpcode()) {
				2882	case ARM::VLD2DUPd16: case ARM::VLD2DUPd32: case ARM::VLD2DUPd8:
				2883	case ARM::VLD2DUPd16wb_fixed: case ARM::VLD2DUPd16wb_register:
				2884	case ARM::VLD2DUPd32wb_fixed: case ARM::VLD2DUPd32wb_register:
				2885	case ARM::VLD2DUPd8wb_fixed: case ARM::VLD2DUPd8wb_register:
				2886	if (!Check(S, DecodeDPairRegisterClass(Inst, Rd, Address, Decoder)))
				2887	return MCDisassembler::Fail;
				2888	break;
Jim Grosbach	ed428bc	2012-03-06 23:10:38 +0000	[diff] [blame]	2889	case ARM::VLD2DUPd16x2: case ARM::VLD2DUPd32x2: case ARM::VLD2DUPd8x2:
				2890	case ARM::VLD2DUPd16x2wb_fixed: case ARM::VLD2DUPd16x2wb_register:
				2891	case ARM::VLD2DUPd32x2wb_fixed: case ARM::VLD2DUPd32x2wb_register:
				2892	case ARM::VLD2DUPd8x2wb_fixed: case ARM::VLD2DUPd8x2wb_register:
				2893	if (!Check(S, DecodeDPairSpacedRegisterClass(Inst, Rd, Address, Decoder)))
				2894	return MCDisassembler::Fail;
				2895	break;
Jim Grosbach	13a292c	2012-03-06 22:01:44 +0000	[diff] [blame]	2896	default:
				2897	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2898	return MCDisassembler::Fail;
				2899	break;
				2900	}
Kevin Enderby	520eb3b	2012-03-06 18:33:12 +0000	[diff] [blame]	2901
				2902	if (Rm != 0xF)
				2903	Inst.addOperand(MCOperand::CreateImm(0));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2904
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2905	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2906	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2907	Inst.addOperand(MCOperand::CreateImm(align));
				2908
Kevin Enderby	29ae538	2012-04-17 00:49:27 +0000	[diff] [blame]	2909	if (Rm != 0xD && Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2910	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2911	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2912	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2913
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2914	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2915	}
				2916
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2917	static DecodeStatus DecodeVLD3DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2918	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2919	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2920
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2921	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2922	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2923	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2924	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2925	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2926
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2927	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2928	return MCDisassembler::Fail;
				2929	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2930	return MCDisassembler::Fail;
				2931	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2932	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2933	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2934	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2935	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2936	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2937
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2938	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2939	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2940	Inst.addOperand(MCOperand::CreateImm(0));
				2941
				2942	if (Rm == 0xD)
				2943	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2944	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2945	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				2946	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2947	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2948
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2949	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2950	}
				2951
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	2952	static DecodeStatus DecodeVLD4DupInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2953	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2954	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	2955
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	2956	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				2957	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				2958	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				2959	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				2960	unsigned size = fieldFromInstruction(Insn, 6, 2);
				2961	unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
				2962	unsigned align = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2963
				2964	if (size == 0x3) {
Tim Northover	00e071a	2012-09-06 15:27:12 +0000	[diff] [blame]	2965	if (align == 0)
				2966	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2967	size = 4;
				2968	align = 16;
				2969	} else {
				2970	if (size == 2) {
				2971	size = 1 << size;
				2972	align *= 8;
				2973	} else {
				2974	size = 1 << size;
				2975	align = 4size;
				2976	}
				2977	}
				2978
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2979	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				2980	return MCDisassembler::Fail;
				2981	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+inc)%32, Address, Decoder)))
				2982	return MCDisassembler::Fail;
				2983	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+2*inc)%32, Address, Decoder)))
				2984	return MCDisassembler::Fail;
				2985	if (!Check(S, DecodeDPRRegisterClass(Inst, (Rd+3*inc)%32, Address, Decoder)))
				2986	return MCDisassembler::Fail;
Owen Anderson	ac92e77	2011-08-22 18:22:06 +0000	[diff] [blame]	2987	if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2988	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2989	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2990	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2991
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2992	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				2993	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	2994	Inst.addOperand(MCOperand::CreateImm(align));
				2995
				2996	if (Rm == 0xD)
				2997	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	2998	else if (Rm != 0xF) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	2999	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3000	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3001	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3002
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3003	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3004	}
				3005
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3006	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3007	DecodeNEONModImmInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3008	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3009	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3010
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3011	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3012	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3013	unsigned imm = fieldFromInstruction(Insn, 0, 4);
				3014	imm \|= fieldFromInstruction(Insn, 16, 3) << 4;
				3015	imm \|= fieldFromInstruction(Insn, 24, 1) << 7;
				3016	imm \|= fieldFromInstruction(Insn, 8, 4) << 8;
				3017	imm \|= fieldFromInstruction(Insn, 5, 1) << 12;
				3018	unsigned Q = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3019
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3020	if (Q) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3021	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3022	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3023	} else {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3024	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3025	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3026	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3027
				3028	Inst.addOperand(MCOperand::CreateImm(imm));
				3029
				3030	switch (Inst.getOpcode()) {
				3031	case ARM::VORRiv4i16:
				3032	case ARM::VORRiv2i32:
				3033	case ARM::VBICiv4i16:
				3034	case ARM::VBICiv2i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3035	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3036	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3037	break;
				3038	case ARM::VORRiv8i16:
				3039	case ARM::VORRiv4i32:
				3040	case ARM::VBICiv8i16:
				3041	case ARM::VBICiv4i32:
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3042	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3043	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3044	break;
				3045	default:
				3046	break;
				3047	}
				3048
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3049	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3050	}
				3051
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3052	static DecodeStatus DecodeVSHLMaxInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3053	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3054	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3055
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3056	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3057	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3058	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3059	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3060	unsigned size = fieldFromInstruction(Insn, 18, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3061
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3062	if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
				3063	return MCDisassembler::Fail;
				3064	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3065	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3066	Inst.addOperand(MCOperand::CreateImm(8 << size));
				3067
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3068	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3069	}
				3070
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3071	static DecodeStatus DecodeShiftRight8Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3072	uint64_t Address, const void *Decoder) {
				3073	Inst.addOperand(MCOperand::CreateImm(8 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3074	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3075	}
				3076
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3077	static DecodeStatus DecodeShiftRight16Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3078	uint64_t Address, const void *Decoder) {
				3079	Inst.addOperand(MCOperand::CreateImm(16 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3080	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3081	}
				3082
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3083	static DecodeStatus DecodeShiftRight32Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3084	uint64_t Address, const void *Decoder) {
				3085	Inst.addOperand(MCOperand::CreateImm(32 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3086	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3087	}
				3088
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3089	static DecodeStatus DecodeShiftRight64Imm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3090	uint64_t Address, const void *Decoder) {
				3091	Inst.addOperand(MCOperand::CreateImm(64 - Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3092	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3093	}
				3094
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3095	static DecodeStatus DecodeTBLInstruction(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3096	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3097	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3098
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3099	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3100	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				3101	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3102	Rn \|= fieldFromInstruction(Insn, 7, 1) << 4;
				3103	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3104	Rm \|= fieldFromInstruction(Insn, 5, 1) << 4;
				3105	unsigned op = fieldFromInstruction(Insn, 6, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3106
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3107	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3108	return MCDisassembler::Fail;
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3109	if (op) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3110	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				3111	return MCDisassembler::Fail; // Writeback
Owen Anderson	ed25385	2011-08-11 18:24:51 +0000	[diff] [blame]	3112	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3113
Jim Grosbach	c988e0c	2012-03-05 19:33:30 +0000	[diff] [blame]	3114	switch (Inst.getOpcode()) {
				3115	case ARM::VTBL2:
				3116	case ARM::VTBX2:
				3117	if (!Check(S, DecodeDPairRegisterClass(Inst, Rn, Address, Decoder)))
				3118	return MCDisassembler::Fail;
				3119	break;
				3120	default:
				3121	if (!Check(S, DecodeDPRRegisterClass(Inst, Rn, Address, Decoder)))
				3122	return MCDisassembler::Fail;
				3123	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3124
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3125	if (!Check(S, DecodeDPRRegisterClass(Inst, Rm, Address, Decoder)))
				3126	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3127
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3128	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3129	}
				3130
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3131	static DecodeStatus DecodeThumbAddSpecialReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3132	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3133	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3134
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3135	unsigned dst = fieldFromInstruction(Insn, 8, 3);
				3136	unsigned imm = fieldFromInstruction(Insn, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3137
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3138	if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
				3139	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3140
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3141	switch(Inst.getOpcode()) {
Owen Anderson	5658b49	2011-08-26 19:39:26 +0000	[diff] [blame]	3142	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3143	return MCDisassembler::Fail;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3144	case ARM::tADR:
Owen Anderson	240d20a	2011-08-26 21:47:57 +0000	[diff] [blame]	3145	break; // tADR does not explicitly represent the PC as an operand.
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3146	case ARM::tADDrSPi:
				3147	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3148	break;
Owen Anderson	a01bcbf	2011-08-26 18:09:22 +0000	[diff] [blame]	3149	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3150
				3151	Inst.addOperand(MCOperand::CreateImm(imm));
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3152	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3153	}
				3154
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3155	static DecodeStatus DecodeThumbBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3156	uint64_t Address, const void *Decoder) {
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3157	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<12>(Val<<1) + 4,
				3158	true, 2, Inst, Decoder))
				3159	Inst.addOperand(MCOperand::CreateImm(SignExtend32<12>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3160	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3161	}
				3162
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3163	static DecodeStatus DecodeT2BROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3164	uint64_t Address, const void *Decoder) {
Kevin Enderby	cabbae6	2012-05-04 22:09:52 +0000	[diff] [blame]	3165	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<21>(Val) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3166	true, 4, Inst, Decoder))
				3167	Inst.addOperand(MCOperand::CreateImm(SignExtend32<21>(Val)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3168	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3169	}
				3170
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3171	static DecodeStatus DecodeThumbCmpBROperand(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3172	uint64_t Address, const void *Decoder) {
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3173	if (!tryAddingSymbolicOperand(Address, Address + (Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3174	true, 2, Inst, Decoder))
Gordon Keiser	772cf46	2013-03-28 19:22:28 +0000	[diff] [blame]	3175	Inst.addOperand(MCOperand::CreateImm(Val << 1));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3176	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3177	}
				3178
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3179	static DecodeStatus DecodeThumbAddrModeRR(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3180	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3181	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3182
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3183	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3184	unsigned Rm = fieldFromInstruction(Val, 3, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3185
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3186	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3187	return MCDisassembler::Fail;
				3188	if (!Check(S, DecodetGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3189	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3190
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3191	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3192	}
				3193
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3194	static DecodeStatus DecodeThumbAddrModeIS(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3195	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3196	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3197
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3198	unsigned Rn = fieldFromInstruction(Val, 0, 3);
				3199	unsigned imm = fieldFromInstruction(Val, 3, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3200
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3201	if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3202	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3203	Inst.addOperand(MCOperand::CreateImm(imm));
				3204
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3205	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3206	}
				3207
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3208	static DecodeStatus DecodeThumbAddrModePC(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3209	uint64_t Address, const void *Decoder) {
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3210	unsigned imm = Val << 2;
				3211
				3212	Inst.addOperand(MCOperand::CreateImm(imm));
				3213	tryAddingPcLoadReferenceComment(Address, (Address & ~2u) + imm + 4, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3214
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3215	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3216	}
				3217
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3218	static DecodeStatus DecodeThumbAddrModeSP(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3219	uint64_t Address, const void *Decoder) {
				3220	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	b498132	2011-08-22 17:56:58 +0000	[diff] [blame]	3221	Inst.addOperand(MCOperand::CreateImm(Val));
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3222
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3223	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3224	}
				3225
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3226	static DecodeStatus DecodeT2AddrModeSOReg(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3227	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3228	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3229
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3230	unsigned Rn = fieldFromInstruction(Val, 6, 4);
				3231	unsigned Rm = fieldFromInstruction(Val, 2, 4);
				3232	unsigned imm = fieldFromInstruction(Val, 0, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3233
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3234	// Thumb stores cannot use PC as dest register.
				3235	switch (Inst.getOpcode()) {
				3236	case ARM::t2STRHs:
				3237	case ARM::t2STRBs:
				3238	case ARM::t2STRs:
				3239	if (Rn == 15)
				3240	return MCDisassembler::Fail;
				3241	default:
				3242	break;
				3243	}
				3244
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3245	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3246	return MCDisassembler::Fail;
				3247	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3248	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3249	Inst.addOperand(MCOperand::CreateImm(imm));
				3250
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3251	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3252	}
				3253
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3254	static DecodeStatus DecodeT2LoadShift(MCInst &Inst, unsigned Insn,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3255	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3256	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3257
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3258	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3259	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3260
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3261	if (Rn == 15) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3262	switch (Inst.getOpcode()) {
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3263	case ARM::t2LDRBs:
				3264	Inst.setOpcode(ARM::t2LDRBpci);
				3265	break;
				3266	case ARM::t2LDRHs:
				3267	Inst.setOpcode(ARM::t2LDRHpci);
				3268	break;
				3269	case ARM::t2LDRSHs:
				3270	Inst.setOpcode(ARM::t2LDRSHpci);
				3271	break;
				3272	case ARM::t2LDRSBs:
				3273	Inst.setOpcode(ARM::t2LDRSBpci);
				3274	break;
				3275	case ARM::t2LDRs:
				3276	Inst.setOpcode(ARM::t2LDRpci);
				3277	break;
				3278	case ARM::t2PLDs:
				3279	Inst.setOpcode(ARM::t2PLDpci);
				3280	break;
				3281	case ARM::t2PLIs:
				3282	Inst.setOpcode(ARM::t2PLIpci);
				3283	break;
				3284	default:
				3285	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3286	}
				3287
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3288	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3289	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3290
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3291	if (Rt == 15) {
				3292	switch (Inst.getOpcode()) {
				3293	case ARM::t2LDRSHs:
				3294	return MCDisassembler::Fail;
				3295	case ARM::t2LDRHs:
				3296	// FIXME: this instruction is only available with MP extensions,
				3297	// this should be checked first but we don't have access to the
				3298	// feature bits here.
				3299	Inst.setOpcode(ARM::t2PLDWs);
				3300	break;
				3301	default:
				3302	break;
				3303	}
				3304	}
				3305
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3306	switch (Inst.getOpcode()) {
				3307	case ARM::t2PLDs:
				3308	case ARM::t2PLDWs:
				3309	case ARM::t2PLIs:
				3310	break;
				3311	default:
				3312	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3313	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3314	}
				3315
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3316	unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
				3317	addrmode \|= fieldFromInstruction(Insn, 0, 4) << 2;
				3318	addrmode \|= fieldFromInstruction(Insn, 16, 4) << 6;
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3319	if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
				3320	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3321
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3322	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3323	}
				3324
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3325	static DecodeStatus DecodeT2LoadImm8(MCInst &Inst, unsigned Insn,
				3326	uint64_t Address, const void* Decoder) {
				3327	DecodeStatus S = MCDisassembler::Success;
				3328
				3329	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3330	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3331	unsigned U = fieldFromInstruction(Insn, 9, 1);
				3332	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3333	imm \|= (U << 8);
				3334	imm \|= (Rn << 9);
				3335
				3336	if (Rn == 15) {
				3337	switch (Inst.getOpcode()) {
				3338	case ARM::t2LDRi8:
				3339	Inst.setOpcode(ARM::t2LDRpci);
				3340	break;
				3341	case ARM::t2LDRBi8:
				3342	Inst.setOpcode(ARM::t2LDRBpci);
				3343	break;
				3344	case ARM::t2LDRSBi8:
				3345	Inst.setOpcode(ARM::t2LDRSBpci);
				3346	break;
				3347	case ARM::t2LDRHi8:
				3348	Inst.setOpcode(ARM::t2LDRHpci);
				3349	break;
				3350	case ARM::t2LDRSHi8:
				3351	Inst.setOpcode(ARM::t2LDRSHpci);
				3352	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3353	case ARM::t2PLDi8:
				3354	Inst.setOpcode(ARM::t2PLDpci);
				3355	break;
				3356	case ARM::t2PLIi8:
				3357	Inst.setOpcode(ARM::t2PLIpci);
				3358	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3359	default:
				3360	return MCDisassembler::Fail;
				3361	}
				3362	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3363	}
				3364
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3365	if (Rt == 15) {
				3366	switch (Inst.getOpcode()) {
				3367	case ARM::t2LDRSHi8:
				3368	return MCDisassembler::Fail;
				3369	default:
				3370	break;
				3371	}
				3372	}
				3373
				3374	switch (Inst.getOpcode()) {
				3375	case ARM::t2PLDi8:
				3376	case ARM::t2PLIi8:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3377	case ARM::t2PLDWi8:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3378	break;
				3379	default:
				3380	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3381	return MCDisassembler::Fail;
				3382	}
				3383
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3384	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3385	return MCDisassembler::Fail;
				3386	return S;
				3387	}
				3388
				3389	static DecodeStatus DecodeT2LoadImm12(MCInst &Inst, unsigned Insn,
				3390	uint64_t Address, const void* Decoder) {
				3391	DecodeStatus S = MCDisassembler::Success;
				3392
				3393	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3394	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3395	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				3396	imm \|= (Rn << 13);
				3397
				3398	if (Rn == 15) {
				3399	switch (Inst.getOpcode()) {
				3400	case ARM::t2LDRi12:
				3401	Inst.setOpcode(ARM::t2LDRpci);
				3402	break;
				3403	case ARM::t2LDRHi12:
				3404	Inst.setOpcode(ARM::t2LDRHpci);
				3405	break;
				3406	case ARM::t2LDRSHi12:
				3407	Inst.setOpcode(ARM::t2LDRSHpci);
				3408	break;
				3409	case ARM::t2LDRBi12:
				3410	Inst.setOpcode(ARM::t2LDRBpci);
				3411	break;
				3412	case ARM::t2LDRSBi12:
				3413	Inst.setOpcode(ARM::t2LDRSBpci);
				3414	break;
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3415	case ARM::t2PLDi12:
				3416	Inst.setOpcode(ARM::t2PLDpci);
				3417	break;
				3418	case ARM::t2PLIi12:
				3419	Inst.setOpcode(ARM::t2PLIpci);
				3420	break;
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3421	default:
				3422	return MCDisassembler::Fail;
				3423	}
				3424	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3425	}
				3426
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3427	if (Rt == 15) {
				3428	switch (Inst.getOpcode()) {
				3429	case ARM::t2LDRSHi12:
				3430	return MCDisassembler::Fail;
				3431	case ARM::t2LDRHi12:
				3432	Inst.setOpcode(ARM::t2PLDi12);
				3433	break;
				3434	default:
				3435	break;
				3436	}
				3437	}
				3438
				3439	switch (Inst.getOpcode()) {
				3440	case ARM::t2PLDi12:
Mihai Popa	c34bf73	2013-08-06 16:07:46 +0000	[diff] [blame]	3441	case ARM::t2PLDWi12:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3442	case ARM::t2PLIi12:
				3443	break;
				3444	default:
				3445	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3446	return MCDisassembler::Fail;
				3447	}
				3448
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3449	if (!Check(S, DecodeT2AddrModeImm12(Inst, imm, Address, Decoder)))
				3450	return MCDisassembler::Fail;
				3451	return S;
				3452	}
				3453
				3454	static DecodeStatus DecodeT2LoadT(MCInst &Inst, unsigned Insn,
				3455	uint64_t Address, const void* Decoder) {
				3456	DecodeStatus S = MCDisassembler::Success;
				3457
				3458	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3459	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3460	unsigned imm = fieldFromInstruction(Insn, 0, 8);
				3461	imm \|= (Rn << 9);
				3462
				3463	if (Rn == 15) {
				3464	switch (Inst.getOpcode()) {
				3465	case ARM::t2LDRT:
				3466	Inst.setOpcode(ARM::t2LDRpci);
				3467	break;
				3468	case ARM::t2LDRBT:
				3469	Inst.setOpcode(ARM::t2LDRBpci);
				3470	break;
				3471	case ARM::t2LDRHT:
				3472	Inst.setOpcode(ARM::t2LDRHpci);
				3473	break;
				3474	case ARM::t2LDRSBT:
				3475	Inst.setOpcode(ARM::t2LDRSBpci);
				3476	break;
				3477	case ARM::t2LDRSHT:
				3478	Inst.setOpcode(ARM::t2LDRSHpci);
				3479	break;
				3480	default:
				3481	return MCDisassembler::Fail;
				3482	}
				3483	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3484	}
				3485
				3486	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3487	return MCDisassembler::Fail;
				3488	if (!Check(S, DecodeT2AddrModeImm8(Inst, imm, Address, Decoder)))
				3489	return MCDisassembler::Fail;
				3490	return S;
				3491	}
				3492
				3493	static DecodeStatus DecodeT2LoadLabel(MCInst &Inst, unsigned Insn,
				3494	uint64_t Address, const void* Decoder) {
				3495	DecodeStatus S = MCDisassembler::Success;
				3496
				3497	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3498	unsigned U = fieldFromInstruction(Insn, 23, 1);
				3499	int imm = fieldFromInstruction(Insn, 0, 12);
				3500
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3501	if (Rt == 15) {
				3502	switch (Inst.getOpcode()) {
				3503	case ARM::t2LDRBpci:
				3504	case ARM::t2LDRHpci:
				3505	Inst.setOpcode(ARM::t2PLDpci);
				3506	break;
				3507	case ARM::t2LDRSBpci:
				3508	Inst.setOpcode(ARM::t2PLIpci);
				3509	break;
				3510	case ARM::t2LDRSHpci:
				3511	return MCDisassembler::Fail;
				3512	default:
				3513	break;
				3514	}
				3515	}
				3516
				3517	switch(Inst.getOpcode()) {
				3518	case ARM::t2PLDpci:
				3519	case ARM::t2PLIpci:
				3520	break;
				3521	default:
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3522	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				3523	return MCDisassembler::Fail;
				3524	}
				3525
				3526	if (!U) {
				3527	// Special case for #-0.
				3528	if (imm == 0)
				3529	imm = INT32_MIN;
				3530	else
				3531	imm = -imm;
				3532	}
				3533	Inst.addOperand(MCOperand::CreateImm(imm));
				3534
				3535	return S;
				3536	}
				3537
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3538	static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3539	uint64_t Address, const void *Decoder) {
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3540	if (Val == 0)
				3541	Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
				3542	else {
				3543	int imm = Val & 0xFF;
				3544
				3545	if (!(Val & 0x100)) imm *= -1;
Richard Smith	228e6d4	2012-08-24 23:29:28 +0000	[diff] [blame]	3546	Inst.addOperand(MCOperand::CreateImm(imm * 4));
Jiangning Liu	6a43bf7	2012-08-02 08:29:50 +0000	[diff] [blame]	3547	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3548
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3549	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3550	}
				3551
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3552	static DecodeStatus DecodeT2AddrModeImm8s4(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3553	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3554	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3555
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3556	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3557	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3558
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3559	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3560	return MCDisassembler::Fail;
				3561	if (!Check(S, DecodeT2Imm8S4(Inst, imm, Address, Decoder)))
				3562	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3563
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3564	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3565	}
				3566
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3567	static DecodeStatus DecodeT2AddrModeImm0_1020s4(MCInst &Inst,unsigned Val,
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3568	uint64_t Address, const void *Decoder) {
				3569	DecodeStatus S = MCDisassembler::Success;
				3570
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3571	unsigned Rn = fieldFromInstruction(Val, 8, 4);
				3572	unsigned imm = fieldFromInstruction(Val, 0, 8);
Jim Grosbach	a05627e	2011-09-09 18:37:27 +0000	[diff] [blame]	3573
				3574	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				3575	return MCDisassembler::Fail;
				3576
				3577	Inst.addOperand(MCOperand::CreateImm(imm));
				3578
				3579	return S;
				3580	}
				3581
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3582	static DecodeStatus DecodeT2Imm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3583	uint64_t Address, const void *Decoder) {
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3584	int imm = Val & 0xFF;
Owen Anderson	fe82365	2011-09-16 21:08:33 +0000	[diff] [blame]	3585	if (Val == 0)
				3586	imm = INT32_MIN;
				3587	else if (!(Val & 0x100))
				3588	imm *= -1;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3589	Inst.addOperand(MCOperand::CreateImm(imm));
				3590
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3591	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3592	}
				3593
				3594
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3595	static DecodeStatus DecodeT2AddrModeImm8(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3596	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3597	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3598
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3599	unsigned Rn = fieldFromInstruction(Val, 9, 4);
				3600	unsigned imm = fieldFromInstruction(Val, 0, 9);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3601
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3602	// Thumb stores cannot use PC as dest register.
				3603	switch (Inst.getOpcode()) {
				3604	case ARM::t2STRT:
				3605	case ARM::t2STRBT:
				3606	case ARM::t2STRHT:
				3607	case ARM::t2STRi8:
				3608	case ARM::t2STRHi8:
				3609	case ARM::t2STRBi8:
				3610	if (Rn == 15)
				3611	return MCDisassembler::Fail;
				3612	break;
				3613	default:
				3614	break;
				3615	}
				3616
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3617	// Some instructions always use an additive offset.
				3618	switch (Inst.getOpcode()) {
				3619	case ARM::t2LDRT:
				3620	case ARM::t2LDRBT:
				3621	case ARM::t2LDRHT:
				3622	case ARM::t2LDRSBT:
				3623	case ARM::t2LDRSHT:
Owen Anderson	ddfcec9	2011-09-19 18:07:10 +0000	[diff] [blame]	3624	case ARM::t2STRT:
				3625	case ARM::t2STRBT:
				3626	case ARM::t2STRHT:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3627	imm \|= 0x100;
				3628	break;
				3629	default:
				3630	break;
				3631	}
				3632
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3633	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3634	return MCDisassembler::Fail;
				3635	if (!Check(S, DecodeT2Imm8(Inst, imm, Address, Decoder)))
				3636	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3637
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3638	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3639	}
				3640
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3641	static DecodeStatus DecodeT2LdStPre(MCInst &Inst, unsigned Insn,
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3642	uint64_t Address, const void *Decoder) {
				3643	DecodeStatus S = MCDisassembler::Success;
				3644
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3645	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3646	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3647	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				3648	addr \|= fieldFromInstruction(Insn, 9, 1) << 8;
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3649	addr \|= Rn << 9;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3650	unsigned load = fieldFromInstruction(Insn, 20, 1);
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3651
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3652	if (Rn == 15) {
				3653	switch (Inst.getOpcode()) {
				3654	case ARM::t2LDR_PRE:
				3655	case ARM::t2LDR_POST:
				3656	Inst.setOpcode(ARM::t2LDRpci);
				3657	break;
				3658	case ARM::t2LDRB_PRE:
				3659	case ARM::t2LDRB_POST:
				3660	Inst.setOpcode(ARM::t2LDRBpci);
				3661	break;
				3662	case ARM::t2LDRH_PRE:
				3663	case ARM::t2LDRH_POST:
				3664	Inst.setOpcode(ARM::t2LDRHpci);
				3665	break;
				3666	case ARM::t2LDRSB_PRE:
				3667	case ARM::t2LDRSB_POST:
Amaury de la Vieuville	4b6c076	2013-06-24 09:11:38 +0000	[diff] [blame]	3668	if (Rt == 15)
				3669	Inst.setOpcode(ARM::t2PLIpci);
				3670	else
				3671	Inst.setOpcode(ARM::t2LDRSBpci);
Amaury de la Vieuville	4d3e3f2	2013-06-18 08:03:06 +0000	[diff] [blame]	3672	break;
				3673	case ARM::t2LDRSH_PRE:
				3674	case ARM::t2LDRSH_POST:
				3675	Inst.setOpcode(ARM::t2LDRSHpci);
				3676	break;
				3677	default:
				3678	return MCDisassembler::Fail;
				3679	}
				3680	return DecodeT2LoadLabel(Inst, Insn, Address, Decoder);
				3681	}
				3682
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3683	if (!load) {
				3684	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3685	return MCDisassembler::Fail;
				3686	}
				3687
Joe Abbey	f686be4	2013-03-26 13:58:53 +0000	[diff] [blame]	3688	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	a9ebf6f	2011-09-12 18:56:30 +0000	[diff] [blame]	3689	return MCDisassembler::Fail;
				3690
				3691	if (load) {
				3692	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3693	return MCDisassembler::Fail;
				3694	}
				3695
				3696	if (!Check(S, DecodeT2AddrModeImm8(Inst, addr, Address, Decoder)))
				3697	return MCDisassembler::Fail;
				3698
				3699	return S;
				3700	}
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3701
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3702	static DecodeStatus DecodeT2AddrModeImm12(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3703	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3704	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3705
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3706	unsigned Rn = fieldFromInstruction(Val, 13, 4);
				3707	unsigned imm = fieldFromInstruction(Val, 0, 12);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3708
Amaury de la Vieuville	e2bb1d1	2013-06-18 08:02:56 +0000	[diff] [blame]	3709	// Thumb stores cannot use PC as dest register.
				3710	switch (Inst.getOpcode()) {
				3711	case ARM::t2STRi12:
				3712	case ARM::t2STRBi12:
				3713	case ARM::t2STRHi12:
				3714	if (Rn == 15)
				3715	return MCDisassembler::Fail;
				3716	default:
				3717	break;
				3718	}
				3719
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3720	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3721	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3722	Inst.addOperand(MCOperand::CreateImm(imm));
				3723
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3724	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3725	}
				3726
				3727
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3728	static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3729	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3730	unsigned imm = fieldFromInstruction(Insn, 0, 7);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3731
				3732	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3733	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3734	Inst.addOperand(MCOperand::CreateImm(imm));
				3735
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3736	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3737	}
				3738
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3739	static DecodeStatus DecodeThumbAddSPReg(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3740	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3741	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3742
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3743	if (Inst.getOpcode() == ARM::tADDrSP) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3744	unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
				3745	Rdm \|= fieldFromInstruction(Insn, 7, 1) << 3;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3746
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3747	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3748	return MCDisassembler::Fail;
Jim Grosbach	9d8f6f3	2012-04-27 23:51:33 +0000	[diff] [blame]	3749	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3750	if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
				3751	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3752	} else if (Inst.getOpcode() == ARM::tADDspr) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3753	unsigned Rm = fieldFromInstruction(Insn, 3, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3754
				3755	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
				3756	Inst.addOperand(MCOperand::CreateReg(ARM::SP));
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3757	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3758	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3759	}
				3760
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3761	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3762	}
				3763
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3764	static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3765	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3766	unsigned imod = fieldFromInstruction(Insn, 4, 1) \| 0x2;
				3767	unsigned flags = fieldFromInstruction(Insn, 0, 3);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3768
				3769	Inst.addOperand(MCOperand::CreateImm(imod));
				3770	Inst.addOperand(MCOperand::CreateImm(flags));
				3771
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3772	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3773	}
				3774
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3775	static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3776	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3777	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3778	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				3779	unsigned add = fieldFromInstruction(Insn, 4, 1);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3780
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	3781	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3782	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3783	Inst.addOperand(MCOperand::CreateImm(add));
				3784
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3785	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3786	}
				3787
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3788	static DecodeStatus DecodeThumbBLXOffset(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3789	uint64_t Address, const void *Decoder) {
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3790	// Val is passed in as S:J1:J2:imm10H:imm10L:'0'
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3791	// Note only one trailing zero not two. Also the J1 and J2 values are from
				3792	// the encoded instruction. So here change to I1 and I2 values via:
				3793	// I1 = NOT(J1 EOR S);
				3794	// I2 = NOT(J2 EOR S);
				3795	// and build the imm32 with two trailing zeros as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3796	// imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3797	unsigned S = (Val >> 23) & 1;
				3798	unsigned J1 = (Val >> 22) & 1;
				3799	unsigned J2 = (Val >> 21) & 1;
				3800	unsigned I1 = !(J1 ^ S);
				3801	unsigned I2 = !(J2 ^ S);
				3802	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3803	int imm32 = SignExtend32<25>(tmp << 1);
				3804
Jim Grosbach	79ebc51	2011-10-20 17:28:20 +0000	[diff] [blame]	3805	if (!tryAddingSymbolicOperand(Address,
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3806	(Address & ~2u) + imm32 + 4,
Kevin Enderby	5dcda64	2011-10-04 22:44:48 +0000	[diff] [blame]	3807	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3808	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3809	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3810	}
				3811
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3812	static DecodeStatus DecodeCoprocessor(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3813	uint64_t Address, const void *Decoder) {
				3814	if (Val == 0xA \|\| Val == 0xB)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3815	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3816
				3817	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3818	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3819	}
				3820
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3821	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3822	DecodeThumbTableBranch(MCInst &Inst, unsigned Insn,
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3823	uint64_t Address, const void *Decoder) {
				3824	DecodeStatus S = MCDisassembler::Success;
				3825
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3826	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3827	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Jim Grosbach	05541f4	2011-09-19 22:21:13 +0000	[diff] [blame]	3828
				3829	if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
				3830	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3831	return MCDisassembler::Fail;
				3832	if (!Check(S, DecoderGPRRegisterClass(Inst, Rm, Address, Decoder)))
				3833	return MCDisassembler::Fail;
				3834	return S;
				3835	}
				3836
				3837	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3838	DecodeThumb2BCCInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3839	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3840	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3841
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3842	unsigned pred = fieldFromInstruction(Insn, 22, 4);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3843	if (pred == 0xE \|\| pred == 0xF) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3844	unsigned opc = fieldFromInstruction(Insn, 4, 28);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3845	switch (opc) {
				3846	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3847	return MCDisassembler::Fail;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3848	case 0xf3bf8f4:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3849	Inst.setOpcode(ARM::t2DSB);
				3850	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3851	case 0xf3bf8f5:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3852	Inst.setOpcode(ARM::t2DMB);
				3853	break;
Owen Anderson	4af0aa9	2011-08-31 22:00:41 +0000	[diff] [blame]	3854	case 0xf3bf8f6:
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3855	Inst.setOpcode(ARM::t2ISB);
Owen Anderson	cd5612d	2011-09-07 17:55:19 +0000	[diff] [blame]	3856	break;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3857	}
				3858
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3859	unsigned imm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3860	return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3861	}
				3862
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3863	unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
				3864	brtarget \|= fieldFromInstruction(Insn, 11, 1) << 19;
				3865	brtarget \|= fieldFromInstruction(Insn, 13, 1) << 18;
				3866	brtarget \|= fieldFromInstruction(Insn, 16, 6) << 12;
				3867	brtarget \|= fieldFromInstruction(Insn, 26, 1) << 20;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3868
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3869	if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
				3870	return MCDisassembler::Fail;
				3871	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3872	return MCDisassembler::Fail;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3873
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3874	return S;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3875	}
				3876
				3877	// Decode a shifted immediate operand. These basically consist
				3878	// of an 8-bit value, and a 4-bit directive that specifies either
				3879	// a splat operation or a rotation.
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3880	static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3881	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3882	unsigned ctrl = fieldFromInstruction(Val, 10, 2);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3883	if (ctrl == 0) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3884	unsigned byte = fieldFromInstruction(Val, 8, 2);
				3885	unsigned imm = fieldFromInstruction(Val, 0, 8);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3886	switch (byte) {
				3887	case 0:
				3888	Inst.addOperand(MCOperand::CreateImm(imm));
				3889	break;
				3890	case 1:
				3891	Inst.addOperand(MCOperand::CreateImm((imm << 16) \| imm));
				3892	break;
				3893	case 2:
				3894	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 8)));
				3895	break;
				3896	case 3:
				3897	Inst.addOperand(MCOperand::CreateImm((imm << 24) \| (imm << 16) \|
				3898	(imm << 8) \| imm));
				3899	break;
				3900	}
				3901	} else {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3902	unsigned unrot = fieldFromInstruction(Val, 0, 7) \| 0x80;
				3903	unsigned rot = fieldFromInstruction(Val, 7, 5);
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3904	unsigned imm = (unrot >> rot) \| (unrot << ((32-rot)&31));
				3905	Inst.addOperand(MCOperand::CreateImm(imm));
				3906	}
				3907
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3908	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3909	}
				3910
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3911	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3912	DecodeThumbBCCTargetOperand(MCInst &Inst, unsigned Val,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3913	uint64_t Address, const void *Decoder){
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3914	if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<9>(Val<<1) + 4,
Kevin Enderby	40d4e47	2012-04-12 23:13:34 +0000	[diff] [blame]	3915	true, 2, Inst, Decoder))
Richard Barton	f1ef87d	2012-06-06 09:12:53 +0000	[diff] [blame]	3916	Inst.addOperand(MCOperand::CreateImm(SignExtend32<9>(Val << 1)));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3917	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3918	}
				3919
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3920	static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val,
Owen Anderson	5d69f63	2011-08-10 17:36:48 +0000	[diff] [blame]	3921	uint64_t Address, const void *Decoder){
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3922	// Val is passed in as S:J1:J2:imm10:imm11
				3923	// Note no trailing zero after imm11. Also the J1 and J2 values are from
				3924	// the encoded instruction. So here change to I1 and I2 values via:
				3925	// I1 = NOT(J1 EOR S);
				3926	// I2 = NOT(J2 EOR S);
				3927	// and build the imm32 with one trailing zero as documented:
NAKAMURA Takumi	70c1aa0	2012-05-22 21:47:02 +0000	[diff] [blame]	3928	// imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', 32);
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3929	unsigned S = (Val >> 23) & 1;
				3930	unsigned J1 = (Val >> 22) & 1;
				3931	unsigned J2 = (Val >> 21) & 1;
				3932	unsigned I1 = !(J1 ^ S);
				3933	unsigned I2 = !(J2 ^ S);
				3934	unsigned tmp = (Val & ~0x600000) \| (I1 << 22) \| (I2 << 21);
				3935	int imm32 = SignExtend32<25>(tmp << 1);
				3936
				3937	if (!tryAddingSymbolicOperand(Address, Address + imm32 + 4,
Kevin Enderby	6fbcd8d	2012-02-23 18:18:17 +0000	[diff] [blame]	3938	true, 4, Inst, Decoder))
Kevin Enderby	9142230	2012-05-03 22:41:56 +0000	[diff] [blame]	3939	Inst.addOperand(MCOperand::CreateImm(imm32));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3940	return MCDisassembler::Success;
Owen Anderson	e0152a7	2011-08-09 20:55:18 +0000	[diff] [blame]	3941	}
				3942
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3943	static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val,
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3944	uint64_t Address, const void *Decoder) {
Jiangning Liu	288e1af	2012-08-02 08:21:27 +0000	[diff] [blame]	3945	if (Val & ~0xf)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3946	return MCDisassembler::Fail;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3947
				3948	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3949	return MCDisassembler::Success;
Owen Anderson	e008931	2011-08-09 23:25:42 +0000	[diff] [blame]	3950	}
				3951
Amaury de la Vieuville	43cb13a	2013-06-10 14:17:08 +0000	[diff] [blame]	3952	static DecodeStatus DecodeInstSyncBarrierOption(MCInst &Inst, unsigned Val,
				3953	uint64_t Address, const void *Decoder) {
				3954	if (Val & ~0xf)
				3955	return MCDisassembler::Fail;
				3956
				3957	Inst.addOperand(MCOperand::CreateImm(Val));
				3958	return MCDisassembler::Success;
				3959	}
				3960
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3961	static DecodeStatus DecodeMSRMask(MCInst &Inst, unsigned Val,
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3962	uint64_t Address, const void *Decoder) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3963	if (!Val) return MCDisassembler::Fail;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3964	Inst.addOperand(MCOperand::CreateImm(Val));
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	3965	return MCDisassembler::Success;
Owen Anderson	6066340	2011-08-11 20:21:46 +0000	[diff] [blame]	3966	}
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3967
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3968	static DecodeStatus DecodeDoubleRegLoad(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3969	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3970	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3971
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3972	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				3973	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3974	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3975
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3976	if (Rn == 0xF)
				3977	S = MCDisassembler::SoftFail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3978
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	3979	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3980	return MCDisassembler::Fail;
				3981	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				3982	return MCDisassembler::Fail;
				3983	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				3984	return MCDisassembler::Fail;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3985
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3986	return S;
Owen Anderson	c5798a3a5	2011-08-12 17:58:32 +0000	[diff] [blame]	3987	}
				3988
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	3989	static DecodeStatus DecodeDoubleRegStore(MCInst &Inst, unsigned Insn,
Jim Grosbach	d14b70d	2011-08-17 21:58:18 +0000	[diff] [blame]	3990	uint64_t Address, const void *Decoder){
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3991	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	3992
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	3993	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				3994	unsigned Rt = fieldFromInstruction(Insn, 0, 4);
				3995	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				3996	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	3997
Tim Northover	27ff504	2013-04-19 15:44:32 +0000	[diff] [blame]	3998	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rd, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	3999	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4000
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4001	if (Rn == 0xF \|\| Rd == Rn \|\| Rd == Rt \|\| Rd == Rt+1)
				4002	S = MCDisassembler::SoftFail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4003
Amaury de la Vieuville	53ff029	2013-06-11 08:03:20 +0000	[diff] [blame]	4004	if (!Check(S, DecodeGPRPairRegisterClass(Inst, Rt, Address, Decoder)))
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4005	return MCDisassembler::Fail;
				4006	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4007	return MCDisassembler::Fail;
				4008	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4009	return MCDisassembler::Fail;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4010
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4011	return S;
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4012	}
				4013
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4014	static DecodeStatus DecodeLDRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4015	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4016	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4017
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4018	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4019	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4020	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4021	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4022	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4023	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4024
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4025	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4026
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4027	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4028	return MCDisassembler::Fail;
				4029	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4030	return MCDisassembler::Fail;
				4031	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4032	return MCDisassembler::Fail;
				4033	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4034	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4035
				4036	return S;
				4037	}
				4038
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4039	static DecodeStatus DecodeLDRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4040	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4041	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4042
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4043	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4044	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4045	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4046	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4047	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4048	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4049	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4050
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4051	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
				4052	if (Rm == 0xF) S = MCDisassembler::SoftFail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4053
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4054	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4055	return MCDisassembler::Fail;
				4056	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4057	return MCDisassembler::Fail;
				4058	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4059	return MCDisassembler::Fail;
				4060	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4061	return MCDisassembler::Fail;
Owen Anderson	16d33f3	2011-08-26 20:43:14 +0000	[diff] [blame]	4062
				4063	return S;
				4064	}
				4065
				4066
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4067	static DecodeStatus DecodeSTRPreImm(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4068	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4069	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4070
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4071	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4072	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4073	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4074	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4075	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4076	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	b685c9f	2011-08-11 21:34:58 +0000	[diff] [blame]	4077
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4078	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4079
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4080	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4081	return MCDisassembler::Fail;
				4082	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4083	return MCDisassembler::Fail;
				4084	if (!Check(S, DecodeAddrModeImm12Operand(Inst, imm, Address, Decoder)))
				4085	return MCDisassembler::Fail;
				4086	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4087	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4088
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4089	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4090	}
				4091
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4092	static DecodeStatus DecodeSTRPreReg(MCInst &Inst, unsigned Insn,
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4093	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4094	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4095
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4096	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4097	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4098	unsigned imm = fieldFromInstruction(Insn, 0, 12);
				4099	imm \|= fieldFromInstruction(Insn, 16, 4) << 13;
				4100	imm \|= fieldFromInstruction(Insn, 23, 1) << 12;
				4101	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4102
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4103	if (Rn == 0xF \|\| Rn == Rt) S = MCDisassembler::SoftFail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4104
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4105	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4106	return MCDisassembler::Fail;
				4107	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4108	return MCDisassembler::Fail;
				4109	if (!Check(S, DecodeSORegMemOperand(Inst, imm, Address, Decoder)))
				4110	return MCDisassembler::Fail;
				4111	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4112	return MCDisassembler::Fail;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4113
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4114	return S;
Owen Anderson	3987a61	2011-08-12 18:12:39 +0000	[diff] [blame]	4115	}
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4116
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4117	static DecodeStatus DecodeVLD1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4118	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4119	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4120
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4121	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4122	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4123	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4124	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4125	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4126
				4127	unsigned align = 0;
				4128	unsigned index = 0;
				4129	switch (size) {
				4130	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4131	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4132	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4133	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4134	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4135	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4136	break;
				4137	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4138	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4139	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4140	index = fieldFromInstruction(Insn, 6, 2);
				4141	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4142	align = 2;
				4143	break;
				4144	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4145	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4146	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4147	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4148
				4149	switch (fieldFromInstruction(Insn, 4, 2)) {
				4150	case 0 :
				4151	align = 0; break;
				4152	case 3:
				4153	align = 4; break;
				4154	default:
				4155	return MCDisassembler::Fail;
				4156	}
				4157	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4158	}
				4159
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4160	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4161	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4162	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4163	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4164	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4165	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4166	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4167	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4168	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4169	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4170	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4171	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4172	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4173	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4174	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4175	}
				4176
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4177	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4178	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4179	Inst.addOperand(MCOperand::CreateImm(index));
				4180
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4181	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4182	}
				4183
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4184	static DecodeStatus DecodeVST1LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4185	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4186	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4187
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4188	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4189	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4190	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4191	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4192	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4193
				4194	unsigned align = 0;
				4195	unsigned index = 0;
				4196	switch (size) {
				4197	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4198	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4199	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4200	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4201	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4202	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4203	break;
				4204	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4205	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4206	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4207	index = fieldFromInstruction(Insn, 6, 2);
				4208	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4209	align = 2;
				4210	break;
				4211	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4212	if (fieldFromInstruction(Insn, 6, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4213	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4214	index = fieldFromInstruction(Insn, 7, 1);
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4215
				4216	switch (fieldFromInstruction(Insn, 4, 2)) {
				4217	case 0:
				4218	align = 0; break;
				4219	case 3:
				4220	align = 4; break;
				4221	default:
				4222	return MCDisassembler::Fail;
				4223	}
				4224	break;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4225	}
				4226
				4227	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4228	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4229	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4230	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4231	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4232	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4233	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4234	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4235	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4236	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4237	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4238	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4239	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4240	}
				4241
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4242	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4243	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4244	Inst.addOperand(MCOperand::CreateImm(index));
				4245
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4246	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4247	}
				4248
				4249
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4250	static DecodeStatus DecodeVLD2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4251	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4252	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4253
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4254	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4255	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4256	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4257	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4258	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4259
				4260	unsigned align = 0;
				4261	unsigned index = 0;
				4262	unsigned inc = 1;
				4263	switch (size) {
				4264	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4265	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4266	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4267	index = fieldFromInstruction(Insn, 5, 3);
				4268	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4269	align = 2;
				4270	break;
				4271	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4272	index = fieldFromInstruction(Insn, 6, 2);
				4273	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4274	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4275	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4276	inc = 2;
				4277	break;
				4278	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4279	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4280	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4281	index = fieldFromInstruction(Insn, 7, 1);
				4282	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4283	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4284	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4285	inc = 2;
				4286	break;
				4287	}
				4288
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4289	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4290	return MCDisassembler::Fail;
				4291	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4292	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4293	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4294	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4295	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4296	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4297	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4298	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4299	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4300	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4301	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4302	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4303	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4304	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4305	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4306	}
				4307
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4308	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4309	return MCDisassembler::Fail;
				4310	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4311	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4312	Inst.addOperand(MCOperand::CreateImm(index));
				4313
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4314	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4315	}
				4316
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4317	static DecodeStatus DecodeVST2LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4318	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4319	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4320
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4321	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4322	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4323	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4324	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4325	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4326
				4327	unsigned align = 0;
				4328	unsigned index = 0;
				4329	unsigned inc = 1;
				4330	switch (size) {
				4331	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4332	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4333	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4334	index = fieldFromInstruction(Insn, 5, 3);
				4335	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4336	align = 2;
				4337	break;
				4338	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4339	index = fieldFromInstruction(Insn, 6, 2);
				4340	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4341	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4342	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4343	inc = 2;
				4344	break;
				4345	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4346	if (fieldFromInstruction(Insn, 5, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4347	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4348	index = fieldFromInstruction(Insn, 7, 1);
				4349	if (fieldFromInstruction(Insn, 4, 1) != 0)
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4350	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4351	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4352	inc = 2;
				4353	break;
				4354	}
				4355
				4356	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4357	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4358	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4359	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4360	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4361	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4362	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4363	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4364	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4365	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4366	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4367	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4368	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4369	}
				4370
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4371	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4372	return MCDisassembler::Fail;
				4373	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4374	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4375	Inst.addOperand(MCOperand::CreateImm(index));
				4376
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4377	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4378	}
				4379
				4380
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4381	static DecodeStatus DecodeVLD3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4382	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4383	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4384
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4385	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4386	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4387	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4388	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4389	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4390
				4391	unsigned align = 0;
				4392	unsigned index = 0;
				4393	unsigned inc = 1;
				4394	switch (size) {
				4395	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4396	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4397	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4398	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4399	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4400	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4401	break;
				4402	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4403	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4404	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4405	index = fieldFromInstruction(Insn, 6, 2);
				4406	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4407	inc = 2;
				4408	break;
				4409	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4410	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4411	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4412	index = fieldFromInstruction(Insn, 7, 1);
				4413	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4414	inc = 2;
				4415	break;
				4416	}
				4417
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4418	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4419	return MCDisassembler::Fail;
				4420	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4421	return MCDisassembler::Fail;
				4422	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4423	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4424
				4425	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4426	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4427	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4428	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4429	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4430	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4431	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4432	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4433	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4434	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4435	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4436	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4437	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4438	}
				4439
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4440	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4441	return MCDisassembler::Fail;
				4442	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4443	return MCDisassembler::Fail;
				4444	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4445	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4446	Inst.addOperand(MCOperand::CreateImm(index));
				4447
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4448	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4449	}
				4450
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4451	static DecodeStatus DecodeVST3LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4452	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4453	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4454
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4455	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4456	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4457	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4458	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4459	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4460
				4461	unsigned align = 0;
				4462	unsigned index = 0;
				4463	unsigned inc = 1;
				4464	switch (size) {
				4465	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4466	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4467	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4468	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4469	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4470	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4471	break;
				4472	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4473	if (fieldFromInstruction(Insn, 4, 1))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4474	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4475	index = fieldFromInstruction(Insn, 6, 2);
				4476	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4477	inc = 2;
				4478	break;
				4479	case 2:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4480	if (fieldFromInstruction(Insn, 4, 2))
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4481	return MCDisassembler::Fail; // UNDEFINED
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4482	index = fieldFromInstruction(Insn, 7, 1);
				4483	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4484	inc = 2;
				4485	break;
				4486	}
				4487
				4488	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4489	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4490	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4491	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4492	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4493	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4494	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4495	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4496	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4497	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4498	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4499	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4500	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4501	}
				4502
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4503	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4504	return MCDisassembler::Fail;
				4505	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4506	return MCDisassembler::Fail;
				4507	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4508	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4509	Inst.addOperand(MCOperand::CreateImm(index));
				4510
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4511	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4512	}
				4513
				4514
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4515	static DecodeStatus DecodeVLD4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4516	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4517	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4518
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4519	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4520	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4521	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4522	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4523	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4524
				4525	unsigned align = 0;
				4526	unsigned index = 0;
				4527	unsigned inc = 1;
				4528	switch (size) {
				4529	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4530	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4531	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4532	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4533	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4534	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4535	break;
				4536	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4537	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4538	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4539	index = fieldFromInstruction(Insn, 6, 2);
				4540	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4541	inc = 2;
				4542	break;
				4543	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4544	switch (fieldFromInstruction(Insn, 4, 2)) {
				4545	case 0:
				4546	align = 0; break;
				4547	case 3:
				4548	return MCDisassembler::Fail;
				4549	default:
				4550	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4551	}
				4552
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4553	index = fieldFromInstruction(Insn, 7, 1);
				4554	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4555	inc = 2;
				4556	break;
				4557	}
				4558
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4559	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4560	return MCDisassembler::Fail;
				4561	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4562	return MCDisassembler::Fail;
				4563	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4564	return MCDisassembler::Fail;
				4565	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4566	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4567
				4568	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4569	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4570	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4571	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4572	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4573	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4574	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4575	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4576	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4577	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4578	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4579	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4580	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4581	}
				4582
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4583	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4584	return MCDisassembler::Fail;
				4585	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4586	return MCDisassembler::Fail;
				4587	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4588	return MCDisassembler::Fail;
				4589	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4590	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4591	Inst.addOperand(MCOperand::CreateImm(index));
				4592
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4593	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4594	}
				4595
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4596	static DecodeStatus DecodeVST4LN(MCInst &Inst, unsigned Insn,
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4597	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4598	DecodeStatus S = MCDisassembler::Success;
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4599
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4600	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4601	unsigned Rm = fieldFromInstruction(Insn, 0, 4);
				4602	unsigned Rd = fieldFromInstruction(Insn, 12, 4);
				4603	Rd \|= fieldFromInstruction(Insn, 22, 1) << 4;
				4604	unsigned size = fieldFromInstruction(Insn, 10, 2);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4605
				4606	unsigned align = 0;
				4607	unsigned index = 0;
				4608	unsigned inc = 1;
				4609	switch (size) {
				4610	default:
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4611	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4612	case 0:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4613	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4614	align = 4;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4615	index = fieldFromInstruction(Insn, 5, 3);
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4616	break;
				4617	case 1:
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4618	if (fieldFromInstruction(Insn, 4, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4619	align = 8;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4620	index = fieldFromInstruction(Insn, 6, 2);
				4621	if (fieldFromInstruction(Insn, 5, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4622	inc = 2;
				4623	break;
				4624	case 2:
Tim Northover	fb3cdd8	2012-09-06 15:17:49 +0000	[diff] [blame]	4625	switch (fieldFromInstruction(Insn, 4, 2)) {
				4626	case 0:
				4627	align = 0; break;
				4628	case 3:
				4629	return MCDisassembler::Fail;
				4630	default:
				4631	align = 4 << fieldFromInstruction(Insn, 4, 2); break;
				4632	}
				4633
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4634	index = fieldFromInstruction(Insn, 7, 1);
				4635	if (fieldFromInstruction(Insn, 6, 1))
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4636	inc = 2;
				4637	break;
				4638	}
				4639
				4640	if (Rm != 0xF) { // Writeback
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4641	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4642	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4643	}
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4644	if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4645	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4646	Inst.addOperand(MCOperand::CreateImm(align));
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4647	if (Rm != 0xF) {
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4648	if (Rm != 0xD) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4649	if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
				4650	return MCDisassembler::Fail;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4651	} else
Owen Anderson	721c370	2011-08-22 18:42:13 +0000	[diff] [blame]	4652	Inst.addOperand(MCOperand::CreateReg(0));
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4653	}
				4654
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4655	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
				4656	return MCDisassembler::Fail;
				4657	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+inc, Address, Decoder)))
				4658	return MCDisassembler::Fail;
				4659	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+2*inc, Address, Decoder)))
				4660	return MCDisassembler::Fail;
				4661	if (!Check(S, DecodeDPRRegisterClass(Inst, Rd+3*inc, Address, Decoder)))
				4662	return MCDisassembler::Fail;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4663	Inst.addOperand(MCOperand::CreateImm(index));
				4664
Owen Anderson	a4043c4	2011-08-17 17:44:15 +0000	[diff] [blame]	4665	return S;
Owen Anderson	b9d82f4	2011-08-15 18:44:44 +0000	[diff] [blame]	4666	}
				4667
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4668	static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4669	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4670	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4671	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4672	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4673	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4674	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4675	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4676
				4677	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4678	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4679
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4680	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4681	return MCDisassembler::Fail;
				4682	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4683	return MCDisassembler::Fail;
				4684	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4685	return MCDisassembler::Fail;
				4686	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4687	return MCDisassembler::Fail;
				4688	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4689	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4690
				4691	return S;
				4692	}
				4693
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4694	static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4695	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4696	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4697	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4698	unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
				4699	unsigned Rm = fieldFromInstruction(Insn, 5, 1);
				4700	unsigned pred = fieldFromInstruction(Insn, 28, 4);
				4701	Rm \|= fieldFromInstruction(Insn, 0, 4) << 1;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4702
				4703	if (Rt == 0xF \|\| Rt2 == 0xF \|\| Rm == 0x1F)
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4704	S = MCDisassembler::SoftFail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4705
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4706	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt , Address, Decoder)))
				4707	return MCDisassembler::Fail;
				4708	if (!Check(S, DecodeGPRRegisterClass(Inst, Rt2 , Address, Decoder)))
				4709	return MCDisassembler::Fail;
				4710	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm , Address, Decoder)))
				4711	return MCDisassembler::Fail;
				4712	if (!Check(S, DecodeSPRRegisterClass(Inst, Rm+1, Address, Decoder)))
				4713	return MCDisassembler::Fail;
				4714	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4715	return MCDisassembler::Fail;
Owen Anderson	df698b0	2011-08-22 20:27:12 +0000	[diff] [blame]	4716
				4717	return S;
				4718	}
Owen Anderson	eb1367b	2011-08-22 23:44:04 +0000	[diff] [blame]	4719
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4720	static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4721	uint64_t Address, const void *Decoder) {
Owen Anderson	03aadae	2011-09-01 23:23:50 +0000	[diff] [blame]	4722	DecodeStatus S = MCDisassembler::Success;
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4723	unsigned pred = fieldFromInstruction(Insn, 4, 4);
				4724	unsigned mask = fieldFromInstruction(Insn, 0, 4);
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4725
				4726	if (pred == 0xF) {
				4727	pred = 0xE;
James Molloy	db4ce60	2011-09-01 18:02:14 +0000	[diff] [blame]	4728	S = MCDisassembler::SoftFail;
Owen Anderson	5230041	2011-08-24 17:21:43 +0000	[diff] [blame]	4729	}
				4730
Amaury de la Vieuville	2f0ac8d	2013-06-24 09:11:45 +0000	[diff] [blame]	4731	if (mask == 0x0)
				4732	return MCDisassembler::Fail;
Owen Anderson	2fa06a7	2011-08-30 22:58:27 +0000	[diff] [blame]	4733
				4734	Inst.addOperand(MCOperand::CreateImm(pred));
				4735	Inst.addOperand(MCOperand::CreateImm(mask));
Owen Anderson	37612a3	2011-08-24 22:40:22 +0000	[diff] [blame]	4736	return S;
				4737	}
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4738
				4739	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4740	DecodeT2LDRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4741	uint64_t Address, const void *Decoder) {
				4742	DecodeStatus S = MCDisassembler::Success;
				4743
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4744	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4745	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4746	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4747	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4748	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4749	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4750	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4751	bool writeback = (W == 1) \| (P == 0);
				4752
				4753	addr \|= (U << 8) \| (Rn << 9);
				4754
				4755	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4756	Check(S, MCDisassembler::SoftFail);
				4757	if (Rt == Rt2)
				4758	Check(S, MCDisassembler::SoftFail);
				4759
				4760	// Rt
				4761	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4762	return MCDisassembler::Fail;
				4763	// Rt2
				4764	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4765	return MCDisassembler::Fail;
				4766	// Writeback operand
				4767	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4768	return MCDisassembler::Fail;
				4769	// addr
				4770	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4771	return MCDisassembler::Fail;
				4772
				4773	return S;
				4774	}
				4775
				4776	static DecodeStatus
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4777	DecodeT2STRDPreInstruction(MCInst &Inst, unsigned Insn,
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4778	uint64_t Address, const void *Decoder) {
				4779	DecodeStatus S = MCDisassembler::Success;
				4780
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4781	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4782	unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
				4783	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4784	unsigned addr = fieldFromInstruction(Insn, 0, 8);
				4785	unsigned W = fieldFromInstruction(Insn, 21, 1);
				4786	unsigned U = fieldFromInstruction(Insn, 23, 1);
				4787	unsigned P = fieldFromInstruction(Insn, 24, 1);
Jim Grosbach	7db8d69	2011-09-08 22:07:06 +0000	[diff] [blame]	4788	bool writeback = (W == 1) \| (P == 0);
				4789
				4790	addr \|= (U << 8) \| (Rn << 9);
				4791
				4792	if (writeback && (Rn == Rt \|\| Rn == Rt2))
				4793	Check(S, MCDisassembler::SoftFail);
				4794
				4795	// Writeback operand
				4796	if (!Check(S, DecoderGPRRegisterClass(Inst, Rn, Address, Decoder)))
				4797	return MCDisassembler::Fail;
				4798	// Rt
				4799	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
				4800	return MCDisassembler::Fail;
				4801	// Rt2
				4802	if (!Check(S, DecoderGPRRegisterClass(Inst, Rt2, Address, Decoder)))
				4803	return MCDisassembler::Fail;
				4804	// addr
				4805	if (!Check(S, DecodeT2AddrModeImm8s4(Inst, addr, Address, Decoder)))
				4806	return MCDisassembler::Fail;
				4807
				4808	return S;
				4809	}
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4810
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4811	static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4812	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4813	unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
				4814	unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4815	if (sign1 != sign2) return MCDisassembler::Fail;
				4816
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4817	unsigned Val = fieldFromInstruction(Insn, 0, 8);
				4818	Val \|= fieldFromInstruction(Insn, 12, 3) << 8;
				4819	Val \|= fieldFromInstruction(Insn, 26, 1) << 11;
Owen Anderson	5bfb0e0	2011-09-09 22:24:36 +0000	[diff] [blame]	4820	Val \|= sign1 << 12;
				4821	Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
				4822
				4823	return MCDisassembler::Success;
				4824	}
				4825
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4826	static DecodeStatus DecodeT2ShifterImmOperand(MCInst &Inst, uint32_t Val,
Owen Anderson	f01e2de	2011-09-26 21:06:22 +0000	[diff] [blame]	4827	uint64_t Address,
				4828	const void *Decoder) {
				4829	DecodeStatus S = MCDisassembler::Success;
				4830
				4831	// Shift of "asr #32" is not allowed in Thumb2 mode.
				4832	if (Val == 0x20) S = MCDisassembler::SoftFail;
				4833	Inst.addOperand(MCOperand::CreateImm(Val));
				4834	return S;
				4835	}
				4836
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4837	static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4838	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4839	unsigned Rt = fieldFromInstruction(Insn, 12, 4);
				4840	unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
				4841	unsigned Rn = fieldFromInstruction(Insn, 16, 4);
				4842	unsigned pred = fieldFromInstruction(Insn, 28, 4);
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4843
				4844	if (pred == 0xF)
				4845	return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
				4846
				4847	DecodeStatus S = MCDisassembler::Success;
Silviu Baranga	ca45af9	2012-04-18 14:18:57 +0000	[diff] [blame]	4848
				4849	if (Rt == Rn \|\| Rn == Rt2)
				4850	S = MCDisassembler::SoftFail;
				4851
Owen Anderson	dde461c	2011-10-28 18:02:13 +0000	[diff] [blame]	4852	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4853	return MCDisassembler::Fail;
				4854	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4855	return MCDisassembler::Fail;
				4856	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4857	return MCDisassembler::Fail;
				4858	if (!Check(S, DecodePredicateOperand(Inst, pred, Address, Decoder)))
				4859	return MCDisassembler::Fail;
				4860
				4861	return S;
				4862	}
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4863
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4864	static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4865	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4866	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4867	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4868	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4869	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4870	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4871	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4872	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4873
				4874	DecodeStatus S = MCDisassembler::Success;
				4875
				4876	// VMOVv2f32 is ambiguous with these decodings.
Owen Anderson	05060f0	2011-11-15 20:30:41 +0000	[diff] [blame]	4877	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4878	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4879	Inst.setOpcode(ARM::VMOVv2f32);
				4880	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4881	}
				4882
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4883	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4884
				4885	if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder)))
				4886	return MCDisassembler::Fail;
				4887	if (!Check(S, DecodeDPRRegisterClass(Inst, Vm, Address, Decoder)))
				4888	return MCDisassembler::Fail;
				4889	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4890
				4891	return S;
				4892	}
				4893
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4894	static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4895	uint64_t Address, const void *Decoder) {
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4896	unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
				4897	Vd \|= (fieldFromInstruction(Insn, 22, 1) << 4);
				4898	unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
				4899	Vm \|= (fieldFromInstruction(Insn, 5, 1) << 4);
				4900	unsigned imm = fieldFromInstruction(Insn, 16, 6);
				4901	unsigned cmode = fieldFromInstruction(Insn, 8, 4);
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4902	unsigned op = fieldFromInstruction(Insn, 5, 1);
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4903
				4904	DecodeStatus S = MCDisassembler::Success;
				4905
				4906	// VMOVv4f32 is ambiguous with these decodings.
				4907	if (!(imm & 0x38) && cmode == 0xF) {
Amaury de la Vieuville	f4ec0c85	2013-06-08 13:54:05 +0000	[diff] [blame]	4908	if (op == 1) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4909	Inst.setOpcode(ARM::VMOVv4f32);
				4910	return DecodeNEONModImmInstruction(Inst, Insn, Address, Decoder);
				4911	}
				4912
Amaury de la Vieuville	ea7bb57	2013-06-08 13:29:11 +0000	[diff] [blame]	4913	if (!(imm & 0x20)) return MCDisassembler::Fail;
Owen Anderson	0ac9058	2011-11-15 19:55:00 +0000	[diff] [blame]	4914
				4915	if (!Check(S, DecodeQPRRegisterClass(Inst, Vd, Address, Decoder)))
				4916	return MCDisassembler::Fail;
				4917	if (!Check(S, DecodeQPRRegisterClass(Inst, Vm, Address, Decoder)))
				4918	return MCDisassembler::Fail;
				4919	Inst.addOperand(MCOperand::CreateImm(64 - imm));
				4920
				4921	return S;
				4922	}
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4923
Quentin Colombet	6f03f62	2013-04-17 18:46:12 +0000	[diff] [blame]	4924	static DecodeStatus DecodeImm0_4(MCInst &Inst, unsigned Insn, uint64_t Address,
				4925	const void *Decoder)
				4926	{
				4927	unsigned Imm = fieldFromInstruction(Insn, 0, 3);
				4928	if (Imm > 4) return MCDisassembler::Fail;
				4929	Inst.addOperand(MCOperand::CreateImm(Imm));
				4930	return MCDisassembler::Success;
				4931	}
				4932
Craig Topper	f6e7e12	2012-03-27 07:21:54 +0000	[diff] [blame]	4933	static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4934	uint64_t Address, const void *Decoder) {
				4935	DecodeStatus S = MCDisassembler::Success;
				4936
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4937	unsigned Rn = fieldFromInstruction(Val, 16, 4);
				4938	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4939	unsigned Rm = fieldFromInstruction(Val, 0, 4);
				4940	Rm \|= (fieldFromInstruction(Val, 23, 1) << 4);
				4941	unsigned Cond = fieldFromInstruction(Val, 28, 4);
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4942
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4943	if (fieldFromInstruction(Val, 8, 4) != 0 \|\| Rn == Rt)
Silviu Baranga	d213f21	2012-03-22 13:24:43 +0000	[diff] [blame]	4944	S = MCDisassembler::SoftFail;
				4945
				4946	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4947	return MCDisassembler::Fail;
				4948	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
				4949	return MCDisassembler::Fail;
				4950	if (!Check(S, DecodeAddrMode7Operand(Inst, Rn, Address, Decoder)))
				4951	return MCDisassembler::Fail;
				4952	if (!Check(S, DecodePostIdxReg(Inst, Rm, Address, Decoder)))
				4953	return MCDisassembler::Fail;
				4954	if (!Check(S, DecodePredicateOperand(Inst, Cond, Address, Decoder)))
				4955	return MCDisassembler::Fail;
				4956
				4957	return S;
				4958	}
				4959
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4960	static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
				4961	uint64_t Address, const void *Decoder) {
				4962
				4963	DecodeStatus S = MCDisassembler::Success;
				4964
Jim Grosbach	ecaef49	2012-08-14 19:06:05 +0000	[diff] [blame]	4965	unsigned CRm = fieldFromInstruction(Val, 0, 4);
				4966	unsigned opc1 = fieldFromInstruction(Val, 4, 4);
				4967	unsigned cop = fieldFromInstruction(Val, 8, 4);
				4968	unsigned Rt = fieldFromInstruction(Val, 12, 4);
				4969	unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
Silviu Baranga	41f1fcd	2012-04-18 13:12:50 +0000	[diff] [blame]	4970
				4971	if ((cop & ~0x1) == 0xa)
				4972	return MCDisassembler::Fail;
				4973
				4974	if (Rt == Rt2)
				4975	S = MCDisassembler::SoftFail;
				4976
				4977	Inst.addOperand(MCOperand::CreateImm(cop));
				4978	Inst.addOperand(MCOperand::CreateImm(opc1));
				4979	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
				4980	return MCDisassembler::Fail;
				4981	if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
				4982	return MCDisassembler::Fail;
				4983	Inst.addOperand(MCOperand::CreateImm(CRm));
				4984
				4985	return S;
				4986	}
				4987