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gerrit-public.fairphone.software / toolchain / llvm-project / 04e2ecfda2add6a01aef02390c5de9629fbea757 / . / llvm / lib / Target / R600 / AMDGPU.td
blob: c4e5efc8d6ef408d34d90b10bc69158c679caffe [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
10// Include AMDIL TD files
11include "AMDILBase.td"
12
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]13//===----------------------------------------------------------------------===//
14// Subtarget Features
15//===----------------------------------------------------------------------===//
16
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]17// Debugging Features
18
19def FeatureDumpCode : SubtargetFeature <"DumpCode",
20 "DumpCode",
21 "true",
22 "Dump MachineInstrs in the CodeEmitter">;
23
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]24def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]25 "EnableIRStructurizer",
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]26 "false",
27 "Disable IR Structurizer">;
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]28
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]29// Target features
30
Tom Stellard783893a2013-11-18 19:43:33 +0000[diff] [blame]31def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
32 "EnableIfCvt",
33 "false",
34 "Disable the if conversion pass">;
35
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]36def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]37 "FP64",
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]38 "true",
39 "Enable 64bit double precision operations">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]40
41def Feature64BitPtr : SubtargetFeature<"64BitPtr",
42 "Is64bit",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]43 "true",
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]44 "Specify if 64bit addressing should be used.">;
45
46def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
47 "Is32on64bit",
48 "false",
49 "Specify if 64bit sized pointers with 32bit addressing should be used.">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]50
51def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
52 "R600ALUInst",
53 "false",
54 "Older version of ALU instructions encoding.">;
55
56def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
57 "HasVertexCache",
58 "true",
59 "Specify use of dedicated vertex cache.">;
60
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]61def FeatureCaymanISA : SubtargetFeature<"caymanISA",
62 "CaymanISA",
63 "true",
64 "Use Cayman ISA">;
65
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]66class SubtargetFeatureFetchLimit <string Value> :
67 SubtargetFeature <"fetch"#Value,
68 "TexVTXClauseSize",
69 Value,
70 "Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]71
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]72def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
73def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
74
Tom Stellard8c347b02014-01-22 21:55:40 +0000[diff] [blame]75class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
76 "wavefrontsize"#Value,
77 "WavefrontSize",
78 !cast<string>(Value),
79 "The number of threads per wavefront">;
80
81def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
82def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
83def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
84
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]85class SubtargetFeatureGeneration <string Value,
86 list<SubtargetFeature> Implies> :
87 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
88 Value#" GPU generation", Implies>;
89
90def FeatureR600 : SubtargetFeatureGeneration<"R600",
91 [FeatureR600ALUInst, FeatureFetchLimit8]>;
92
93def FeatureR700 : SubtargetFeatureGeneration<"R700",
94 [FeatureFetchLimit16]>;
95
96def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
97 [FeatureFetchLimit16]>;
98
99def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard8c347b02014-01-22 21:55:40 +0000[diff] [blame]100 [FeatureFetchLimit16, FeatureWavefrontSize64]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]101
102def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
103 [Feature64BitPtr, FeatureFP64]>;
104
Tom Stellard6e1ee472013-10-29 16:37:28 +0000[diff] [blame]105def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
106 [Feature64BitPtr, FeatureFP64]>;
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]107//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]108
109def AMDGPUInstrInfo : InstrInfo {
110 let guessInstructionProperties = 1;
111}
112
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]113def AMDGPU : Target {
114 // Pull in Instruction Info:
115 let InstructionSet = AMDGPUInstrInfo;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]116}
117
118// Include AMDGPU TD files
119include "R600Schedule.td"
120include "SISchedule.td"
121include "Processors.td"
122include "AMDGPUInstrInfo.td"
123include "AMDGPUIntrinsics.td"
124include "AMDGPURegisterInfo.td"
125include "AMDGPUInstructions.td"
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]126include "AMDGPUCallingConv.td"