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gerrit-public.fairphone.software / toolchain / llvm-project / 4c08fe284125d6505008239c39b3847d5818ff40 / . / llvm / test / CodeGen / X86 / setcc-logic.ll
blob: eca33130ecb4029a6c4ba32033934df2298a3c72 [file] [log] [blame]
Sanjay Patel303abb82017-03-31 17:55:07 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4define zeroext i1 @all_bits_clear(i32 %P, i32 %Q) nounwind {
5; CHECK-LABEL: all_bits_clear:
6; CHECK: # BB#0:
7; CHECK-NEXT: orl %esi, %edi
8; CHECK-NEXT: sete %al
9; CHECK-NEXT: retq
10 %a = icmp eq i32 %P, 0
11 %b = icmp eq i32 %Q, 0
12 %c = and i1 %a, %b
13 ret i1 %c
14}
15
16define zeroext i1 @all_sign_bits_clear(i32 %P, i32 %Q) nounwind {
17; CHECK-LABEL: all_sign_bits_clear:
18; CHECK: # BB#0:
19; CHECK-NEXT: orl %esi, %edi
20; CHECK-NEXT: setns %al
21; CHECK-NEXT: retq
22 %a = icmp sgt i32 %P, -1
23 %b = icmp sgt i32 %Q, -1
24 %c = and i1 %a, %b
25 ret i1 %c
26}
27
28define zeroext i1 @all_bits_set(i32 %P, i32 %Q) nounwind {
29; CHECK-LABEL: all_bits_set:
30; CHECK: # BB#0:
31; CHECK-NEXT: andl %esi, %edi
32; CHECK-NEXT: cmpl $-1, %edi
33; CHECK-NEXT: sete %al
34; CHECK-NEXT: retq
35 %a = icmp eq i32 %P, -1
36 %b = icmp eq i32 %Q, -1
37 %c = and i1 %a, %b
38 ret i1 %c
39}
40
41define zeroext i1 @all_sign_bits_set(i32 %P, i32 %Q) nounwind {
42; CHECK-LABEL: all_sign_bits_set:
43; CHECK: # BB#0:
44; CHECK-NEXT: testl %edi, %edi
45; CHECK-NEXT: sets %cl
46; CHECK-NEXT: testl %esi, %esi
47; CHECK-NEXT: sets %al
48; CHECK-NEXT: andb %cl, %al
49; CHECK-NEXT: retq
50 %a = icmp slt i32 %P, 0
51 %b = icmp slt i32 %Q, 0
52 %c = and i1 %a, %b
53 ret i1 %c
54}
55
56define zeroext i1 @any_bits_set(i32 %P, i32 %Q) nounwind {
57; CHECK-LABEL: any_bits_set:
58; CHECK: # BB#0:
59; CHECK-NEXT: orl %esi, %edi
60; CHECK-NEXT: setne %al
61; CHECK-NEXT: retq
62 %a = icmp ne i32 %P, 0
63 %b = icmp ne i32 %Q, 0
64 %c = or i1 %a, %b
65 ret i1 %c
66}
67
68define zeroext i1 @any_sign_bits_set(i32 %P, i32 %Q) nounwind {
69; CHECK-LABEL: any_sign_bits_set:
70; CHECK: # BB#0:
71; CHECK-NEXT: orl %esi, %edi
72; CHECK-NEXT: shrl $31, %edi
73; CHECK-NEXT: movl %edi, %eax
74; CHECK-NEXT: retq
75 %a = icmp slt i32 %P, 0
76 %b = icmp slt i32 %Q, 0
77 %c = or i1 %a, %b
78 ret i1 %c
79}
80
81define zeroext i1 @any_bits_clear(i32 %P, i32 %Q) nounwind {
82; CHECK-LABEL: any_bits_clear:
83; CHECK: # BB#0:
84; CHECK-NEXT: andl %esi, %edi
85; CHECK-NEXT: cmpl $-1, %edi
86; CHECK-NEXT: setne %al
87; CHECK-NEXT: retq
88 %a = icmp ne i32 %P, -1
89 %b = icmp ne i32 %Q, -1
90 %c = or i1 %a, %b
91 ret i1 %c
92}
93
94define zeroext i1 @any_sign_bits_clear(i32 %P, i32 %Q) nounwind {
95; CHECK-LABEL: any_sign_bits_clear:
96; CHECK: # BB#0:
97; CHECK-NEXT: testl %esi, %edi
98; CHECK-NEXT: setns %al
99; CHECK-NEXT: retq
100 %a = icmp sgt i32 %P, -1
101 %b = icmp sgt i32 %Q, -1
102 %c = or i1 %a, %b
103 ret i1 %c
104}
105
106; PR3351 - (P == 0) & (Q == 0) -> (P|Q) == 0
107define i32 @all_bits_clear_branch(i32* %P, i32* %Q) nounwind {
108; CHECK-LABEL: all_bits_clear_branch:
109; CHECK: # BB#0: # %entry
110; CHECK-NEXT: orq %rsi, %rdi
111; CHECK-NEXT: jne .LBB8_2
112; CHECK-NEXT: # BB#1: # %bb1
113; CHECK-NEXT: movl $4, %eax
114; CHECK-NEXT: retq
115; CHECK-NEXT: .LBB8_2: # %return
116; CHECK-NEXT: movl $192, %eax
117; CHECK-NEXT: retq
118entry:
119 %a = icmp eq i32* %P, null
120 %b = icmp eq i32* %Q, null
121 %c = and i1 %a, %b
122 br i1 %c, label %bb1, label %return
123
124bb1:
125 ret i32 4
126
127return:
128 ret i32 192
129}
130
131define i32 @all_sign_bits_clear_branch(i32 %P, i32 %Q) nounwind {
132; CHECK-LABEL: all_sign_bits_clear_branch:
133; CHECK: # BB#0: # %entry
134; CHECK-NEXT: testl %edi, %edi
135; CHECK-NEXT: js .LBB9_3
136; CHECK-NEXT: # BB#1: # %entry
137; CHECK-NEXT: testl %esi, %esi
138; CHECK-NEXT: js .LBB9_3
139; CHECK-NEXT: # BB#2: # %bb1
140; CHECK-NEXT: movl $4, %eax
141; CHECK-NEXT: retq
142; CHECK-NEXT: .LBB9_3: # %return
143; CHECK-NEXT: movl $192, %eax
144; CHECK-NEXT: retq
145entry:
146 %a = icmp sgt i32 %P, -1
147 %b = icmp sgt i32 %Q, -1
148 %c = and i1 %a, %b
149 br i1 %c, label %bb1, label %return
150
151bb1:
152 ret i32 4
153
154return:
155 ret i32 192
156}
157
158define i32 @all_bits_set_branch(i32 %P, i32 %Q) nounwind {
159; CHECK-LABEL: all_bits_set_branch:
160; CHECK: # BB#0: # %entry
161; CHECK-NEXT: cmpl $-1, %edi
162; CHECK-NEXT: jne .LBB10_3
163; CHECK-NEXT: # BB#1: # %entry
164; CHECK-NEXT: cmpl $-1, %esi
165; CHECK-NEXT: jne .LBB10_3
166; CHECK-NEXT: # BB#2: # %bb1
167; CHECK-NEXT: movl $4, %eax
168; CHECK-NEXT: retq
169; CHECK-NEXT: .LBB10_3: # %return
170; CHECK-NEXT: movl $192, %eax
171; CHECK-NEXT: retq
172entry:
173 %a = icmp eq i32 %P, -1
174 %b = icmp eq i32 %Q, -1
175 %c = and i1 %a, %b
176 br i1 %c, label %bb1, label %return
177
178bb1:
179 ret i32 4
180
181return:
182 ret i32 192
183}
184
185define i32 @all_sign_bits_set_branch(i32 %P, i32 %Q) nounwind {
186; CHECK-LABEL: all_sign_bits_set_branch:
187; CHECK: # BB#0: # %entry
188; CHECK-NEXT: testl %edi, %edi
189; CHECK-NEXT: jns .LBB11_3
190; CHECK-NEXT: # BB#1: # %entry
191; CHECK-NEXT: testl %esi, %esi
192; CHECK-NEXT: jns .LBB11_3
193; CHECK-NEXT: # BB#2: # %bb1
194; CHECK-NEXT: movl $4, %eax
195; CHECK-NEXT: retq
196; CHECK-NEXT: .LBB11_3: # %return
197; CHECK-NEXT: movl $192, %eax
198; CHECK-NEXT: retq
199entry:
200 %a = icmp slt i32 %P, 0
201 %b = icmp slt i32 %Q, 0
202 %c = and i1 %a, %b
203 br i1 %c, label %bb1, label %return
204
205bb1:
206 ret i32 4
207
208return:
209 ret i32 192
210}
211
212; PR3351 - (P != 0) | (Q != 0) -> (P|Q) != 0
213define i32 @any_bits_set_branch(i32* %P, i32* %Q) nounwind {
214; CHECK-LABEL: any_bits_set_branch:
215; CHECK: # BB#0: # %entry
216; CHECK-NEXT: orq %rsi, %rdi
217; CHECK-NEXT: je .LBB12_2
218; CHECK-NEXT: # BB#1: # %bb1
219; CHECK-NEXT: movl $4, %eax
220; CHECK-NEXT: retq
221; CHECK-NEXT: .LBB12_2: # %return
222; CHECK-NEXT: movl $192, %eax
223; CHECK-NEXT: retq
224entry:
225 %a = icmp ne i32* %P, null
226 %b = icmp ne i32* %Q, null
227 %c = or i1 %a, %b
228 br i1 %c, label %bb1, label %return
229
230bb1:
231 ret i32 4
232
233return:
234 ret i32 192
235}
236
237define i32 @any_sign_bits_set_branch(i32 %P, i32 %Q) nounwind {
238; CHECK-LABEL: any_sign_bits_set_branch:
239; CHECK: # BB#0: # %entry
240; CHECK-NEXT: testl %edi, %edi
241; CHECK-NEXT: js .LBB13_2
242; CHECK-NEXT: # BB#1: # %entry
243; CHECK-NEXT: testl %esi, %esi
244; CHECK-NEXT: js .LBB13_2
245; CHECK-NEXT: # BB#3: # %return
246; CHECK-NEXT: movl $192, %eax
247; CHECK-NEXT: retq
248; CHECK-NEXT: .LBB13_2: # %bb1
249; CHECK-NEXT: movl $4, %eax
250; CHECK-NEXT: retq
251entry:
252 %a = icmp slt i32 %P, 0
253 %b = icmp slt i32 %Q, 0
254 %c = or i1 %a, %b
255 br i1 %c, label %bb1, label %return
256
257bb1:
258 ret i32 4
259
260return:
261 ret i32 192
262}
263
264define i32 @any_bits_clear_branch(i32 %P, i32 %Q) nounwind {
265; CHECK-LABEL: any_bits_clear_branch:
266; CHECK: # BB#0: # %entry
267; CHECK-NEXT: cmpl $-1, %edi
268; CHECK-NEXT: jne .LBB14_2
269; CHECK-NEXT: # BB#1: # %entry
270; CHECK-NEXT: cmpl $-1, %esi
271; CHECK-NEXT: jne .LBB14_2
272; CHECK-NEXT: # BB#3: # %return
273; CHECK-NEXT: movl $192, %eax
274; CHECK-NEXT: retq
275; CHECK-NEXT: .LBB14_2: # %bb1
276; CHECK-NEXT: movl $4, %eax
277; CHECK-NEXT: retq
278entry:
279 %a = icmp ne i32 %P, -1
280 %b = icmp ne i32 %Q, -1
281 %c = or i1 %a, %b
282 br i1 %c, label %bb1, label %return
283
284bb1:
285 ret i32 4
286
287return:
288 ret i32 192
289}
290
291define i32 @any_sign_bits_clear_branch(i32 %P, i32 %Q) nounwind {
292; CHECK-LABEL: any_sign_bits_clear_branch:
293; CHECK: # BB#0: # %entry
294; CHECK-NEXT: testl %edi, %edi
295; CHECK-NEXT: jns .LBB15_2
296; CHECK-NEXT: # BB#1: # %entry
297; CHECK-NEXT: testl %esi, %esi
298; CHECK-NEXT: jns .LBB15_2
299; CHECK-NEXT: # BB#3: # %return
300; CHECK-NEXT: movl $192, %eax
301; CHECK-NEXT: retq
302; CHECK-NEXT: .LBB15_2: # %bb1
303; CHECK-NEXT: movl $4, %eax
304; CHECK-NEXT: retq
305entry:
306 %a = icmp sgt i32 %P, -1
307 %b = icmp sgt i32 %Q, -1
308 %c = or i1 %a, %b
309 br i1 %c, label %bb1, label %return
310
311bb1:
312 ret i32 4
313
314return:
315 ret i32 192
316}
317
318define zeroext i1 @ne_neg1_and_ne_zero(i64 %x) nounwind {
319; CHECK-LABEL: ne_neg1_and_ne_zero:
320; CHECK: # BB#0:
321; CHECK-NEXT: incq %rdi
322; CHECK-NEXT: cmpq $1, %rdi
323; CHECK-NEXT: seta %al
324; CHECK-NEXT: retq
325 %cmp1 = icmp ne i64 %x, -1
326 %cmp2 = icmp ne i64 %x, 0
327 %and = and i1 %cmp1, %cmp2
328 ret i1 %and
329}
330
331; PR32401 - https://bugs.llvm.org/show_bug.cgi?id=32401
332
333define zeroext i1 @cmpeq_logical(i8 %a, i8 %b, i8 %c, i8 %d) nounwind {
334; CHECK-LABEL: cmpeq_logical:
335; CHECK: # BB#0:
336; CHECK-NEXT: cmpb %sil, %dil
337; CHECK-NEXT: sete %sil
338; CHECK-NEXT: cmpb %cl, %dl
339; CHECK-NEXT: sete %al
340; CHECK-NEXT: andb %sil, %al
341; CHECK-NEXT: retq
342 %cmp1 = icmp eq i8 %a, %b
343 %cmp2 = icmp eq i8 %c, %d
344 %and = and i1 %cmp1, %cmp2
345 ret i1 %and
346}
347