| Matt Arsenault | f14db7a | 2016-07-20 15:20:35 +0000 | [diff] [blame] | 1 | ; RUN: opt -mtriple=amdgcn-- -S -structurizecfg -si-annotate-control-flow %s | FileCheck -check-prefix=OPT %s |
| 2 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s |
| 3 | |
| 4 | ; Uses llvm.amdgcn.break |
| 5 | |
| 6 | ; OPT-LABEL: @break_loop( |
| 7 | ; OPT: bb1: |
| 8 | ; OPT: call i64 @llvm.amdgcn.break(i64 |
| 9 | ; OPT-NEXT: br i1 %cmp0, label %bb4, label %Flow |
| 10 | |
| 11 | ; OPT: bb4: |
| 12 | ; OPT: load volatile |
| 13 | ; OPT: xor i1 %cmp1 |
| 14 | ; OPT: call i64 @llvm.amdgcn.if.break( |
| 15 | ; OPT: br label %Flow |
| 16 | |
| 17 | ; OPT: Flow: |
| 18 | ; OPT: call i1 @llvm.amdgcn.loop(i64 |
| 19 | ; OPT: br i1 %{{[0-9]+}}, label %bb9, label %bb1 |
| 20 | |
| 21 | ; OPT: bb9: |
| 22 | ; OPT: call void @llvm.amdgcn.end.cf(i64 |
| 23 | |
| 24 | ; TODO: Can remove exec fixes in return block |
| 25 | ; GCN-LABEL: {{^}}break_loop: |
| 26 | ; GCN: s_mov_b64 [[INITMASK:s\[[0-9]+:[0-9]+\]]], 0{{$}} |
| 27 | |
| 28 | ; GCN: [[LOOP_ENTRY:BB[0-9]+_[0-9]+]]: ; %bb1 |
| 29 | ; GCN: s_or_b64 [[MASK:s\[[0-9]+:[0-9]+\]]], exec, [[INITMASK]] |
| 30 | ; GCN: v_cmp_lt_i32_e32 vcc, |
| 31 | ; GCN: s_and_b64 vcc, exec, vcc |
| 32 | ; GCN-NEXT: s_cbranch_vccnz [[FLOW:BB[0-9]+_[0-9]+]] |
| 33 | |
| 34 | ; GCN: ; BB#2: ; %bb4 |
| 35 | ; GCN: buffer_load_dword |
| 36 | ; GCN: v_cmp_ge_i32_e32 vcc, |
| 37 | ; GCN: s_or_b64 [[MASK]], vcc, [[INITMASK]] |
| 38 | |
| 39 | ; GCN: [[FLOW]]: |
| 40 | ; GCN: s_mov_b64 [[INITMASK]], [[MASK]] |
| 41 | ; GCN: s_andn2_b64 exec, exec, [[MASK]] |
| 42 | ; GCN-NEXT: s_cbranch_execnz [[LOOP_ENTRY]] |
| 43 | |
| 44 | ; GCN: ; BB#4: ; %bb9 |
| 45 | ; GCN-NEXT: s_or_b64 exec, exec, [[MASK]] |
| 46 | ; GCN-NEXT: s_endpgm |
| 47 | define void @break_loop(i32 %arg) #0 { |
| 48 | bb: |
| 49 | %id = call i32 @llvm.amdgcn.workitem.id.x() |
| 50 | %tmp = sub i32 %id, %arg |
| 51 | br label %bb1 |
| 52 | |
| 53 | bb1: |
| 54 | %lsr.iv = phi i32 [ undef, %bb ], [ %lsr.iv.next, %bb4 ] |
| 55 | %lsr.iv.next = add i32 %lsr.iv, 1 |
| 56 | %cmp0 = icmp slt i32 %lsr.iv.next, 0 |
| 57 | br i1 %cmp0, label %bb4, label %bb9 |
| 58 | |
| 59 | bb4: |
| 60 | %load = load volatile i32, i32 addrspace(1)* undef, align 4 |
| 61 | %cmp1 = icmp slt i32 %tmp, %load |
| 62 | br i1 %cmp1, label %bb1, label %bb9 |
| 63 | |
| 64 | bb9: |
| 65 | ret void |
| 66 | } |
| 67 | |
| 68 | declare i32 @llvm.amdgcn.workitem.id.x() #1 |
| 69 | |
| 70 | attributes #0 = { nounwind } |
| 71 | attributes #1 = { nounwind readnone } |