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gerrit-public.fairphone.software / toolchain / llvm-project / 01cd2e7a4bc6af6fd33f1c4f8284b5d184dcec7b / . / llvm / test / CodeGen / Mips / llvm-ir / select-dbl.ll
blob: ed8d9030ccf767a9754d38b865c0263d26d3c35f [file] [log] [blame]
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=ALL -check-prefix=CMOV \
5; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN: -check-prefix=ALL -check-prefix=CMOV \
8; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN: -check-prefix=ALL -check-prefix=CMOV \
11; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN: -check-prefix=ALL -check-prefix=CMOV \
14; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]32define double @tst_select_i1_double(i1 %s, double %x, double %y) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]33entry:
34 ; ALL-LABEL: tst_select_i1_double:
35
36 ; M2: andi $[[T0:[0-9]+]], $4, 1
37 ; M2: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
38 ; M2: nop
39 ; M2: ldc1 $f0, 16($sp)
40 ; M2: jr $ra
41 ; M2: nop
42 ; M2: $[[BB0]]:
43 ; M2: mtc1 $7, $f0
44 ; M2: jr $ra
45 ; M2: mtc1 $6, $f1
46
47 ; CMOV-32: mtc1 $7, $[[F0:f[0-9]+]]
48 ; CMOV-32R1: mtc1 $6, $f{{[0-9]+}}
49 ; CMOV-32R2-R5: mthc1 $6, $[[F0]]
50 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
51 ; CMOV-32: ldc1 $f0, 16($sp)
52 ; CMOV-32: movn.d $f0, $[[F0]], $[[T0]]
53
54 ; SEL-32: mtc1 $7, $[[F0:f[0-9]+]]
55 ; SEL-32: mthc1 $6, $[[F0]]
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]56 ; SEL-32: sll $[[T0:[0-9]+]], $4, 31
57 ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]58 ; SEL-32: ldc1 $[[F1:f[0-9]+]], 16($sp)
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]59 ; SEL-32: mtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]60 ; SEL-32: sel.d $f0, $[[F1]], $[[F0]]
61
62 ; M3: andi $[[T0:[0-9]+]], $4, 1
63 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
64 ; M3: nop
65 ; M3: mov.d $f13, $f14
66 ; M3: $[[BB0]]:
67 ; M3: jr $ra
68 ; M3: mov.d $f0, $f13
69
70 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
71 ; CMOV-64: movn.d $f14, $f13, $[[T0]]
72 ; CMOV-64: mov.d $f0, $f14
73
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]74 ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63
75 ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
76 ; SEL-64: dmtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]77 ; SEL-64: sel.d $f0, $f14, $f13
78 %r = select i1 %s, double %x, double %y
79 ret double %r
80}
81
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]82define double @tst_select_i1_double_reordered(double %x, double %y, i1 %s) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]83entry:
84 ; ALL-LABEL: tst_select_i1_double_reordered:
85
86 ; M2: lw $[[T0:[0-9]+]], 16($sp)
87 ; M2: andi $[[T1:[0-9]+]], $[[T0]], 1
88 ; M2: bnez $[[T1]], $[[BB0:BB[0-9_]+]]
89 ; M2: nop
90 ; M2: mov.d $f12, $f14
91 ; M2: $[[BB0]]:
92 ; M2: jr $ra
93 ; M2: mov.d $f0, $f12
94
95 ; CMOV-32: lw $[[T0:[0-9]+]], 16($sp)
96 ; CMOV-32: andi $[[T1:[0-9]+]], $[[T0]], 1
97 ; CMOV-32: movn.d $f14, $f12, $[[T1]]
98 ; CMOV-32: mov.d $f0, $f14
99
100 ; SEL-32: lw $[[T0:[0-9]+]], 16($sp)
101 ; SEL-32: mtc1 $[[T0]], $f0
102 ; SEL-32: sel.d $f0, $f14, $f12
103
104 ; M3: andi $[[T0:[0-9]+]], $6, 1
105 ; M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
106 ; M3: nop
107 ; M3: mov.d $f12, $f13
108 ; M3: $[[BB0]]:
109 ; M3: jr $ra
110 ; M3: mov.d $f0, $f12
111
112 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
113 ; CMOV-64: movn.d $f13, $f12, $[[T0]]
114 ; CMOV-64: mov.d $f0, $f13
115
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]116 ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63
117 ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
118 ; SEL-64: dmtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]119 ; SEL-64: sel.d $f0, $f13, $f12
120 %r = select i1 %s, double %x, double %y
121 ret double %r
122}
123
124define double @tst_select_fcmp_olt_double(double %x, double %y) {
125entry:
126 ; ALL-LABEL: tst_select_fcmp_olt_double:
127
128 ; M2: c.olt.d $f12, $f14
129 ; M3: c.olt.d $f12, $f13
130 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
131 ; M2-M3: nop
132 ; M2: mov.d $f12, $f14
133 ; M3: mov.d $f12, $f13
134 ; M2-M3: $[[BB0]]:
135 ; M2-M3: jr $ra
136 ; M2-M3: mov.d $f0, $f12
137
138 ; CMOV-32: c.olt.d $f12, $f14
139 ; CMOV-32: movt.d $f14, $f12, $fcc0
140 ; CMOV-32: mov.d $f0, $f14
141
142 ; SEL-32: cmp.lt.d $f0, $f12, $f14
143 ; SEL-32: sel.d $f0, $f14, $f12
144
145 ; CMOV-64: c.olt.d $f12, $f13
146 ; CMOV-64: movt.d $f13, $f12, $fcc0
147 ; CMOV-64: mov.d $f0, $f13
148
149 ; SEL-64: cmp.lt.d $f0, $f12, $f13
150 ; SEL-64: sel.d $f0, $f13, $f12
151 %s = fcmp olt double %x, %y
152 %r = select i1 %s, double %x, double %y
153 ret double %r
154}
155
156define double @tst_select_fcmp_ole_double(double %x, double %y) {
157entry:
158 ; ALL-LABEL: tst_select_fcmp_ole_double:
159
160 ; M2: c.ole.d $f12, $f14
161 ; M3: c.ole.d $f12, $f13
162 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
163 ; M2-M3: nop
164 ; M2: mov.d $f12, $f14
165 ; M3: mov.d $f12, $f13
166 ; M2-M3: $[[BB0]]:
167 ; M2-M3: jr $ra
168 ; M2-M3: mov.d $f0, $f12
169
170 ; CMOV-32: c.ole.d $f12, $f14
171 ; CMOV-32: movt.d $f14, $f12, $fcc0
172 ; CMOV-32: mov.d $f0, $f14
173
174 ; SEL-32: cmp.le.d $f0, $f12, $f14
175 ; SEL-32: sel.d $f0, $f14, $f12
176
177 ; CMOV-64: c.ole.d $f12, $f13
178 ; CMOV-64: movt.d $f13, $f12, $fcc0
179 ; CMOV-64: mov.d $f0, $f13
180
181 ; SEL-64: cmp.le.d $f0, $f12, $f13
182 ; SEL-64: sel.d $f0, $f13, $f12
183 %s = fcmp ole double %x, %y
184 %r = select i1 %s, double %x, double %y
185 ret double %r
186}
187
188define double @tst_select_fcmp_ogt_double(double %x, double %y) {
189entry:
190 ; ALL-LABEL: tst_select_fcmp_ogt_double:
191
192 ; M2: c.ule.d $f12, $f14
193 ; M3: c.ule.d $f12, $f13
194 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
195 ; M2-M3: nop
196 ; M2: mov.d $f12, $f14
197 ; M3: mov.d $f12, $f13
198 ; M2-M3: $[[BB0]]:
199 ; M2-M3: jr $ra
200 ; M2-M3: mov.d $f0, $f12
201
202 ; CMOV-32: c.ule.d $f12, $f14
203 ; CMOV-32: movf.d $f14, $f12, $fcc0
204 ; CMOV-32: mov.d $f0, $f14
205
206 ; SEL-32: cmp.lt.d $f0, $f14, $f12
207 ; SEL-32: sel.d $f0, $f14, $f12
208
209 ; CMOV-64: c.ule.d $f12, $f13
210 ; CMOV-64: movf.d $f13, $f12, $fcc0
211 ; CMOV-64: mov.d $f0, $f13
212
213 ; SEL-64: cmp.lt.d $f0, $f13, $f12
214 ; SEL-64: sel.d $f0, $f13, $f12
215 %s = fcmp ogt double %x, %y
216 %r = select i1 %s, double %x, double %y
217 ret double %r
218}
219
220define double @tst_select_fcmp_oge_double(double %x, double %y) {
221entry:
222 ; ALL-LABEL: tst_select_fcmp_oge_double:
223
224 ; M2: c.ult.d $f12, $f14
225 ; M3: c.ult.d $f12, $f13
226 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
227 ; M2-M3: nop
228 ; M2: mov.d $f12, $f14
229 ; M3: mov.d $f12, $f13
230 ; M2-M3: $[[BB0]]:
231 ; M2-M3: jr $ra
232 ; M2-M3: mov.d $f0, $f12
233
234 ; CMOV-32: c.ult.d $f12, $f14
235 ; CMOV-32: movf.d $f14, $f12, $fcc0
236 ; CMOV-32: mov.d $f0, $f14
237
238 ; SEL-32: cmp.le.d $f0, $f14, $f12
239 ; SEL-32: sel.d $f0, $f14, $f12
240
241 ; CMOV-64: c.ult.d $f12, $f13
242 ; CMOV-64: movf.d $f13, $f12, $fcc0
243 ; CMOV-64: mov.d $f0, $f13
244
245 ; SEL-64: cmp.le.d $f0, $f13, $f12
246 ; SEL-64: sel.d $f0, $f13, $f12
247 %s = fcmp oge double %x, %y
248 %r = select i1 %s, double %x, double %y
249 ret double %r
250}
251
252define double @tst_select_fcmp_oeq_double(double %x, double %y) {
253entry:
254 ; ALL-LABEL: tst_select_fcmp_oeq_double:
255
256 ; M2: c.eq.d $f12, $f14
257 ; M3: c.eq.d $f12, $f13
258 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
259 ; M2-M3: nop
260 ; M2: mov.d $f12, $f14
261 ; M3: mov.d $f12, $f13
262 ; M2-M3: $[[BB0]]:
263 ; M2-M3: jr $ra
264 ; M2-M3: mov.d $f0, $f12
265
266 ; CMOV-32: c.eq.d $f12, $f14
267 ; CMOV-32: movt.d $f14, $f12, $fcc0
268 ; CMOV-32: mov.d $f0, $f14
269
270 ; SEL-32: cmp.eq.d $f0, $f12, $f14
271 ; SEL-32: sel.d $f0, $f14, $f12
272
273 ; CMOV-64: c.eq.d $f12, $f13
274 ; CMOV-64: movt.d $f13, $f12, $fcc0
275 ; CMOV-64: mov.d $f0, $f13
276
277 ; SEL-64: cmp.eq.d $f0, $f12, $f13
278 ; SEL-64: sel.d $f0, $f13, $f12
279 %s = fcmp oeq double %x, %y
280 %r = select i1 %s, double %x, double %y
281 ret double %r
282}
283
284define double @tst_select_fcmp_one_double(double %x, double %y) {
285entry:
286 ; ALL-LABEL: tst_select_fcmp_one_double:
287
288 ; M2: c.ueq.d $f12, $f14
289 ; M3: c.ueq.d $f12, $f13
290 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
291 ; M2-M3: nop
292 ; M2: mov.d $f12, $f14
293 ; M3: mov.d $f12, $f13
294 ; M2-M3: $[[BB0]]:
295 ; M2-M3: jr $ra
296 ; M2-M3: mov.d $f0, $f12
297
298 ; CMOV-32: c.ueq.d $f12, $f14
299 ; CMOV-32: movf.d $f14, $f12, $fcc0
300 ; CMOV-32: mov.d $f0, $f14
301
302 ; SEL-32: cmp.ueq.d $f0, $f12, $f14
303 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
304 ; SEL-32: not $[[T0]], $[[T0]]
305 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
306 ; SEL-32: sel.d $f0, $f14, $f12
307
308 ; CMOV-64: c.ueq.d $f12, $f13
309 ; CMOV-64: movf.d $f13, $f12, $fcc0
310 ; CMOV-64: mov.d $f0, $f13
311
312 ; SEL-64: cmp.ueq.d $f0, $f12, $f13
313 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
314 ; SEL-64: not $[[T0]], $[[T0]]
315 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
316 ; SEL-64: sel.d $f0, $f13, $f12
317 %s = fcmp one double %x, %y
318 %r = select i1 %s, double %x, double %y
319 ret double %r
320}