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gerrit-public.fairphone.software / toolchain / llvm-project / 01cd2e7a4bc6af6fd33f1c4f8284b5d184dcec7b / . / llvm / test / CodeGen / Mips / llvm-ir / select-flt.ll
blob: c554c6983bfb1b973687651cd371bfdbd3908819 [file] [log] [blame]
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]1; RUN: llc < %s -march=mips -mcpu=mips2 | FileCheck %s \
2; RUN: -check-prefix=ALL -check-prefix=M2 -check-prefix=M2-M3
3; RUN: llc < %s -march=mips -mcpu=mips32 | FileCheck %s \
4; RUN: -check-prefix=ALL -check-prefix=CMOV \
5; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R1
6; RUN: llc < %s -march=mips -mcpu=mips32r2 | FileCheck %s \
7; RUN: -check-prefix=ALL -check-prefix=CMOV \
8; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
9; RUN: llc < %s -march=mips -mcpu=mips32r3 | FileCheck %s \
10; RUN: -check-prefix=ALL -check-prefix=CMOV \
11; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
12; RUN: llc < %s -march=mips -mcpu=mips32r5 | FileCheck %s \
13; RUN: -check-prefix=ALL -check-prefix=CMOV \
14; RUN: -check-prefix=CMOV-32 -check-prefix=CMOV-32R2-R5
15; RUN: llc < %s -march=mips -mcpu=mips32r6 | FileCheck %s \
16; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-32
17; RUN: llc < %s -march=mips64 -mcpu=mips3 | FileCheck %s \
18; RUN: -check-prefix=ALL -check-prefix=M3 -check-prefix=M2-M3
19; RUN: llc < %s -march=mips64 -mcpu=mips4 | FileCheck %s \
20; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
21; RUN: llc < %s -march=mips64 -mcpu=mips64 | FileCheck %s \
22; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
23; RUN: llc < %s -march=mips64 -mcpu=mips64r2 | FileCheck %s \
24; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
25; RUN: llc < %s -march=mips64 -mcpu=mips64r3 | FileCheck %s \
26; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
27; RUN: llc < %s -march=mips64 -mcpu=mips64r5 | FileCheck %s \
28; RUN: -check-prefix=ALL -check-prefix=CMOV -check-prefix=CMOV-64
29; RUN: llc < %s -march=mips64 -mcpu=mips64r6 | FileCheck %s \
30; RUN: -check-prefix=ALL -check-prefix=SEL -check-prefix=SEL-64
31
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]32define float @tst_select_i1_float(i1 %s, float %x, float %y) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]33entry:
34 ; ALL-LABEL: tst_select_i1_float:
35
36 ; M2-M3: andi $[[T0:[0-9]+]], $4, 1
37 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
38 ; M2-M3: nop
39 ; M2: jr $ra
40 ; M2: mtc1 $6, $f0
41 ; M3: mov.s $f13, $f14
42 ; M2-M3: $[[BB0]]:
43 ; M2-M3: jr $ra
44 ; M2: mtc1 $5, $f0
45 ; M3: mov.s $f0, $f13
46
47 ; CMOV-32: mtc1 $6, $f0
48 ; CMOV-32: mtc1 $5, $f1
49 ; CMOV-32: andi $[[T0:[0-9]+]], $4, 1
50 ; CMOV-32: movn.s $f0, $f1, $[[T0]]
51
52 ; SEL-32: mtc1 $5, $[[F0:f[0-9]+]]
53 ; SEL-32: mtc1 $6, $[[F1:f[0-9]+]]
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]54 ; SEL-32: sll $[[T0:[0-9]+]], $4, 31
55 ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
56 ; SEL-32: mtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]57 ; SEL-32: sel.s $f0, $[[F1]], $[[F0]]
58
59 ; CMOV-64: andi $[[T0:[0-9]+]], $4, 1
60 ; CMOV-64: movn.s $f14, $f13, $[[T0]]
61 ; CMOV-64: mov.s $f0, $f14
62
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]63 ; SEL-64: dsll $[[T0:[0-9]+]], $4, 63
64 ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
65 ; SEL-64: dmtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]66 ; SEL-64: sel.s $f0, $f14, $f13
67 %r = select i1 %s, float %x, float %y
68 ret float %r
69}
70
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]71define float @tst_select_i1_float_reordered(float %x, float %y, i1 %s) {
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]72entry:
73 ; ALL-LABEL: tst_select_i1_float_reordered:
74
75 ; M2-M3: andi $[[T0:[0-9]+]], $6, 1
76 ; M2-M3: bnez $[[T0]], $[[BB0:BB[0-9_]+]]
77 ; M2-M3: nop
78 ; M2: mov.s $f12, $f14
79 ; M3: mov.s $f12, $f13
80 ; M2-M3: $[[BB0]]:
81 ; M2-M3: jr $ra
82 ; M2-M3: mov.s $f0, $f12
83
84 ; CMOV-32: andi $[[T0:[0-9]+]], $6, 1
85 ; CMOV-32: movn.s $f14, $f12, $[[T0]]
86 ; CMOV-32: mov.s $f0, $f14
87
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]88 ; SEL-32: sll $[[T0:[0-9]+]], $6, 31
89 ; SEL-32: sra $[[T1:[0-9]+]], $[[T0]], 31
90 ; SEL-32: mtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]91 ; SEL-32: sel.s $f0, $f14, $f12
92
93 ; CMOV-64: andi $[[T0:[0-9]+]], $6, 1
94 ; CMOV-64: movn.s $f13, $f12, $[[T0]]
95 ; CMOV-64: mov.s $f0, $f13
96
Vasileios Kalintiris3a8f7f92016-03-01 10:08:01 +0000[diff] [blame]97 ; SEL-64: dsll $[[T0:[0-9]+]], $6, 63
98 ; SEL-64: dsra $[[T1:[0-9]+]], $[[T0]], 63
99 ; SEL-64: dmtc1 $[[T1]], $f0
Vasileios Kalintirisa0520372016-02-01 15:19:35 +0000[diff] [blame]100 ; SEL-64: sel.s $f0, $f13, $f12
101 %r = select i1 %s, float %x, float %y
102 ret float %r
103}
104
105define float @tst_select_fcmp_olt_float(float %x, float %y) {
106entry:
107 ; ALL-LABEL: tst_select_fcmp_olt_float:
108
109 ; M2: c.olt.s $f12, $f14
110 ; M3: c.olt.s $f12, $f13
111 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
112 ; M2-M3: nop
113 ; M2: mov.s $f12, $f14
114 ; M3: mov.s $f12, $f13
115 ; M2-M3: $[[BB0]]:
116 ; M2-M3: jr $ra
117 ; M2-M3: mov.s $f0, $f12
118
119 ; CMOV-32: c.olt.s $f12, $f14
120 ; CMOV-32: movt.s $f14, $f12, $fcc0
121 ; CMOV-32: mov.s $f0, $f14
122
123 ; SEL-32: cmp.lt.s $f0, $f12, $f14
124 ; SEL-32: sel.s $f0, $f14, $f12
125
126 ; CMOV-64: c.olt.s $f12, $f13
127 ; CMOV-64: movt.s $f13, $f12, $fcc0
128 ; CMOV-64: mov.s $f0, $f13
129
130 ; SEL-64: cmp.lt.s $f0, $f12, $f13
131 ; SEL-64: sel.s $f0, $f13, $f12
132 %s = fcmp olt float %x, %y
133 %r = select i1 %s, float %x, float %y
134 ret float %r
135}
136
137define float @tst_select_fcmp_ole_float(float %x, float %y) {
138entry:
139 ; ALL-LABEL: tst_select_fcmp_ole_float:
140
141 ; M2: c.ole.s $f12, $f14
142 ; M3: c.ole.s $f12, $f13
143 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
144 ; M2-M3: nop
145 ; M2: mov.s $f12, $f14
146 ; M3: mov.s $f12, $f13
147 ; M2-M3: $[[BB0]]:
148 ; M2-M3: jr $ra
149 ; M2-M3: mov.s $f0, $f12
150
151 ; CMOV-32: c.ole.s $f12, $f14
152 ; CMOV-32: movt.s $f14, $f12, $fcc0
153 ; CMOV-32: mov.s $f0, $f14
154
155 ; SEL-32: cmp.le.s $f0, $f12, $f14
156 ; SEL-32: sel.s $f0, $f14, $f12
157
158 ; CMOV-64: c.ole.s $f12, $f13
159 ; CMOV-64: movt.s $f13, $f12, $fcc0
160 ; CMOV-64: mov.s $f0, $f13
161
162 ; SEL-64: cmp.le.s $f0, $f12, $f13
163 ; SEL-64: sel.s $f0, $f13, $f12
164 %s = fcmp ole float %x, %y
165 %r = select i1 %s, float %x, float %y
166 ret float %r
167}
168
169define float @tst_select_fcmp_ogt_float(float %x, float %y) {
170entry:
171 ; ALL-LABEL: tst_select_fcmp_ogt_float:
172
173 ; M2: c.ule.s $f12, $f14
174 ; M3: c.ule.s $f12, $f13
175 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
176 ; M2-M3: nop
177 ; M2: mov.s $f12, $f14
178 ; M3: mov.s $f12, $f13
179 ; M2-M3: $[[BB0]]:
180 ; M2-M3: jr $ra
181 ; M2-M3: mov.s $f0, $f12
182
183 ; CMOV-32: c.ule.s $f12, $f14
184 ; CMOV-32: movf.s $f14, $f12, $fcc0
185 ; CMOV-32: mov.s $f0, $f14
186
187 ; SEL-32: cmp.lt.s $f0, $f14, $f12
188 ; SEL-32: sel.s $f0, $f14, $f12
189
190 ; CMOV-64: c.ule.s $f12, $f13
191 ; CMOV-64: movf.s $f13, $f12, $fcc0
192 ; CMOV-64: mov.s $f0, $f13
193
194 ; SEL-64: cmp.lt.s $f0, $f13, $f12
195 ; SEL-64: sel.s $f0, $f13, $f12
196 %s = fcmp ogt float %x, %y
197 %r = select i1 %s, float %x, float %y
198 ret float %r
199}
200
201define float @tst_select_fcmp_oge_float(float %x, float %y) {
202entry:
203 ; ALL-LABEL: tst_select_fcmp_oge_float:
204
205 ; M2: c.ult.s $f12, $f14
206 ; M3: c.ult.s $f12, $f13
207 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
208 ; M2-M3: nop
209 ; M2: mov.s $f12, $f14
210 ; M3: mov.s $f12, $f13
211 ; M2-M3: $[[BB0]]:
212 ; M2-M3: jr $ra
213 ; M2-M3: mov.s $f0, $f12
214
215 ; CMOV-32: c.ult.s $f12, $f14
216 ; CMOV-32: movf.s $f14, $f12, $fcc0
217 ; CMOV-32: mov.s $f0, $f14
218
219 ; SEL-32: cmp.le.s $f0, $f14, $f12
220 ; SEL-32: sel.s $f0, $f14, $f12
221
222 ; CMOV-64: c.ult.s $f12, $f13
223 ; CMOV-64: movf.s $f13, $f12, $fcc0
224 ; CMOV-64: mov.s $f0, $f13
225
226 ; SEL-64: cmp.le.s $f0, $f13, $f12
227 ; SEL-64: sel.s $f0, $f13, $f12
228 %s = fcmp oge float %x, %y
229 %r = select i1 %s, float %x, float %y
230 ret float %r
231}
232
233define float @tst_select_fcmp_oeq_float(float %x, float %y) {
234entry:
235 ; ALL-LABEL: tst_select_fcmp_oeq_float:
236
237 ; M2: c.eq.s $f12, $f14
238 ; M3: c.eq.s $f12, $f13
239 ; M2-M3: bc1t $[[BB0:BB[0-9_]+]]
240 ; M2-M3: nop
241 ; M2: mov.s $f12, $f14
242 ; M3: mov.s $f12, $f13
243 ; M2-M3: $[[BB0]]:
244 ; M2-M3: jr $ra
245 ; M2-M3: mov.s $f0, $f12
246
247 ; CMOV-32: c.eq.s $f12, $f14
248 ; CMOV-32: movt.s $f14, $f12, $fcc0
249 ; CMOV-32: mov.s $f0, $f14
250
251 ; SEL-32: cmp.eq.s $f0, $f12, $f14
252 ; SEL-32: sel.s $f0, $f14, $f12
253
254 ; CMOV-64: c.eq.s $f12, $f13
255 ; CMOV-64: movt.s $f13, $f12, $fcc0
256 ; CMOV-64: mov.s $f0, $f13
257
258 ; SEL-64: cmp.eq.s $f0, $f12, $f13
259 ; SEL-64: sel.s $f0, $f13, $f12
260 %s = fcmp oeq float %x, %y
261 %r = select i1 %s, float %x, float %y
262 ret float %r
263}
264
265define float @tst_select_fcmp_one_float(float %x, float %y) {
266entry:
267 ; ALL-LABEL: tst_select_fcmp_one_float:
268
269 ; M2: c.ueq.s $f12, $f14
270 ; M3: c.ueq.s $f12, $f13
271 ; M2-M3: bc1f $[[BB0:BB[0-9_]+]]
272 ; M2-M3: nop
273 ; M2: mov.s $f12, $f14
274 ; M3: mov.s $f12, $f13
275 ; M2-M3: $[[BB0]]:
276 ; M2-M3: jr $ra
277 ; M2-M3: mov.s $f0, $f12
278
279 ; CMOV-32: c.ueq.s $f12, $f14
280 ; CMOV-32: movf.s $f14, $f12, $fcc0
281 ; CMOV-32: mov.s $f0, $f14
282
283 ; SEL-32: cmp.ueq.s $f0, $f12, $f14
284 ; SEL-32: mfc1 $[[T0:[0-9]+]], $f0
285 ; SEL-32: not $[[T0]], $[[T0]]
286 ; SEL-32: mtc1 $[[T0:[0-9]+]], $f0
287 ; SEL-32: sel.s $f0, $f14, $f12
288
289 ; CMOV-64: c.ueq.s $f12, $f13
290 ; CMOV-64: movf.s $f13, $f12, $fcc0
291 ; CMOV-64: mov.s $f0, $f13
292
293 ; SEL-64: cmp.ueq.s $f0, $f12, $f13
294 ; SEL-64: mfc1 $[[T0:[0-9]+]], $f0
295 ; SEL-64: not $[[T0]], $[[T0]]
296 ; SEL-64: mtc1 $[[T0:[0-9]+]], $f0
297 ; SEL-64: sel.s $f0, $f13, $f12
298
299 %s = fcmp one float %x, %y
300 %r = select i1 %s, float %x, float %y
301 ret float %r
302}