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gerrit-public.fairphone.software / toolchain / llvm-project / de16172d9d7cdc5dccf66e8a55aef43bc2381526 / . / llvm / lib / Target / AArch64 / AArch64LoadStoreOptimizer.cpp
blob: 48d49d8a73ada25cecd4893e8b89fe5d780d582c [file] [log] [blame]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1//=- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that performs load / store related peephole
11// optimizations. This pass should be run after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstrInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]16#include "AArch64Subtarget.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "llvm/ADT/BitVector.h"
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/ADT/Statistic.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]21#include "llvm/CodeGen/MachineBasicBlock.h"
22#include "llvm/CodeGen/MachineFunctionPass.h"
23#include "llvm/CodeGen/MachineInstr.h"
24#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]25#include "llvm/Support/CommandLine.h"
26#include "llvm/Support/Debug.h"
27#include "llvm/Support/ErrorHandling.h"
28#include "llvm/Support/raw_ostream.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]29#include "llvm/Target/TargetInstrInfo.h"
30#include "llvm/Target/TargetMachine.h"
31#include "llvm/Target/TargetRegisterInfo.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]32using namespace llvm;
33
34#define DEBUG_TYPE "aarch64-ldst-opt"
35
36/// AArch64AllocLoadStoreOpt - Post-register allocation pass to combine
37/// load / store instructions to form ldp / stp instructions.
38
39STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
40STATISTIC(NumPostFolded, "Number of post-index updates folded");
41STATISTIC(NumPreFolded, "Number of pre-index updates folded");
42STATISTIC(NumUnscaledPairCreated,
43 "Number of load/store from unscaled generated");
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]44STATISTIC(NumNarrowLoadsPromoted, "Number of narrow loads promoted");
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]45STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]46STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]48static cl::opt<unsigned> ScanLimit("aarch64-load-store-scan-limit",
49 cl::init(20), cl::Hidden);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]50
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]51namespace llvm {
52void initializeAArch64LoadStoreOptPass(PassRegistry &);
53}
54
55#define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
56
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]57namespace {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]58
59typedef struct LdStPairFlags {
60 // If a matching instruction is found, MergeForward is set to true if the
61 // merge is to remove the first instruction and replace the second with
62 // a pair-wise insn, and false if the reverse is true.
63 bool MergeForward;
64
65 // SExtIdx gives the index of the result of the load pair that must be
66 // extended. The value of SExtIdx assumes that the paired load produces the
67 // value in this order: (I, returned iterator), i.e., -1 means no value has
68 // to be extended, 0 means I, and 1 means the returned iterator.
69 int SExtIdx;
70
71 LdStPairFlags() : MergeForward(false), SExtIdx(-1) {}
72
73 void setMergeForward(bool V = true) { MergeForward = V; }
74 bool getMergeForward() const { return MergeForward; }
75
76 void setSExtIdx(int V) { SExtIdx = V; }
77 int getSExtIdx() const { return SExtIdx; }
78
79} LdStPairFlags;
80
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]81struct AArch64LoadStoreOpt : public MachineFunctionPass {
82 static char ID;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]83 AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]84 initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
85 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]86
87 const AArch64InstrInfo *TII;
88 const TargetRegisterInfo *TRI;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]89 const AArch64Subtarget *Subtarget;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]90
91 // Scan the instructions looking for a load/store that can be combined
92 // with the current instruction into a load/store pair.
93 // Return the matching instruction if one is found, else MBB->end().
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]94 MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]95 LdStPairFlags &Flags,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]96 unsigned Limit);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]97
98 // Scan the instructions looking for a store that writes to the address from
99 // which the current load instruction reads. Return true if one is found.
100 bool findMatchingStore(MachineBasicBlock::iterator I, unsigned Limit,
101 MachineBasicBlock::iterator &StoreI);
102
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]103 // Merge the two instructions indicated into a single pair-wise instruction.
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]104 // If MergeForward is true, erase the first instruction and fold its
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]105 // operation into the second. If false, the reverse. Return the instruction
106 // following the first instruction (which may change during processing).
107 MachineBasicBlock::iterator
108 mergePairedInsns(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]109 MachineBasicBlock::iterator Paired,
Chad Rosierfe5399f2015-07-21 17:47:56 +0000[diff] [blame]110 const LdStPairFlags &Flags);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]111
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]112 // Promote the load that reads directly from the address stored to.
113 MachineBasicBlock::iterator
114 promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
115 MachineBasicBlock::iterator StoreI);
116
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]117 // Scan the instruction list to find a base register update that can
118 // be combined with the current instruction (a load or store) using
119 // pre or post indexed addressing with writeback. Scan forwards.
120 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]121 findMatchingUpdateInsnForward(MachineBasicBlock::iterator I,
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]122 int UnscaledOffset);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]123
124 // Scan the instruction list to find a base register update that can
125 // be combined with the current instruction (a load or store) using
126 // pre or post indexed addressing with writeback. Scan backwards.
127 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]128 findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]129
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]130 // Find an instruction that updates the base register of the ld/st
131 // instruction.
132 bool isMatchingUpdateInsn(MachineInstr *MemMI, MachineInstr *MI,
133 unsigned BaseReg, int Offset);
134
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]135 // Merge a pre- or post-index base register update into a ld/st instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]136 MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]137 mergeUpdateInsn(MachineBasicBlock::iterator I,
138 MachineBasicBlock::iterator Update, bool IsPreIdx);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]139
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]140 // Find and merge foldable ldr/str instructions.
141 bool tryToMergeLdStInst(MachineBasicBlock::iterator &MBBI);
142
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]143 // Find and promote load instructions which read directly from store.
144 bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
145
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]146 // Check if converting two narrow loads into a single wider load with
147 // bitfield extracts could be enabled.
148 bool enableNarrowLdMerge(MachineFunction &Fn);
149
150 bool optimizeBlock(MachineBasicBlock &MBB, bool enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]151
152 bool runOnMachineFunction(MachineFunction &Fn) override;
153
154 const char *getPassName() const override {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]155 return AARCH64_LOAD_STORE_OPT_NAME;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]156 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]157};
158char AArch64LoadStoreOpt::ID = 0;
Jim Grosbach1eee3df2014-08-11 22:42:31 +0000[diff] [blame]159} // namespace
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]160
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]161INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
162 AARCH64_LOAD_STORE_OPT_NAME, false, false)
163
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]164static bool isUnscaledLdSt(unsigned Opc) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]165 switch (Opc) {
166 default:
167 return false;
168 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]169 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]170 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]171 case AArch64::STURBBi:
172 case AArch64::STURHHi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]173 case AArch64::STURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]174 case AArch64::STURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]175 case AArch64::LDURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]176 case AArch64::LDURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]177 case AArch64::LDURQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]178 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]179 case AArch64::LDURXi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]180 case AArch64::LDURSWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]181 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]182 case AArch64::LDURBBi:
183 case AArch64::LDURSBWi:
184 case AArch64::LDURSHWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]185 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186 }
187}
188
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]189static bool isUnscaledLdSt(MachineInstr *MI) {
190 return isUnscaledLdSt(MI->getOpcode());
191}
192
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]193static unsigned getBitExtrOpcode(MachineInstr *MI) {
194 switch (MI->getOpcode()) {
195 default:
196 llvm_unreachable("Unexpected opcode.");
197 case AArch64::LDRBBui:
198 case AArch64::LDURBBi:
199 case AArch64::LDRHHui:
200 case AArch64::LDURHHi:
201 return AArch64::UBFMWri;
202 case AArch64::LDRSBWui:
203 case AArch64::LDURSBWi:
204 case AArch64::LDRSHWui:
205 case AArch64::LDURSHWi:
206 return AArch64::SBFMWri;
207 }
208}
209
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]210static bool isNarrowStore(unsigned Opc) {
211 switch (Opc) {
212 default:
213 return false;
214 case AArch64::STRBBui:
215 case AArch64::STURBBi:
216 case AArch64::STRHHui:
217 case AArch64::STURHHi:
218 return true;
219 }
220}
221
222static bool isNarrowStore(MachineInstr *MI) {
223 return isNarrowStore(MI->getOpcode());
224}
225
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]226static bool isNarrowLoad(unsigned Opc) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]227 switch (Opc) {
228 default:
229 return false;
230 case AArch64::LDRHHui:
231 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]232 case AArch64::LDRBBui:
233 case AArch64::LDURBBi:
234 case AArch64::LDRSHWui:
235 case AArch64::LDURSHWi:
236 case AArch64::LDRSBWui:
237 case AArch64::LDURSBWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]238 return true;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]239 }
240}
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]241
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]242static bool isNarrowLoad(MachineInstr *MI) {
243 return isNarrowLoad(MI->getOpcode());
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]244}
245
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]246// Scaling factor for unscaled load or store.
247static int getMemScale(MachineInstr *MI) {
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]248 switch (MI->getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]249 default:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]250 llvm_unreachable("Opcode has unknown scale!");
251 case AArch64::LDRBBui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]252 case AArch64::LDURBBi:
253 case AArch64::LDRSBWui:
254 case AArch64::LDURSBWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]255 case AArch64::STRBBui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]256 case AArch64::STURBBi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]257 return 1;
258 case AArch64::LDRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]259 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]260 case AArch64::LDRSHWui:
261 case AArch64::LDURSHWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]262 case AArch64::STRHHui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]263 case AArch64::STURHHi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]264 return 2;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]265 case AArch64::LDRSui:
266 case AArch64::LDURSi:
267 case AArch64::LDRSWui:
268 case AArch64::LDURSWi:
269 case AArch64::LDRWui:
270 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]271 case AArch64::STRSui:
272 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]273 case AArch64::STRWui:
274 case AArch64::STURWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]275 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]276 case AArch64::LDPSWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]277 case AArch64::LDPWi:
278 case AArch64::STPSi:
279 case AArch64::STPWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]280 return 4;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]281 case AArch64::LDRDui:
282 case AArch64::LDURDi:
283 case AArch64::LDRXui:
284 case AArch64::LDURXi:
285 case AArch64::STRDui:
286 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]287 case AArch64::STRXui:
288 case AArch64::STURXi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]289 case AArch64::LDPDi:
290 case AArch64::LDPXi:
291 case AArch64::STPDi:
292 case AArch64::STPXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]293 return 8;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]294 case AArch64::LDRQui:
295 case AArch64::LDURQi:
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]296 case AArch64::STRQui:
297 case AArch64::STURQi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]298 case AArch64::LDPQi:
299 case AArch64::STPQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]300 return 16;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]301 }
302}
303
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]304static unsigned getMatchingNonSExtOpcode(unsigned Opc,
305 bool *IsValidLdStrOpc = nullptr) {
306 if (IsValidLdStrOpc)
307 *IsValidLdStrOpc = true;
308 switch (Opc) {
309 default:
310 if (IsValidLdStrOpc)
311 *IsValidLdStrOpc = false;
312 return UINT_MAX;
313 case AArch64::STRDui:
314 case AArch64::STURDi:
315 case AArch64::STRQui:
316 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]317 case AArch64::STRBBui:
318 case AArch64::STURBBi:
319 case AArch64::STRHHui:
320 case AArch64::STURHHi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]321 case AArch64::STRWui:
322 case AArch64::STURWi:
323 case AArch64::STRXui:
324 case AArch64::STURXi:
325 case AArch64::LDRDui:
326 case AArch64::LDURDi:
327 case AArch64::LDRQui:
328 case AArch64::LDURQi:
329 case AArch64::LDRWui:
330 case AArch64::LDURWi:
331 case AArch64::LDRXui:
332 case AArch64::LDURXi:
333 case AArch64::STRSui:
334 case AArch64::STURSi:
335 case AArch64::LDRSui:
336 case AArch64::LDURSi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]337 case AArch64::LDRHHui:
338 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]339 case AArch64::LDRBBui:
340 case AArch64::LDURBBi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]341 return Opc;
342 case AArch64::LDRSWui:
343 return AArch64::LDRWui;
344 case AArch64::LDURSWi:
345 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]346 case AArch64::LDRSBWui:
347 return AArch64::LDRBBui;
348 case AArch64::LDRSHWui:
349 return AArch64::LDRHHui;
350 case AArch64::LDURSBWi:
351 return AArch64::LDURBBi;
352 case AArch64::LDURSHWi:
353 return AArch64::LDURHHi;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]354 }
355}
356
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]357static unsigned getMatchingPairOpcode(unsigned Opc) {
358 switch (Opc) {
359 default:
360 llvm_unreachable("Opcode has no pairwise equivalent!");
361 case AArch64::STRSui:
362 case AArch64::STURSi:
363 return AArch64::STPSi;
364 case AArch64::STRDui:
365 case AArch64::STURDi:
366 return AArch64::STPDi;
367 case AArch64::STRQui:
368 case AArch64::STURQi:
369 return AArch64::STPQi;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]370 case AArch64::STRBBui:
371 return AArch64::STRHHui;
372 case AArch64::STRHHui:
373 return AArch64::STRWui;
374 case AArch64::STURBBi:
375 return AArch64::STURHHi;
376 case AArch64::STURHHi:
377 return AArch64::STURWi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]378 case AArch64::STRWui:
379 case AArch64::STURWi:
380 return AArch64::STPWi;
381 case AArch64::STRXui:
382 case AArch64::STURXi:
383 return AArch64::STPXi;
384 case AArch64::LDRSui:
385 case AArch64::LDURSi:
386 return AArch64::LDPSi;
387 case AArch64::LDRDui:
388 case AArch64::LDURDi:
389 return AArch64::LDPDi;
390 case AArch64::LDRQui:
391 case AArch64::LDURQi:
392 return AArch64::LDPQi;
393 case AArch64::LDRWui:
394 case AArch64::LDURWi:
395 return AArch64::LDPWi;
396 case AArch64::LDRXui:
397 case AArch64::LDURXi:
398 return AArch64::LDPXi;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]399 case AArch64::LDRSWui:
400 case AArch64::LDURSWi:
401 return AArch64::LDPSWi;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]402 case AArch64::LDRHHui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]403 case AArch64::LDRSHWui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]404 return AArch64::LDRWui;
405 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]406 case AArch64::LDURSHWi:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]407 return AArch64::LDURWi;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]408 case AArch64::LDRBBui:
409 case AArch64::LDRSBWui:
410 return AArch64::LDRHHui;
411 case AArch64::LDURBBi:
412 case AArch64::LDURSBWi:
413 return AArch64::LDURHHi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]414 }
415}
416
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]417static unsigned isMatchingStore(MachineInstr *LoadInst,
418 MachineInstr *StoreInst) {
419 unsigned LdOpc = LoadInst->getOpcode();
420 unsigned StOpc = StoreInst->getOpcode();
421 switch (LdOpc) {
422 default:
423 llvm_unreachable("Unsupported load instruction!");
424 case AArch64::LDRBBui:
425 return StOpc == AArch64::STRBBui || StOpc == AArch64::STRHHui ||
426 StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
427 case AArch64::LDURBBi:
428 return StOpc == AArch64::STURBBi || StOpc == AArch64::STURHHi ||
429 StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
430 case AArch64::LDRHHui:
431 return StOpc == AArch64::STRHHui || StOpc == AArch64::STRWui ||
432 StOpc == AArch64::STRXui;
433 case AArch64::LDURHHi:
434 return StOpc == AArch64::STURHHi || StOpc == AArch64::STURWi ||
435 StOpc == AArch64::STURXi;
436 case AArch64::LDRWui:
437 return StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
438 case AArch64::LDURWi:
439 return StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
440 case AArch64::LDRXui:
441 return StOpc == AArch64::STRXui;
442 case AArch64::LDURXi:
443 return StOpc == AArch64::STURXi;
444 }
445}
446
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]447static unsigned getPreIndexedOpcode(unsigned Opc) {
448 switch (Opc) {
449 default:
450 llvm_unreachable("Opcode has no pre-indexed equivalent!");
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]451 case AArch64::STRSui:
452 return AArch64::STRSpre;
453 case AArch64::STRDui:
454 return AArch64::STRDpre;
455 case AArch64::STRQui:
456 return AArch64::STRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]457 case AArch64::STRBBui:
458 return AArch64::STRBBpre;
459 case AArch64::STRHHui:
460 return AArch64::STRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]461 case AArch64::STRWui:
462 return AArch64::STRWpre;
463 case AArch64::STRXui:
464 return AArch64::STRXpre;
465 case AArch64::LDRSui:
466 return AArch64::LDRSpre;
467 case AArch64::LDRDui:
468 return AArch64::LDRDpre;
469 case AArch64::LDRQui:
470 return AArch64::LDRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]471 case AArch64::LDRBBui:
472 return AArch64::LDRBBpre;
473 case AArch64::LDRHHui:
474 return AArch64::LDRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]475 case AArch64::LDRWui:
476 return AArch64::LDRWpre;
477 case AArch64::LDRXui:
478 return AArch64::LDRXpre;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]479 case AArch64::LDRSWui:
480 return AArch64::LDRSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]481 case AArch64::LDPSi:
482 return AArch64::LDPSpre;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]483 case AArch64::LDPSWi:
484 return AArch64::LDPSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]485 case AArch64::LDPDi:
486 return AArch64::LDPDpre;
487 case AArch64::LDPQi:
488 return AArch64::LDPQpre;
489 case AArch64::LDPWi:
490 return AArch64::LDPWpre;
491 case AArch64::LDPXi:
492 return AArch64::LDPXpre;
493 case AArch64::STPSi:
494 return AArch64::STPSpre;
495 case AArch64::STPDi:
496 return AArch64::STPDpre;
497 case AArch64::STPQi:
498 return AArch64::STPQpre;
499 case AArch64::STPWi:
500 return AArch64::STPWpre;
501 case AArch64::STPXi:
502 return AArch64::STPXpre;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]503 }
504}
505
506static unsigned getPostIndexedOpcode(unsigned Opc) {
507 switch (Opc) {
508 default:
509 llvm_unreachable("Opcode has no post-indexed wise equivalent!");
510 case AArch64::STRSui:
511 return AArch64::STRSpost;
512 case AArch64::STRDui:
513 return AArch64::STRDpost;
514 case AArch64::STRQui:
515 return AArch64::STRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]516 case AArch64::STRBBui:
517 return AArch64::STRBBpost;
518 case AArch64::STRHHui:
519 return AArch64::STRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]520 case AArch64::STRWui:
521 return AArch64::STRWpost;
522 case AArch64::STRXui:
523 return AArch64::STRXpost;
524 case AArch64::LDRSui:
525 return AArch64::LDRSpost;
526 case AArch64::LDRDui:
527 return AArch64::LDRDpost;
528 case AArch64::LDRQui:
529 return AArch64::LDRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]530 case AArch64::LDRBBui:
531 return AArch64::LDRBBpost;
532 case AArch64::LDRHHui:
533 return AArch64::LDRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]534 case AArch64::LDRWui:
535 return AArch64::LDRWpost;
536 case AArch64::LDRXui:
537 return AArch64::LDRXpost;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]538 case AArch64::LDRSWui:
539 return AArch64::LDRSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]540 case AArch64::LDPSi:
541 return AArch64::LDPSpost;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]542 case AArch64::LDPSWi:
543 return AArch64::LDPSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]544 case AArch64::LDPDi:
545 return AArch64::LDPDpost;
546 case AArch64::LDPQi:
547 return AArch64::LDPQpost;
548 case AArch64::LDPWi:
549 return AArch64::LDPWpost;
550 case AArch64::LDPXi:
551 return AArch64::LDPXpost;
552 case AArch64::STPSi:
553 return AArch64::STPSpost;
554 case AArch64::STPDi:
555 return AArch64::STPDpost;
556 case AArch64::STPQi:
557 return AArch64::STPQpost;
558 case AArch64::STPWi:
559 return AArch64::STPWpost;
560 case AArch64::STPXi:
561 return AArch64::STPXpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]562 }
563}
564
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]565static bool isPairedLdSt(const MachineInstr *MI) {
566 switch (MI->getOpcode()) {
567 default:
568 return false;
569 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]570 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]571 case AArch64::LDPDi:
572 case AArch64::LDPQi:
573 case AArch64::LDPWi:
574 case AArch64::LDPXi:
575 case AArch64::STPSi:
576 case AArch64::STPDi:
577 case AArch64::STPQi:
578 case AArch64::STPWi:
579 case AArch64::STPXi:
580 return true;
581 }
582}
583
584static const MachineOperand &getLdStRegOp(const MachineInstr *MI,
585 unsigned PairedRegOp = 0) {
586 assert(PairedRegOp < 2 && "Unexpected register operand idx.");
587 unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
588 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]589}
590
591static const MachineOperand &getLdStBaseOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]592 unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
593 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]594}
595
596static const MachineOperand &getLdStOffsetOp(const MachineInstr *MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]597 unsigned Idx = isPairedLdSt(MI) ? 3 : 2;
598 return MI->getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]599}
600
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]601static bool isLdOffsetInRangeOfSt(MachineInstr *LoadInst,
602 MachineInstr *StoreInst) {
603 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
604 int LoadSize = getMemScale(LoadInst);
605 int StoreSize = getMemScale(StoreInst);
606 int UnscaledStOffset = isUnscaledLdSt(StoreInst)
607 ? getLdStOffsetOp(StoreInst).getImm()
608 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
609 int UnscaledLdOffset = isUnscaledLdSt(LoadInst)
610 ? getLdStOffsetOp(LoadInst).getImm()
611 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
612 return (UnscaledStOffset <= UnscaledLdOffset) &&
613 (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
614}
615
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]616MachineBasicBlock::iterator
617AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
618 MachineBasicBlock::iterator Paired,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]619 const LdStPairFlags &Flags) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]620 MachineBasicBlock::iterator NextI = I;
621 ++NextI;
622 // If NextI is the second of the two instructions to be merged, we need
623 // to skip one further. Either way we merge will invalidate the iterator,
624 // and we don't need to scan the new instruction, as it's a pairwise
625 // instruction, which we're not considering for further action anyway.
626 if (NextI == Paired)
627 ++NextI;
628
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]629 int SExtIdx = Flags.getSExtIdx();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]630 unsigned Opc =
631 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]632 bool IsUnscaled = isUnscaledLdSt(Opc);
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]633 int OffsetStride = IsUnscaled ? getMemScale(I) : 1;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]634
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]635 bool MergeForward = Flags.getMergeForward();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]636 unsigned NewOpc = getMatchingPairOpcode(Opc);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]637 // Insert our new paired instruction after whichever of the paired
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]638 // instructions MergeForward indicates.
639 MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
640 // Also based on MergeForward is from where we copy the base register operand
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]641 // so we get the flags compatible with the input code.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]642 const MachineOperand &BaseRegOp =
643 MergeForward ? getLdStBaseOp(Paired) : getLdStBaseOp(I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]644
645 // Which register is Rt and which is Rt2 depends on the offset order.
646 MachineInstr *RtMI, *Rt2MI;
Chad Rosier08ef4622015-09-03 16:41:28 +0000[diff] [blame]647 if (getLdStOffsetOp(I).getImm() ==
648 getLdStOffsetOp(Paired).getImm() + OffsetStride) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]649 RtMI = Paired;
650 Rt2MI = I;
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]651 // Here we swapped the assumption made for SExtIdx.
652 // I.e., we turn ldp I, Paired into ldp Paired, I.
653 // Update the index accordingly.
654 if (SExtIdx != -1)
655 SExtIdx = (SExtIdx + 1) % 2;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]656 } else {
657 RtMI = I;
658 Rt2MI = Paired;
659 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]660
James Molloy5b18b4c2015-10-23 10:41:38 +0000[diff] [blame]661 int OffsetImm = getLdStOffsetOp(RtMI).getImm();
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]662
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]663 if (isNarrowLoad(Opc)) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]664 // Change the scaled offset from small to large type.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]665 if (!IsUnscaled) {
666 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]667 OffsetImm /= 2;
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]668 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]669 MachineInstr *RtNewDest = MergeForward ? I : Paired;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]670 // When merging small (< 32 bit) loads for big-endian targets, the order of
671 // the component parts gets swapped.
672 if (!Subtarget->isLittleEndian())
673 std::swap(RtMI, Rt2MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]674 // Construct the new load instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]675 MachineInstr *NewMemMI, *BitExtMI1, *BitExtMI2;
676 NewMemMI = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
677 TII->get(NewOpc))
678 .addOperand(getLdStRegOp(RtNewDest))
679 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]680 .addImm(OffsetImm)
681 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]682
683 DEBUG(
684 dbgs()
685 << "Creating the new load and extract. Replacing instructions:\n ");
686 DEBUG(I->print(dbgs()));
687 DEBUG(dbgs() << " ");
688 DEBUG(Paired->print(dbgs()));
689 DEBUG(dbgs() << " with instructions:\n ");
690 DEBUG((NewMemMI)->print(dbgs()));
691
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]692 int Width = getMemScale(I) == 1 ? 8 : 16;
693 int LSBLow = 0;
694 int LSBHigh = Width;
695 int ImmsLow = LSBLow + Width - 1;
696 int ImmsHigh = LSBHigh + Width - 1;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]697 MachineInstr *ExtDestMI = MergeForward ? Paired : I;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]698 if ((ExtDestMI == Rt2MI) == Subtarget->isLittleEndian()) {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]699 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]700 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]701 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]702 .addOperand(getLdStRegOp(Rt2MI))
703 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]704 .addImm(LSBHigh)
705 .addImm(ImmsHigh);
706 // Create the bitfield extract for low bits.
707 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
708 // For unsigned, prefer to use AND for low bits.
709 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
710 TII->get(AArch64::ANDWri))
711 .addOperand(getLdStRegOp(RtMI))
712 .addReg(getLdStRegOp(RtNewDest).getReg())
713 .addImm(ImmsLow);
714 } else {
715 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
716 TII->get(getBitExtrOpcode(RtMI)))
717 .addOperand(getLdStRegOp(RtMI))
718 .addReg(getLdStRegOp(RtNewDest).getReg())
719 .addImm(LSBLow)
720 .addImm(ImmsLow);
721 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]722 } else {
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]723 // Create the bitfield extract for low bits.
724 if (RtMI->getOpcode() == getMatchingNonSExtOpcode(RtMI->getOpcode())) {
725 // For unsigned, prefer to use AND for low bits.
726 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
727 TII->get(AArch64::ANDWri))
728 .addOperand(getLdStRegOp(RtMI))
729 .addReg(getLdStRegOp(RtNewDest).getReg())
730 .addImm(ImmsLow);
731 } else {
732 BitExtMI1 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
733 TII->get(getBitExtrOpcode(RtMI)))
734 .addOperand(getLdStRegOp(RtMI))
735 .addReg(getLdStRegOp(RtNewDest).getReg())
736 .addImm(LSBLow)
737 .addImm(ImmsLow);
738 }
739
740 // Create the bitfield extract for high bits.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]741 BitExtMI2 = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]742 TII->get(getBitExtrOpcode(Rt2MI)))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]743 .addOperand(getLdStRegOp(Rt2MI))
744 .addReg(getLdStRegOp(RtNewDest).getReg())
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]745 .addImm(LSBHigh)
746 .addImm(ImmsHigh);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]747 }
748 DEBUG(dbgs() << " ");
749 DEBUG((BitExtMI1)->print(dbgs()));
750 DEBUG(dbgs() << " ");
751 DEBUG((BitExtMI2)->print(dbgs()));
752 DEBUG(dbgs() << "\n");
753
754 // Erase the old instructions.
755 I->eraseFromParent();
756 Paired->eraseFromParent();
757 return NextI;
758 }
759
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]760 // Construct the new instruction.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]761 MachineInstrBuilder MIB;
762 if (isNarrowStore(Opc)) {
763 // Change the scaled offset from small to large type.
764 if (!IsUnscaled) {
765 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
766 OffsetImm /= 2;
767 }
768 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
769 TII->get(NewOpc))
770 .addOperand(getLdStRegOp(I))
771 .addOperand(BaseRegOp)
Philip Reamesc86ed002016-01-06 04:39:03 +0000[diff] [blame]772 .addImm(OffsetImm)
773 .setMemRefs(I->mergeMemRefsWith(*Paired));
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]774 } else {
775 // Handle Unscaled
776 if (IsUnscaled)
777 OffsetImm /= OffsetStride;
778 MIB = BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
779 TII->get(NewOpc))
780 .addOperand(getLdStRegOp(RtMI))
781 .addOperand(getLdStRegOp(Rt2MI))
782 .addOperand(BaseRegOp)
783 .addImm(OffsetImm);
784 }
785
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]786 (void)MIB;
787
788 // FIXME: Do we need/want to copy the mem operands from the source
789 // instructions? Probably. What uses them after this?
790
791 DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
792 DEBUG(I->print(dbgs()));
793 DEBUG(dbgs() << " ");
794 DEBUG(Paired->print(dbgs()));
795 DEBUG(dbgs() << " with instruction:\n ");
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]796
797 if (SExtIdx != -1) {
798 // Generate the sign extension for the proper result of the ldp.
799 // I.e., with X1, that would be:
800 // %W1<def> = KILL %W1, %X1<imp-def>
801 // %X1<def> = SBFMXri %X1<kill>, 0, 31
802 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
803 // Right now, DstMO has the extended register, since it comes from an
804 // extended opcode.
805 unsigned DstRegX = DstMO.getReg();
806 // Get the W variant of that register.
807 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
808 // Update the result of LDP to use the W instead of the X variant.
809 DstMO.setReg(DstRegW);
810 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
811 DEBUG(dbgs() << "\n");
812 // Make the machine verifier happy by providing a definition for
813 // the X register.
814 // Insert this definition right after the generated LDP, i.e., before
815 // InsertionPoint.
816 MachineInstrBuilder MIBKill =
817 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
818 TII->get(TargetOpcode::KILL), DstRegW)
819 .addReg(DstRegW)
820 .addReg(DstRegX, RegState::Define);
821 MIBKill->getOperand(2).setImplicit();
822 // Create the sign extension.
823 MachineInstrBuilder MIBSXTW =
824 BuildMI(*I->getParent(), InsertionPoint, I->getDebugLoc(),
825 TII->get(AArch64::SBFMXri), DstRegX)
826 .addReg(DstRegX)
827 .addImm(0)
828 .addImm(31);
829 (void)MIBSXTW;
830 DEBUG(dbgs() << " Extend operand:\n ");
831 DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
832 DEBUG(dbgs() << "\n");
833 } else {
834 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
835 DEBUG(dbgs() << "\n");
836 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]837
838 // Erase the old instructions.
839 I->eraseFromParent();
840 Paired->eraseFromParent();
841
842 return NextI;
843}
844
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]845MachineBasicBlock::iterator
846AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
847 MachineBasicBlock::iterator StoreI) {
848 MachineBasicBlock::iterator NextI = LoadI;
849 ++NextI;
850
851 int LoadSize = getMemScale(LoadI);
852 int StoreSize = getMemScale(StoreI);
853 unsigned LdRt = getLdStRegOp(LoadI).getReg();
854 unsigned StRt = getLdStRegOp(StoreI).getReg();
855 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
856
857 assert((IsStoreXReg ||
858 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
859 "Unexpected RegClass");
860
861 MachineInstr *BitExtMI;
862 if (LoadSize == StoreSize && (LoadSize == 4 || LoadSize == 8)) {
863 // Remove the load, if the destination register of the loads is the same
864 // register for stored value.
865 if (StRt == LdRt && LoadSize == 8) {
866 DEBUG(dbgs() << "Remove load instruction:\n ");
867 DEBUG(LoadI->print(dbgs()));
868 DEBUG(dbgs() << "\n");
869 LoadI->eraseFromParent();
870 return NextI;
871 }
872 // Replace the load with a mov if the load and store are in the same size.
873 BitExtMI =
874 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
875 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
876 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
877 .addReg(StRt)
878 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0));
879 } else {
880 // FIXME: Currently we disable this transformation in big-endian targets as
881 // performance and correctness are verified only in little-endian.
882 if (!Subtarget->isLittleEndian())
883 return NextI;
884 bool IsUnscaled = isUnscaledLdSt(LoadI);
885 assert(IsUnscaled == isUnscaledLdSt(StoreI) && "Unsupported ld/st match");
886 assert(LoadSize <= StoreSize && "Invalid load size");
887 int UnscaledLdOffset = IsUnscaled
888 ? getLdStOffsetOp(LoadI).getImm()
889 : getLdStOffsetOp(LoadI).getImm() * LoadSize;
890 int UnscaledStOffset = IsUnscaled
891 ? getLdStOffsetOp(StoreI).getImm()
892 : getLdStOffsetOp(StoreI).getImm() * StoreSize;
893 int Width = LoadSize * 8;
894 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
895 int Imms = Immr + Width - 1;
896 unsigned DestReg = IsStoreXReg
897 ? TRI->getMatchingSuperReg(LdRt, AArch64::sub_32,
898 &AArch64::GPR64RegClass)
899 : LdRt;
900
901 assert((UnscaledLdOffset >= UnscaledStOffset &&
902 (UnscaledLdOffset + LoadSize) <= UnscaledStOffset + StoreSize) &&
903 "Invalid offset");
904
905 Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
906 Imms = Immr + Width - 1;
907 if (UnscaledLdOffset == UnscaledStOffset) {
908 uint32_t AndMaskEncoded = ((IsStoreXReg ? 1 : 0) << 12) // N
909 | ((Immr) << 6) // immr
910 | ((Imms) << 0) // imms
911 ;
912
913 BitExtMI =
914 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
915 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
916 DestReg)
917 .addReg(StRt)
918 .addImm(AndMaskEncoded);
919 } else {
920 BitExtMI =
921 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
922 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
923 DestReg)
924 .addReg(StRt)
925 .addImm(Immr)
926 .addImm(Imms);
927 }
928 }
929
930 DEBUG(dbgs() << "Promoting load by replacing :\n ");
931 DEBUG(StoreI->print(dbgs()));
932 DEBUG(dbgs() << " ");
933 DEBUG(LoadI->print(dbgs()));
934 DEBUG(dbgs() << " with instructions:\n ");
935 DEBUG(StoreI->print(dbgs()));
936 DEBUG(dbgs() << " ");
937 DEBUG((BitExtMI)->print(dbgs()));
938 DEBUG(dbgs() << "\n");
939
940 // Erase the old instructions.
941 LoadI->eraseFromParent();
942 return NextI;
943}
944
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]945/// trackRegDefsUses - Remember what registers the specified instruction uses
946/// and modifies.
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]947static void trackRegDefsUses(const MachineInstr *MI, BitVector &ModifiedRegs,
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]948 BitVector &UsedRegs,
949 const TargetRegisterInfo *TRI) {
Pete Cooper7be8f8f2015-08-03 19:04:32 +0000[diff] [blame]950 for (const MachineOperand &MO : MI->operands()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]951 if (MO.isRegMask())
952 ModifiedRegs.setBitsNotInMask(MO.getRegMask());
953
954 if (!MO.isReg())
955 continue;
956 unsigned Reg = MO.getReg();
957 if (MO.isDef()) {
958 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
959 ModifiedRegs.set(*AI);
960 } else {
961 assert(MO.isUse() && "Reg operand not a def and not a use?!?");
962 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
963 UsedRegs.set(*AI);
964 }
965 }
966}
967
968static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]969 // Convert the byte-offset used by unscaled into an "element" offset used
970 // by the scaled pair load/store instructions.
Chad Rosier08ef4622015-09-03 16:41:28 +0000[diff] [blame]971 if (IsUnscaled)
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]972 Offset /= OffsetStride;
973
974 return Offset <= 63 && Offset >= -64;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]975}
976
977// Do alignment, specialized to power of 2 and for signed ints,
978// avoiding having to do a C-style cast from uint_64t to int when
Rui Ueyamada00f2f2016-01-14 21:06:47 +0000[diff] [blame]979// using alignTo from include/llvm/Support/MathExtras.h.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]980// FIXME: Move this function to include/MathExtras.h?
981static int alignTo(int Num, int PowOf2) {
982 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
983}
984
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]985static bool mayAlias(MachineInstr *MIa, MachineInstr *MIb,
986 const AArch64InstrInfo *TII) {
987 // One of the instructions must modify memory.
988 if (!MIa->mayStore() && !MIb->mayStore())
989 return false;
990
991 // Both instructions must be memory operations.
992 if (!MIa->mayLoadOrStore() && !MIb->mayLoadOrStore())
993 return false;
994
995 return !TII->areMemAccessesTriviallyDisjoint(MIa, MIb);
996}
997
998static bool mayAlias(MachineInstr *MIa,
999 SmallVectorImpl<MachineInstr *> &MemInsns,
1000 const AArch64InstrInfo *TII) {
1001 for (auto &MIb : MemInsns)
1002 if (mayAlias(MIa, MIb, TII))
1003 return true;
1004
1005 return false;
1006}
1007
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1008bool AArch64LoadStoreOpt::findMatchingStore(
1009 MachineBasicBlock::iterator I, unsigned Limit,
1010 MachineBasicBlock::iterator &StoreI) {
1011 MachineBasicBlock::iterator E = I->getParent()->begin();
1012 MachineBasicBlock::iterator MBBI = I;
1013 MachineInstr *FirstMI = I;
1014 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1015
1016 // Track which registers have been modified and used between the first insn
1017 // and the second insn.
1018 BitVector ModifiedRegs, UsedRegs;
1019 ModifiedRegs.resize(TRI->getNumRegs());
1020 UsedRegs.resize(TRI->getNumRegs());
1021
1022 for (unsigned Count = 0; MBBI != E && Count < Limit;) {
1023 --MBBI;
1024 MachineInstr *MI = MBBI;
1025 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1026 // optimization by changing how far we scan.
1027 if (MI->isDebugValue())
1028 continue;
1029 // Now that we know this is a real instruction, count it.
1030 ++Count;
1031
1032 // If the load instruction reads directly from the address to which the
1033 // store instruction writes and the stored value is not modified, we can
1034 // promote the load. Since we do not handle stores with pre-/post-index,
1035 // it's unnecessary to check if BaseReg is modified by the store itself.
1036 if (MI->mayStore() && isMatchingStore(FirstMI, MI) &&
1037 BaseReg == getLdStBaseOp(MI).getReg() &&
1038 isLdOffsetInRangeOfSt(FirstMI, MI) &&
1039 !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
1040 StoreI = MBBI;
1041 return true;
1042 }
1043
1044 if (MI->isCall())
1045 return false;
1046
1047 // Update modified / uses register lists.
1048 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1049
1050 // Otherwise, if the base register is modified, we have no match, so
1051 // return early.
1052 if (ModifiedRegs[BaseReg])
1053 return false;
1054
1055 // If we encounter a store aliased with the load, return early.
1056 if (MI->mayStore() && mayAlias(FirstMI, MI, TII))
1057 return false;
1058 }
1059 return false;
1060}
1061
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1062/// findMatchingInsn - Scan the instructions looking for a load/store that can
1063/// be combined with the current instruction into a load/store pair.
1064MachineBasicBlock::iterator
1065AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1066 LdStPairFlags &Flags, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1067 MachineBasicBlock::iterator E = I->getParent()->end();
1068 MachineBasicBlock::iterator MBBI = I;
1069 MachineInstr *FirstMI = I;
1070 ++MBBI;
1071
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1072 unsigned Opc = FirstMI->getOpcode();
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]1073 bool MayLoad = FirstMI->mayLoad();
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1074 bool IsUnscaled = isUnscaledLdSt(FirstMI);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1075 unsigned Reg = getLdStRegOp(FirstMI).getReg();
1076 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1077 int Offset = getLdStOffsetOp(FirstMI).getImm();
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1078 bool IsNarrowStore = isNarrowStore(Opc);
1079
1080 // For narrow stores, find only the case where the stored value is WZR.
1081 if (IsNarrowStore && Reg != AArch64::WZR)
1082 return E;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1083
1084 // Early exit if the first instruction modifies the base register.
1085 // e.g., ldr x0, [x0]
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1086 if (FirstMI->modifiesRegister(BaseReg, TRI))
1087 return E;
Chad Rosiercaed6db2015-08-10 17:17:19 +0000[diff] [blame]1088
1089 // Early exit if the offset if not possible to match. (6 bits of positive
1090 // range, plus allow an extra one in case we find a later insn that matches
1091 // with Offset-1)
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]1092 int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1093 if (!(isNarrowLoad(Opc) || IsNarrowStore) &&
1094 !inBoundsForPair(IsUnscaled, Offset, OffsetStride))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1095 return E;
1096
1097 // Track which registers have been modified and used between the first insn
1098 // (inclusive) and the second insn.
1099 BitVector ModifiedRegs, UsedRegs;
1100 ModifiedRegs.resize(TRI->getNumRegs());
1101 UsedRegs.resize(TRI->getNumRegs());
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1102
1103 // Remember any instructions that read/write memory between FirstMI and MI.
1104 SmallVector<MachineInstr *, 4> MemInsns;
1105
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1106 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
1107 MachineInstr *MI = MBBI;
1108 // Skip DBG_VALUE instructions. Otherwise debug info can affect the
1109 // optimization by changing how far we scan.
1110 if (MI->isDebugValue())
1111 continue;
1112
1113 // Now that we know this is a real instruction, count it.
1114 ++Count;
1115
Chad Rosier08ef4622015-09-03 16:41:28 +0000[diff] [blame]1116 bool CanMergeOpc = Opc == MI->getOpcode();
1117 Flags.setSExtIdx(-1);
1118 if (!CanMergeOpc) {
1119 bool IsValidLdStrOpc;
1120 unsigned NonSExtOpc = getMatchingNonSExtOpcode(Opc, &IsValidLdStrOpc);
1121 assert(IsValidLdStrOpc &&
1122 "Given Opc should be a Load or Store with an immediate");
1123 // Opc will be the first instruction in the pair.
1124 Flags.setSExtIdx(NonSExtOpc == (unsigned)Opc ? 1 : 0);
1125 CanMergeOpc = NonSExtOpc == getMatchingNonSExtOpcode(MI->getOpcode());
1126 }
1127
1128 if (CanMergeOpc && getLdStOffsetOp(MI).isImm()) {
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1129 assert(MI->mayLoadOrStore() && "Expected memory operation.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1130 // If we've found another instruction with the same opcode, check to see
1131 // if the base and offset are compatible with our starting instruction.
1132 // These instructions all have scaled immediate operands, so we just
1133 // check for +1/-1. Make sure to check the new instruction offset is
1134 // actually an immediate and not a symbolic reference destined for
1135 // a relocation.
1136 //
1137 // Pairwise instructions have a 7-bit signed offset field. Single insns
1138 // have a 12-bit unsigned offset field. To be a valid combine, the
1139 // final offset must be in range.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1140 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
1141 int MIOffset = getLdStOffsetOp(MI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1142 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1143 (Offset + OffsetStride == MIOffset))) {
1144 int MinOffset = Offset < MIOffset ? Offset : MIOffset;
1145 // If this is a volatile load/store that otherwise matched, stop looking
1146 // as something is going on that we don't have enough information to
1147 // safely transform. Similarly, stop if we see a hint to avoid pairs.
1148 if (MI->hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
1149 return E;
1150 // If the resultant immediate offset of merging these instructions
1151 // is out of range for a pairwise instruction, bail and keep looking.
Chad Rosier08ef4622015-09-03 16:41:28 +0000[diff] [blame]1152 bool MIIsUnscaled = isUnscaledLdSt(MI);
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1153 bool IsNarrowLoad = isNarrowLoad(MI->getOpcode());
1154 if (!IsNarrowLoad &&
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1155 !inBoundsForPair(MIIsUnscaled, MinOffset, OffsetStride)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1156 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1157 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1158 continue;
1159 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1160
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1161 if (IsNarrowLoad || IsNarrowStore) {
1162 // If the alignment requirements of the scaled wide load/store
1163 // instruction can't express the offset of the scaled narrow
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1164 // input, bail and keep looking.
1165 if (!IsUnscaled && alignTo(MinOffset, 2) != MinOffset) {
1166 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1167 MemInsns.push_back(MI);
1168 continue;
1169 }
1170 } else {
1171 // If the alignment requirements of the paired (scaled) instruction
1172 // can't express the offset of the unscaled input, bail and keep
1173 // looking.
1174 if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
1175 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1176 MemInsns.push_back(MI);
1177 continue;
1178 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1179 }
1180 // If the destination register of the loads is the same register, bail
1181 // and keep looking. A load-pair instruction with both destination
1182 // registers the same is UNPREDICTABLE and will result in an exception.
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1183 // For narrow stores, allow only when the stored value is the same
1184 // (i.e., WZR).
1185 if ((MayLoad && Reg == getLdStRegOp(MI).getReg()) ||
1186 (IsNarrowStore && Reg != getLdStRegOp(MI).getReg())) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1187 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Chad Rosierc56a9132015-08-10 18:42:45 +0000[diff] [blame]1188 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1189 continue;
1190 }
1191
1192 // If the Rt of the second instruction was not modified or used between
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1193 // the two instructions and none of the instructions between the second
1194 // and first alias with the second, we can combine the second into the
1195 // first.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1196 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
1197 !(MI->mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1198 !mayAlias(MI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1199 Flags.setMergeForward(false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1200 return MBBI;
1201 }
1202
1203 // Likewise, if the Rt of the first instruction is not modified or used
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1204 // between the two instructions and none of the instructions between the
1205 // first and the second alias with the first, we can combine the first
1206 // into the second.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1207 if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
Chad Rosier5f668e12015-09-03 14:19:43 +0000[diff] [blame]1208 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1209 !mayAlias(FirstMI, MemInsns, TII)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1210 Flags.setMergeForward(true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1211 return MBBI;
1212 }
1213 // Unable to combine these instructions due to interference in between.
1214 // Keep looking.
1215 }
1216 }
1217
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1218 // If the instruction wasn't a matching load or store. Stop searching if we
1219 // encounter a call instruction that might modify memory.
1220 if (MI->isCall())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1221 return E;
1222
1223 // Update modified / uses register lists.
1224 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1225
1226 // Otherwise, if the base register is modified, we have no match, so
1227 // return early.
1228 if (ModifiedRegs[BaseReg])
1229 return E;
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1230
1231 // Update list of instructions that read/write memory.
1232 if (MI->mayLoadOrStore())
1233 MemInsns.push_back(MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1234 }
1235 return E;
1236}
1237
1238MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1239AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
1240 MachineBasicBlock::iterator Update,
1241 bool IsPreIdx) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1242 assert((Update->getOpcode() == AArch64::ADDXri ||
1243 Update->getOpcode() == AArch64::SUBXri) &&
1244 "Unexpected base register update instruction to merge!");
1245 MachineBasicBlock::iterator NextI = I;
1246 // Return the instruction following the merged instruction, which is
1247 // the instruction following our unmerged load. Unless that's the add/sub
1248 // instruction we're merging, in which case it's the one after that.
1249 if (++NextI == Update)
1250 ++NextI;
1251
1252 int Value = Update->getOperand(2).getImm();
1253 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1254 "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1255 if (Update->getOpcode() == AArch64::SUBXri)
1256 Value = -Value;
1257
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1258 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1259 : getPostIndexedOpcode(I->getOpcode());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1260 MachineInstrBuilder MIB;
1261 if (!isPairedLdSt(I)) {
1262 // Non-paired instruction.
1263 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1264 .addOperand(getLdStRegOp(Update))
1265 .addOperand(getLdStRegOp(I))
1266 .addOperand(getLdStBaseOp(I))
1267 .addImm(Value);
1268 } else {
1269 // Paired instruction.
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1270 int Scale = getMemScale(I);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1271 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
1272 .addOperand(getLdStRegOp(Update))
1273 .addOperand(getLdStRegOp(I, 0))
1274 .addOperand(getLdStRegOp(I, 1))
1275 .addOperand(getLdStBaseOp(I))
1276 .addImm(Value / Scale);
1277 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1278 (void)MIB;
1279
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1280 if (IsPreIdx)
1281 DEBUG(dbgs() << "Creating pre-indexed load/store.");
1282 else
1283 DEBUG(dbgs() << "Creating post-indexed load/store.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1284 DEBUG(dbgs() << " Replacing instructions:\n ");
1285 DEBUG(I->print(dbgs()));
1286 DEBUG(dbgs() << " ");
1287 DEBUG(Update->print(dbgs()));
1288 DEBUG(dbgs() << " with instruction:\n ");
1289 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
1290 DEBUG(dbgs() << "\n");
1291
1292 // Erase the old instructions for the block.
1293 I->eraseFromParent();
1294 Update->eraseFromParent();
1295
1296 return NextI;
1297}
1298
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1299bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr *MemMI,
1300 MachineInstr *MI,
1301 unsigned BaseReg, int Offset) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1302 switch (MI->getOpcode()) {
1303 default:
1304 break;
1305 case AArch64::SUBXri:
1306 // Negate the offset for a SUB instruction.
1307 Offset *= -1;
1308 // FALLTHROUGH
1309 case AArch64::ADDXri:
1310 // Make sure it's a vanilla immediate operand, not a relocation or
1311 // anything else we can't handle.
1312 if (!MI->getOperand(2).isImm())
1313 break;
1314 // Watch out for 1 << 12 shifted value.
1315 if (AArch64_AM::getShiftValue(MI->getOperand(3).getImm()))
1316 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1317
1318 // The update instruction source and destination register must be the
1319 // same as the load/store base register.
1320 if (MI->getOperand(0).getReg() != BaseReg ||
1321 MI->getOperand(1).getReg() != BaseReg)
1322 break;
1323
1324 bool IsPairedInsn = isPairedLdSt(MemMI);
1325 int UpdateOffset = MI->getOperand(2).getImm();
1326 // For non-paired load/store instructions, the immediate must fit in a
1327 // signed 9-bit integer.
1328 if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
1329 break;
1330
1331 // For paired load/store instructions, the immediate must be a multiple of
1332 // the scaling factor. The scaled offset must also fit into a signed 7-bit
1333 // integer.
1334 if (IsPairedInsn) {
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1335 int Scale = getMemScale(MemMI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1336 if (UpdateOffset % Scale != 0)
1337 break;
1338
1339 int ScaledOffset = UpdateOffset / Scale;
1340 if (ScaledOffset > 64 || ScaledOffset < -64)
1341 break;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1342 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1343
1344 // If we have a non-zero Offset, we check that it matches the amount
1345 // we're adding to the register.
1346 if (!Offset || Offset == MI->getOperand(2).getImm())
1347 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1348 break;
1349 }
1350 return false;
1351}
1352
1353MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]1354 MachineBasicBlock::iterator I, int UnscaledOffset) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1355 MachineBasicBlock::iterator E = I->getParent()->end();
1356 MachineInstr *MemMI = I;
1357 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1358
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1359 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1360 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1361
Chad Rosierb7c5b912015-10-01 13:43:05 +0000[diff] [blame]1362 // Scan forward looking for post-index opportunities. Updating instructions
1363 // can't be formed if the memory instruction doesn't have the offset we're
1364 // looking for.
1365 if (MIUnscaledOffset != UnscaledOffset)
1366 return E;
1367
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1368 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1369 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1370 bool IsPairedInsn = isPairedLdSt(MemMI);
1371 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1372 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1373 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1374 return E;
1375 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1376
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1377 // Track which registers have been modified and used between the first insn
1378 // (inclusive) and the second insn.
1379 BitVector ModifiedRegs, UsedRegs;
1380 ModifiedRegs.resize(TRI->getNumRegs());
1381 UsedRegs.resize(TRI->getNumRegs());
1382 ++MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1383 for (; MBBI != E; ++MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1384 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1385 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1386 if (MI->isDebugValue())
1387 continue;
1388
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1389 // If we found a match, return it.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1390 if (isMatchingUpdateInsn(I, MI, BaseReg, UnscaledOffset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1391 return MBBI;
1392
1393 // Update the status of what the instruction clobbered and used.
1394 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1395
1396 // Otherwise, if the base register is used or modified, we have no match, so
1397 // return early.
1398 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1399 return E;
1400 }
1401 return E;
1402}
1403
1404MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]1405 MachineBasicBlock::iterator I) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1406 MachineBasicBlock::iterator B = I->getParent()->begin();
1407 MachineBasicBlock::iterator E = I->getParent()->end();
1408 MachineInstr *MemMI = I;
1409 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1410
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1411 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
1412 int Offset = getLdStOffsetOp(MemMI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1413
1414 // If the load/store is the first instruction in the block, there's obviously
1415 // not any matching update. Ditto if the memory offset isn't zero.
1416 if (MBBI == B || Offset != 0)
1417 return E;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1418 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1419 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1420 bool IsPairedInsn = isPairedLdSt(MemMI);
1421 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1422 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1423 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1424 return E;
1425 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1426
1427 // Track which registers have been modified and used between the first insn
1428 // (inclusive) and the second insn.
1429 BitVector ModifiedRegs, UsedRegs;
1430 ModifiedRegs.resize(TRI->getNumRegs());
1431 UsedRegs.resize(TRI->getNumRegs());
1432 --MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1433 for (; MBBI != B; --MBBI) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1434 MachineInstr *MI = MBBI;
Chad Rosierb11c82d2016-01-19 21:27:05 +0000[diff] [blame]1435 // Skip DBG_VALUE instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1436 if (MI->isDebugValue())
1437 continue;
1438
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1439 // If we found a match, return it.
Chad Rosier11c825f2015-09-30 19:44:40 +0000[diff] [blame]1440 if (isMatchingUpdateInsn(I, MI, BaseReg, Offset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1441 return MBBI;
1442
1443 // Update the status of what the instruction clobbered and used.
1444 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
1445
1446 // Otherwise, if the base register is used or modified, we have no match, so
1447 // return early.
1448 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1449 return E;
1450 }
1451 return E;
1452}
1453
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1454bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
1455 MachineBasicBlock::iterator &MBBI) {
1456 MachineInstr *MI = MBBI;
1457 // If this is a volatile load, don't mess with it.
1458 if (MI->hasOrderedMemoryRef())
1459 return false;
1460
1461 // Make sure this is a reg+imm.
1462 // FIXME: It is possible to extend it to handle reg+reg cases.
1463 if (!getLdStOffsetOp(MI).isImm())
1464 return false;
1465
1466 // Look backward up to ScanLimit instructions.
1467 MachineBasicBlock::iterator StoreI;
1468 if (findMatchingStore(MBBI, ScanLimit, StoreI)) {
1469 ++NumLoadsFromStoresPromoted;
1470 // Promote the load. Keeping the iterator straight is a
1471 // pain, so we let the merge routine tell us what the next instruction
1472 // is after it's done mucking about.
1473 MBBI = promoteLoadFromStore(MBBI, StoreI);
1474 return true;
1475 }
1476 return false;
1477}
1478
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1479bool AArch64LoadStoreOpt::tryToMergeLdStInst(
1480 MachineBasicBlock::iterator &MBBI) {
1481 MachineInstr *MI = MBBI;
1482 MachineBasicBlock::iterator E = MI->getParent()->end();
1483 // If this is a volatile load/store, don't mess with it.
1484 if (MI->hasOrderedMemoryRef())
1485 return false;
1486
1487 // Make sure this is a reg+imm (as opposed to an address reloc).
1488 if (!getLdStOffsetOp(MI).isImm())
1489 return false;
1490
1491 // Check if this load/store has a hint to avoid pair formation.
1492 // MachineMemOperands hints are set by the AArch64StorePairSuppress pass.
1493 if (TII->isLdStPairSuppressed(MI))
1494 return false;
1495
1496 // Look ahead up to ScanLimit instructions for a pairable instruction.
1497 LdStPairFlags Flags;
1498 MachineBasicBlock::iterator Paired = findMatchingInsn(MBBI, Flags, ScanLimit);
1499 if (Paired != E) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1500 if (isNarrowLoad(MI)) {
1501 ++NumNarrowLoadsPromoted;
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1502 } else if (isNarrowStore(MI)) {
1503 ++NumZeroStoresPromoted;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1504 } else {
1505 ++NumPairCreated;
1506 if (isUnscaledLdSt(MI))
1507 ++NumUnscaledPairCreated;
1508 }
1509
1510 // Merge the loads into a pair. Keeping the iterator straight is a
1511 // pain, so we let the merge routine tell us what the next instruction
1512 // is after it's done mucking about.
1513 MBBI = mergePairedInsns(MBBI, Paired, Flags);
1514 return true;
1515 }
1516 return false;
1517}
1518
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1519bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
1520 bool enableNarrowLdOpt) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1521 bool Modified = false;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1522 // Three tranformations to do here:
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1523 // 1) Find loads that directly read from stores and promote them by
1524 // replacing with mov instructions. If the store is wider than the load,
1525 // the load will be replaced with a bitfield extract.
1526 // e.g.,
1527 // str w1, [x0, #4]
1528 // ldrh w2, [x0, #6]
1529 // ; becomes
1530 // str w1, [x0, #4]
1531 // lsr w2, w1, #16
1532 // 2) Find narrow loads that can be converted into a single wider load
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1533 // with bitfield extract instructions.
1534 // e.g.,
1535 // ldrh w0, [x2]
1536 // ldrh w1, [x2, #2]
1537 // ; becomes
1538 // ldr w0, [x2]
1539 // ubfx w1, w0, #16, #16
1540 // and w0, w0, #ffff
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1541 // 3) Find loads and stores that can be merged into a single load or store
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1542 // pair instruction.
1543 // e.g.,
1544 // ldr x0, [x2]
1545 // ldr x1, [x2, #8]
1546 // ; becomes
1547 // ldp x0, x1, [x2]
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1548 // 4) Find base register updates that can be merged into the load or store
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1549 // as a base-reg writeback.
1550 // e.g.,
1551 // ldr x0, [x2]
1552 // add x2, x2, #4
1553 // ; becomes
1554 // ldr x0, [x2], #4
1555
1556 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1557 MBBI != E;) {
1558 MachineInstr *MI = MBBI;
1559 switch (MI->getOpcode()) {
1560 default:
1561 // Just move on to the next instruction.
1562 ++MBBI;
1563 break;
1564 // Scaled instructions.
1565 case AArch64::LDRBBui:
1566 case AArch64::LDRHHui:
1567 case AArch64::LDRWui:
1568 case AArch64::LDRXui:
1569 // Unscaled instructions.
1570 case AArch64::LDURBBi:
1571 case AArch64::LDURHHi:
1572 case AArch64::LDURWi:
1573 case AArch64::LDURXi: {
1574 if (tryToPromoteLoadFromStore(MBBI)) {
1575 Modified = true;
1576 break;
1577 }
1578 ++MBBI;
1579 break;
1580 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1581 }
1582 }
1583
1584 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1585 enableNarrowLdOpt && MBBI != E;) {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1586 MachineInstr *MI = MBBI;
1587 switch (MI->getOpcode()) {
1588 default:
1589 // Just move on to the next instruction.
1590 ++MBBI;
1591 break;
1592 // Scaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1593 case AArch64::LDRBBui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1594 case AArch64::LDRHHui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1595 case AArch64::LDRSBWui:
1596 case AArch64::LDRSHWui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1597 case AArch64::STRBBui:
1598 case AArch64::STRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1599 // Unscaled instructions.
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]1600 case AArch64::LDURBBi:
1601 case AArch64::LDURHHi:
1602 case AArch64::LDURSBWi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1603 case AArch64::LDURSHWi:
1604 case AArch64::STURBBi:
1605 case AArch64::STURHHi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1606 if (tryToMergeLdStInst(MBBI)) {
1607 Modified = true;
1608 break;
1609 }
1610 ++MBBI;
1611 break;
1612 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1613 }
1614 }
1615
1616 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1617 MBBI != E;) {
1618 MachineInstr *MI = MBBI;
1619 switch (MI->getOpcode()) {
1620 default:
1621 // Just move on to the next instruction.
1622 ++MBBI;
1623 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1624 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1625 case AArch64::STRSui:
1626 case AArch64::STRDui:
1627 case AArch64::STRQui:
1628 case AArch64::STRXui:
1629 case AArch64::STRWui:
1630 case AArch64::LDRSui:
1631 case AArch64::LDRDui:
1632 case AArch64::LDRQui:
1633 case AArch64::LDRXui:
1634 case AArch64::LDRWui:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1635 case AArch64::LDRSWui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1636 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1637 case AArch64::STURSi:
1638 case AArch64::STURDi:
1639 case AArch64::STURQi:
1640 case AArch64::STURWi:
1641 case AArch64::STURXi:
1642 case AArch64::LDURSi:
1643 case AArch64::LDURDi:
1644 case AArch64::LDURQi:
1645 case AArch64::LDURWi:
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]1646 case AArch64::LDURXi:
1647 case AArch64::LDURSWi: {
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1648 if (tryToMergeLdStInst(MBBI)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1649 Modified = true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1650 break;
1651 }
1652 ++MBBI;
1653 break;
1654 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1655 }
1656 }
1657
1658 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1659 MBBI != E;) {
1660 MachineInstr *MI = MBBI;
1661 // Do update merging. It's simpler to keep this separate from the above
1662 // switch, though not strictly necessary.
Matthias Braunfa3872e2015-05-18 20:27:55 +0000[diff] [blame]1663 unsigned Opc = MI->getOpcode();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1664 switch (Opc) {
1665 default:
1666 // Just move on to the next instruction.
1667 ++MBBI;
1668 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1669 // Scaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1670 case AArch64::STRSui:
1671 case AArch64::STRDui:
1672 case AArch64::STRQui:
1673 case AArch64::STRXui:
1674 case AArch64::STRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1675 case AArch64::STRHHui:
1676 case AArch64::STRBBui:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1677 case AArch64::LDRSui:
1678 case AArch64::LDRDui:
1679 case AArch64::LDRQui:
1680 case AArch64::LDRXui:
1681 case AArch64::LDRWui:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]1682 case AArch64::LDRHHui:
1683 case AArch64::LDRBBui:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1684 // Unscaled instructions.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1685 case AArch64::STURSi:
1686 case AArch64::STURDi:
1687 case AArch64::STURQi:
1688 case AArch64::STURWi:
1689 case AArch64::STURXi:
1690 case AArch64::LDURSi:
1691 case AArch64::LDURDi:
1692 case AArch64::LDURQi:
1693 case AArch64::LDURWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1694 case AArch64::LDURXi:
1695 // Paired instructions.
1696 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]1697 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1698 case AArch64::LDPDi:
1699 case AArch64::LDPQi:
1700 case AArch64::LDPWi:
1701 case AArch64::LDPXi:
1702 case AArch64::STPSi:
1703 case AArch64::STPDi:
1704 case AArch64::STPQi:
1705 case AArch64::STPWi:
1706 case AArch64::STPXi: {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1707 // Make sure this is a reg+imm (as opposed to an address reloc).
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1708 if (!getLdStOffsetOp(MI).isImm()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1709 ++MBBI;
1710 break;
1711 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1712 // Look forward to try to form a post-index instruction. For example,
1713 // ldr x0, [x20]
1714 // add x20, x20, #32
1715 // merged into:
1716 // ldr x0, [x20], #32
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1717 MachineBasicBlock::iterator Update =
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]1718 findMatchingUpdateInsnForward(MBBI, 0);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1719 if (Update != E) {
1720 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1721 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1722 Modified = true;
1723 ++NumPostFolded;
1724 break;
1725 }
1726 // Don't know how to handle pre/post-index versions, so move to the next
1727 // instruction.
Chad Rosier22eb7102015-08-06 17:37:18 +0000[diff] [blame]1728 if (isUnscaledLdSt(Opc)) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1729 ++MBBI;
1730 break;
1731 }
1732
1733 // Look back to try to find a pre-index instruction. For example,
1734 // add x0, x0, #8
1735 // ldr x1, [x0]
1736 // merged into:
1737 // ldr x1, [x0, #8]!
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]1738 Update = findMatchingUpdateInsnBackward(MBBI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1739 if (Update != E) {
1740 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1741 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1742 Modified = true;
1743 ++NumPreFolded;
1744 break;
1745 }
Chad Rosier7a83d772015-10-01 13:09:44 +0000[diff] [blame]1746 // The immediate in the load/store is scaled by the size of the memory
1747 // operation. The immediate in the add we're looking for,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1748 // however, is not, so adjust here.
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1749 int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1750
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1751 // Look forward to try to find a post-index instruction. For example,
1752 // ldr x1, [x0, #64]
1753 // add x0, x0, #64
1754 // merged into:
1755 // ldr x1, [x0, #64]!
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]1756 Update = findMatchingUpdateInsnForward(MBBI, UnscaledOffset);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1757 if (Update != E) {
1758 // Merge the update into the ld/st.
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1759 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1760 Modified = true;
1761 ++NumPreFolded;
1762 break;
1763 }
1764
1765 // Nothing found. Just move to the next instruction.
1766 ++MBBI;
1767 break;
1768 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1769 }
1770 }
1771
1772 return Modified;
1773}
1774
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1775bool AArch64LoadStoreOpt::enableNarrowLdMerge(MachineFunction &Fn) {
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1776 bool ProfitableArch = Subtarget->isCortexA57();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1777 // FIXME: The benefit from converting narrow loads into a wider load could be
1778 // microarchitectural as it assumes that a single load with two bitfield
1779 // extracts is cheaper than two narrow loads. Currently, this conversion is
1780 // enabled only in cortex-a57 on which performance benefits were verified.
Jun Bum Limc12c2792015-11-19 18:41:27 +0000[diff] [blame]1781 return ProfitableArch && !Subtarget->requiresStrictAlign();
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1782}
1783
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1784bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]1785 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1786 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1787 TRI = Subtarget->getRegisterInfo();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1788
1789 bool Modified = false;
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1790 bool enableNarrowLdOpt = enableNarrowLdMerge(Fn);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1791 for (auto &MBB : Fn)
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1792 Modified |= optimizeBlock(MBB, enableNarrowLdOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1793
1794 return Modified;
1795}
1796
1797// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep
1798// loads and stores near one another?
1799
Chad Rosier43f5c842015-08-05 12:40:13 +0000[diff] [blame]1800/// createAArch64LoadStoreOptimizationPass - returns an instance of the
1801/// load / store optimization pass.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1802FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1803 return new AArch64LoadStoreOpt();
1804}