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Valery Pykhtine330cfa2016-09-20 10:41:16 +00001//===-- VOP3Instructions.td - Vector Instruction Defintions ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
10//===----------------------------------------------------------------------===//
11// VOP3 Classes
12//===----------------------------------------------------------------------===//
13
14class getVOP3ModPat<VOPProfile P, SDPatternOperator node> {
15 list<dag> ret3 = [(set P.DstVT:$vdst,
16 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
17 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
18 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers))))];
19
20 list<dag> ret2 = [(set P.DstVT:$vdst,
21 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
22 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers))))];
23
24 list<dag> ret1 = [(set P.DstVT:$vdst,
25 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod))))];
26
27 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
28 !if(!eq(P.NumSrcArgs, 2), ret2,
29 ret1));
30}
31
32class getVOP3Pat<VOPProfile P, SDPatternOperator node> {
33 list<dag> ret3 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1, P.Src2VT:$src2))];
34 list<dag> ret2 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0, P.Src1VT:$src1))];
35 list<dag> ret1 = [(set P.DstVT:$vdst, (node P.Src0VT:$src0))];
36 list<dag> ret = !if(!eq(P.NumSrcArgs, 3), ret3,
37 !if(!eq(P.NumSrcArgs, 2), ret2,
38 ret1));
39}
40
41class VOP3Inst<string OpName, VOPProfile P, SDPatternOperator node = null_frag, bit VOP3Only = 0> :
Valery Pykhtin355103f2016-09-23 09:08:07 +000042 VOP3_Pseudo<OpName, P,
Valery Pykhtine330cfa2016-09-20 10:41:16 +000043 !if(P.HasModifiers, getVOP3ModPat<P, node>.ret, getVOP3Pat<P, node>.ret),
44 VOP3Only>;
45
46// Special case for v_div_fmas_{f32|f64}, since it seems to be the
47// only VOP instruction that implicitly reads VCC.
48let Asm64 = " $vdst, $src0_modifiers, $src1_modifiers, $src2_modifiers$clamp$omod" in {
49def VOP_F32_F32_F32_F32_VCC : VOPProfile<[f32, f32, f32, f32]> {
50 let Outs64 = (outs DstRC.RegClass:$vdst);
51}
52def VOP_F64_F64_F64_F64_VCC : VOPProfile<[f64, f64, f64, f64]> {
53 let Outs64 = (outs DstRC.RegClass:$vdst);
54}
55}
56
57class getVOP3VCC<VOPProfile P, SDPatternOperator node> {
58 list<dag> ret =
59 [(set P.DstVT:$vdst,
60 (node (P.Src0VT (VOP3Mods0 P.Src0VT:$src0, i32:$src0_modifiers, i1:$clamp, i32:$omod)),
61 (P.Src1VT (VOP3Mods P.Src1VT:$src1, i32:$src1_modifiers)),
62 (P.Src2VT (VOP3Mods P.Src2VT:$src2, i32:$src2_modifiers)),
63 (i1 VCC)))];
64}
65
66class VOP3_Profile<VOPProfile P> : VOPProfile<P.ArgVT> {
67 // FIXME: Hack to stop printing _e64
68 let Outs64 = (outs DstRC.RegClass:$vdst);
69 let Asm64 = " " # P.Asm64;
70}
71
72class VOP3b_Profile<ValueType vt> : VOPProfile<[vt, vt, vt, vt]> {
Matt Arsenault3b99f122017-01-19 06:04:12 +000073 // v_div_scale_{f32|f64} do not support input modifiers.
74 let HasModifiers = 0;
Valery Pykhtine330cfa2016-09-20 10:41:16 +000075 let Outs64 = (outs DstRC:$vdst, SReg_64:$sdst);
Matt Arsenault3b99f122017-01-19 06:04:12 +000076 let Asm64 = " $vdst, $sdst, $src0, $src1, $src2";
Valery Pykhtine330cfa2016-09-20 10:41:16 +000077}
78
79def VOP3b_F32_I1_F32_F32_F32 : VOP3b_Profile<f32> {
80 // FIXME: Hack to stop printing _e64
81 let DstRC = RegisterOperand<VGPR_32>;
82}
83
84def VOP3b_F64_I1_F64_F64_F64 : VOP3b_Profile<f64> {
85 // FIXME: Hack to stop printing _e64
86 let DstRC = RegisterOperand<VReg_64>;
87}
88
89//===----------------------------------------------------------------------===//
90// VOP3 Instructions
91//===----------------------------------------------------------------------===//
92
93let isCommutable = 1 in {
94
95def V_MAD_LEGACY_F32 : VOP3Inst <"v_mad_legacy_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
96def V_MAD_F32 : VOP3Inst <"v_mad_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fmad>;
97def V_MAD_I32_I24 : VOP3Inst <"v_mad_i32_i24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_i24>;
98def V_MAD_U32_U24 : VOP3Inst <"v_mad_u32_u24", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUmad_u24>;
99def V_FMA_F32 : VOP3Inst <"v_fma_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, fma>;
100def V_FMA_F64 : VOP3Inst <"v_fma_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, fma>;
101def V_LERP_U8 : VOP3Inst <"v_lerp_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_lerp>;
102
103let SchedRW = [WriteDoubleAdd] in {
104def V_ADD_F64 : VOP3Inst <"v_add_f64", VOP3_Profile<VOP_F64_F64_F64>, fadd, 1>;
105def V_MUL_F64 : VOP3Inst <"v_mul_f64", VOP3_Profile<VOP_F64_F64_F64>, fmul, 1>;
106def V_MIN_F64 : VOP3Inst <"v_min_f64", VOP3_Profile<VOP_F64_F64_F64>, fminnum, 1>;
107def V_MAX_F64 : VOP3Inst <"v_max_f64", VOP3_Profile<VOP_F64_F64_F64>, fmaxnum, 1>;
108} // End SchedRW = [WriteDoubleAdd]
109
110let SchedRW = [WriteQuarterRate32] in {
111def V_MUL_LO_U32 : VOP3Inst <"v_mul_lo_u32", VOP3_Profile<VOP_I32_I32_I32>>;
112def V_MUL_HI_U32 : VOP3Inst <"v_mul_hi_u32", VOP3_Profile<VOP_I32_I32_I32>, mulhu>;
113def V_MUL_LO_I32 : VOP3Inst <"v_mul_lo_i32", VOP3_Profile<VOP_I32_I32_I32>>;
114def V_MUL_HI_I32 : VOP3Inst <"v_mul_hi_i32", VOP3_Profile<VOP_I32_I32_I32>, mulhs>;
115} // End SchedRW = [WriteQuarterRate32]
116
117let Uses = [VCC, EXEC] in {
118// v_div_fmas_f32:
119// result = src0 * src1 + src2
120// if (vcc)
121// result *= 2^32
122//
Valery Pykhtin355103f2016-09-23 09:08:07 +0000123def V_DIV_FMAS_F32 : VOP3_Pseudo <"v_div_fmas_f32", VOP_F32_F32_F32_F32_VCC,
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000124 getVOP3VCC<VOP_F32_F32_F32_F32_VCC, AMDGPUdiv_fmas>.ret> {
125 let SchedRW = [WriteFloatFMA];
126}
127// v_div_fmas_f64:
128// result = src0 * src1 + src2
129// if (vcc)
130// result *= 2^64
131//
Valery Pykhtin355103f2016-09-23 09:08:07 +0000132def V_DIV_FMAS_F64 : VOP3_Pseudo <"v_div_fmas_f64", VOP_F64_F64_F64_F64_VCC,
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000133 getVOP3VCC<VOP_F64_F64_F64_F64_VCC, AMDGPUdiv_fmas>.ret> {
134 let SchedRW = [WriteDouble];
135}
136} // End Uses = [VCC, EXEC]
137
138} // End isCommutable = 1
139
140def V_CUBEID_F32 : VOP3Inst <"v_cubeid_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubeid>;
141def V_CUBESC_F32 : VOP3Inst <"v_cubesc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubesc>;
142def V_CUBETC_F32 : VOP3Inst <"v_cubetc_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubetc>;
143def V_CUBEMA_F32 : VOP3Inst <"v_cubema_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, int_amdgcn_cubema>;
144def V_BFE_U32 : VOP3Inst <"v_bfe_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_u32>;
145def V_BFE_I32 : VOP3Inst <"v_bfe_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfe_i32>;
146def V_BFI_B32 : VOP3Inst <"v_bfi_b32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUbfi>;
147def V_ALIGNBIT_B32 : VOP3Inst <"v_alignbit_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
148def V_ALIGNBYTE_B32 : VOP3Inst <"v_alignbyte_b32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
149def V_MIN3_F32 : VOP3Inst <"v_min3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmin3>;
150def V_MIN3_I32 : VOP3Inst <"v_min3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmin3>;
151def V_MIN3_U32 : VOP3Inst <"v_min3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumin3>;
152def V_MAX3_F32 : VOP3Inst <"v_max3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmax3>;
153def V_MAX3_I32 : VOP3Inst <"v_max3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmax3>;
154def V_MAX3_U32 : VOP3Inst <"v_max3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumax3>;
155def V_MED3_F32 : VOP3Inst <"v_med3_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUfmed3>;
156def V_MED3_I32 : VOP3Inst <"v_med3_i32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUsmed3>;
157def V_MED3_U32 : VOP3Inst <"v_med3_u32", VOP3_Profile<VOP_I32_I32_I32_I32>, AMDGPUumed3>;
158def V_SAD_U8 : VOP3Inst <"v_sad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u8>;
159def V_SAD_HI_U8 : VOP3Inst <"v_sad_hi_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_hi_u8>;
160def V_SAD_U16 : VOP3Inst <"v_sad_u16", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_sad_u16>;
161def V_SAD_U32 : VOP3Inst <"v_sad_u32", VOP3_Profile<VOP_I32_I32_I32_I32>>;
162def V_CVT_PK_U8_F32 : VOP3Inst<"v_cvt_pk_u8_f32", VOP3_Profile<VOP_I32_F32_I32_I32>, int_amdgcn_cvt_pk_u8_f32>;
163def V_DIV_FIXUP_F32 : VOP3Inst <"v_div_fixup_f32", VOP3_Profile<VOP_F32_F32_F32_F32>, AMDGPUdiv_fixup>;
164
165let SchedRW = [WriteDoubleAdd] in {
166def V_DIV_FIXUP_F64 : VOP3Inst <"v_div_fixup_f64", VOP3_Profile<VOP_F64_F64_F64_F64>, AMDGPUdiv_fixup>;
167def V_LDEXP_F64 : VOP3Inst <"v_ldexp_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUldexp, 1>;
168} // End SchedRW = [WriteDoubleAdd]
169
Valery Pykhtin355103f2016-09-23 09:08:07 +0000170def V_DIV_SCALE_F32 : VOP3_Pseudo <"v_div_scale_f32", VOP3b_F32_I1_F32_F32_F32, [], 1> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000171 let SchedRW = [WriteFloatFMA, WriteSALU];
Matt Arsenault81da1142016-11-15 00:05:42 +0000172 let hasExtraSrcRegAllocReq = 1;
Matt Arsenault3b99f122017-01-19 06:04:12 +0000173 let AsmMatchConverter = "";
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000174}
175
176// Double precision division pre-scale.
Valery Pykhtin355103f2016-09-23 09:08:07 +0000177def V_DIV_SCALE_F64 : VOP3_Pseudo <"v_div_scale_f64", VOP3b_F64_I1_F64_F64_F64, [], 1> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000178 let SchedRW = [WriteDouble, WriteSALU];
Matt Arsenault81da1142016-11-15 00:05:42 +0000179 let hasExtraSrcRegAllocReq = 1;
Matt Arsenault3b99f122017-01-19 06:04:12 +0000180 let AsmMatchConverter = "";
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000181}
182
183def V_MSAD_U8 : VOP3Inst <"v_msad_u8", VOP3_Profile<VOP_I32_I32_I32_I32>, int_amdgcn_msad_u8>;
184def V_MQSAD_PK_U16_U8 : VOP3Inst <"v_mqsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_mqsad_pk_u16_u8>;
185
186def V_TRIG_PREOP_F64 : VOP3Inst <"v_trig_preop_f64", VOP3_Profile<VOP_F64_F64_I32>, AMDGPUtrig_preop> {
187 let SchedRW = [WriteDouble];
188}
189
190// These instructions only exist on SI and CI
191let SubtargetPredicate = isSICI in {
192def V_LSHL_B64 : VOP3Inst <"v_lshl_b64", VOP3_Profile<VOP_I64_I64_I32>>;
193def V_LSHR_B64 : VOP3Inst <"v_lshr_b64", VOP3_Profile<VOP_I64_I64_I32>>;
194def V_ASHR_I64 : VOP3Inst <"v_ashr_i64", VOP3_Profile<VOP_I64_I64_I32>>;
195def V_MULLIT_F32 : VOP3Inst <"v_mullit_f32", VOP3_Profile<VOP_F32_F32_F32_F32>>;
196} // End SubtargetPredicate = isSICI
197
198let SubtargetPredicate = isVI in {
199def V_LSHLREV_B64 : VOP3Inst <"v_lshlrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
200def V_LSHRREV_B64 : VOP3Inst <"v_lshrrev_b64", VOP3_Profile<VOP_I64_I32_I64>>;
201def V_ASHRREV_I64 : VOP3Inst <"v_ashrrev_i64", VOP3_Profile<VOP_I64_I32_I64>>;
202} // End SubtargetPredicate = isVI
203
204
205let SubtargetPredicate = isCIVI in {
206
207def V_MQSAD_U16_U8 : VOP3Inst <"v_mqsad_u16_u8", VOP3_Profile<VOP_I32_I32_I32>>;
208def V_QSAD_PK_U16_U8 : VOP3Inst <"v_qsad_pk_u16_u8", VOP3_Profile<VOP_I64_I64_I32_I64>, int_amdgcn_qsad_pk_u16_u8>;
209def V_MQSAD_U32_U8 : VOP3Inst <"v_mqsad_u32_u8", VOP3_Profile<VOP_V4I32_I64_I32_V4I32>, int_amdgcn_mqsad_u32_u8>;
210
211let isCommutable = 1 in {
212def V_MAD_U64_U32 : VOP3Inst <"v_mad_u64_u32", VOP3_Profile<VOP_I64_I32_I32_I64>>;
213
214// XXX - Does this set VCC?
215def V_MAD_I64_I32 : VOP3Inst <"v_mad_i64_i32", VOP3_Profile<VOP_I64_I32_I32_I64>>;
216} // End isCommutable = 1
217
218} // End SubtargetPredicate = isCIVI
219
220
221let SubtargetPredicate = isVI in {
222
223let isCommutable = 1 in {
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000224
225def V_DIV_FIXUP_F16 : VOP3Inst <"v_div_fixup_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, AMDGPUdiv_fixup>;
226def V_FMA_F16 : VOP3Inst <"v_fma_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fma>;
227def V_INTERP_P1LL_F16 : VOP3Inst <"v_interp_p1ll_f16", VOP3_Profile<VOP_F32_F32_F16>>;
228def V_INTERP_P1LV_F16 : VOP3Inst <"v_interp_p1lv_f16", VOP3_Profile<VOP_F32_F32_F16_F16>>;
229def V_INTERP_P2_F16 : VOP3Inst <"v_interp_p2_f16", VOP3_Profile<VOP_F16_F32_F16_F32>>;
230def V_MAD_F16 : VOP3Inst <"v_mad_f16", VOP3_Profile<VOP_F16_F16_F16_F16>, fmad>;
231
232def V_MAD_U16 : VOP3Inst <"v_mad_u16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
233def V_MAD_I16 : VOP3Inst <"v_mad_i16", VOP3_Profile<VOP_I16_I16_I16_I16>>;
234
235} // End isCommutable = 1
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000236
237} // End SubtargetPredicate = isVI
238
Tom Stellard115a6152016-11-10 16:02:37 +0000239let Predicates = [isVI] in {
240
241multiclass Tenary_i16_Pats <SDPatternOperator op1, SDPatternOperator op2,
242 Instruction inst, SDPatternOperator op3> {
243def : Pat<
244 (op2 (op1 i16:$src0, i16:$src1), i16:$src2),
245 (inst i16:$src0, i16:$src1, i16:$src2)
246>;
247
248def : Pat<
249 (i32 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
250 (inst i16:$src0, i16:$src1, i16:$src2)
251>;
252
253def : Pat<
254 (i64 (op3 (op2 (op1 i16:$src0, i16:$src1), i16:$src2))),
255 (REG_SEQUENCE VReg_64,
256 (inst i16:$src0, i16:$src1, i16:$src2), sub0,
257 (V_MOV_B32_e32 (i32 0)), sub1)
258>;
259}
260
261defm: Tenary_i16_Pats<mul, add, V_MAD_U16, zext>;
262defm: Tenary_i16_Pats<mul, add, V_MAD_I16, sext>;
263
264} // End Predicates = [isVI]
265
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000266
267//===----------------------------------------------------------------------===//
268// Target
269//===----------------------------------------------------------------------===//
270
271//===----------------------------------------------------------------------===//
272// SI
273//===----------------------------------------------------------------------===//
274
275let AssemblerPredicates = [isSICI], DecoderNamespace = "SICI" in {
276
277multiclass VOP3_Real_si<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000278 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
279 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000280}
281
282multiclass VOP3be_Real_si<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000283 def _si : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
284 VOP3be_si <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000285}
286
287} // End AssemblerPredicates = [isSICI], DecoderNamespace = "SICI"
288
289defm V_MAD_LEGACY_F32 : VOP3_Real_si <0x140>;
290defm V_MAD_F32 : VOP3_Real_si <0x141>;
291defm V_MAD_I32_I24 : VOP3_Real_si <0x142>;
292defm V_MAD_U32_U24 : VOP3_Real_si <0x143>;
293defm V_CUBEID_F32 : VOP3_Real_si <0x144>;
294defm V_CUBESC_F32 : VOP3_Real_si <0x145>;
295defm V_CUBETC_F32 : VOP3_Real_si <0x146>;
296defm V_CUBEMA_F32 : VOP3_Real_si <0x147>;
297defm V_BFE_U32 : VOP3_Real_si <0x148>;
298defm V_BFE_I32 : VOP3_Real_si <0x149>;
299defm V_BFI_B32 : VOP3_Real_si <0x14a>;
300defm V_FMA_F32 : VOP3_Real_si <0x14b>;
301defm V_FMA_F64 : VOP3_Real_si <0x14c>;
302defm V_LERP_U8 : VOP3_Real_si <0x14d>;
303defm V_ALIGNBIT_B32 : VOP3_Real_si <0x14e>;
304defm V_ALIGNBYTE_B32 : VOP3_Real_si <0x14f>;
305defm V_MULLIT_F32 : VOP3_Real_si <0x150>;
306defm V_MIN3_F32 : VOP3_Real_si <0x151>;
307defm V_MIN3_I32 : VOP3_Real_si <0x152>;
308defm V_MIN3_U32 : VOP3_Real_si <0x153>;
309defm V_MAX3_F32 : VOP3_Real_si <0x154>;
310defm V_MAX3_I32 : VOP3_Real_si <0x155>;
311defm V_MAX3_U32 : VOP3_Real_si <0x156>;
312defm V_MED3_F32 : VOP3_Real_si <0x157>;
313defm V_MED3_I32 : VOP3_Real_si <0x158>;
314defm V_MED3_U32 : VOP3_Real_si <0x159>;
315defm V_SAD_U8 : VOP3_Real_si <0x15a>;
316defm V_SAD_HI_U8 : VOP3_Real_si <0x15b>;
317defm V_SAD_U16 : VOP3_Real_si <0x15c>;
318defm V_SAD_U32 : VOP3_Real_si <0x15d>;
319defm V_CVT_PK_U8_F32 : VOP3_Real_si <0x15e>;
320defm V_DIV_FIXUP_F32 : VOP3_Real_si <0x15f>;
321defm V_DIV_FIXUP_F64 : VOP3_Real_si <0x160>;
322defm V_LSHL_B64 : VOP3_Real_si <0x161>;
323defm V_LSHR_B64 : VOP3_Real_si <0x162>;
324defm V_ASHR_I64 : VOP3_Real_si <0x163>;
325defm V_ADD_F64 : VOP3_Real_si <0x164>;
326defm V_MUL_F64 : VOP3_Real_si <0x165>;
327defm V_MIN_F64 : VOP3_Real_si <0x166>;
328defm V_MAX_F64 : VOP3_Real_si <0x167>;
329defm V_LDEXP_F64 : VOP3_Real_si <0x168>;
330defm V_MUL_LO_U32 : VOP3_Real_si <0x169>;
331defm V_MUL_HI_U32 : VOP3_Real_si <0x16a>;
332defm V_MUL_LO_I32 : VOP3_Real_si <0x16b>;
333defm V_MUL_HI_I32 : VOP3_Real_si <0x16c>;
334defm V_DIV_SCALE_F32 : VOP3be_Real_si <0x16d>;
335defm V_DIV_SCALE_F64 : VOP3be_Real_si <0x16e>;
336defm V_DIV_FMAS_F32 : VOP3_Real_si <0x16f>;
337defm V_DIV_FMAS_F64 : VOP3_Real_si <0x170>;
338defm V_MSAD_U8 : VOP3_Real_si <0x171>;
339defm V_MQSAD_PK_U16_U8 : VOP3_Real_si <0x173>;
340defm V_TRIG_PREOP_F64 : VOP3_Real_si <0x174>;
341
342//===----------------------------------------------------------------------===//
343// CI
344//===----------------------------------------------------------------------===//
345
346multiclass VOP3_Real_ci<bits<9> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000347 def _ci : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.SI>,
348 VOP3e_si <op, !cast<VOP3_Pseudo>(NAME).Pfl> {
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000349 let AssemblerPredicates = [isCIOnly];
350 let DecoderNamespace = "CI";
351 }
352}
353
354defm V_MQSAD_U16_U8 : VOP3_Real_ci <0x172>;
355defm V_QSAD_PK_U16_U8 : VOP3_Real_ci <0x172>;
356defm V_MQSAD_U32_U8 : VOP3_Real_ci <0x174>;
357defm V_MAD_U64_U32 : VOP3_Real_ci <0x176>;
358defm V_MAD_I64_I32 : VOP3_Real_ci <0x177>;
359
360//===----------------------------------------------------------------------===//
361// VI
362//===----------------------------------------------------------------------===//
363
364let AssemblerPredicates = [isVI], DecoderNamespace = "VI" in {
365
366multiclass VOP3_Real_vi<bits<10> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000367 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
368 VOP3e_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000369}
370
371multiclass VOP3be_Real_vi<bits<10> op> {
Valery Pykhtin355103f2016-09-23 09:08:07 +0000372 def _vi : VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
373 VOP3be_vi <op, !cast<VOP3_Pseudo>(NAME).Pfl>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000374}
375
376} // End AssemblerPredicates = [isVI], DecoderNamespace = "VI"
377
378defm V_MQSAD_U16_U8 : VOP3_Real_vi <0x172>;
379defm V_MAD_U64_U32 : VOP3_Real_vi <0x176>;
380defm V_MAD_I64_I32 : VOP3_Real_vi <0x177>;
381
382defm V_MAD_LEGACY_F32 : VOP3_Real_vi <0x1c0>;
383defm V_MAD_F32 : VOP3_Real_vi <0x1c1>;
384defm V_MAD_I32_I24 : VOP3_Real_vi <0x1c2>;
385defm V_MAD_U32_U24 : VOP3_Real_vi <0x1c3>;
386defm V_CUBEID_F32 : VOP3_Real_vi <0x1c4>;
387defm V_CUBESC_F32 : VOP3_Real_vi <0x1c5>;
388defm V_CUBETC_F32 : VOP3_Real_vi <0x1c6>;
389defm V_CUBEMA_F32 : VOP3_Real_vi <0x1c7>;
390defm V_BFE_U32 : VOP3_Real_vi <0x1c8>;
391defm V_BFE_I32 : VOP3_Real_vi <0x1c9>;
392defm V_BFI_B32 : VOP3_Real_vi <0x1ca>;
393defm V_FMA_F32 : VOP3_Real_vi <0x1cb>;
394defm V_FMA_F64 : VOP3_Real_vi <0x1cc>;
395defm V_LERP_U8 : VOP3_Real_vi <0x1cd>;
396defm V_ALIGNBIT_B32 : VOP3_Real_vi <0x1ce>;
397defm V_ALIGNBYTE_B32 : VOP3_Real_vi <0x1cf>;
398defm V_MIN3_F32 : VOP3_Real_vi <0x1d0>;
399defm V_MIN3_I32 : VOP3_Real_vi <0x1d1>;
400defm V_MIN3_U32 : VOP3_Real_vi <0x1d2>;
401defm V_MAX3_F32 : VOP3_Real_vi <0x1d3>;
402defm V_MAX3_I32 : VOP3_Real_vi <0x1d4>;
403defm V_MAX3_U32 : VOP3_Real_vi <0x1d5>;
404defm V_MED3_F32 : VOP3_Real_vi <0x1d6>;
405defm V_MED3_I32 : VOP3_Real_vi <0x1d7>;
406defm V_MED3_U32 : VOP3_Real_vi <0x1d8>;
407defm V_SAD_U8 : VOP3_Real_vi <0x1d9>;
408defm V_SAD_HI_U8 : VOP3_Real_vi <0x1da>;
409defm V_SAD_U16 : VOP3_Real_vi <0x1db>;
410defm V_SAD_U32 : VOP3_Real_vi <0x1dc>;
411defm V_CVT_PK_U8_F32 : VOP3_Real_vi <0x1dd>;
412defm V_DIV_FIXUP_F32 : VOP3_Real_vi <0x1de>;
413defm V_DIV_FIXUP_F64 : VOP3_Real_vi <0x1df>;
414defm V_DIV_SCALE_F32 : VOP3be_Real_vi <0x1e0>;
415defm V_DIV_SCALE_F64 : VOP3be_Real_vi <0x1e1>;
416defm V_DIV_FMAS_F32 : VOP3_Real_vi <0x1e2>;
417defm V_DIV_FMAS_F64 : VOP3_Real_vi <0x1e3>;
418defm V_MSAD_U8 : VOP3_Real_vi <0x1e4>;
419defm V_QSAD_PK_U16_U8 : VOP3_Real_vi <0x1e5>;
420defm V_MQSAD_PK_U16_U8 : VOP3_Real_vi <0x1e6>;
421defm V_MQSAD_U32_U8 : VOP3_Real_vi <0x1e7>;
422
423defm V_MAD_F16 : VOP3_Real_vi <0x1ea>;
424defm V_MAD_U16 : VOP3_Real_vi <0x1eb>;
425defm V_MAD_I16 : VOP3_Real_vi <0x1ec>;
426
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000427defm V_FMA_F16 : VOP3_Real_vi <0x1ee>;
428defm V_DIV_FIXUP_F16 : VOP3_Real_vi <0x1ef>;
429
430defm V_INTERP_P1LL_F16 : VOP3_Real_vi <0x274>;
431defm V_INTERP_P1LV_F16 : VOP3_Real_vi <0x275>;
432defm V_INTERP_P2_F16 : VOP3_Real_vi <0x276>;
Valery Pykhtine330cfa2016-09-20 10:41:16 +0000433defm V_ADD_F64 : VOP3_Real_vi <0x280>;
434defm V_MUL_F64 : VOP3_Real_vi <0x281>;
435defm V_MIN_F64 : VOP3_Real_vi <0x282>;
436defm V_MAX_F64 : VOP3_Real_vi <0x283>;
437defm V_LDEXP_F64 : VOP3_Real_vi <0x284>;
438defm V_MUL_LO_U32 : VOP3_Real_vi <0x285>;
439
440// removed from VI as identical to V_MUL_LO_U32
441let isAsmParserOnly = 1 in {
442defm V_MUL_LO_I32 : VOP3_Real_vi <0x285>;
443}
444
445defm V_MUL_HI_U32 : VOP3_Real_vi <0x286>;
446defm V_MUL_HI_I32 : VOP3_Real_vi <0x287>;
447
448defm V_LSHLREV_B64 : VOP3_Real_vi <0x28f>;
449defm V_LSHRREV_B64 : VOP3_Real_vi <0x290>;
450defm V_ASHRREV_I64 : VOP3_Real_vi <0x291>;
451defm V_TRIG_PREOP_F64 : VOP3_Real_vi <0x292>;