| Matt Arsenault | e57206d | 2016-05-25 18:07:36 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s | 
| Marek Olsak | 7517077 | 2015-01-27 17:27:15 +0000 | [diff] [blame] | 2 | ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s | 
| Tom Stellard | 20ee94f | 2013-08-14 22:22:09 +0000 | [diff] [blame] | 3 |  | 
|  | 4 | ; This test just checks that the compiler doesn't crash. | 
| Matt Arsenault | 2acc7a4 | 2014-06-11 19:31:13 +0000 | [diff] [blame] | 5 |  | 
| Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 6 | ; FUNC-LABEL: {{^}}v32i8_to_v8i32: | 
| Matt Arsenault | 3ea0633 | 2017-02-22 00:02:21 +0000 | [diff] [blame] | 7 | define amdgpu_ps float @v32i8_to_v8i32(<32 x i8> addrspace(2)* inreg) #0 { | 
| Tom Stellard | 20ee94f | 2013-08-14 22:22:09 +0000 | [diff] [blame] | 8 | entry: | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 9 | %1 = load <32 x i8>, <32 x i8> addrspace(2)* %0 | 
| Tom Stellard | 20ee94f | 2013-08-14 22:22:09 +0000 | [diff] [blame] | 10 | %2 = bitcast <32 x i8> %1 to <8 x i32> | 
|  | 11 | %3 = extractelement <8 x i32> %2, i32 1 | 
|  | 12 | %4 = icmp ne i32 %3, 0 | 
|  | 13 | %5 = select i1 %4, float 0.0, float 1.0 | 
| Matt Arsenault | 3ea0633 | 2017-02-22 00:02:21 +0000 | [diff] [blame] | 14 | ret float %5 | 
| Tom Stellard | 20ee94f | 2013-08-14 22:22:09 +0000 | [diff] [blame] | 15 | } | 
|  | 16 |  | 
| Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 17 | ; FUNC-LABEL: {{^}}i8ptr_v16i8ptr: | 
| Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 18 | ; SI: s_endpgm | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 19 | define amdgpu_kernel void @i8ptr_v16i8ptr(<16 x i8> addrspace(1)* %out, i8 addrspace(1)* %in) { | 
| Tom Stellard | 6c7a7e8 | 2014-02-13 23:34:12 +0000 | [diff] [blame] | 20 | entry: | 
|  | 21 | %0 = bitcast i8 addrspace(1)* %in to <16 x i8> addrspace(1)* | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 22 | %1 = load <16 x i8>, <16 x i8> addrspace(1)* %0 | 
| Tom Stellard | 6c7a7e8 | 2014-02-13 23:34:12 +0000 | [diff] [blame] | 23 | store <16 x i8> %1, <16 x i8> addrspace(1)* %out | 
|  | 24 | ret void | 
|  | 25 | } | 
| Matt Arsenault | 064c206 | 2014-06-11 17:40:32 +0000 | [diff] [blame] | 26 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 27 | define amdgpu_kernel void @f32_to_v2i16(<2 x i16> addrspace(1)* %out, float addrspace(1)* %in) nounwind { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 28 | %load = load float, float addrspace(1)* %in, align 4 | 
| Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 29 | %fadd32 = fadd float %load, 1.0 | 
|  | 30 | %bc = bitcast float %fadd32 to <2 x i16> | 
|  | 31 | %add.bitcast = add <2 x i16> %bc, <i16 2, i16 2> | 
|  | 32 | store <2 x i16> %add.bitcast, <2 x i16> addrspace(1)* %out | 
| Matt Arsenault | 064c206 | 2014-06-11 17:40:32 +0000 | [diff] [blame] | 33 | ret void | 
|  | 34 | } | 
|  | 35 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 36 | define amdgpu_kernel void @v2i16_to_f32(float addrspace(1)* %out, <2 x i16> addrspace(1)* %in) nounwind { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 37 | %load = load <2 x i16>, <2 x i16> addrspace(1)* %in, align 4 | 
| Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 38 | %add.v2i16 = add <2 x i16> %load, <i16 2, i16 2> | 
|  | 39 | %bc = bitcast <2 x i16> %add.v2i16 to float | 
|  | 40 | %fadd.bitcast = fadd float %bc, 1.0 | 
|  | 41 | store float %fadd.bitcast, float addrspace(1)* %out | 
|  | 42 | ret void | 
|  | 43 | } | 
|  | 44 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 45 | define amdgpu_kernel void @f32_to_v2f16(<2 x half> addrspace(1)* %out, float addrspace(1)* %in) nounwind { | 
| Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 46 | %load = load float, float addrspace(1)* %in, align 4 | 
|  | 47 | %fadd32 = fadd float %load, 1.0 | 
|  | 48 | %bc = bitcast float %fadd32 to <2 x half> | 
|  | 49 | %add.bitcast = fadd <2 x half> %bc, <half 2.0, half 2.0> | 
|  | 50 | store <2 x half> %add.bitcast, <2 x half> addrspace(1)* %out | 
|  | 51 | ret void | 
|  | 52 | } | 
|  | 53 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 54 | define amdgpu_kernel void @v2f16_to_f32(float addrspace(1)* %out, <2 x half> addrspace(1)* %in) nounwind { | 
| Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 55 | %load = load <2 x half>, <2 x half> addrspace(1)* %in, align 4 | 
|  | 56 | %add.v2f16 = fadd <2 x half> %load, <half 2.0, half 2.0> | 
|  | 57 | %bc = bitcast <2 x half> %add.v2f16 to float | 
|  | 58 | %fadd.bitcast = fadd float %bc, 1.0 | 
|  | 59 | store float %fadd.bitcast, float addrspace(1)* %out | 
| Matt Arsenault | 064c206 | 2014-06-11 17:40:32 +0000 | [diff] [blame] | 60 | ret void | 
|  | 61 | } | 
| Matt Arsenault | 364a674 | 2014-06-11 17:50:44 +0000 | [diff] [blame] | 62 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 63 | define amdgpu_kernel void @v4i8_to_i32(i32 addrspace(1)* %out, <4 x i8> addrspace(1)* %in) nounwind { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 64 | %load = load <4 x i8>, <4 x i8> addrspace(1)* %in, align 4 | 
| Matt Arsenault | 364a674 | 2014-06-11 17:50:44 +0000 | [diff] [blame] | 65 | %bc = bitcast <4 x i8> %load to i32 | 
|  | 66 | store i32 %bc, i32 addrspace(1)* %out, align 4 | 
|  | 67 | ret void | 
|  | 68 | } | 
|  | 69 |  | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 70 | define amdgpu_kernel void @i32_to_v4i8(<4 x i8> addrspace(1)* %out, i32 addrspace(1)* %in) nounwind { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 71 | %load = load i32, i32 addrspace(1)* %in, align 4 | 
| Matt Arsenault | 364a674 | 2014-06-11 17:50:44 +0000 | [diff] [blame] | 72 | %bc = bitcast i32 %load to <4 x i8> | 
|  | 73 | store <4 x i8> %bc, <4 x i8> addrspace(1)* %out, align 4 | 
|  | 74 | ret void | 
|  | 75 | } | 
| Matt Arsenault | 2acc7a4 | 2014-06-11 19:31:13 +0000 | [diff] [blame] | 76 |  | 
| Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 77 | ; FUNC-LABEL: {{^}}bitcast_v2i32_to_f64: | 
| Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 78 | ; SI: s_endpgm | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 79 | define amdgpu_kernel void @bitcast_v2i32_to_f64(double addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 80 | %val = load <2 x i32>, <2 x i32> addrspace(1)* %in, align 8 | 
| Matt Arsenault | 2acc7a4 | 2014-06-11 19:31:13 +0000 | [diff] [blame] | 81 | %add = add <2 x i32> %val, <i32 4, i32 9> | 
|  | 82 | %bc = bitcast <2 x i32> %add to double | 
| Matt Arsenault | eb522e6 | 2017-02-27 22:15:25 +0000 | [diff] [blame] | 83 | %fadd.bc = fadd double %bc, 1.0 | 
|  | 84 | store double %fadd.bc, double addrspace(1)* %out, align 8 | 
| Matt Arsenault | 2acc7a4 | 2014-06-11 19:31:13 +0000 | [diff] [blame] | 85 | ret void | 
|  | 86 | } | 
|  | 87 |  | 
| Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 88 | ; FUNC-LABEL: {{^}}bitcast_f64_to_v2i32: | 
| Tom Stellard | 326d6ec | 2014-11-05 14:50:53 +0000 | [diff] [blame] | 89 | ; SI: s_endpgm | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 90 | define amdgpu_kernel void @bitcast_f64_to_v2i32(<2 x i32> addrspace(1)* %out, double addrspace(1)* %in) { | 
| David Blaikie | a79ac14 | 2015-02-27 21:17:42 +0000 | [diff] [blame] | 91 | %val = load double, double addrspace(1)* %in, align 8 | 
| Matt Arsenault | 2acc7a4 | 2014-06-11 19:31:13 +0000 | [diff] [blame] | 92 | %add = fadd double %val, 4.0 | 
|  | 93 | %bc = bitcast double %add to <2 x i32> | 
|  | 94 | store <2 x i32> %bc, <2 x i32> addrspace(1)* %out, align 8 | 
|  | 95 | ret void | 
|  | 96 | } | 
| Matt Arsenault | e57206d | 2016-05-25 18:07:36 +0000 | [diff] [blame] | 97 |  | 
|  | 98 | ; FUNC-LABEL: {{^}}bitcast_v2i64_to_v2f64: | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 99 | define amdgpu_kernel void @bitcast_v2i64_to_v2f64(i32 %cond, <2 x double> addrspace(1)* %out, <2 x i64> %value) { | 
| Matt Arsenault | e57206d | 2016-05-25 18:07:36 +0000 | [diff] [blame] | 100 | entry: | 
|  | 101 | %cmp0 = icmp eq i32 %cond, 0 | 
|  | 102 | br i1 %cmp0, label %if, label %end | 
|  | 103 |  | 
|  | 104 | if: | 
|  | 105 | %cast = bitcast <2 x i64> %value to <2 x double> | 
|  | 106 | br label %end | 
|  | 107 |  | 
|  | 108 | end: | 
|  | 109 | %phi = phi <2 x double> [zeroinitializer, %entry], [%cast, %if] | 
|  | 110 | store <2 x double> %phi, <2 x double> addrspace(1)* %out | 
|  | 111 | ret void | 
|  | 112 | } | 
|  | 113 |  | 
|  | 114 | ; FUNC-LABEL: {{^}}bitcast_v2f64_to_v2i64: | 
| Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame^] | 115 | define amdgpu_kernel void @bitcast_v2f64_to_v2i64(i32 %cond, <2 x i64> addrspace(1)* %out, <2 x double> %value) { | 
| Matt Arsenault | e57206d | 2016-05-25 18:07:36 +0000 | [diff] [blame] | 116 | entry: | 
|  | 117 | %cmp0 = icmp eq i32 %cond, 0 | 
|  | 118 | br i1 %cmp0, label %if, label %end | 
|  | 119 |  | 
|  | 120 | if: | 
|  | 121 | %cast = bitcast <2 x double> %value to <2 x i64> | 
|  | 122 | br label %end | 
|  | 123 |  | 
|  | 124 | end: | 
|  | 125 | %phi = phi <2 x i64> [zeroinitializer, %entry], [%cast, %if] | 
|  | 126 | store <2 x i64> %phi, <2 x i64> addrspace(1)* %out | 
|  | 127 | ret void | 
|  | 128 | } |