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Jim Grosbacheb431da2010-01-06 16:48:02 +00001//===----- AggressiveAntiDepBreaker.cpp - Anti-dep breaker ----------------===//
David Goodwinde11f362009-10-26 19:32:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file implements the AggressiveAntiDepBreaker class, which
11// implements register anti-dependence breaking during post-RA
12// scheduling. It attempts to break all anti-dependencies within a
13// block.
14//
15//===----------------------------------------------------------------------===//
16
David Goodwinde11f362009-10-26 19:32:42 +000017#include "AggressiveAntiDepBreaker.h"
18#include "llvm/CodeGen/MachineBasicBlock.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineInstr.h"
Andrew Trick05ff4662012-06-06 20:29:31 +000021#include "llvm/CodeGen/RegisterClassInfo.h"
David Goodwine056d102009-10-26 22:31:16 +000022#include "llvm/Support/CommandLine.h"
David Goodwinde11f362009-10-26 19:32:42 +000023#include "llvm/Support/Debug.h"
24#include "llvm/Support/ErrorHandling.h"
25#include "llvm/Support/raw_ostream.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000026#include "llvm/Target/TargetInstrInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000027#include "llvm/Target/TargetMachine.h"
28#include "llvm/Target/TargetRegisterInfo.h"
David Goodwinde11f362009-10-26 19:32:42 +000029using namespace llvm;
30
Chandler Carruth1b9dde02014-04-22 02:02:50 +000031#define DEBUG_TYPE "post-RA-sched"
32
David Goodwindd1c6192009-11-19 23:12:37 +000033// If DebugDiv > 0 then only break antidep with (ID % DebugDiv) == DebugMod
34static cl::opt<int>
35DebugDiv("agg-antidep-debugdiv",
Bob Wilson67dd3a42010-04-09 21:38:26 +000036 cl::desc("Debug control for aggressive anti-dep breaker"),
37 cl::init(0), cl::Hidden);
David Goodwindd1c6192009-11-19 23:12:37 +000038static cl::opt<int>
39DebugMod("agg-antidep-debugmod",
Bob Wilson67dd3a42010-04-09 21:38:26 +000040 cl::desc("Debug control for aggressive anti-dep breaker"),
41 cl::init(0), cl::Hidden);
David Goodwindd1c6192009-11-19 23:12:37 +000042
David Goodwina45fe672009-12-09 17:18:22 +000043AggressiveAntiDepState::AggressiveAntiDepState(const unsigned TargetRegs,
44 MachineBasicBlock *BB) :
Bill Wendling51a9c0a2010-07-15 19:58:14 +000045 NumTargetRegs(TargetRegs), GroupNodes(TargetRegs, 0),
46 GroupNodeIndices(TargetRegs, 0),
47 KillIndices(TargetRegs, 0),
48 DefIndices(TargetRegs, 0)
49{
David Goodwina45fe672009-12-09 17:18:22 +000050 const unsigned BBSize = BB->size();
51 for (unsigned i = 0; i < NumTargetRegs; ++i) {
52 // Initialize all registers to be in their own group. Initially we
53 // assign the register to the same-indexed GroupNode.
54 GroupNodeIndices[i] = i;
55 // Initialize the indices to indicate that no registers are live.
56 KillIndices[i] = ~0u;
57 DefIndices[i] = BBSize;
58 }
David Goodwinde11f362009-10-26 19:32:42 +000059}
60
Bill Wendling5a8d15c2010-07-15 19:41:20 +000061unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) {
David Goodwinde11f362009-10-26 19:32:42 +000062 unsigned Node = GroupNodeIndices[Reg];
63 while (GroupNodes[Node] != Node)
64 Node = GroupNodes[Node];
65
66 return Node;
67}
68
David Goodwinb9fe5d52009-11-13 19:52:48 +000069void AggressiveAntiDepState::GetGroupRegs(
70 unsigned Group,
71 std::vector<unsigned> &Regs,
72 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference> *RegRefs)
David Goodwinde11f362009-10-26 19:32:42 +000073{
David Goodwina45fe672009-12-09 17:18:22 +000074 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) {
David Goodwinb9fe5d52009-11-13 19:52:48 +000075 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0))
David Goodwinde11f362009-10-26 19:32:42 +000076 Regs.push_back(Reg);
77 }
78}
79
David Goodwine056d102009-10-26 22:31:16 +000080unsigned AggressiveAntiDepState::UnionGroups(unsigned Reg1, unsigned Reg2)
David Goodwinde11f362009-10-26 19:32:42 +000081{
82 assert(GroupNodes[0] == 0 && "GroupNode 0 not parent!");
83 assert(GroupNodeIndices[0] == 0 && "Reg 0 not in Group 0!");
Jim Grosbacheb431da2010-01-06 16:48:02 +000084
David Goodwinde11f362009-10-26 19:32:42 +000085 // find group for each register
86 unsigned Group1 = GetGroup(Reg1);
87 unsigned Group2 = GetGroup(Reg2);
Jim Grosbacheb431da2010-01-06 16:48:02 +000088
David Goodwinde11f362009-10-26 19:32:42 +000089 // if either group is 0, then that must become the parent
90 unsigned Parent = (Group1 == 0) ? Group1 : Group2;
91 unsigned Other = (Parent == Group1) ? Group2 : Group1;
92 GroupNodes.at(Other) = Parent;
93 return Parent;
94}
Jim Grosbacheb431da2010-01-06 16:48:02 +000095
David Goodwine056d102009-10-26 22:31:16 +000096unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg)
David Goodwinde11f362009-10-26 19:32:42 +000097{
98 // Create a new GroupNode for Reg. Reg's existing GroupNode must
99 // stay as is because there could be other GroupNodes referring to
100 // it.
101 unsigned idx = GroupNodes.size();
102 GroupNodes.push_back(idx);
103 GroupNodeIndices[Reg] = idx;
104 return idx;
105}
106
David Goodwine056d102009-10-26 22:31:16 +0000107bool AggressiveAntiDepState::IsLive(unsigned Reg)
David Goodwinde11f362009-10-26 19:32:42 +0000108{
109 // KillIndex must be defined and DefIndex not defined for a register
110 // to be live.
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u));
112}
113
David Goodwine056d102009-10-26 22:31:16 +0000114
115
116AggressiveAntiDepBreaker::
David Goodwincf89db12009-11-10 00:15:47 +0000117AggressiveAntiDepBreaker(MachineFunction& MFi,
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000118 const RegisterClassInfo &RCI,
Evan Cheng0d639a22011-07-01 21:01:15 +0000119 TargetSubtargetInfo::RegClassVector& CriticalPathRCs) :
David Goodwine056d102009-10-26 22:31:16 +0000120 AntiDepBreaker(), MF(MFi),
121 MRI(MF.getRegInfo()),
Evan Chengf128bdc2010-06-16 07:35:02 +0000122 TII(MF.getTarget().getInstrInfo()),
David Goodwine056d102009-10-26 22:31:16 +0000123 TRI(MF.getTarget().getRegisterInfo()),
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000124 RegClassInfo(RCI),
Craig Topperc0196b12014-04-14 00:51:57 +0000125 State(nullptr) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000126 /* Collect a bitset of all registers that are only broken if they
127 are on the critical path. */
128 for (unsigned i = 0, e = CriticalPathRCs.size(); i < e; ++i) {
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]);
130 if (CriticalPathSet.none())
131 CriticalPathSet = CPSet;
132 else
133 CriticalPathSet |= CPSet;
134 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000135
David Greene75a2efb2009-12-24 00:14:25 +0000136 DEBUG(dbgs() << "AntiDep Critical-Path Registers:");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000137 DEBUG(for (int r = CriticalPathSet.find_first(); r != -1;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000138 r = CriticalPathSet.find_next(r))
David Greene75a2efb2009-12-24 00:14:25 +0000139 dbgs() << " " << TRI->getName(r));
140 DEBUG(dbgs() << '\n');
David Goodwine056d102009-10-26 22:31:16 +0000141}
142
143AggressiveAntiDepBreaker::~AggressiveAntiDepBreaker() {
144 delete State;
David Goodwine056d102009-10-26 22:31:16 +0000145}
146
147void AggressiveAntiDepBreaker::StartBlock(MachineBasicBlock *BB) {
Craig Topperc0196b12014-04-14 00:51:57 +0000148 assert(!State);
David Goodwina45fe672009-12-09 17:18:22 +0000149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB);
David Goodwine056d102009-10-26 22:31:16 +0000150
Evan Cheng7f8e5632011-12-07 07:15:52 +0000151 bool IsReturnBlock = (!BB->empty() && BB->back().isReturn());
Bill Wendling030b0282010-07-15 18:43:09 +0000152 std::vector<unsigned> &KillIndices = State->GetKillIndices();
153 std::vector<unsigned> &DefIndices = State->GetDefIndices();
David Goodwine056d102009-10-26 22:31:16 +0000154
Jakob Stoklund Olesenc3386792013-02-05 18:21:52 +0000155 // Examine the live-in regs of all successors.
Evan Chengf128bdc2010-06-16 07:35:02 +0000156 for (MachineBasicBlock::succ_iterator SI = BB->succ_begin(),
157 SE = BB->succ_end(); SI != SE; ++SI)
158 for (MachineBasicBlock::livein_iterator I = (*SI)->livein_begin(),
159 E = (*SI)->livein_end(); I != E; ++I) {
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000160 for (MCRegAliasIterator AI(*I, TRI, true); AI.isValid(); ++AI) {
161 unsigned Reg = *AI;
Jakob Stoklund Olesenbe1c8d32010-12-14 23:23:15 +0000162 State->UnionGroups(Reg, 0);
163 KillIndices[Reg] = BB->size();
164 DefIndices[Reg] = ~0u;
Evan Chengf128bdc2010-06-16 07:35:02 +0000165 }
166 }
167
David Goodwine056d102009-10-26 22:31:16 +0000168 // Mark live-out callee-saved registers. In a return block this is
169 // all callee-saved registers. In non-return this is any
170 // callee-saved register that is not saved in the prolog.
171 const MachineFrameInfo *MFI = MF.getFrameInfo();
172 BitVector Pristine = MFI->getPristineRegs(BB);
Craig Topper840beec2014-04-04 05:16:06 +0000173 for (const MCPhysReg *I = TRI->getCalleeSavedRegs(&MF); *I; ++I) {
David Goodwine056d102009-10-26 22:31:16 +0000174 unsigned Reg = *I;
175 if (!IsReturnBlock && !Pristine.test(Reg)) continue;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000176 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
177 unsigned AliasReg = *AI;
David Goodwine056d102009-10-26 22:31:16 +0000178 State->UnionGroups(AliasReg, 0);
179 KillIndices[AliasReg] = BB->size();
180 DefIndices[AliasReg] = ~0u;
181 }
182 }
183}
184
185void AggressiveAntiDepBreaker::FinishBlock() {
186 delete State;
Craig Topperc0196b12014-04-14 00:51:57 +0000187 State = nullptr;
David Goodwine056d102009-10-26 22:31:16 +0000188}
189
190void AggressiveAntiDepBreaker::Observe(MachineInstr *MI, unsigned Count,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000191 unsigned InsertPosIndex) {
David Goodwine056d102009-10-26 22:31:16 +0000192 assert(Count < InsertPosIndex && "Instruction index out of expected range!");
193
David Goodwinfaa76602009-10-29 23:30:59 +0000194 std::set<unsigned> PassthruRegs;
195 GetPassthruRegs(MI, PassthruRegs);
196 PrescanInstruction(MI, Count, PassthruRegs);
197 ScanInstruction(MI, Count);
198
David Greene75a2efb2009-12-24 00:14:25 +0000199 DEBUG(dbgs() << "Observe: ");
David Goodwine056d102009-10-26 22:31:16 +0000200 DEBUG(MI->dump());
David Greene75a2efb2009-12-24 00:14:25 +0000201 DEBUG(dbgs() << "\tRegs:");
David Goodwine056d102009-10-26 22:31:16 +0000202
Bill Wendling030b0282010-07-15 18:43:09 +0000203 std::vector<unsigned> &DefIndices = State->GetDefIndices();
David Goodwina45fe672009-12-09 17:18:22 +0000204 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) {
David Goodwine056d102009-10-26 22:31:16 +0000205 // If Reg is current live, then mark that it can't be renamed as
206 // we don't know the extent of its live-range anymore (now that it
207 // has been scheduled). If it is not live but was defined in the
208 // previous schedule region, then set its def index to the most
209 // conservative location (i.e. the beginning of the previous
210 // schedule region).
211 if (State->IsLive(Reg)) {
212 DEBUG(if (State->GetGroup(Reg) != 0)
Jim Grosbacheb431da2010-01-06 16:48:02 +0000213 dbgs() << " " << TRI->getName(Reg) << "=g" <<
David Goodwine056d102009-10-26 22:31:16 +0000214 State->GetGroup(Reg) << "->g0(region live-out)");
215 State->UnionGroups(Reg, 0);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000216 } else if ((DefIndices[Reg] < InsertPosIndex)
217 && (DefIndices[Reg] >= Count)) {
David Goodwine056d102009-10-26 22:31:16 +0000218 DefIndices[Reg] = Count;
219 }
220 }
David Greene75a2efb2009-12-24 00:14:25 +0000221 DEBUG(dbgs() << '\n');
David Goodwine056d102009-10-26 22:31:16 +0000222}
223
David Goodwinde11f362009-10-26 19:32:42 +0000224bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr *MI,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000225 MachineOperand& MO)
David Goodwinde11f362009-10-26 19:32:42 +0000226{
227 if (!MO.isReg() || !MO.isImplicit())
228 return false;
229
230 unsigned Reg = MO.getReg();
231 if (Reg == 0)
232 return false;
233
Craig Topperc0196b12014-04-14 00:51:57 +0000234 MachineOperand *Op = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000235 if (MO.isDef())
236 Op = MI->findRegisterUseOperand(Reg, true);
237 else
238 Op = MI->findRegisterDefOperand(Reg);
239
Craig Topperc0196b12014-04-14 00:51:57 +0000240 return(Op && Op->isImplicit());
David Goodwinde11f362009-10-26 19:32:42 +0000241}
242
243void AggressiveAntiDepBreaker::GetPassthruRegs(MachineInstr *MI,
244 std::set<unsigned>& PassthruRegs) {
245 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
246 MachineOperand &MO = MI->getOperand(i);
247 if (!MO.isReg()) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000248 if ((MO.isDef() && MI->isRegTiedToUseOperand(i)) ||
David Goodwinde11f362009-10-26 19:32:42 +0000249 IsImplicitDefUse(MI, MO)) {
250 const unsigned Reg = MO.getReg();
Chad Rosierabdb1d62013-05-22 23:17:36 +0000251 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
252 SubRegs.isValid(); ++SubRegs)
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000253 PassthruRegs.insert(*SubRegs);
David Goodwinde11f362009-10-26 19:32:42 +0000254 }
255 }
256}
257
David Goodwin80a03cc2009-11-20 19:32:48 +0000258/// AntiDepEdges - Return in Edges the anti- and output- dependencies
259/// in SU that we want to consider for breaking.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000260static void AntiDepEdges(const SUnit *SU, std::vector<const SDep*>& Edges) {
David Goodwin80a03cc2009-11-20 19:32:48 +0000261 SmallSet<unsigned, 4> RegSet;
Dan Gohman35bc4d42010-04-19 23:11:58 +0000262 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
David Goodwinde11f362009-10-26 19:32:42 +0000263 P != PE; ++P) {
David Goodwinda83f7d2009-11-12 19:08:21 +0000264 if ((P->getKind() == SDep::Anti) || (P->getKind() == SDep::Output)) {
David Goodwinde11f362009-10-26 19:32:42 +0000265 unsigned Reg = P->getReg();
David Goodwin80a03cc2009-11-20 19:32:48 +0000266 if (RegSet.count(Reg) == 0) {
David Goodwinde11f362009-10-26 19:32:42 +0000267 Edges.push_back(&*P);
David Goodwin80a03cc2009-11-20 19:32:48 +0000268 RegSet.insert(Reg);
David Goodwinde11f362009-10-26 19:32:42 +0000269 }
270 }
271 }
272}
273
David Goodwinb9fe5d52009-11-13 19:52:48 +0000274/// CriticalPathStep - Return the next SUnit after SU on the bottom-up
275/// critical path.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000276static const SUnit *CriticalPathStep(const SUnit *SU) {
Craig Topperc0196b12014-04-14 00:51:57 +0000277 const SDep *Next = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000278 unsigned NextDepth = 0;
279 // Find the predecessor edge with the greatest depth.
Craig Topperc0196b12014-04-14 00:51:57 +0000280 if (SU) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000281 for (SUnit::const_pred_iterator P = SU->Preds.begin(), PE = SU->Preds.end();
David Goodwinb9fe5d52009-11-13 19:52:48 +0000282 P != PE; ++P) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000283 const SUnit *PredSU = P->getSUnit();
David Goodwinb9fe5d52009-11-13 19:52:48 +0000284 unsigned PredLatency = P->getLatency();
285 unsigned PredTotalLatency = PredSU->getDepth() + PredLatency;
286 // In the case of a latency tie, prefer an anti-dependency edge over
287 // other types of edges.
288 if (NextDepth < PredTotalLatency ||
289 (NextDepth == PredTotalLatency && P->getKind() == SDep::Anti)) {
290 NextDepth = PredTotalLatency;
291 Next = &*P;
292 }
293 }
294 }
295
Craig Topperc0196b12014-04-14 00:51:57 +0000296 return (Next) ? Next->getSUnit() : nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000297}
298
David Goodwin9f1b2d42009-10-29 19:17:04 +0000299void AggressiveAntiDepBreaker::HandleLastUse(unsigned Reg, unsigned KillIdx,
Jim Grosbacheb431da2010-01-06 16:48:02 +0000300 const char *tag,
301 const char *header,
David Goodwindd1c6192009-11-19 23:12:37 +0000302 const char *footer) {
Bill Wendling030b0282010-07-15 18:43:09 +0000303 std::vector<unsigned> &KillIndices = State->GetKillIndices();
304 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000305 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwin9f1b2d42009-10-29 19:17:04 +0000306 RegRefs = State->GetRegRefs();
307
308 if (!State->IsLive(Reg)) {
309 KillIndices[Reg] = KillIdx;
310 DefIndices[Reg] = ~0u;
311 RegRefs.erase(Reg);
312 State->LeaveGroup(Reg);
Craig Topperc0196b12014-04-14 00:51:57 +0000313 DEBUG(if (header) {
314 dbgs() << header << TRI->getName(Reg); header = nullptr; });
David Greene75a2efb2009-12-24 00:14:25 +0000315 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << tag);
David Goodwin9f1b2d42009-10-29 19:17:04 +0000316 }
317 // Repeat for subregisters.
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000318 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
319 unsigned SubregReg = *SubRegs;
David Goodwin9f1b2d42009-10-29 19:17:04 +0000320 if (!State->IsLive(SubregReg)) {
321 KillIndices[SubregReg] = KillIdx;
322 DefIndices[SubregReg] = ~0u;
323 RegRefs.erase(SubregReg);
324 State->LeaveGroup(SubregReg);
Craig Topperc0196b12014-04-14 00:51:57 +0000325 DEBUG(if (header) {
326 dbgs() << header << TRI->getName(Reg); header = nullptr; });
David Greene75a2efb2009-12-24 00:14:25 +0000327 DEBUG(dbgs() << " " << TRI->getName(SubregReg) << "->g" <<
David Goodwin9f1b2d42009-10-29 19:17:04 +0000328 State->GetGroup(SubregReg) << tag);
329 }
330 }
David Goodwindd1c6192009-11-19 23:12:37 +0000331
Craig Topperc0196b12014-04-14 00:51:57 +0000332 DEBUG(if (!header && footer) dbgs() << footer);
David Goodwin9f1b2d42009-10-29 19:17:04 +0000333}
334
Jim Grosbacheb431da2010-01-06 16:48:02 +0000335void AggressiveAntiDepBreaker::PrescanInstruction(MachineInstr *MI,
336 unsigned Count,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000337 std::set<unsigned>& PassthruRegs) {
Bill Wendling030b0282010-07-15 18:43:09 +0000338 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000339 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000340 RegRefs = State->GetRegRefs();
341
David Goodwin9f1b2d42009-10-29 19:17:04 +0000342 // Handle dead defs by simulating a last-use of the register just
Chris Lattner0ab5e2c2011-04-15 05:18:47 +0000343 // after the def. A dead def can occur because the def is truly
David Goodwin9f1b2d42009-10-29 19:17:04 +0000344 // dead, or because only a subregister is live at the def. If we
345 // don't do this the dead def will be incorrectly merged into the
346 // previous def.
David Goodwinde11f362009-10-26 19:32:42 +0000347 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
348 MachineOperand &MO = MI->getOperand(i);
349 if (!MO.isReg() || !MO.isDef()) continue;
350 unsigned Reg = MO.getReg();
351 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000352
David Goodwindd1c6192009-11-19 23:12:37 +0000353 HandleLastUse(Reg, Count + 1, "", "\tDead Def: ", "\n");
David Goodwinde11f362009-10-26 19:32:42 +0000354 }
355
David Greene75a2efb2009-12-24 00:14:25 +0000356 DEBUG(dbgs() << "\tDef Groups:");
David Goodwinde11f362009-10-26 19:32:42 +0000357 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
358 MachineOperand &MO = MI->getOperand(i);
359 if (!MO.isReg() || !MO.isDef()) continue;
360 unsigned Reg = MO.getReg();
361 if (Reg == 0) continue;
362
Jim Grosbacheb431da2010-01-06 16:48:02 +0000363 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" << State->GetGroup(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000364
David Goodwin9f1b2d42009-10-29 19:17:04 +0000365 // If MI's defs have a special allocation requirement, don't allow
David Goodwinde11f362009-10-26 19:32:42 +0000366 // any def registers to be changed. Also assume all registers
367 // defined in a call must not be changed (ABI).
Evan Cheng7f8e5632011-12-07 07:15:52 +0000368 if (MI->isCall() || MI->hasExtraDefRegAllocReq() ||
Evan Chengf128bdc2010-06-16 07:35:02 +0000369 TII->isPredicated(MI)) {
David Greene75a2efb2009-12-24 00:14:25 +0000370 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
David Goodwine056d102009-10-26 22:31:16 +0000371 State->UnionGroups(Reg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000372 }
373
374 // Any aliased that are live at this point are completely or
David Goodwin9f1b2d42009-10-29 19:17:04 +0000375 // partially defined here, so group those aliases with Reg.
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000376 for (MCRegAliasIterator AI(Reg, TRI, false); AI.isValid(); ++AI) {
377 unsigned AliasReg = *AI;
David Goodwine056d102009-10-26 22:31:16 +0000378 if (State->IsLive(AliasReg)) {
379 State->UnionGroups(Reg, AliasReg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000380 DEBUG(dbgs() << "->g" << State->GetGroup(Reg) << "(via " <<
David Goodwinde11f362009-10-26 19:32:42 +0000381 TRI->getName(AliasReg) << ")");
382 }
383 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000384
David Goodwinde11f362009-10-26 19:32:42 +0000385 // Note register reference...
Craig Topperc0196b12014-04-14 00:51:57 +0000386 const TargetRegisterClass *RC = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000387 if (i < MI->getDesc().getNumOperands())
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000388 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
David Goodwine056d102009-10-26 22:31:16 +0000389 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
David Goodwinde11f362009-10-26 19:32:42 +0000390 RegRefs.insert(std::make_pair(Reg, RR));
391 }
392
David Greene75a2efb2009-12-24 00:14:25 +0000393 DEBUG(dbgs() << '\n');
David Goodwin9f1b2d42009-10-29 19:17:04 +0000394
395 // Scan the register defs for this instruction and update
396 // live-ranges.
397 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
398 MachineOperand &MO = MI->getOperand(i);
399 if (!MO.isReg() || !MO.isDef()) continue;
400 unsigned Reg = MO.getReg();
401 if (Reg == 0) continue;
David Goodwindd1c6192009-11-19 23:12:37 +0000402 // Ignore KILLs and passthru registers for liveness...
Chris Lattnerb06015a2010-02-09 19:54:29 +0000403 if (MI->isKill() || (PassthruRegs.count(Reg) != 0))
David Goodwindd1c6192009-11-19 23:12:37 +0000404 continue;
David Goodwin9f1b2d42009-10-29 19:17:04 +0000405
David Goodwindd1c6192009-11-19 23:12:37 +0000406 // Update def for Reg and aliases.
Hal Finkel121caf62014-02-26 20:20:30 +0000407 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI) {
408 // We need to be careful here not to define already-live super registers.
409 // If the super register is already live, then this definition is not
410 // a definition of the whole super register (just a partial insertion
411 // into it). Earlier subregister definitions (which we've not yet visited
412 // because we're iterating bottom-up) need to be linked to the same group
413 // as this definition.
414 if (TRI->isSuperRegister(Reg, *AI) && State->IsLive(*AI))
415 continue;
416
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000417 DefIndices[*AI] = Count;
Hal Finkel121caf62014-02-26 20:20:30 +0000418 }
David Goodwin9f1b2d42009-10-29 19:17:04 +0000419 }
David Goodwinde11f362009-10-26 19:32:42 +0000420}
421
422void AggressiveAntiDepBreaker::ScanInstruction(MachineInstr *MI,
Bob Wilson67dd3a42010-04-09 21:38:26 +0000423 unsigned Count) {
David Greene75a2efb2009-12-24 00:14:25 +0000424 DEBUG(dbgs() << "\tUse Groups:");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000425 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000426 RegRefs = State->GetRegRefs();
David Goodwinde11f362009-10-26 19:32:42 +0000427
Evan Chengf128bdc2010-06-16 07:35:02 +0000428 // If MI's uses have special allocation requirement, don't allow
429 // any use registers to be changed. Also assume all registers
430 // used in a call must not be changed (ABI).
431 // FIXME: The issue with predicated instruction is more complex. We are being
432 // conservatively here because the kill markers cannot be trusted after
433 // if-conversion:
434 // %R6<def> = LDR %SP, %reg0, 92, pred:14, pred:%reg0; mem:LD4[FixedStack14]
435 // ...
436 // STR %R0, %R6<kill>, %reg0, 0, pred:0, pred:%CPSR; mem:ST4[%395]
437 // %R6<def> = LDR %SP, %reg0, 100, pred:0, pred:%CPSR; mem:LD4[FixedStack12]
438 // STR %R0, %R6<kill>, %reg0, 0, pred:14, pred:%reg0; mem:ST4[%396](align=8)
439 //
440 // The first R6 kill is not really a kill since it's killed by a predicated
441 // instruction which may not be executed. The second R6 def may or may not
442 // re-define R6 so it's not safe to change it since the last R6 use cannot be
443 // changed.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000444 bool Special = MI->isCall() ||
445 MI->hasExtraSrcRegAllocReq() ||
Evan Chengf128bdc2010-06-16 07:35:02 +0000446 TII->isPredicated(MI);
447
David Goodwinde11f362009-10-26 19:32:42 +0000448 // Scan the register uses for this instruction and update
449 // live-ranges, groups and RegRefs.
450 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
451 MachineOperand &MO = MI->getOperand(i);
452 if (!MO.isReg() || !MO.isUse()) continue;
453 unsigned Reg = MO.getReg();
454 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000455
456 DEBUG(dbgs() << " " << TRI->getName(Reg) << "=g" <<
457 State->GetGroup(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000458
459 // It wasn't previously live but now it is, this is a kill. Forget
460 // the previous live-range information and start a new live-range
461 // for the register.
David Goodwin9f1b2d42009-10-29 19:17:04 +0000462 HandleLastUse(Reg, Count, "(last-use)");
David Goodwinde11f362009-10-26 19:32:42 +0000463
Evan Chengf128bdc2010-06-16 07:35:02 +0000464 if (Special) {
David Greene75a2efb2009-12-24 00:14:25 +0000465 DEBUG(if (State->GetGroup(Reg) != 0) dbgs() << "->g0(alloc-req)");
David Goodwine056d102009-10-26 22:31:16 +0000466 State->UnionGroups(Reg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000467 }
468
469 // Note register reference...
Craig Topperc0196b12014-04-14 00:51:57 +0000470 const TargetRegisterClass *RC = nullptr;
David Goodwinde11f362009-10-26 19:32:42 +0000471 if (i < MI->getDesc().getNumOperands())
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000472 RC = TII->getRegClass(MI->getDesc(), i, TRI, MF);
David Goodwine056d102009-10-26 22:31:16 +0000473 AggressiveAntiDepState::RegisterReference RR = { &MO, RC };
David Goodwinde11f362009-10-26 19:32:42 +0000474 RegRefs.insert(std::make_pair(Reg, RR));
475 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000476
David Greene75a2efb2009-12-24 00:14:25 +0000477 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000478
479 // Form a group of all defs and uses of a KILL instruction to ensure
480 // that all registers are renamed as a group.
Chris Lattnerb06015a2010-02-09 19:54:29 +0000481 if (MI->isKill()) {
David Greene75a2efb2009-12-24 00:14:25 +0000482 DEBUG(dbgs() << "\tKill Group:");
David Goodwinde11f362009-10-26 19:32:42 +0000483
484 unsigned FirstReg = 0;
485 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
486 MachineOperand &MO = MI->getOperand(i);
487 if (!MO.isReg()) continue;
488 unsigned Reg = MO.getReg();
489 if (Reg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000490
David Goodwinde11f362009-10-26 19:32:42 +0000491 if (FirstReg != 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000492 DEBUG(dbgs() << "=" << TRI->getName(Reg));
David Goodwine056d102009-10-26 22:31:16 +0000493 State->UnionGroups(FirstReg, Reg);
David Goodwinde11f362009-10-26 19:32:42 +0000494 } else {
David Greene75a2efb2009-12-24 00:14:25 +0000495 DEBUG(dbgs() << " " << TRI->getName(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000496 FirstReg = Reg;
497 }
498 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000499
David Greene75a2efb2009-12-24 00:14:25 +0000500 DEBUG(dbgs() << "->g" << State->GetGroup(FirstReg) << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000501 }
502}
503
504BitVector AggressiveAntiDepBreaker::GetRenameRegisters(unsigned Reg) {
505 BitVector BV(TRI->getNumRegs(), false);
506 bool first = true;
507
508 // Check all references that need rewriting for Reg. For each, use
509 // the corresponding register class to narrow the set of registers
510 // that are appropriate for renaming.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000511 std::pair<std::multimap<unsigned,
David Goodwine056d102009-10-26 22:31:16 +0000512 AggressiveAntiDepState::RegisterReference>::iterator,
513 std::multimap<unsigned,
514 AggressiveAntiDepState::RegisterReference>::iterator>
515 Range = State->GetRegRefs().equal_range(Reg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000516 for (std::multimap<unsigned,
517 AggressiveAntiDepState::RegisterReference>::iterator Q = Range.first,
518 QE = Range.second; Q != QE; ++Q) {
David Goodwinde11f362009-10-26 19:32:42 +0000519 const TargetRegisterClass *RC = Q->second.RC;
Craig Topperc0196b12014-04-14 00:51:57 +0000520 if (!RC) continue;
David Goodwinde11f362009-10-26 19:32:42 +0000521
522 BitVector RCBV = TRI->getAllocatableSet(MF, RC);
523 if (first) {
524 BV |= RCBV;
525 first = false;
526 } else {
527 BV &= RCBV;
528 }
529
David Greene75a2efb2009-12-24 00:14:25 +0000530 DEBUG(dbgs() << " " << RC->getName());
David Goodwinde11f362009-10-26 19:32:42 +0000531 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000532
David Goodwinde11f362009-10-26 19:32:42 +0000533 return BV;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000534}
David Goodwinde11f362009-10-26 19:32:42 +0000535
536bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters(
David Goodwin7d8878a2009-11-05 01:19:35 +0000537 unsigned AntiDepGroupIndex,
538 RenameOrderType& RenameOrder,
539 std::map<unsigned, unsigned> &RenameMap) {
Bill Wendling030b0282010-07-15 18:43:09 +0000540 std::vector<unsigned> &KillIndices = State->GetKillIndices();
541 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000542 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000543 RegRefs = State->GetRegRefs();
544
David Goodwinb9fe5d52009-11-13 19:52:48 +0000545 // Collect all referenced registers in the same group as
546 // AntiDepReg. These all need to be renamed together if we are to
547 // break the anti-dependence.
David Goodwinde11f362009-10-26 19:32:42 +0000548 std::vector<unsigned> Regs;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000549 State->GetGroupRegs(AntiDepGroupIndex, Regs, &RegRefs);
David Goodwinde11f362009-10-26 19:32:42 +0000550 assert(Regs.size() > 0 && "Empty register group!");
551 if (Regs.size() == 0)
552 return false;
553
554 // Find the "superest" register in the group. At the same time,
555 // collect the BitVector of registers that can be used to rename
556 // each register.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000557 DEBUG(dbgs() << "\tRename Candidates for Group g" << AntiDepGroupIndex
558 << ":\n");
David Goodwinde11f362009-10-26 19:32:42 +0000559 std::map<unsigned, BitVector> RenameRegisterMap;
560 unsigned SuperReg = 0;
561 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
562 unsigned Reg = Regs[i];
563 if ((SuperReg == 0) || TRI->isSuperRegister(SuperReg, Reg))
564 SuperReg = Reg;
565
566 // If Reg has any references, then collect possible rename regs
567 if (RegRefs.count(Reg) > 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000568 DEBUG(dbgs() << "\t\t" << TRI->getName(Reg) << ":");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000569
David Goodwinde11f362009-10-26 19:32:42 +0000570 BitVector BV = GetRenameRegisters(Reg);
571 RenameRegisterMap.insert(std::pair<unsigned, BitVector>(Reg, BV));
572
David Greene75a2efb2009-12-24 00:14:25 +0000573 DEBUG(dbgs() << " ::");
David Goodwinde11f362009-10-26 19:32:42 +0000574 DEBUG(for (int r = BV.find_first(); r != -1; r = BV.find_next(r))
David Greene75a2efb2009-12-24 00:14:25 +0000575 dbgs() << " " << TRI->getName(r));
576 DEBUG(dbgs() << "\n");
David Goodwinde11f362009-10-26 19:32:42 +0000577 }
578 }
579
580 // All group registers should be a subreg of SuperReg.
581 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
582 unsigned Reg = Regs[i];
583 if (Reg == SuperReg) continue;
584 bool IsSub = TRI->isSubRegister(SuperReg, Reg);
Will Schmidt44ff8f02014-07-31 19:50:53 +0000585 // FIXME: remove this once PR18663 has been properly fixed. For now,
586 // return a conservative answer:
587 // assert(IsSub && "Expecting group subregister");
David Goodwinde11f362009-10-26 19:32:42 +0000588 if (!IsSub)
589 return false;
590 }
591
David Goodwin5305dc02009-11-20 23:33:54 +0000592#ifndef NDEBUG
593 // If DebugDiv > 0 then only rename (renamecnt % DebugDiv) == DebugMod
594 if (DebugDiv > 0) {
595 static int renamecnt = 0;
596 if (renamecnt++ % DebugDiv != DebugMod)
597 return false;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000598
David Greene75a2efb2009-12-24 00:14:25 +0000599 dbgs() << "*** Performing rename " << TRI->getName(SuperReg) <<
David Goodwin5305dc02009-11-20 23:33:54 +0000600 " for debug ***\n";
601 }
602#endif
603
David Goodwin7d8878a2009-11-05 01:19:35 +0000604 // Check each possible rename register for SuperReg in round-robin
605 // order. If that register is available, and the corresponding
606 // registers are available for the other group subregisters, then we
607 // can use those registers to rename.
Rafael Espindola871c7242010-07-12 02:55:34 +0000608
609 // FIXME: Using getMinimalPhysRegClass is very conservative. We should
610 // check every use of the register and find the largest register class
611 // that can be used in all of them.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000612 const TargetRegisterClass *SuperRC =
Rafael Espindola871c7242010-07-12 02:55:34 +0000613 TRI->getMinimalPhysRegClass(SuperReg, MVT::Other);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000614
Jakob Stoklund Olesenbdb55e02012-11-29 03:34:17 +0000615 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC);
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000616 if (Order.empty()) {
David Greene75a2efb2009-12-24 00:14:25 +0000617 DEBUG(dbgs() << "\tEmpty Super Regclass!!\n");
David Goodwin7d8878a2009-11-05 01:19:35 +0000618 return false;
619 }
620
David Greene75a2efb2009-12-24 00:14:25 +0000621 DEBUG(dbgs() << "\tFind Registers:");
David Goodwindd1c6192009-11-19 23:12:37 +0000622
David Goodwin7d8878a2009-11-05 01:19:35 +0000623 if (RenameOrder.count(SuperRC) == 0)
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000624 RenameOrder.insert(RenameOrderType::value_type(SuperRC, Order.size()));
David Goodwin7d8878a2009-11-05 01:19:35 +0000625
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000626 unsigned OrigR = RenameOrder[SuperRC];
627 unsigned EndR = ((OrigR == Order.size()) ? 0 : OrigR);
628 unsigned R = OrigR;
David Goodwin7d8878a2009-11-05 01:19:35 +0000629 do {
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000630 if (R == 0) R = Order.size();
David Goodwin7d8878a2009-11-05 01:19:35 +0000631 --R;
Jakob Stoklund Olesen4f5f84c2011-06-16 21:56:21 +0000632 const unsigned NewSuperReg = Order[R];
Jim Grosbach944aece2010-09-02 17:12:55 +0000633 // Don't consider non-allocatable registers
Jakob Stoklund Olesenf67bf3e2012-10-15 22:41:03 +0000634 if (!MRI.isAllocatable(NewSuperReg)) continue;
David Goodwinde11f362009-10-26 19:32:42 +0000635 // Don't replace a register with itself.
David Goodwin5305dc02009-11-20 23:33:54 +0000636 if (NewSuperReg == SuperReg) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000637
David Greene75a2efb2009-12-24 00:14:25 +0000638 DEBUG(dbgs() << " [" << TRI->getName(NewSuperReg) << ':');
David Goodwin5305dc02009-11-20 23:33:54 +0000639 RenameMap.clear();
640
641 // For each referenced group register (which must be a SuperReg or
642 // a subregister of SuperReg), find the corresponding subregister
643 // of NewSuperReg and make sure it is free to be renamed.
644 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
645 unsigned Reg = Regs[i];
646 unsigned NewReg = 0;
647 if (Reg == SuperReg) {
648 NewReg = NewSuperReg;
649 } else {
650 unsigned NewSubRegIdx = TRI->getSubRegIndex(SuperReg, Reg);
651 if (NewSubRegIdx != 0)
652 NewReg = TRI->getSubReg(NewSuperReg, NewSubRegIdx);
David Goodwinde11f362009-10-26 19:32:42 +0000653 }
David Goodwin5305dc02009-11-20 23:33:54 +0000654
David Greene75a2efb2009-12-24 00:14:25 +0000655 DEBUG(dbgs() << " " << TRI->getName(NewReg));
Jim Grosbacheb431da2010-01-06 16:48:02 +0000656
David Goodwin5305dc02009-11-20 23:33:54 +0000657 // Check if Reg can be renamed to NewReg.
658 BitVector BV = RenameRegisterMap[Reg];
659 if (!BV.test(NewReg)) {
David Greene75a2efb2009-12-24 00:14:25 +0000660 DEBUG(dbgs() << "(no rename)");
David Goodwin5305dc02009-11-20 23:33:54 +0000661 goto next_super_reg;
662 }
663
664 // If NewReg is dead and NewReg's most recent def is not before
665 // Regs's kill, it's safe to replace Reg with NewReg. We
666 // must also check all aliases of NewReg, because we can't define a
667 // register when any sub or super is already live.
668 if (State->IsLive(NewReg) || (KillIndices[Reg] > DefIndices[NewReg])) {
David Greene75a2efb2009-12-24 00:14:25 +0000669 DEBUG(dbgs() << "(live)");
David Goodwin5305dc02009-11-20 23:33:54 +0000670 goto next_super_reg;
671 } else {
672 bool found = false;
Jakob Stoklund Olesen54038d72012-06-01 23:28:30 +0000673 for (MCRegAliasIterator AI(NewReg, TRI, false); AI.isValid(); ++AI) {
674 unsigned AliasReg = *AI;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000675 if (State->IsLive(AliasReg) ||
676 (KillIndices[Reg] > DefIndices[AliasReg])) {
David Greene75a2efb2009-12-24 00:14:25 +0000677 DEBUG(dbgs() << "(alias " << TRI->getName(AliasReg) << " live)");
David Goodwin5305dc02009-11-20 23:33:54 +0000678 found = true;
679 break;
680 }
681 }
682 if (found)
683 goto next_super_reg;
684 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000685
David Goodwin5305dc02009-11-20 23:33:54 +0000686 // Record that 'Reg' can be renamed to 'NewReg'.
687 RenameMap.insert(std::pair<unsigned, unsigned>(Reg, NewReg));
David Goodwinde11f362009-10-26 19:32:42 +0000688 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000689
David Goodwin5305dc02009-11-20 23:33:54 +0000690 // If we fall-out here, then every register in the group can be
691 // renamed, as recorded in RenameMap.
692 RenameOrder.erase(SuperRC);
693 RenameOrder.insert(RenameOrderType::value_type(SuperRC, R));
David Greene75a2efb2009-12-24 00:14:25 +0000694 DEBUG(dbgs() << "]\n");
David Goodwin5305dc02009-11-20 23:33:54 +0000695 return true;
696
697 next_super_reg:
David Greene75a2efb2009-12-24 00:14:25 +0000698 DEBUG(dbgs() << ']');
David Goodwin7d8878a2009-11-05 01:19:35 +0000699 } while (R != EndR);
David Goodwinde11f362009-10-26 19:32:42 +0000700
David Greene75a2efb2009-12-24 00:14:25 +0000701 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000702
703 // No registers are free and available!
704 return false;
705}
706
707/// BreakAntiDependencies - Identifiy anti-dependencies within the
708/// ScheduleDAG and break them by renaming registers.
709///
David Goodwine056d102009-10-26 22:31:16 +0000710unsigned AggressiveAntiDepBreaker::BreakAntiDependencies(
Dan Gohman35bc4d42010-04-19 23:11:58 +0000711 const std::vector<SUnit>& SUnits,
712 MachineBasicBlock::iterator Begin,
713 MachineBasicBlock::iterator End,
Devang Patelf02a3762011-06-02 21:26:52 +0000714 unsigned InsertPosIndex,
715 DbgValueVector &DbgValues) {
716
Bill Wendling030b0282010-07-15 18:43:09 +0000717 std::vector<unsigned> &KillIndices = State->GetKillIndices();
718 std::vector<unsigned> &DefIndices = State->GetDefIndices();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000719 std::multimap<unsigned, AggressiveAntiDepState::RegisterReference>&
David Goodwine056d102009-10-26 22:31:16 +0000720 RegRefs = State->GetRegRefs();
721
David Goodwinde11f362009-10-26 19:32:42 +0000722 // The code below assumes that there is at least one instruction,
723 // so just duck out immediately if the block is empty.
David Goodwin8501dbbe2009-11-03 20:57:50 +0000724 if (SUnits.empty()) return 0;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000725
David Goodwin7d8878a2009-11-05 01:19:35 +0000726 // For each regclass the next register to use for renaming.
727 RenameOrderType RenameOrder;
David Goodwinde11f362009-10-26 19:32:42 +0000728
729 // ...need a map from MI to SUnit.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000730 std::map<MachineInstr *, const SUnit *> MISUnitMap;
David Goodwinde11f362009-10-26 19:32:42 +0000731 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000732 const SUnit *SU = &SUnits[i];
733 MISUnitMap.insert(std::pair<MachineInstr *, const SUnit *>(SU->getInstr(),
734 SU));
David Goodwinde11f362009-10-26 19:32:42 +0000735 }
736
David Goodwinb9fe5d52009-11-13 19:52:48 +0000737 // Track progress along the critical path through the SUnit graph as
738 // we walk the instructions. This is needed for regclasses that only
739 // break critical-path anti-dependencies.
Craig Topperc0196b12014-04-14 00:51:57 +0000740 const SUnit *CriticalPathSU = nullptr;
741 MachineInstr *CriticalPathMI = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000742 if (CriticalPathSet.any()) {
743 for (unsigned i = 0, e = SUnits.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000744 const SUnit *SU = &SUnits[i];
Jim Grosbacheb431da2010-01-06 16:48:02 +0000745 if (!CriticalPathSU ||
746 ((SU->getDepth() + SU->Latency) >
David Goodwinb9fe5d52009-11-13 19:52:48 +0000747 (CriticalPathSU->getDepth() + CriticalPathSU->Latency))) {
748 CriticalPathSU = SU;
749 }
750 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000751
David Goodwinb9fe5d52009-11-13 19:52:48 +0000752 CriticalPathMI = CriticalPathSU->getInstr();
753 }
754
Jim Grosbacheb431da2010-01-06 16:48:02 +0000755#ifndef NDEBUG
David Greene75a2efb2009-12-24 00:14:25 +0000756 DEBUG(dbgs() << "\n===== Aggressive anti-dependency breaking\n");
757 DEBUG(dbgs() << "Available regs:");
David Goodwin80a03cc2009-11-20 19:32:48 +0000758 for (unsigned Reg = 0; Reg < TRI->getNumRegs(); ++Reg) {
759 if (!State->IsLive(Reg))
David Greene75a2efb2009-12-24 00:14:25 +0000760 DEBUG(dbgs() << " " << TRI->getName(Reg));
David Goodwinde11f362009-10-26 19:32:42 +0000761 }
David Greene75a2efb2009-12-24 00:14:25 +0000762 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000763#endif
764
765 // Attempt to break anti-dependence edges. Walk the instructions
766 // from the bottom up, tracking information about liveness as we go
767 // to help determine which registers are available.
768 unsigned Broken = 0;
769 unsigned Count = InsertPosIndex - 1;
770 for (MachineBasicBlock::iterator I = End, E = Begin;
771 I != E; --Count) {
772 MachineInstr *MI = --I;
773
Hal Finkel8606e3c2012-01-16 22:53:41 +0000774 if (MI->isDebugValue())
775 continue;
776
David Greene75a2efb2009-12-24 00:14:25 +0000777 DEBUG(dbgs() << "Anti: ");
David Goodwinde11f362009-10-26 19:32:42 +0000778 DEBUG(MI->dump());
779
780 std::set<unsigned> PassthruRegs;
781 GetPassthruRegs(MI, PassthruRegs);
782
783 // Process the defs in MI...
784 PrescanInstruction(MI, Count, PassthruRegs);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000785
David Goodwin80a03cc2009-11-20 19:32:48 +0000786 // The dependence edges that represent anti- and output-
David Goodwinb9fe5d52009-11-13 19:52:48 +0000787 // dependencies that are candidates for breaking.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000788 std::vector<const SDep *> Edges;
789 const SUnit *PathSU = MISUnitMap[MI];
David Goodwin80a03cc2009-11-20 19:32:48 +0000790 AntiDepEdges(PathSU, Edges);
David Goodwinb9fe5d52009-11-13 19:52:48 +0000791
792 // If MI is not on the critical path, then we don't rename
793 // registers in the CriticalPathSet.
Craig Topperc0196b12014-04-14 00:51:57 +0000794 BitVector *ExcludeRegs = nullptr;
David Goodwinb9fe5d52009-11-13 19:52:48 +0000795 if (MI == CriticalPathMI) {
796 CriticalPathSU = CriticalPathStep(CriticalPathSU);
Craig Topperc0196b12014-04-14 00:51:57 +0000797 CriticalPathMI = (CriticalPathSU) ? CriticalPathSU->getInstr() : nullptr;
Hal Finkel6f1ff8e2013-09-12 04:22:31 +0000798 } else if (CriticalPathSet.any()) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000799 ExcludeRegs = &CriticalPathSet;
800 }
801
David Goodwinde11f362009-10-26 19:32:42 +0000802 // Ignore KILL instructions (they form a group in ScanInstruction
803 // but don't cause any anti-dependence breaking themselves)
Chris Lattnerb06015a2010-02-09 19:54:29 +0000804 if (!MI->isKill()) {
David Goodwinde11f362009-10-26 19:32:42 +0000805 // Attempt to break each anti-dependency...
806 for (unsigned i = 0, e = Edges.size(); i != e; ++i) {
Dan Gohman35bc4d42010-04-19 23:11:58 +0000807 const SDep *Edge = Edges[i];
David Goodwinde11f362009-10-26 19:32:42 +0000808 SUnit *NextSU = Edge->getSUnit();
Jim Grosbacheb431da2010-01-06 16:48:02 +0000809
David Goodwinda83f7d2009-11-12 19:08:21 +0000810 if ((Edge->getKind() != SDep::Anti) &&
811 (Edge->getKind() != SDep::Output)) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000812
David Goodwinde11f362009-10-26 19:32:42 +0000813 unsigned AntiDepReg = Edge->getReg();
David Greene75a2efb2009-12-24 00:14:25 +0000814 DEBUG(dbgs() << "\tAntidep reg: " << TRI->getName(AntiDepReg));
David Goodwinde11f362009-10-26 19:32:42 +0000815 assert(AntiDepReg != 0 && "Anti-dependence on reg0?");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000816
Jakob Stoklund Olesenf67bf3e2012-10-15 22:41:03 +0000817 if (!MRI.isAllocatable(AntiDepReg)) {
David Goodwinde11f362009-10-26 19:32:42 +0000818 // Don't break anti-dependencies on non-allocatable registers.
David Greene75a2efb2009-12-24 00:14:25 +0000819 DEBUG(dbgs() << " (non-allocatable)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000820 continue;
Craig Topperc0196b12014-04-14 00:51:57 +0000821 } else if (ExcludeRegs && ExcludeRegs->test(AntiDepReg)) {
David Goodwinb9fe5d52009-11-13 19:52:48 +0000822 // Don't break anti-dependencies for critical path registers
823 // if not on the critical path
David Greene75a2efb2009-12-24 00:14:25 +0000824 DEBUG(dbgs() << " (not critical-path)\n");
David Goodwinb9fe5d52009-11-13 19:52:48 +0000825 continue;
David Goodwinde11f362009-10-26 19:32:42 +0000826 } else if (PassthruRegs.count(AntiDepReg) != 0) {
827 // If the anti-dep register liveness "passes-thru", then
828 // don't try to change it. It will be changed along with
829 // the use if required to break an earlier antidep.
David Greene75a2efb2009-12-24 00:14:25 +0000830 DEBUG(dbgs() << " (passthru)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000831 continue;
832 } else {
833 // No anti-dep breaking for implicit deps
834 MachineOperand *AntiDepOp = MI->findRegisterDefOperand(AntiDepReg);
Craig Topperc0196b12014-04-14 00:51:57 +0000835 assert(AntiDepOp && "Can't find index for defined register operand");
836 if (!AntiDepOp || AntiDepOp->isImplicit()) {
David Greene75a2efb2009-12-24 00:14:25 +0000837 DEBUG(dbgs() << " (implicit)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000838 continue;
839 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000840
David Goodwinde11f362009-10-26 19:32:42 +0000841 // If the SUnit has other dependencies on the SUnit that
842 // it anti-depends on, don't bother breaking the
843 // anti-dependency since those edges would prevent such
844 // units from being scheduled past each other
845 // regardless.
David Goodwin80a03cc2009-11-20 19:32:48 +0000846 //
847 // Also, if there are dependencies on other SUnits with the
848 // same register as the anti-dependency, don't attempt to
849 // break it.
Dan Gohman35bc4d42010-04-19 23:11:58 +0000850 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
David Goodwinde11f362009-10-26 19:32:42 +0000851 PE = PathSU->Preds.end(); P != PE; ++P) {
David Goodwin80a03cc2009-11-20 19:32:48 +0000852 if (P->getSUnit() == NextSU ?
853 (P->getKind() != SDep::Anti || P->getReg() != AntiDepReg) :
854 (P->getKind() == SDep::Data && P->getReg() == AntiDepReg)) {
855 AntiDepReg = 0;
856 break;
857 }
858 }
Dan Gohman35bc4d42010-04-19 23:11:58 +0000859 for (SUnit::const_pred_iterator P = PathSU->Preds.begin(),
David Goodwin80a03cc2009-11-20 19:32:48 +0000860 PE = PathSU->Preds.end(); P != PE; ++P) {
861 if ((P->getSUnit() == NextSU) && (P->getKind() != SDep::Anti) &&
862 (P->getKind() != SDep::Output)) {
David Greene75a2efb2009-12-24 00:14:25 +0000863 DEBUG(dbgs() << " (real dependency)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000864 AntiDepReg = 0;
865 break;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000866 } else if ((P->getSUnit() != NextSU) &&
867 (P->getKind() == SDep::Data) &&
David Goodwin80a03cc2009-11-20 19:32:48 +0000868 (P->getReg() == AntiDepReg)) {
David Greene75a2efb2009-12-24 00:14:25 +0000869 DEBUG(dbgs() << " (other dependency)\n");
David Goodwin80a03cc2009-11-20 19:32:48 +0000870 AntiDepReg = 0;
871 break;
David Goodwinde11f362009-10-26 19:32:42 +0000872 }
873 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000874
David Goodwinde11f362009-10-26 19:32:42 +0000875 if (AntiDepReg == 0) continue;
876 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000877
David Goodwinde11f362009-10-26 19:32:42 +0000878 assert(AntiDepReg != 0);
879 if (AntiDepReg == 0) continue;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000880
David Goodwinde11f362009-10-26 19:32:42 +0000881 // Determine AntiDepReg's register group.
David Goodwine056d102009-10-26 22:31:16 +0000882 const unsigned GroupIndex = State->GetGroup(AntiDepReg);
David Goodwinde11f362009-10-26 19:32:42 +0000883 if (GroupIndex == 0) {
David Greene75a2efb2009-12-24 00:14:25 +0000884 DEBUG(dbgs() << " (zero group)\n");
David Goodwinde11f362009-10-26 19:32:42 +0000885 continue;
886 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000887
David Greene75a2efb2009-12-24 00:14:25 +0000888 DEBUG(dbgs() << '\n');
Jim Grosbacheb431da2010-01-06 16:48:02 +0000889
David Goodwinde11f362009-10-26 19:32:42 +0000890 // Look for a suitable register to use to break the anti-dependence.
891 std::map<unsigned, unsigned> RenameMap;
David Goodwin7d8878a2009-11-05 01:19:35 +0000892 if (FindSuitableFreeRegisters(GroupIndex, RenameOrder, RenameMap)) {
David Greene75a2efb2009-12-24 00:14:25 +0000893 DEBUG(dbgs() << "\tBreaking anti-dependence edge on "
David Goodwinde11f362009-10-26 19:32:42 +0000894 << TRI->getName(AntiDepReg) << ":");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000895
David Goodwinde11f362009-10-26 19:32:42 +0000896 // Handle each group register...
897 for (std::map<unsigned, unsigned>::iterator
898 S = RenameMap.begin(), E = RenameMap.end(); S != E; ++S) {
899 unsigned CurrReg = S->first;
900 unsigned NewReg = S->second;
Jim Grosbacheb431da2010-01-06 16:48:02 +0000901
902 DEBUG(dbgs() << " " << TRI->getName(CurrReg) << "->" <<
903 TRI->getName(NewReg) << "(" <<
David Goodwinde11f362009-10-26 19:32:42 +0000904 RegRefs.count(CurrReg) << " refs)");
Jim Grosbacheb431da2010-01-06 16:48:02 +0000905
David Goodwinde11f362009-10-26 19:32:42 +0000906 // Update the references to the old register CurrReg to
907 // refer to the new register NewReg.
Jim Grosbacheb431da2010-01-06 16:48:02 +0000908 std::pair<std::multimap<unsigned,
909 AggressiveAntiDepState::RegisterReference>::iterator,
David Goodwine056d102009-10-26 22:31:16 +0000910 std::multimap<unsigned,
Jim Grosbacheb431da2010-01-06 16:48:02 +0000911 AggressiveAntiDepState::RegisterReference>::iterator>
David Goodwinde11f362009-10-26 19:32:42 +0000912 Range = RegRefs.equal_range(CurrReg);
Jim Grosbacheb431da2010-01-06 16:48:02 +0000913 for (std::multimap<unsigned,
914 AggressiveAntiDepState::RegisterReference>::iterator
David Goodwinde11f362009-10-26 19:32:42 +0000915 Q = Range.first, QE = Range.second; Q != QE; ++Q) {
916 Q->second.Operand->setReg(NewReg);
Jim Grosbach12ac8f02010-06-01 23:48:44 +0000917 // If the SU for the instruction being updated has debug
918 // information related to the anti-dependency register, make
919 // sure to update that as well.
920 const SUnit *SU = MISUnitMap[Q->second.Operand->getParent()];
Jim Grosbach84854832010-06-02 15:29:36 +0000921 if (!SU) continue;
Devang Patelf02a3762011-06-02 21:26:52 +0000922 for (DbgValueVector::iterator DVI = DbgValues.begin(),
923 DVE = DbgValues.end(); DVI != DVE; ++DVI)
924 if (DVI->second == Q->second.Operand->getParent())
925 UpdateDbgValue(DVI->first, AntiDepReg, NewReg);
David Goodwinde11f362009-10-26 19:32:42 +0000926 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000927
David Goodwinde11f362009-10-26 19:32:42 +0000928 // We just went back in time and modified history; the
929 // liveness information for CurrReg is now inconsistent. Set
930 // the state as if it were dead.
David Goodwine056d102009-10-26 22:31:16 +0000931 State->UnionGroups(NewReg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000932 RegRefs.erase(NewReg);
933 DefIndices[NewReg] = DefIndices[CurrReg];
934 KillIndices[NewReg] = KillIndices[CurrReg];
Jim Grosbacheb431da2010-01-06 16:48:02 +0000935
David Goodwine056d102009-10-26 22:31:16 +0000936 State->UnionGroups(CurrReg, 0);
David Goodwinde11f362009-10-26 19:32:42 +0000937 RegRefs.erase(CurrReg);
938 DefIndices[CurrReg] = KillIndices[CurrReg];
939 KillIndices[CurrReg] = ~0u;
940 assert(((KillIndices[CurrReg] == ~0u) !=
941 (DefIndices[CurrReg] == ~0u)) &&
942 "Kill and Def maps aren't consistent for AntiDepReg!");
943 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000944
David Goodwinde11f362009-10-26 19:32:42 +0000945 ++Broken;
David Greene75a2efb2009-12-24 00:14:25 +0000946 DEBUG(dbgs() << '\n');
David Goodwinde11f362009-10-26 19:32:42 +0000947 }
948 }
949 }
950
951 ScanInstruction(MI, Count);
952 }
Jim Grosbacheb431da2010-01-06 16:48:02 +0000953
David Goodwinde11f362009-10-26 19:32:42 +0000954 return Broken;
955}