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gerrit-public.fairphone.software / toolchain / llvm-project / 8a937e00d81d2d44b3fa81511052862b410c9599 / . / llvm / lib / Target / AArch64 / AArch64LoadStoreOptimizer.cpp
blob: e52ba23b7ab610b7530e6f55ef59c69a6b6a49f6 [file] [log] [blame]
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]1//===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a pass that performs load / store related peephole
11// optimizations. This pass should be run after register allocation.
12//
13//===----------------------------------------------------------------------===//
14
15#include "AArch64InstrInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]16#include "AArch64Subtarget.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]17#include "MCTargetDesc/AArch64AddressingModes.h"
18#include "llvm/ADT/BitVector.h"
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]19#include "llvm/ADT/SmallVector.h"
Benjamin Kramer1f8930e2014-07-25 11:42:14 +0000[diff] [blame]20#include "llvm/ADT/Statistic.h"
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]21#include "llvm/ADT/StringRef.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]22#include "llvm/ADT/iterator_range.h"
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]23#include "llvm/Analysis/AliasAnalysis.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]24#include "llvm/CodeGen/MachineBasicBlock.h"
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFunction.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineFunctionPass.h"
27#include "llvm/CodeGen/MachineInstr.h"
28#include "llvm/CodeGen/MachineInstrBuilder.h"
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]29#include "llvm/CodeGen/MachineOperand.h"
David Blaikieb3bde2e2017-11-17 01:07:10 +0000[diff] [blame]30#include "llvm/CodeGen/TargetRegisterInfo.h"
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]31#include "llvm/IR/DebugLoc.h"
32#include "llvm/MC/MCRegisterInfo.h"
33#include "llvm/Pass.h"
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
35#include "llvm/Support/Debug.h"
36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]38#include <cassert>
39#include <cstdint>
40#include <iterator>
41#include <limits>
42
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]43using namespace llvm;
44
45#define DEBUG_TYPE "aarch64-ldst-opt"
46
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]47STATISTIC(NumPairCreated, "Number of load/store pair instructions generated");
48STATISTIC(NumPostFolded, "Number of post-index updates folded");
49STATISTIC(NumPreFolded, "Number of pre-index updates folded");
50STATISTIC(NumUnscaledPairCreated,
51 "Number of load/store from unscaled generated");
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]52STATISTIC(NumZeroStoresPromoted, "Number of narrow zero stores promoted");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]53STATISTIC(NumLoadsFromStoresPromoted, "Number of loads from stores promoted");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]54
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]55// The LdStLimit limits how far we search for load/store pairs.
56static cl::opt<unsigned> LdStLimit("aarch64-load-store-scan-limit",
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]57 cl::init(20), cl::Hidden);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]58
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]59// The UpdateLimit limits how far we search for update instructions when we form
60// pre-/post-index instructions.
61static cl::opt<unsigned> UpdateLimit("aarch64-update-scan-limit", cl::init(100),
62 cl::Hidden);
63
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]64#define AARCH64_LOAD_STORE_OPT_NAME "AArch64 load / store optimization pass"
65
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]66namespace {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]67
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]68using LdStPairFlags = struct LdStPairFlags {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]69 // If a matching instruction is found, MergeForward is set to true if the
70 // merge is to remove the first instruction and replace the second with
71 // a pair-wise insn, and false if the reverse is true.
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]72 bool MergeForward = false;
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]73
74 // SExtIdx gives the index of the result of the load pair that must be
75 // extended. The value of SExtIdx assumes that the paired load produces the
76 // value in this order: (I, returned iterator), i.e., -1 means no value has
77 // to be extended, 0 means I, and 1 means the returned iterator.
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]78 int SExtIdx = -1;
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]79
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]80 LdStPairFlags() = default;
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]81
82 void setMergeForward(bool V = true) { MergeForward = V; }
83 bool getMergeForward() const { return MergeForward; }
84
85 void setSExtIdx(int V) { SExtIdx = V; }
86 int getSExtIdx() const { return SExtIdx; }
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]87};
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]88
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]89struct AArch64LoadStoreOpt : public MachineFunctionPass {
90 static char ID;
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]91
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]92 AArch64LoadStoreOpt() : MachineFunctionPass(ID) {
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]93 initializeAArch64LoadStoreOptPass(*PassRegistry::getPassRegistry());
94 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]95
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]96 AliasAnalysis *AA;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]97 const AArch64InstrInfo *TII;
98 const TargetRegisterInfo *TRI;
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]99 const AArch64Subtarget *Subtarget;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]100
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]101 // Track which registers have been modified and used.
102 BitVector ModifiedRegs, UsedRegs;
103
Eugene Zelenko96d933d2017-07-25 23:51:02 +0000[diff] [blame]104 void getAnalysisUsage(AnalysisUsage &AU) const override {
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]105 AU.addRequired<AAResultsWrapperPass>();
106 MachineFunctionPass::getAnalysisUsage(AU);
107 }
108
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]109 // Scan the instructions looking for a load/store that can be combined
110 // with the current instruction into a load/store pair.
111 // Return the matching instruction if one is found, else MBB->end().
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]112 MachineBasicBlock::iterator findMatchingInsn(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]113 LdStPairFlags &Flags,
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]114 unsigned Limit,
115 bool FindNarrowMerge);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]116
117 // Scan the instructions looking for a store that writes to the address from
118 // which the current load instruction reads. Return true if one is found.
119 bool findMatchingStore(MachineBasicBlock::iterator I, unsigned Limit,
120 MachineBasicBlock::iterator &StoreI);
121
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]122 // Merge the two instructions indicated into a wider narrow store instruction.
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]123 MachineBasicBlock::iterator
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]124 mergeNarrowZeroStores(MachineBasicBlock::iterator I,
125 MachineBasicBlock::iterator MergeMI,
126 const LdStPairFlags &Flags);
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]127
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]128 // Merge the two instructions indicated into a single pair-wise instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]129 MachineBasicBlock::iterator
130 mergePairedInsns(MachineBasicBlock::iterator I,
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]131 MachineBasicBlock::iterator Paired,
Chad Rosierfe5399f2015-07-21 17:47:56 +0000[diff] [blame]132 const LdStPairFlags &Flags);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]133
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]134 // Promote the load that reads directly from the address stored to.
135 MachineBasicBlock::iterator
136 promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
137 MachineBasicBlock::iterator StoreI);
138
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]139 // Scan the instruction list to find a base register update that can
140 // be combined with the current instruction (a load or store) using
141 // pre or post indexed addressing with writeback. Scan forwards.
142 MachineBasicBlock::iterator
Chad Rosier234bf6f2016-01-18 21:56:40 +0000[diff] [blame]143 findMatchingUpdateInsnForward(MachineBasicBlock::iterator I,
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]144 int UnscaledOffset, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]145
146 // Scan the instruction list to find a base register update that can
147 // be combined with the current instruction (a load or store) using
148 // pre or post indexed addressing with writeback. Scan backwards.
149 MachineBasicBlock::iterator
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]150 findMatchingUpdateInsnBackward(MachineBasicBlock::iterator I, unsigned Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]151
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]152 // Find an instruction that updates the base register of the ld/st
153 // instruction.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]154 bool isMatchingUpdateInsn(MachineInstr &MemMI, MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]155 unsigned BaseReg, int Offset);
156
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]157 // Merge a pre- or post-index base register update into a ld/st instruction.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]158 MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]159 mergeUpdateInsn(MachineBasicBlock::iterator I,
160 MachineBasicBlock::iterator Update, bool IsPreIdx);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]161
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]162 // Find and merge zero store instructions.
163 bool tryToMergeZeroStInst(MachineBasicBlock::iterator &MBBI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]164
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]165 // Find and pair ldr/str instructions.
166 bool tryToPairLdStInst(MachineBasicBlock::iterator &MBBI);
167
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]168 // Find and promote load instructions which read directly from store.
169 bool tryToPromoteLoadFromStore(MachineBasicBlock::iterator &MBBI);
170
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]171 // Find and merge a base register updates before or after a ld/st instruction.
172 bool tryToMergeLdStUpdate(MachineBasicBlock::iterator &MBBI);
173
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]174 bool optimizeBlock(MachineBasicBlock &MBB, bool EnableNarrowZeroStOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]175
176 bool runOnMachineFunction(MachineFunction &Fn) override;
177
Derek Schuff1dbf7a52016-04-04 17:09:25 +0000[diff] [blame]178 MachineFunctionProperties getRequiredProperties() const override {
179 return MachineFunctionProperties().set(
Matthias Braun1eb47362016-08-25 01:27:13 +0000[diff] [blame]180 MachineFunctionProperties::Property::NoVRegs);
Derek Schuff1dbf7a52016-04-04 17:09:25 +0000[diff] [blame]181 }
182
Mehdi Amini117296c2016-10-01 02:56:57 +0000[diff] [blame]183 StringRef getPassName() const override { return AARCH64_LOAD_STORE_OPT_NAME; }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]184};
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]185
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]186char AArch64LoadStoreOpt::ID = 0;
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]187
188} // end anonymous namespace
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]189
Chad Rosier96530b32015-08-05 13:44:51 +0000[diff] [blame]190INITIALIZE_PASS(AArch64LoadStoreOpt, "aarch64-ldst-opt",
191 AARCH64_LOAD_STORE_OPT_NAME, false, false)
192
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]193static bool isNarrowStore(unsigned Opc) {
194 switch (Opc) {
195 default:
196 return false;
197 case AArch64::STRBBui:
198 case AArch64::STURBBi:
199 case AArch64::STRHHui:
200 case AArch64::STURHHi:
201 return true;
202 }
203}
204
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]205// Scaling factor for unscaled load or store.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]206static int getMemScale(MachineInstr &MI) {
207 switch (MI.getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]208 default:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]209 llvm_unreachable("Opcode has unknown scale!");
210 case AArch64::LDRBBui:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]211 case AArch64::LDURBBi:
212 case AArch64::LDRSBWui:
213 case AArch64::LDURSBWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]214 case AArch64::STRBBui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]215 case AArch64::STURBBi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]216 return 1;
217 case AArch64::LDRHHui:
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]218 case AArch64::LDURHHi:
Jun Bum Lim4c35cca2015-11-19 17:21:41 +0000[diff] [blame]219 case AArch64::LDRSHWui:
220 case AArch64::LDURSHWi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]221 case AArch64::STRHHui:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]222 case AArch64::STURHHi:
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]223 return 2;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]224 case AArch64::LDRSui:
225 case AArch64::LDURSi:
226 case AArch64::LDRSWui:
227 case AArch64::LDURSWi:
228 case AArch64::LDRWui:
229 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]230 case AArch64::STRSui:
231 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]232 case AArch64::STRWui:
233 case AArch64::STURWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]234 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]235 case AArch64::LDPSWi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]236 case AArch64::LDPWi:
237 case AArch64::STPSi:
238 case AArch64::STPWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]239 return 4;
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]240 case AArch64::LDRDui:
241 case AArch64::LDURDi:
242 case AArch64::LDRXui:
243 case AArch64::LDURXi:
244 case AArch64::STRDui:
245 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]246 case AArch64::STRXui:
247 case AArch64::STURXi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]248 case AArch64::LDPDi:
249 case AArch64::LDPXi:
250 case AArch64::STPDi:
251 case AArch64::STPXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]252 return 8;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]253 case AArch64::LDRQui:
254 case AArch64::LDURQi:
Chad Rosiera4d32172015-09-29 14:57:10 +0000[diff] [blame]255 case AArch64::STRQui:
256 case AArch64::STURQi:
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]257 case AArch64::LDPQi:
258 case AArch64::STPQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]259 return 16;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]260 }
261}
262
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]263static unsigned getMatchingNonSExtOpcode(unsigned Opc,
264 bool *IsValidLdStrOpc = nullptr) {
265 if (IsValidLdStrOpc)
266 *IsValidLdStrOpc = true;
267 switch (Opc) {
268 default:
269 if (IsValidLdStrOpc)
270 *IsValidLdStrOpc = false;
Eugene Zelenko11f69072017-01-25 00:29:26 +0000[diff] [blame]271 return std::numeric_limits<unsigned>::max();
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]272 case AArch64::STRDui:
273 case AArch64::STURDi:
274 case AArch64::STRQui:
275 case AArch64::STURQi:
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]276 case AArch64::STRBBui:
277 case AArch64::STURBBi:
278 case AArch64::STRHHui:
279 case AArch64::STURHHi:
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]280 case AArch64::STRWui:
281 case AArch64::STURWi:
282 case AArch64::STRXui:
283 case AArch64::STURXi:
284 case AArch64::LDRDui:
285 case AArch64::LDURDi:
286 case AArch64::LDRQui:
287 case AArch64::LDURQi:
288 case AArch64::LDRWui:
289 case AArch64::LDURWi:
290 case AArch64::LDRXui:
291 case AArch64::LDURXi:
292 case AArch64::STRSui:
293 case AArch64::STURSi:
294 case AArch64::LDRSui:
295 case AArch64::LDURSi:
296 return Opc;
297 case AArch64::LDRSWui:
298 return AArch64::LDRWui;
299 case AArch64::LDURSWi:
300 return AArch64::LDURWi;
301 }
302}
303
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]304static unsigned getMatchingWideOpcode(unsigned Opc) {
305 switch (Opc) {
306 default:
307 llvm_unreachable("Opcode has no wide equivalent!");
308 case AArch64::STRBBui:
309 return AArch64::STRHHui;
310 case AArch64::STRHHui:
311 return AArch64::STRWui;
312 case AArch64::STURBBi:
313 return AArch64::STURHHi;
314 case AArch64::STURHHi:
315 return AArch64::STURWi;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]316 case AArch64::STURWi:
317 return AArch64::STURXi;
318 case AArch64::STRWui:
319 return AArch64::STRXui;
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]320 }
321}
322
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]323static unsigned getMatchingPairOpcode(unsigned Opc) {
324 switch (Opc) {
325 default:
326 llvm_unreachable("Opcode has no pairwise equivalent!");
327 case AArch64::STRSui:
328 case AArch64::STURSi:
329 return AArch64::STPSi;
330 case AArch64::STRDui:
331 case AArch64::STURDi:
332 return AArch64::STPDi;
333 case AArch64::STRQui:
334 case AArch64::STURQi:
335 return AArch64::STPQi;
336 case AArch64::STRWui:
337 case AArch64::STURWi:
338 return AArch64::STPWi;
339 case AArch64::STRXui:
340 case AArch64::STURXi:
341 return AArch64::STPXi;
342 case AArch64::LDRSui:
343 case AArch64::LDURSi:
344 return AArch64::LDPSi;
345 case AArch64::LDRDui:
346 case AArch64::LDURDi:
347 return AArch64::LDPDi;
348 case AArch64::LDRQui:
349 case AArch64::LDURQi:
350 return AArch64::LDPQi;
351 case AArch64::LDRWui:
352 case AArch64::LDURWi:
353 return AArch64::LDPWi;
354 case AArch64::LDRXui:
355 case AArch64::LDURXi:
356 return AArch64::LDPXi;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]357 case AArch64::LDRSWui:
358 case AArch64::LDURSWi:
359 return AArch64::LDPSWi;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]360 }
361}
362
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]363static unsigned isMatchingStore(MachineInstr &LoadInst,
364 MachineInstr &StoreInst) {
365 unsigned LdOpc = LoadInst.getOpcode();
366 unsigned StOpc = StoreInst.getOpcode();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]367 switch (LdOpc) {
368 default:
369 llvm_unreachable("Unsupported load instruction!");
370 case AArch64::LDRBBui:
371 return StOpc == AArch64::STRBBui || StOpc == AArch64::STRHHui ||
372 StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
373 case AArch64::LDURBBi:
374 return StOpc == AArch64::STURBBi || StOpc == AArch64::STURHHi ||
375 StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
376 case AArch64::LDRHHui:
377 return StOpc == AArch64::STRHHui || StOpc == AArch64::STRWui ||
378 StOpc == AArch64::STRXui;
379 case AArch64::LDURHHi:
380 return StOpc == AArch64::STURHHi || StOpc == AArch64::STURWi ||
381 StOpc == AArch64::STURXi;
382 case AArch64::LDRWui:
383 return StOpc == AArch64::STRWui || StOpc == AArch64::STRXui;
384 case AArch64::LDURWi:
385 return StOpc == AArch64::STURWi || StOpc == AArch64::STURXi;
386 case AArch64::LDRXui:
387 return StOpc == AArch64::STRXui;
388 case AArch64::LDURXi:
389 return StOpc == AArch64::STURXi;
390 }
391}
392
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]393static unsigned getPreIndexedOpcode(unsigned Opc) {
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]394 // FIXME: We don't currently support creating pre-indexed loads/stores when
395 // the load or store is the unscaled version. If we decide to perform such an
396 // optimization in the future the cases for the unscaled loads/stores will
397 // need to be added here.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]398 switch (Opc) {
399 default:
400 llvm_unreachable("Opcode has no pre-indexed equivalent!");
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]401 case AArch64::STRSui:
402 return AArch64::STRSpre;
403 case AArch64::STRDui:
404 return AArch64::STRDpre;
405 case AArch64::STRQui:
406 return AArch64::STRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]407 case AArch64::STRBBui:
408 return AArch64::STRBBpre;
409 case AArch64::STRHHui:
410 return AArch64::STRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]411 case AArch64::STRWui:
412 return AArch64::STRWpre;
413 case AArch64::STRXui:
414 return AArch64::STRXpre;
415 case AArch64::LDRSui:
416 return AArch64::LDRSpre;
417 case AArch64::LDRDui:
418 return AArch64::LDRDpre;
419 case AArch64::LDRQui:
420 return AArch64::LDRQpre;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]421 case AArch64::LDRBBui:
422 return AArch64::LDRBBpre;
423 case AArch64::LDRHHui:
424 return AArch64::LDRHHpre;
Tilmann Scheller5d8d72c2014-06-04 12:40:35 +0000[diff] [blame]425 case AArch64::LDRWui:
426 return AArch64::LDRWpre;
427 case AArch64::LDRXui:
428 return AArch64::LDRXpre;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]429 case AArch64::LDRSWui:
430 return AArch64::LDRSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]431 case AArch64::LDPSi:
432 return AArch64::LDPSpre;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]433 case AArch64::LDPSWi:
434 return AArch64::LDPSWpre;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]435 case AArch64::LDPDi:
436 return AArch64::LDPDpre;
437 case AArch64::LDPQi:
438 return AArch64::LDPQpre;
439 case AArch64::LDPWi:
440 return AArch64::LDPWpre;
441 case AArch64::LDPXi:
442 return AArch64::LDPXpre;
443 case AArch64::STPSi:
444 return AArch64::STPSpre;
445 case AArch64::STPDi:
446 return AArch64::STPDpre;
447 case AArch64::STPQi:
448 return AArch64::STPQpre;
449 case AArch64::STPWi:
450 return AArch64::STPWpre;
451 case AArch64::STPXi:
452 return AArch64::STPXpre;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]453 }
454}
455
456static unsigned getPostIndexedOpcode(unsigned Opc) {
457 switch (Opc) {
458 default:
459 llvm_unreachable("Opcode has no post-indexed wise equivalent!");
460 case AArch64::STRSui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]461 case AArch64::STURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]462 return AArch64::STRSpost;
463 case AArch64::STRDui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]464 case AArch64::STURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]465 return AArch64::STRDpost;
466 case AArch64::STRQui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]467 case AArch64::STURQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]468 return AArch64::STRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]469 case AArch64::STRBBui:
470 return AArch64::STRBBpost;
471 case AArch64::STRHHui:
472 return AArch64::STRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]473 case AArch64::STRWui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]474 case AArch64::STURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]475 return AArch64::STRWpost;
476 case AArch64::STRXui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]477 case AArch64::STURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]478 return AArch64::STRXpost;
479 case AArch64::LDRSui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]480 case AArch64::LDURSi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]481 return AArch64::LDRSpost;
482 case AArch64::LDRDui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]483 case AArch64::LDURDi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]484 return AArch64::LDRDpost;
485 case AArch64::LDRQui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]486 case AArch64::LDURQi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]487 return AArch64::LDRQpost;
Chad Rosierdabe2532015-09-29 18:26:15 +0000[diff] [blame]488 case AArch64::LDRBBui:
489 return AArch64::LDRBBpost;
490 case AArch64::LDRHHui:
491 return AArch64::LDRHHpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]492 case AArch64::LDRWui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]493 case AArch64::LDURWi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]494 return AArch64::LDRWpost;
495 case AArch64::LDRXui:
Chad Rosier14fc82a2017-08-04 16:44:06 +0000[diff] [blame]496 case AArch64::LDURXi:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]497 return AArch64::LDRXpost;
Quentin Colombet29f55332015-01-24 01:25:54 +0000[diff] [blame]498 case AArch64::LDRSWui:
499 return AArch64::LDRSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]500 case AArch64::LDPSi:
501 return AArch64::LDPSpost;
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]502 case AArch64::LDPSWi:
503 return AArch64::LDPSWpost;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]504 case AArch64::LDPDi:
505 return AArch64::LDPDpost;
506 case AArch64::LDPQi:
507 return AArch64::LDPQpost;
508 case AArch64::LDPWi:
509 return AArch64::LDPWpost;
510 case AArch64::LDPXi:
511 return AArch64::LDPXpost;
512 case AArch64::STPSi:
513 return AArch64::STPSpost;
514 case AArch64::STPDi:
515 return AArch64::STPDpost;
516 case AArch64::STPQi:
517 return AArch64::STPQpost;
518 case AArch64::STPWi:
519 return AArch64::STPWpost;
520 case AArch64::STPXi:
521 return AArch64::STPXpost;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]522 }
523}
524
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]525static bool isPairedLdSt(const MachineInstr &MI) {
526 switch (MI.getOpcode()) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]527 default:
528 return false;
529 case AArch64::LDPSi:
Chad Rosier43150122015-09-29 20:39:55 +0000[diff] [blame]530 case AArch64::LDPSWi:
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]531 case AArch64::LDPDi:
532 case AArch64::LDPQi:
533 case AArch64::LDPWi:
534 case AArch64::LDPXi:
535 case AArch64::STPSi:
536 case AArch64::STPDi:
537 case AArch64::STPQi:
538 case AArch64::STPWi:
539 case AArch64::STPXi:
540 return true;
541 }
542}
543
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]544static const MachineOperand &getLdStRegOp(const MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]545 unsigned PairedRegOp = 0) {
546 assert(PairedRegOp < 2 && "Unexpected register operand idx.");
547 unsigned Idx = isPairedLdSt(MI) ? PairedRegOp : 0;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]548 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]549}
550
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]551static const MachineOperand &getLdStBaseOp(const MachineInstr &MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]552 unsigned Idx = isPairedLdSt(MI) ? 2 : 1;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]553 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]554}
555
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]556static const MachineOperand &getLdStOffsetOp(const MachineInstr &MI) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]557 unsigned Idx = isPairedLdSt(MI) ? 3 : 2;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]558 return MI.getOperand(Idx);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]559}
560
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]561static bool isLdOffsetInRangeOfSt(MachineInstr &LoadInst,
562 MachineInstr &StoreInst,
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]563 const AArch64InstrInfo *TII) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]564 assert(isMatchingStore(LoadInst, StoreInst) && "Expect only matched ld/st.");
565 int LoadSize = getMemScale(LoadInst);
566 int StoreSize = getMemScale(StoreInst);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]567 int UnscaledStOffset = TII->isUnscaledLdSt(StoreInst)
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]568 ? getLdStOffsetOp(StoreInst).getImm()
569 : getLdStOffsetOp(StoreInst).getImm() * StoreSize;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]570 int UnscaledLdOffset = TII->isUnscaledLdSt(LoadInst)
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]571 ? getLdStOffsetOp(LoadInst).getImm()
572 : getLdStOffsetOp(LoadInst).getImm() * LoadSize;
573 return (UnscaledStOffset <= UnscaledLdOffset) &&
574 (UnscaledLdOffset + LoadSize <= (UnscaledStOffset + StoreSize));
575}
576
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]577static bool isPromotableZeroStoreInst(MachineInstr &MI) {
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]578 unsigned Opc = MI.getOpcode();
579 return (Opc == AArch64::STRWui || Opc == AArch64::STURWi ||
580 isNarrowStore(Opc)) &&
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]581 getLdStRegOp(MI).getReg() == AArch64::WZR;
582}
583
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]584static bool isPromotableLoadFromStore(MachineInstr &MI) {
585 switch (MI.getOpcode()) {
586 default:
587 return false;
588 // Scaled instructions.
589 case AArch64::LDRBBui:
590 case AArch64::LDRHHui:
591 case AArch64::LDRWui:
592 case AArch64::LDRXui:
593 // Unscaled instructions.
594 case AArch64::LDURBBi:
595 case AArch64::LDURHHi:
596 case AArch64::LDURWi:
597 case AArch64::LDURXi:
598 return true;
599 }
600}
601
602static bool isMergeableLdStUpdate(MachineInstr &MI) {
603 unsigned Opc = MI.getOpcode();
604 switch (Opc) {
605 default:
606 return false;
607 // Scaled instructions.
608 case AArch64::STRSui:
609 case AArch64::STRDui:
610 case AArch64::STRQui:
611 case AArch64::STRXui:
612 case AArch64::STRWui:
613 case AArch64::STRHHui:
614 case AArch64::STRBBui:
615 case AArch64::LDRSui:
616 case AArch64::LDRDui:
617 case AArch64::LDRQui:
618 case AArch64::LDRXui:
619 case AArch64::LDRWui:
620 case AArch64::LDRHHui:
621 case AArch64::LDRBBui:
622 // Unscaled instructions.
623 case AArch64::STURSi:
624 case AArch64::STURDi:
625 case AArch64::STURQi:
626 case AArch64::STURWi:
627 case AArch64::STURXi:
628 case AArch64::LDURSi:
629 case AArch64::LDURDi:
630 case AArch64::LDURQi:
631 case AArch64::LDURWi:
632 case AArch64::LDURXi:
633 // Paired instructions.
634 case AArch64::LDPSi:
635 case AArch64::LDPSWi:
636 case AArch64::LDPDi:
637 case AArch64::LDPQi:
638 case AArch64::LDPWi:
639 case AArch64::LDPXi:
640 case AArch64::STPSi:
641 case AArch64::STPDi:
642 case AArch64::STPQi:
643 case AArch64::STPWi:
644 case AArch64::STPXi:
645 // Make sure this is a reg+imm (as opposed to an address reloc).
646 if (!getLdStOffsetOp(MI).isImm())
647 return false;
648
649 return true;
650 }
651}
652
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]653MachineBasicBlock::iterator
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]654AArch64LoadStoreOpt::mergeNarrowZeroStores(MachineBasicBlock::iterator I,
655 MachineBasicBlock::iterator MergeMI,
656 const LdStPairFlags &Flags) {
657 assert(isPromotableZeroStoreInst(*I) && isPromotableZeroStoreInst(*MergeMI) &&
658 "Expected promotable zero stores.");
659
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]660 MachineBasicBlock::iterator NextI = I;
661 ++NextI;
662 // If NextI is the second of the two instructions to be merged, we need
663 // to skip one further. Either way we merge will invalidate the iterator,
664 // and we don't need to scan the new instruction, as it's a pairwise
665 // instruction, which we're not considering for further action anyway.
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]666 if (NextI == MergeMI)
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]667 ++NextI;
668
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]669 unsigned Opc = I->getOpcode();
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]670 bool IsScaled = !TII->isUnscaledLdSt(Opc);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]671 int OffsetStride = IsScaled ? 1 : getMemScale(*I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]672
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]673 bool MergeForward = Flags.getMergeForward();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]674 // Insert our new paired instruction after whichever of the paired
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]675 // instructions MergeForward indicates.
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]676 MachineBasicBlock::iterator InsertionPoint = MergeForward ? MergeMI : I;
Tilmann Scheller4aad3bd2014-06-04 12:36:28 +0000[diff] [blame]677 // Also based on MergeForward is from where we copy the base register operand
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]678 // so we get the flags compatible with the input code.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]679 const MachineOperand &BaseRegOp =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]680 MergeForward ? getLdStBaseOp(*MergeMI) : getLdStBaseOp(*I);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]681
682 // Which register is Rt and which is Rt2 depends on the offset order.
Davide Italiano5df60662016-11-07 19:11:25 +0000[diff] [blame]683 MachineInstr *RtMI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]684 if (getLdStOffsetOp(*I).getImm() ==
Davide Italiano5df60662016-11-07 19:11:25 +0000[diff] [blame]685 getLdStOffsetOp(*MergeMI).getImm() + OffsetStride)
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]686 RtMI = &*MergeMI;
Davide Italiano5df60662016-11-07 19:11:25 +0000[diff] [blame]687 else
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]688 RtMI = &*I;
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]689
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]690 int OffsetImm = getLdStOffsetOp(*RtMI).getImm();
Chad Rosier11eedc92016-02-09 19:17:18 +0000[diff] [blame]691 // Change the scaled offset from small to large type.
692 if (IsScaled) {
693 assert(((OffsetImm & 1) == 0) && "Unexpected offset to merge");
694 OffsetImm /= 2;
695 }
696
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]697 // Construct the new instruction.
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]698 DebugLoc DL = I->getDebugLoc();
699 MachineBasicBlock *MBB = I->getParent();
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]700 MachineInstrBuilder MIB;
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]701 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingWideOpcode(Opc)))
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]702 .addReg(isNarrowStore(Opc) ? AArch64::WZR : AArch64::XZR)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]703 .add(BaseRegOp)
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]704 .addImm(OffsetImm)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]705 .setMemRefs(I->mergeMemRefsWith(*MergeMI))
706 .setMIFlags(I->mergeFlagsWith(*MergeMI));
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]707 (void)MIB;
708
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]709 DEBUG(dbgs() << "Creating wider store. Replacing instructions:\n ");
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]710 DEBUG(I->print(dbgs()));
711 DEBUG(dbgs() << " ");
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]712 DEBUG(MergeMI->print(dbgs()));
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]713 DEBUG(dbgs() << " with instruction:\n ");
714 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
715 DEBUG(dbgs() << "\n");
716
717 // Erase the old instructions.
718 I->eraseFromParent();
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]719 MergeMI->eraseFromParent();
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]720 return NextI;
721}
722
723MachineBasicBlock::iterator
724AArch64LoadStoreOpt::mergePairedInsns(MachineBasicBlock::iterator I,
725 MachineBasicBlock::iterator Paired,
726 const LdStPairFlags &Flags) {
727 MachineBasicBlock::iterator NextI = I;
728 ++NextI;
729 // If NextI is the second of the two instructions to be merged, we need
730 // to skip one further. Either way we merge will invalidate the iterator,
731 // and we don't need to scan the new instruction, as it's a pairwise
732 // instruction, which we're not considering for further action anyway.
733 if (NextI == Paired)
734 ++NextI;
735
736 int SExtIdx = Flags.getSExtIdx();
737 unsigned Opc =
738 SExtIdx == -1 ? I->getOpcode() : getMatchingNonSExtOpcode(I->getOpcode());
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]739 bool IsUnscaled = TII->isUnscaledLdSt(Opc);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]740 int OffsetStride = IsUnscaled ? getMemScale(*I) : 1;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]741
742 bool MergeForward = Flags.getMergeForward();
743 // Insert our new paired instruction after whichever of the paired
744 // instructions MergeForward indicates.
745 MachineBasicBlock::iterator InsertionPoint = MergeForward ? Paired : I;
746 // Also based on MergeForward is from where we copy the base register operand
747 // so we get the flags compatible with the input code.
748 const MachineOperand &BaseRegOp =
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]749 MergeForward ? getLdStBaseOp(*Paired) : getLdStBaseOp(*I);
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]750
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]751 int Offset = getLdStOffsetOp(*I).getImm();
752 int PairedOffset = getLdStOffsetOp(*Paired).getImm();
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]753 bool PairedIsUnscaled = TII->isUnscaledLdSt(Paired->getOpcode());
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]754 if (IsUnscaled != PairedIsUnscaled) {
755 // We're trying to pair instructions that differ in how they are scaled. If
756 // I is scaled then scale the offset of Paired accordingly. Otherwise, do
757 // the opposite (i.e., make Paired's offset unscaled).
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]758 int MemSize = getMemScale(*Paired);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]759 if (PairedIsUnscaled) {
760 // If the unscaled offset isn't a multiple of the MemSize, we can't
761 // pair the operations together.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]762 assert(!(PairedOffset % getMemScale(*Paired)) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]763 "Offset should be a multiple of the stride!");
764 PairedOffset /= MemSize;
765 } else {
766 PairedOffset *= MemSize;
767 }
768 }
769
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]770 // Which register is Rt and which is Rt2 depends on the offset order.
771 MachineInstr *RtMI, *Rt2MI;
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]772 if (Offset == PairedOffset + OffsetStride) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]773 RtMI = &*Paired;
774 Rt2MI = &*I;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]775 // Here we swapped the assumption made for SExtIdx.
776 // I.e., we turn ldp I, Paired into ldp Paired, I.
777 // Update the index accordingly.
778 if (SExtIdx != -1)
779 SExtIdx = (SExtIdx + 1) % 2;
780 } else {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]781 RtMI = &*I;
782 Rt2MI = &*Paired;
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]783 }
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]784 int OffsetImm = getLdStOffsetOp(*RtMI).getImm();
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]785 // Scale the immediate offset, if necessary.
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]786 if (TII->isUnscaledLdSt(RtMI->getOpcode())) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]787 assert(!(OffsetImm % getMemScale(*RtMI)) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]788 "Unscaled offset cannot be scaled.");
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]789 OffsetImm /= getMemScale(*RtMI);
Chad Rosier87e33412016-02-09 20:18:07 +0000[diff] [blame]790 }
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]791
792 // Construct the new instruction.
793 MachineInstrBuilder MIB;
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]794 DebugLoc DL = I->getDebugLoc();
795 MachineBasicBlock *MBB = I->getParent();
Matthias Braun2e8c11e2017-01-20 18:04:27 +0000[diff] [blame]796 MachineOperand RegOp0 = getLdStRegOp(*RtMI);
797 MachineOperand RegOp1 = getLdStRegOp(*Rt2MI);
798 // Kill flags may become invalid when moving stores for pairing.
799 if (RegOp0.isUse()) {
800 if (!MergeForward) {
801 // Clear kill flags on store if moving upwards. Example:
802 // STRWui %w0, ...
803 // USE %w1
804 // STRWui kill %w1 ; need to clear kill flag when moving STRWui upwards
805 RegOp0.setIsKill(false);
806 RegOp1.setIsKill(false);
807 } else {
808 // Clear kill flags of the first stores register. Example:
809 // STRWui %w1, ...
810 // USE kill %w1 ; need to clear kill flag when moving STRWui downwards
811 // STRW %w0
812 unsigned Reg = getLdStRegOp(*I).getReg();
813 for (MachineInstr &MI : make_range(std::next(I), Paired))
814 MI.clearRegisterKills(Reg, TRI);
815 }
816 }
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]817 MIB = BuildMI(*MBB, InsertionPoint, DL, TII->get(getMatchingPairOpcode(Opc)))
Matthias Braun2e8c11e2017-01-20 18:04:27 +0000[diff] [blame]818 .add(RegOp0)
819 .add(RegOp1)
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]820 .add(BaseRegOp)
Chad Rosiere40b9512016-03-08 17:16:38 +0000[diff] [blame]821 .addImm(OffsetImm)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]822 .setMemRefs(I->mergeMemRefsWith(*Paired))
823 .setMIFlags(I->mergeFlagsWith(*Paired));
Chad Rosierb5933d72016-02-09 19:02:12 +0000[diff] [blame]824
825 (void)MIB;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]826
827 DEBUG(dbgs() << "Creating pair load/store. Replacing instructions:\n ");
828 DEBUG(I->print(dbgs()));
829 DEBUG(dbgs() << " ");
830 DEBUG(Paired->print(dbgs()));
831 DEBUG(dbgs() << " with instruction:\n ");
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]832 if (SExtIdx != -1) {
833 // Generate the sign extension for the proper result of the ldp.
834 // I.e., with X1, that would be:
Francis Visoiu Mistriha8a83d12017-12-07 10:40:31 +0000[diff] [blame]835 // %w1 = KILL %w1, implicit-def %x1
836 // %x1 = SBFMXri killed %x1, 0, 31
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]837 MachineOperand &DstMO = MIB->getOperand(SExtIdx);
838 // Right now, DstMO has the extended register, since it comes from an
839 // extended opcode.
840 unsigned DstRegX = DstMO.getReg();
841 // Get the W variant of that register.
842 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
843 // Update the result of LDP to use the W instead of the X variant.
844 DstMO.setReg(DstRegW);
845 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
846 DEBUG(dbgs() << "\n");
847 // Make the machine verifier happy by providing a definition for
848 // the X register.
849 // Insert this definition right after the generated LDP, i.e., before
850 // InsertionPoint.
851 MachineInstrBuilder MIBKill =
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]852 BuildMI(*MBB, InsertionPoint, DL, TII->get(TargetOpcode::KILL), DstRegW)
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]853 .addReg(DstRegW)
854 .addReg(DstRegX, RegState::Define);
855 MIBKill->getOperand(2).setImplicit();
856 // Create the sign extension.
857 MachineInstrBuilder MIBSXTW =
Chad Rosierc46ef882016-02-09 19:33:42 +0000[diff] [blame]858 BuildMI(*MBB, InsertionPoint, DL, TII->get(AArch64::SBFMXri), DstRegX)
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]859 .addReg(DstRegX)
860 .addImm(0)
861 .addImm(31);
862 (void)MIBSXTW;
863 DEBUG(dbgs() << " Extend operand:\n ");
864 DEBUG(((MachineInstr *)MIBSXTW)->print(dbgs()));
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]865 } else {
866 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
Quentin Colombet66b61632015-03-06 22:42:10 +0000[diff] [blame]867 }
Chad Rosier1c44c5982016-02-09 20:27:45 +0000[diff] [blame]868 DEBUG(dbgs() << "\n");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]869
870 // Erase the old instructions.
871 I->eraseFromParent();
872 Paired->eraseFromParent();
873
874 return NextI;
875}
876
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]877MachineBasicBlock::iterator
878AArch64LoadStoreOpt::promoteLoadFromStore(MachineBasicBlock::iterator LoadI,
879 MachineBasicBlock::iterator StoreI) {
880 MachineBasicBlock::iterator NextI = LoadI;
881 ++NextI;
882
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]883 int LoadSize = getMemScale(*LoadI);
884 int StoreSize = getMemScale(*StoreI);
885 unsigned LdRt = getLdStRegOp(*LoadI).getReg();
Florian Hahn80e48512017-06-21 08:47:23 +0000[diff] [blame]886 const MachineOperand &StMO = getLdStRegOp(*StoreI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]887 unsigned StRt = getLdStRegOp(*StoreI).getReg();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]888 bool IsStoreXReg = TRI->getRegClass(AArch64::GPR64RegClassID)->contains(StRt);
889
890 assert((IsStoreXReg ||
891 TRI->getRegClass(AArch64::GPR32RegClassID)->contains(StRt)) &&
892 "Unexpected RegClass");
893
894 MachineInstr *BitExtMI;
895 if (LoadSize == StoreSize && (LoadSize == 4 || LoadSize == 8)) {
896 // Remove the load, if the destination register of the loads is the same
897 // register for stored value.
898 if (StRt == LdRt && LoadSize == 8) {
Tim Northover9ac3e422017-06-26 18:49:25 +0000[diff] [blame]899 for (MachineInstr &MI : make_range(StoreI->getIterator(),
900 LoadI->getIterator())) {
901 if (MI.killsRegister(StRt, TRI)) {
902 MI.clearRegisterKills(StRt, TRI);
903 break;
904 }
905 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]906 DEBUG(dbgs() << "Remove load instruction:\n ");
907 DEBUG(LoadI->print(dbgs()));
908 DEBUG(dbgs() << "\n");
909 LoadI->eraseFromParent();
910 return NextI;
911 }
912 // Replace the load with a mov if the load and store are in the same size.
913 BitExtMI =
914 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
915 TII->get(IsStoreXReg ? AArch64::ORRXrs : AArch64::ORRWrs), LdRt)
916 .addReg(IsStoreXReg ? AArch64::XZR : AArch64::WZR)
Florian Hahn80e48512017-06-21 08:47:23 +0000[diff] [blame]917 .add(StMO)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]918 .addImm(AArch64_AM::getShifterImm(AArch64_AM::LSL, 0))
919 .setMIFlags(LoadI->getFlags());
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]920 } else {
921 // FIXME: Currently we disable this transformation in big-endian targets as
922 // performance and correctness are verified only in little-endian.
923 if (!Subtarget->isLittleEndian())
924 return NextI;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]925 bool IsUnscaled = TII->isUnscaledLdSt(*LoadI);
926 assert(IsUnscaled == TII->isUnscaledLdSt(*StoreI) &&
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]927 "Unsupported ld/st match");
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]928 assert(LoadSize <= StoreSize && "Invalid load size");
929 int UnscaledLdOffset = IsUnscaled
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]930 ? getLdStOffsetOp(*LoadI).getImm()
931 : getLdStOffsetOp(*LoadI).getImm() * LoadSize;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]932 int UnscaledStOffset = IsUnscaled
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]933 ? getLdStOffsetOp(*StoreI).getImm()
934 : getLdStOffsetOp(*StoreI).getImm() * StoreSize;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]935 int Width = LoadSize * 8;
936 int Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
937 int Imms = Immr + Width - 1;
938 unsigned DestReg = IsStoreXReg
939 ? TRI->getMatchingSuperReg(LdRt, AArch64::sub_32,
940 &AArch64::GPR64RegClass)
941 : LdRt;
942
943 assert((UnscaledLdOffset >= UnscaledStOffset &&
944 (UnscaledLdOffset + LoadSize) <= UnscaledStOffset + StoreSize) &&
945 "Invalid offset");
946
947 Immr = 8 * (UnscaledLdOffset - UnscaledStOffset);
948 Imms = Immr + Width - 1;
949 if (UnscaledLdOffset == UnscaledStOffset) {
950 uint32_t AndMaskEncoded = ((IsStoreXReg ? 1 : 0) << 12) // N
951 | ((Immr) << 6) // immr
952 | ((Imms) << 0) // imms
953 ;
954
955 BitExtMI =
956 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
957 TII->get(IsStoreXReg ? AArch64::ANDXri : AArch64::ANDWri),
958 DestReg)
Florian Hahn80e48512017-06-21 08:47:23 +0000[diff] [blame]959 .add(StMO)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]960 .addImm(AndMaskEncoded)
961 .setMIFlags(LoadI->getFlags());
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]962 } else {
963 BitExtMI =
964 BuildMI(*LoadI->getParent(), LoadI, LoadI->getDebugLoc(),
965 TII->get(IsStoreXReg ? AArch64::UBFMXri : AArch64::UBFMWri),
966 DestReg)
Florian Hahn80e48512017-06-21 08:47:23 +0000[diff] [blame]967 .add(StMO)
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]968 .addImm(Immr)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]969 .addImm(Imms)
970 .setMIFlags(LoadI->getFlags());
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]971 }
972 }
Matthias Braun76bb4132016-12-16 23:55:43 +0000[diff] [blame]973
Matthias Braund9a59a82017-02-17 23:15:03 +0000[diff] [blame]974 // Clear kill flags between store and load.
975 for (MachineInstr &MI : make_range(StoreI->getIterator(),
976 BitExtMI->getIterator()))
Florian Hahn8552e592017-06-21 09:51:52 +0000[diff] [blame]977 if (MI.killsRegister(StRt, TRI)) {
978 MI.clearRegisterKills(StRt, TRI);
979 break;
980 }
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]981
982 DEBUG(dbgs() << "Promoting load by replacing :\n ");
983 DEBUG(StoreI->print(dbgs()));
984 DEBUG(dbgs() << " ");
985 DEBUG(LoadI->print(dbgs()));
986 DEBUG(dbgs() << " with instructions:\n ");
987 DEBUG(StoreI->print(dbgs()));
988 DEBUG(dbgs() << " ");
989 DEBUG((BitExtMI)->print(dbgs()));
990 DEBUG(dbgs() << "\n");
991
992 // Erase the old instructions.
993 LoadI->eraseFromParent();
994 return NextI;
995}
996
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]997static bool inBoundsForPair(bool IsUnscaled, int Offset, int OffsetStride) {
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]998 // Convert the byte-offset used by unscaled into an "element" offset used
999 // by the scaled pair load/store instructions.
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1000 if (IsUnscaled) {
1001 // If the byte-offset isn't a multiple of the stride, there's no point
1002 // trying to match it.
1003 if (Offset % OffsetStride)
1004 return false;
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]1005 Offset /= OffsetStride;
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1006 }
Chad Rosier3dd0e942015-08-18 16:20:03 +0000[diff] [blame]1007 return Offset <= 63 && Offset >= -64;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1008}
1009
1010// Do alignment, specialized to power of 2 and for signed ints,
1011// avoiding having to do a C-style cast from uint_64t to int when
Rui Ueyamada00f2f2016-01-14 21:06:47 +0000[diff] [blame]1012// using alignTo from include/llvm/Support/MathExtras.h.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1013// FIXME: Move this function to include/MathExtras.h?
1014static int alignTo(int Num, int PowOf2) {
1015 return (Num + PowOf2 - 1) & ~(PowOf2 - 1);
1016}
1017
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1018static bool mayAlias(MachineInstr &MIa, MachineInstr &MIb,
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1019 AliasAnalysis *AA) {
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1020 // One of the instructions must modify memory.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1021 if (!MIa.mayStore() && !MIb.mayStore())
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1022 return false;
1023
1024 // Both instructions must be memory operations.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1025 if (!MIa.mayLoadOrStore() && !MIb.mayLoadOrStore())
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1026 return false;
1027
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1028 return MIa.mayAlias(AA, MIb, /*UseTBAA*/false);
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1029}
1030
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1031static bool mayAlias(MachineInstr &MIa,
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1032 SmallVectorImpl<MachineInstr *> &MemInsns,
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1033 AliasAnalysis *AA) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]1034 for (MachineInstr *MIb : MemInsns)
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1035 if (mayAlias(MIa, *MIb, AA))
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1036 return true;
1037
1038 return false;
1039}
1040
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1041bool AArch64LoadStoreOpt::findMatchingStore(
1042 MachineBasicBlock::iterator I, unsigned Limit,
1043 MachineBasicBlock::iterator &StoreI) {
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1044 MachineBasicBlock::iterator B = I->getParent()->begin();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1045 MachineBasicBlock::iterator MBBI = I;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1046 MachineInstr &LoadMI = *I;
Chad Rosier5c6a66c2016-02-09 15:59:57 +0000[diff] [blame]1047 unsigned BaseReg = getLdStBaseOp(LoadMI).getReg();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1048
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1049 // If the load is the first instruction in the block, there's obviously
1050 // not any matching store.
1051 if (MBBI == B)
1052 return false;
1053
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1054 // Track which registers have been modified and used between the first insn
1055 // and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1056 ModifiedRegs.reset();
1057 UsedRegs.reset();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1058
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1059 unsigned Count = 0;
1060 do {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1061 --MBBI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1062 MachineInstr &MI = *MBBI;
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1063
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1064 // Don't count transient instructions towards the search limit since there
1065 // may be different numbers of them if e.g. debug information is present.
1066 if (!MI.isTransient())
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1067 ++Count;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1068
1069 // If the load instruction reads directly from the address to which the
1070 // store instruction writes and the stored value is not modified, we can
1071 // promote the load. Since we do not handle stores with pre-/post-index,
1072 // it's unnecessary to check if BaseReg is modified by the store itself.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1073 if (MI.mayStore() && isMatchingStore(LoadMI, MI) &&
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1074 BaseReg == getLdStBaseOp(MI).getReg() &&
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]1075 isLdOffsetInRangeOfSt(LoadMI, MI, TII) &&
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1076 !ModifiedRegs[getLdStRegOp(MI).getReg()]) {
1077 StoreI = MBBI;
1078 return true;
1079 }
1080
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1081 if (MI.isCall())
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1082 return false;
1083
1084 // Update modified / uses register lists.
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1085 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1086
1087 // Otherwise, if the base register is modified, we have no match, so
1088 // return early.
1089 if (ModifiedRegs[BaseReg])
1090 return false;
1091
1092 // If we encounter a store aliased with the load, return early.
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1093 if (MI.mayStore() && mayAlias(LoadMI, MI, AA))
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1094 return false;
Jun Bum Lim633b2d82016-02-11 16:18:24 +0000[diff] [blame]1095 } while (MBBI != B && Count < Limit);
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1096 return false;
1097}
1098
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1099// Returns true if FirstMI and MI are candidates for merging or pairing.
1100// Otherwise, returns false.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1101static bool areCandidatesToMergeOrPair(MachineInstr &FirstMI, MachineInstr &MI,
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1102 LdStPairFlags &Flags,
1103 const AArch64InstrInfo *TII) {
1104 // If this is volatile or if pairing is suppressed, not a candidate.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1105 if (MI.hasOrderedMemoryRef() || TII->isLdStPairSuppressed(MI))
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1106 return false;
1107
1108 // We should have already checked FirstMI for pair suppression and volatility.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1109 assert(!FirstMI.hasOrderedMemoryRef() &&
1110 !TII->isLdStPairSuppressed(FirstMI) &&
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1111 "FirstMI shouldn't get here if either of these checks are true.");
1112
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1113 unsigned OpcA = FirstMI.getOpcode();
1114 unsigned OpcB = MI.getOpcode();
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1115
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1116 // Opcodes match: nothing more to check.
1117 if (OpcA == OpcB)
1118 return true;
1119
1120 // Try to match a sign-extended load/store with a zero-extended load/store.
1121 bool IsValidLdStrOpc, PairIsValidLdStrOpc;
1122 unsigned NonSExtOpc = getMatchingNonSExtOpcode(OpcA, &IsValidLdStrOpc);
1123 assert(IsValidLdStrOpc &&
1124 "Given Opc should be a Load or Store with an immediate");
1125 // OpcA will be the first instruction in the pair.
1126 if (NonSExtOpc == getMatchingNonSExtOpcode(OpcB, &PairIsValidLdStrOpc)) {
1127 Flags.setSExtIdx(NonSExtOpc == (unsigned)OpcA ? 1 : 0);
1128 return true;
1129 }
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1130
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1131 // If the second instruction isn't even a mergable/pairable load/store, bail
1132 // out.
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1133 if (!PairIsValidLdStrOpc)
1134 return false;
1135
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1136 // FIXME: We don't support merging narrow stores with mixed scaled/unscaled
1137 // offsets.
1138 if (isNarrowStore(OpcA) || isNarrowStore(OpcB))
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1139 return false;
1140
1141 // Try to match an unscaled load/store with a scaled load/store.
Chad Rosiere4e15ba2016-03-09 17:29:48 +0000[diff] [blame]1142 return TII->isUnscaledLdSt(OpcA) != TII->isUnscaledLdSt(OpcB) &&
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1143 getMatchingPairOpcode(OpcA) == getMatchingPairOpcode(OpcB);
1144
1145 // FIXME: Can we also match a mixed sext/zext unscaled/scaled pair?
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1146}
1147
Chad Rosier9f4ec2e2016-02-10 18:49:28 +0000[diff] [blame]1148/// Scan the instructions looking for a load/store that can be combined with the
1149/// current instruction into a wider equivalent or a load/store pair.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1150MachineBasicBlock::iterator
1151AArch64LoadStoreOpt::findMatchingInsn(MachineBasicBlock::iterator I,
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1152 LdStPairFlags &Flags, unsigned Limit,
1153 bool FindNarrowMerge) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1154 MachineBasicBlock::iterator E = I->getParent()->end();
1155 MachineBasicBlock::iterator MBBI = I;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1156 MachineInstr &FirstMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1157 ++MBBI;
1158
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1159 bool MayLoad = FirstMI.mayLoad();
1160 bool IsUnscaled = TII->isUnscaledLdSt(FirstMI);
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1161 unsigned Reg = getLdStRegOp(FirstMI).getReg();
1162 unsigned BaseReg = getLdStBaseOp(FirstMI).getReg();
1163 int Offset = getLdStOffsetOp(FirstMI).getImm();
Chad Rosierf11d0402015-10-01 18:17:12 +0000[diff] [blame]1164 int OffsetStride = IsUnscaled ? getMemScale(FirstMI) : 1;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1165 bool IsPromotableZeroStore = isPromotableZeroStoreInst(FirstMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1166
1167 // Track which registers have been modified and used between the first insn
1168 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1169 ModifiedRegs.reset();
1170 UsedRegs.reset();
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1171
1172 // Remember any instructions that read/write memory between FirstMI and MI.
1173 SmallVector<MachineInstr *, 4> MemInsns;
1174
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1175 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1176 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1177
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1178 // Don't count transient instructions towards the search limit since there
1179 // may be different numbers of them if e.g. debug information is present.
1180 if (!MI.isTransient())
1181 ++Count;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1182
Chad Rosier18896c02016-02-04 16:01:40 +0000[diff] [blame]1183 Flags.setSExtIdx(-1);
Chad Rosierc5083c22016-06-10 20:47:14 +0000[diff] [blame]1184 if (areCandidatesToMergeOrPair(FirstMI, MI, Flags, TII) &&
Chad Rosierc3f6cb92016-02-10 19:45:48 +0000[diff] [blame]1185 getLdStOffsetOp(MI).isImm()) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1186 assert(MI.mayLoadOrStore() && "Expected memory operation.");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1187 // If we've found another instruction with the same opcode, check to see
1188 // if the base and offset are compatible with our starting instruction.
1189 // These instructions all have scaled immediate operands, so we just
1190 // check for +1/-1. Make sure to check the new instruction offset is
1191 // actually an immediate and not a symbolic reference destined for
1192 // a relocation.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1193 unsigned MIBaseReg = getLdStBaseOp(MI).getReg();
1194 int MIOffset = getLdStOffsetOp(MI).getImm();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1195 bool MIIsUnscaled = TII->isUnscaledLdSt(MI);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1196 if (IsUnscaled != MIIsUnscaled) {
1197 // We're trying to pair instructions that differ in how they are scaled.
1198 // If FirstMI is scaled then scale the offset of MI accordingly.
1199 // Otherwise, do the opposite (i.e., make MI's offset unscaled).
1200 int MemSize = getMemScale(MI);
1201 if (MIIsUnscaled) {
1202 // If the unscaled offset isn't a multiple of the MemSize, we can't
1203 // pair the operations together: bail and keep looking.
Eli Friedmanf184e4b2016-08-12 20:39:51 +0000[diff] [blame]1204 if (MIOffset % MemSize) {
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1205 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Eli Friedmanf184e4b2016-08-12 20:39:51 +0000[diff] [blame]1206 MemInsns.push_back(&MI);
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1207 continue;
Eli Friedmanf184e4b2016-08-12 20:39:51 +0000[diff] [blame]1208 }
Chad Rosier00f9d232016-02-11 14:25:08 +0000[diff] [blame]1209 MIOffset /= MemSize;
1210 } else {
1211 MIOffset *= MemSize;
1212 }
1213 }
1214
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1215 if (BaseReg == MIBaseReg && ((Offset == MIOffset + OffsetStride) ||
1216 (Offset + OffsetStride == MIOffset))) {
1217 int MinOffset = Offset < MIOffset ? Offset : MIOffset;
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1218 if (FindNarrowMerge) {
Jun Bum Lim80ec0d32015-11-20 21:14:07 +0000[diff] [blame]1219 // If the alignment requirements of the scaled wide load/store
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1220 // instruction can't express the offset of the scaled narrow input,
1221 // bail and keep looking. For promotable zero stores, allow only when
1222 // the stored value is the same (i.e., WZR).
1223 if ((!IsUnscaled && alignTo(MinOffset, 2) != MinOffset) ||
1224 (IsPromotableZeroStore && Reg != getLdStRegOp(MI).getReg())) {
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1225 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1226 MemInsns.push_back(&MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1227 continue;
1228 }
1229 } else {
Chad Rosierd1f6c842016-06-10 20:49:18 +0000[diff] [blame]1230 // Pairwise instructions have a 7-bit signed offset field. Single
1231 // insns have a 12-bit unsigned offset field. If the resultant
1232 // immediate offset of merging these instructions is out of range for
1233 // a pairwise instruction, bail and keep looking.
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1234 if (!inBoundsForPair(IsUnscaled, MinOffset, OffsetStride)) {
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1235 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1236 MemInsns.push_back(&MI);
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1237 continue;
1238 }
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1239 // If the alignment requirements of the paired (scaled) instruction
1240 // can't express the offset of the unscaled input, bail and keep
1241 // looking.
1242 if (IsUnscaled && (alignTo(MinOffset, OffsetStride) != MinOffset)) {
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1243 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1244 MemInsns.push_back(&MI);
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1245 continue;
1246 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1247 }
1248 // If the destination register of the loads is the same register, bail
1249 // and keep looking. A load-pair instruction with both destination
1250 // registers the same is UNPREDICTABLE and will result in an exception.
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1251 if (MayLoad && Reg == getLdStRegOp(MI).getReg()) {
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1252 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1253 MemInsns.push_back(&MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1254 continue;
1255 }
1256
1257 // If the Rt of the second instruction was not modified or used between
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1258 // the two instructions and none of the instructions between the second
1259 // and first alias with the second, we can combine the second into the
1260 // first.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1261 if (!ModifiedRegs[getLdStRegOp(MI).getReg()] &&
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1262 !(MI.mayLoad() && UsedRegs[getLdStRegOp(MI).getReg()]) &&
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1263 !mayAlias(MI, MemInsns, AA)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1264 Flags.setMergeForward(false);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1265 return MBBI;
1266 }
1267
1268 // Likewise, if the Rt of the first instruction is not modified or used
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1269 // between the two instructions and none of the instructions between the
1270 // first and the second alias with the first, we can combine the first
1271 // into the second.
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1272 if (!ModifiedRegs[getLdStRegOp(FirstMI).getReg()] &&
Chad Rosier5f668e12015-09-03 14:19:43 +0000[diff] [blame]1273 !(MayLoad && UsedRegs[getLdStRegOp(FirstMI).getReg()]) &&
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1274 !mayAlias(FirstMI, MemInsns, AA)) {
Chad Rosier96a18a92015-07-21 17:42:04 +0000[diff] [blame]1275 Flags.setMergeForward(true);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1276 return MBBI;
1277 }
1278 // Unable to combine these instructions due to interference in between.
1279 // Keep looking.
1280 }
1281 }
1282
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1283 // If the instruction wasn't a matching load or store. Stop searching if we
1284 // encounter a call instruction that might modify memory.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1285 if (MI.isCall())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1286 return E;
1287
1288 // Update modified / uses register lists.
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1289 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1290
1291 // Otherwise, if the base register is modified, we have no match, so
1292 // return early.
1293 if (ModifiedRegs[BaseReg])
1294 return E;
Chad Rosierce8e5ab2015-05-21 21:36:46 +0000[diff] [blame]1295
1296 // Update list of instructions that read/write memory.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1297 if (MI.mayLoadOrStore())
1298 MemInsns.push_back(&MI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1299 }
1300 return E;
1301}
1302
1303MachineBasicBlock::iterator
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1304AArch64LoadStoreOpt::mergeUpdateInsn(MachineBasicBlock::iterator I,
1305 MachineBasicBlock::iterator Update,
1306 bool IsPreIdx) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1307 assert((Update->getOpcode() == AArch64::ADDXri ||
1308 Update->getOpcode() == AArch64::SUBXri) &&
1309 "Unexpected base register update instruction to merge!");
1310 MachineBasicBlock::iterator NextI = I;
1311 // Return the instruction following the merged instruction, which is
1312 // the instruction following our unmerged load. Unless that's the add/sub
1313 // instruction we're merging, in which case it's the one after that.
1314 if (++NextI == Update)
1315 ++NextI;
1316
1317 int Value = Update->getOperand(2).getImm();
1318 assert(AArch64_AM::getShiftValue(Update->getOperand(3).getImm()) == 0 &&
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1319 "Can't merge 1 << 12 offset into pre-/post-indexed load / store");
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1320 if (Update->getOpcode() == AArch64::SUBXri)
1321 Value = -Value;
1322
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1323 unsigned NewOpc = IsPreIdx ? getPreIndexedOpcode(I->getOpcode())
1324 : getPostIndexedOpcode(I->getOpcode());
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1325 MachineInstrBuilder MIB;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1326 if (!isPairedLdSt(*I)) {
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1327 // Non-paired instruction.
1328 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1329 .add(getLdStRegOp(*Update))
1330 .add(getLdStRegOp(*I))
1331 .add(getLdStBaseOp(*I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1332 .addImm(Value)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]1333 .setMemRefs(I->memoperands_begin(), I->memoperands_end())
1334 .setMIFlags(I->mergeFlagsWith(*Update));
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1335 } else {
1336 // Paired instruction.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1337 int Scale = getMemScale(*I);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1338 MIB = BuildMI(*I->getParent(), I, I->getDebugLoc(), TII->get(NewOpc))
Diana Picus116bbab2017-01-13 09:58:52 +0000[diff] [blame]1339 .add(getLdStRegOp(*Update))
1340 .add(getLdStRegOp(*I, 0))
1341 .add(getLdStRegOp(*I, 1))
1342 .add(getLdStBaseOp(*I))
Chad Rosier3ada75f2016-01-28 15:38:24 +0000[diff] [blame]1343 .addImm(Value / Scale)
Francis Visoiu Mistrih084e7d82018-03-14 17:10:58 +0000[diff] [blame]1344 .setMemRefs(I->memoperands_begin(), I->memoperands_end())
1345 .setMIFlags(I->mergeFlagsWith(*Update));
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1346 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1347 (void)MIB;
1348
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1349 if (IsPreIdx) {
1350 ++NumPreFolded;
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1351 DEBUG(dbgs() << "Creating pre-indexed load/store.");
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1352 } else {
1353 ++NumPostFolded;
Chad Rosier2dfd3542015-09-23 13:51:44 +0000[diff] [blame]1354 DEBUG(dbgs() << "Creating post-indexed load/store.");
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1355 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1356 DEBUG(dbgs() << " Replacing instructions:\n ");
1357 DEBUG(I->print(dbgs()));
1358 DEBUG(dbgs() << " ");
1359 DEBUG(Update->print(dbgs()));
1360 DEBUG(dbgs() << " with instruction:\n ");
1361 DEBUG(((MachineInstr *)MIB)->print(dbgs()));
1362 DEBUG(dbgs() << "\n");
1363
1364 // Erase the old instructions for the block.
1365 I->eraseFromParent();
1366 Update->eraseFromParent();
1367
1368 return NextI;
1369}
1370
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1371bool AArch64LoadStoreOpt::isMatchingUpdateInsn(MachineInstr &MemMI,
1372 MachineInstr &MI,
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1373 unsigned BaseReg, int Offset) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1374 switch (MI.getOpcode()) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1375 default:
1376 break;
1377 case AArch64::SUBXri:
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1378 case AArch64::ADDXri:
1379 // Make sure it's a vanilla immediate operand, not a relocation or
1380 // anything else we can't handle.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1381 if (!MI.getOperand(2).isImm())
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1382 break;
1383 // Watch out for 1 << 12 shifted value.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1384 if (AArch64_AM::getShiftValue(MI.getOperand(3).getImm()))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1385 break;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1386
1387 // The update instruction source and destination register must be the
1388 // same as the load/store base register.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1389 if (MI.getOperand(0).getReg() != BaseReg ||
1390 MI.getOperand(1).getReg() != BaseReg)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1391 break;
1392
1393 bool IsPairedInsn = isPairedLdSt(MemMI);
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1394 int UpdateOffset = MI.getOperand(2).getImm();
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1395 if (MI.getOpcode() == AArch64::SUBXri)
1396 UpdateOffset = -UpdateOffset;
1397
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1398 // For non-paired load/store instructions, the immediate must fit in a
1399 // signed 9-bit integer.
1400 if (!IsPairedInsn && (UpdateOffset > 255 || UpdateOffset < -256))
1401 break;
1402
1403 // For paired load/store instructions, the immediate must be a multiple of
1404 // the scaling factor. The scaled offset must also fit into a signed 7-bit
1405 // integer.
1406 if (IsPairedInsn) {
Chad Rosier32d4d372015-09-29 16:07:32 +0000[diff] [blame]1407 int Scale = getMemScale(MemMI);
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1408 if (UpdateOffset % Scale != 0)
1409 break;
1410
1411 int ScaledOffset = UpdateOffset / Scale;
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1412 if (ScaledOffset > 63 || ScaledOffset < -64)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1413 break;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1414 }
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1415
1416 // If we have a non-zero Offset, we check that it matches the amount
1417 // we're adding to the register.
Eli Friedman8585e9d2016-08-12 20:28:02 +0000[diff] [blame]1418 if (!Offset || Offset == UpdateOffset)
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1419 return true;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1420 break;
1421 }
1422 return false;
1423}
1424
1425MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnForward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1426 MachineBasicBlock::iterator I, int UnscaledOffset, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1427 MachineBasicBlock::iterator E = I->getParent()->end();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1428 MachineInstr &MemMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1429 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1430
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1431 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
Chad Rosier0b15e7c2015-10-01 13:33:31 +0000[diff] [blame]1432 int MIUnscaledOffset = getLdStOffsetOp(MemMI).getImm() * getMemScale(MemMI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1433
Chad Rosierb7c5b912015-10-01 13:43:05 +0000[diff] [blame]1434 // Scan forward looking for post-index opportunities. Updating instructions
1435 // can't be formed if the memory instruction doesn't have the offset we're
1436 // looking for.
1437 if (MIUnscaledOffset != UnscaledOffset)
1438 return E;
1439
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1440 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1441 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1442 bool IsPairedInsn = isPairedLdSt(MemMI);
1443 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1444 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1445 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1446 return E;
1447 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1448
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1449 // Track which registers have been modified and used between the first insn
1450 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1451 ModifiedRegs.reset();
1452 UsedRegs.reset();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1453 ++MBBI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1454 for (unsigned Count = 0; MBBI != E && Count < Limit; ++MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1455 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1456
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1457 // Don't count transient instructions towards the search limit since there
1458 // may be different numbers of them if e.g. debug information is present.
1459 if (!MI.isTransient())
1460 ++Count;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1461
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1462 // If we found a match, return it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1463 if (isMatchingUpdateInsn(*I, MI, BaseReg, UnscaledOffset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1464 return MBBI;
1465
1466 // Update the status of what the instruction clobbered and used.
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1467 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1468
1469 // Otherwise, if the base register is used or modified, we have no match, so
1470 // return early.
1471 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1472 return E;
1473 }
1474 return E;
1475}
1476
1477MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1478 MachineBasicBlock::iterator I, unsigned Limit) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1479 MachineBasicBlock::iterator B = I->getParent()->begin();
1480 MachineBasicBlock::iterator E = I->getParent()->end();
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1481 MachineInstr &MemMI = *I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1482 MachineBasicBlock::iterator MBBI = I;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1483
Chad Rosierf77e9092015-08-06 15:50:12 +0000[diff] [blame]1484 unsigned BaseReg = getLdStBaseOp(MemMI).getReg();
1485 int Offset = getLdStOffsetOp(MemMI).getImm();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1486
1487 // If the load/store is the first instruction in the block, there's obviously
1488 // not any matching update. Ditto if the memory offset isn't zero.
1489 if (MBBI == B || Offset != 0)
1490 return E;
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1491 // If the base register overlaps a destination register, we can't
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1492 // merge the update.
Chad Rosier1bbd7fb2015-09-25 17:48:17 +0000[diff] [blame]1493 bool IsPairedInsn = isPairedLdSt(MemMI);
1494 for (unsigned i = 0, e = IsPairedInsn ? 2 : 1; i != e; ++i) {
1495 unsigned DestReg = getLdStRegOp(MemMI, i).getReg();
1496 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg))
1497 return E;
1498 }
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1499
1500 // Track which registers have been modified and used between the first insn
1501 // (inclusive) and the second insn.
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1502 ModifiedRegs.reset();
1503 UsedRegs.reset();
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1504 unsigned Count = 0;
1505 do {
1506 --MBBI;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1507 MachineInstr &MI = *MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1508
Geoff Berry4ff2e362016-07-21 15:20:25 +0000[diff] [blame]1509 // Don't count transient instructions towards the search limit since there
1510 // may be different numbers of them if e.g. debug information is present.
1511 if (!MI.isTransient())
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1512 ++Count;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1513
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1514 // If we found a match, return it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1515 if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset))
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1516 return MBBI;
1517
1518 // Update the status of what the instruction clobbered and used.
Jun Bum Lim2ecb7ba2018-03-22 20:06:47 +0000[diff] [blame]1519 TII->trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1520
1521 // Otherwise, if the base register is used or modified, we have no match, so
1522 // return early.
1523 if (ModifiedRegs[BaseReg] || UsedRegs[BaseReg])
1524 return E;
Geoff Berry173b14d2016-02-09 20:47:21 +0000[diff] [blame]1525 } while (MBBI != B && Count < Limit);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1526 return E;
1527}
1528
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1529bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
1530 MachineBasicBlock::iterator &MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1531 MachineInstr &MI = *MBBI;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1532 // If this is a volatile load, don't mess with it.
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1533 if (MI.hasOrderedMemoryRef())
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1534 return false;
1535
1536 // Make sure this is a reg+imm.
1537 // FIXME: It is possible to extend it to handle reg+reg cases.
1538 if (!getLdStOffsetOp(MI).isImm())
1539 return false;
1540
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1541 // Look backward up to LdStLimit instructions.
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1542 MachineBasicBlock::iterator StoreI;
Chad Rosier35706ad2016-02-04 21:26:02 +0000[diff] [blame]1543 if (findMatchingStore(MBBI, LdStLimit, StoreI)) {
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1544 ++NumLoadsFromStoresPromoted;
1545 // Promote the load. Keeping the iterator straight is a
1546 // pain, so we let the merge routine tell us what the next instruction
1547 // is after it's done mucking about.
1548 MBBI = promoteLoadFromStore(MBBI, StoreI);
1549 return true;
1550 }
1551 return false;
1552}
1553
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1554// Merge adjacent zero stores into a wider store.
1555bool AArch64LoadStoreOpt::tryToMergeZeroStInst(
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1556 MachineBasicBlock::iterator &MBBI) {
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1557 assert(isPromotableZeroStoreInst(*MBBI) && "Expected narrow store.");
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1558 MachineInstr &MI = *MBBI;
1559 MachineBasicBlock::iterator E = MI.getParent()->end();
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1560
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1561 if (!TII->isCandidateToMergeOrPair(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1562 return false;
1563
1564 // Look ahead up to LdStLimit instructions for a mergable instruction.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1565 LdStPairFlags Flags;
Jun Bum Lim397eb7b2016-02-12 15:25:39 +0000[diff] [blame]1566 MachineBasicBlock::iterator MergeMI =
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1567 findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ true);
Chad Rosierd7363db2016-02-09 19:09:22 +0000[diff] [blame]1568 if (MergeMI != E) {
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1569 ++NumZeroStoresPromoted;
1570
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1571 // Keeping the iterator straight is a pain, so we let the merge routine tell
1572 // us what the next instruction is after it's done mucking about.
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1573 MBBI = mergeNarrowZeroStores(MBBI, MergeMI, Flags);
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1574 return true;
1575 }
1576 return false;
1577}
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1578
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1579// Find loads and stores that can be merged into a single load or store pair
1580// instruction.
1581bool AArch64LoadStoreOpt::tryToPairLdStInst(MachineBasicBlock::iterator &MBBI) {
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1582 MachineInstr &MI = *MBBI;
1583 MachineBasicBlock::iterator E = MI.getParent()->end();
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1584
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1585 if (!TII->isCandidateToMergeOrPair(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1586 return false;
1587
Chad Rosierfc3bf1f2016-02-10 15:52:46 +0000[diff] [blame]1588 // Early exit if the offset is not possible to match. (6 bits of positive
1589 // range, plus allow an extra one in case we find a later insn that matches
1590 // with Offset-1)
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1591 bool IsUnscaled = TII->isUnscaledLdSt(MI);
Chad Rosierfc3bf1f2016-02-10 15:52:46 +0000[diff] [blame]1592 int Offset = getLdStOffsetOp(MI).getImm();
1593 int OffsetStride = IsUnscaled ? getMemScale(MI) : 1;
Nirav Dave0f9d1112017-01-04 21:21:46 +0000[diff] [blame]1594 // Allow one more for offset.
1595 if (Offset > 0)
1596 Offset -= OffsetStride;
Chad Rosierfc3bf1f2016-02-10 15:52:46 +0000[diff] [blame]1597 if (!inBoundsForPair(IsUnscaled, Offset, OffsetStride))
1598 return false;
1599
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1600 // Look ahead up to LdStLimit instructions for a pairable instruction.
1601 LdStPairFlags Flags;
Jun Bum Limcf974432016-03-31 14:47:24 +0000[diff] [blame]1602 MachineBasicBlock::iterator Paired =
1603 findMatchingInsn(MBBI, Flags, LdStLimit, /* FindNarrowMerge = */ false);
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1604 if (Paired != E) {
1605 ++NumPairCreated;
Duncan P. N. Exon Smithab53fd92016-07-08 20:29:42 +0000[diff] [blame]1606 if (TII->isUnscaledLdSt(MI))
Chad Rosier24c46ad2016-02-09 18:10:20 +0000[diff] [blame]1607 ++NumUnscaledPairCreated;
1608 // Keeping the iterator straight is a pain, so we let the merge routine tell
1609 // us what the next instruction is after it's done mucking about.
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1610 MBBI = mergePairedInsns(MBBI, Paired, Flags);
1611 return true;
1612 }
1613 return false;
1614}
1615
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1616bool AArch64LoadStoreOpt::tryToMergeLdStUpdate
1617 (MachineBasicBlock::iterator &MBBI) {
1618 MachineInstr &MI = *MBBI;
1619 MachineBasicBlock::iterator E = MI.getParent()->end();
1620 MachineBasicBlock::iterator Update;
1621
1622 // Look forward to try to form a post-index instruction. For example,
1623 // ldr x0, [x20]
1624 // add x20, x20, #32
1625 // merged into:
1626 // ldr x0, [x20], #32
1627 Update = findMatchingUpdateInsnForward(MBBI, 0, UpdateLimit);
1628 if (Update != E) {
1629 // Merge the update into the ld/st.
1630 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/false);
1631 return true;
1632 }
1633
1634 // Don't know how to handle unscaled pre/post-index versions below, so bail.
1635 if (TII->isUnscaledLdSt(MI.getOpcode()))
1636 return false;
1637
1638 // Look back to try to find a pre-index instruction. For example,
1639 // add x0, x0, #8
1640 // ldr x1, [x0]
1641 // merged into:
1642 // ldr x1, [x0, #8]!
1643 Update = findMatchingUpdateInsnBackward(MBBI, UpdateLimit);
1644 if (Update != E) {
1645 // Merge the update into the ld/st.
1646 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
1647 return true;
1648 }
1649
1650 // The immediate in the load/store is scaled by the size of the memory
1651 // operation. The immediate in the add we're looking for,
1652 // however, is not, so adjust here.
1653 int UnscaledOffset = getLdStOffsetOp(MI).getImm() * getMemScale(MI);
1654
1655 // Look forward to try to find a post-index instruction. For example,
1656 // ldr x1, [x0, #64]
1657 // add x0, x0, #64
1658 // merged into:
1659 // ldr x1, [x0, #64]!
1660 Update = findMatchingUpdateInsnForward(MBBI, UnscaledOffset, UpdateLimit);
1661 if (Update != E) {
1662 // Merge the update into the ld/st.
1663 MBBI = mergeUpdateInsn(MBBI, Update, /*IsPreIdx=*/true);
1664 return true;
1665 }
1666
1667 return false;
1668}
1669
Jun Bum Lim22fe15e2015-11-06 16:27:47 +0000[diff] [blame]1670bool AArch64LoadStoreOpt::optimizeBlock(MachineBasicBlock &MBB,
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1671 bool EnableNarrowZeroStOpt) {
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1672 bool Modified = false;
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1673 // Four tranformations to do here:
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1674 // 1) Find loads that directly read from stores and promote them by
1675 // replacing with mov instructions. If the store is wider than the load,
1676 // the load will be replaced with a bitfield extract.
1677 // e.g.,
1678 // str w1, [x0, #4]
1679 // ldrh w2, [x0, #6]
1680 // ; becomes
1681 // str w1, [x0, #4]
NAKAMURA Takumife1202c2016-06-20 00:37:41 +0000[diff] [blame]1682 // lsr w2, w1, #16
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1683 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1684 MBBI != E;) {
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1685 if (isPromotableLoadFromStore(*MBBI) && tryToPromoteLoadFromStore(MBBI))
1686 Modified = true;
1687 else
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1688 ++MBBI;
Jun Bum Lim6755c3b2015-12-22 16:36:16 +0000[diff] [blame]1689 }
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1690 // 2) Merge adjacent zero stores into a wider store.
Jun Bum Lim1de2d442016-02-05 20:02:03 +0000[diff] [blame]1691 // e.g.,
1692 // strh wzr, [x0]
1693 // strh wzr, [x0, #2]
1694 // ; becomes
1695 // str wzr, [x0]
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1696 // e.g.,
1697 // str wzr, [x0]
1698 // str wzr, [x0, #4]
1699 // ; becomes
1700 // str xzr, [x0]
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1701 if (EnableNarrowZeroStOpt)
1702 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1703 MBBI != E;) {
1704 if (isPromotableZeroStoreInst(*MBBI) && tryToMergeZeroStInst(MBBI))
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1705 Modified = true;
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1706 else
Jun Bum Lim33be4992016-05-06 15:08:57 +0000[diff] [blame]1707 ++MBBI;
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1708 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1709 // 3) Find loads and stores that can be merged into a single load or store
1710 // pair instruction.
1711 // e.g.,
1712 // ldr x0, [x2]
1713 // ldr x1, [x2, #8]
1714 // ; becomes
1715 // ldp x0, x1, [x2]
Jun Bum Limc9879ec2015-10-27 19:16:03 +0000[diff] [blame]1716 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1717 MBBI != E;) {
Geoff Berry22dfbc52016-08-12 15:26:00 +0000[diff] [blame]1718 if (TII->isPairableLdStInst(*MBBI) && tryToPairLdStInst(MBBI))
1719 Modified = true;
1720 else
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1721 ++MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1722 }
Chad Rosierdbdb1d62016-02-01 21:38:31 +0000[diff] [blame]1723 // 4) Find base register updates that can be merged into the load or store
1724 // as a base-reg writeback.
1725 // e.g.,
1726 // ldr x0, [x2]
1727 // add x2, x2, #4
1728 // ; becomes
1729 // ldr x0, [x2], #4
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1730 for (MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
1731 MBBI != E;) {
Evandro Menezes5ba804b2017-11-15 21:06:22 +0000[diff] [blame]1732 if (isMergeableLdStUpdate(*MBBI) && tryToMergeLdStUpdate(MBBI))
1733 Modified = true;
1734 else
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1735 ++MBBI;
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1736 }
1737
1738 return Modified;
1739}
1740
1741bool AArch64LoadStoreOpt::runOnMachineFunction(MachineFunction &Fn) {
Matthias Braunf1caa282017-12-15 22:22:58 +0000[diff] [blame]1742 if (skipFunction(Fn.getFunction()))
Andrew Kaylor1ac98bb2016-04-25 21:58:52 +0000[diff] [blame]1743 return false;
1744
Oliver Stannardd414c992015-11-10 11:04:18 +0000[diff] [blame]1745 Subtarget = &static_cast<const AArch64Subtarget &>(Fn.getSubtarget());
1746 TII = static_cast<const AArch64InstrInfo *>(Subtarget->getInstrInfo());
1747 TRI = Subtarget->getRegisterInfo();
Chad Rosiera69dcb62017-03-17 14:19:55 +0000[diff] [blame]1748 AA = &getAnalysis<AAResultsWrapperPass>().getAAResults();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1749
Chad Rosierbba881e2016-02-02 15:02:30 +0000[diff] [blame]1750 // Resize the modified and used register bitfield trackers. We do this once
1751 // per function and then clear the bitfield each time we optimize a load or
1752 // store.
1753 ModifiedRegs.resize(TRI->getNumRegs());
1754 UsedRegs.resize(TRI->getNumRegs());
1755
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1756 bool Modified = false;
Chad Rosier10c7aaa2016-11-11 14:10:12 +0000[diff] [blame]1757 bool enableNarrowZeroStOpt = !Subtarget->requiresStrictAlign();
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1758 for (auto &MBB : Fn)
Chad Rosierd6daac42016-11-07 15:27:22 +0000[diff] [blame]1759 Modified |= optimizeBlock(MBB, enableNarrowZeroStOpt);
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1760
1761 return Modified;
1762}
1763
Chad Rosier8ade0342016-11-11 19:52:45 +0000[diff] [blame]1764// FIXME: Do we need/want a pre-alloc pass like ARM has to try to keep loads and
1765// stores near one another? Note: The pre-RA instruction scheduler already has
1766// hooks to try and schedule pairable loads/stores together to improve pairing
1767// opportunities. Thus, pre-RA pairing pass may not be worth the effort.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1768
Chad Rosier3f8b09d2016-02-09 19:42:19 +0000[diff] [blame]1769// FIXME: When pairing store instructions it's very possible for this pass to
1770// hoist a store with a KILL marker above another use (without a KILL marker).
1771// The resulting IR is invalid, but nothing uses the KILL markers after this
1772// pass, so it's never caused a problem in practice.
1773
Chad Rosier43f5c842015-08-05 12:40:13 +0000[diff] [blame]1774/// createAArch64LoadStoreOptimizationPass - returns an instance of the
1775/// load / store optimization pass.
Tim Northover3b0846e2014-05-24 12:50:23 +0000[diff] [blame]1776FunctionPass *llvm::createAArch64LoadStoreOptimizationPass() {
1777 return new AArch64LoadStoreOpt();
1778}