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gerrit-public.fairphone.software / toolchain / llvm-project / 3cbe014027270091a946de3ed48ce1206e728596 / . / llvm / test / CodeGen / R600 / mul_uint24.ll
blob: a4139619bfae253a66634f0534d3e5fb4fed8c9f [file] [log] [blame]
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK
2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK
Tom Stellard70f13db2013-10-10 17:11:46 +0000[diff] [blame]3; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]4
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]5; EG-CHECK-LABEL: @u32_mul24
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]6; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]7; SI-CHECK-LABEL: @u32_mul24
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]8; SI-CHECK: V_MUL_U32_U24
9
10define void @u32_mul24(i32 addrspace(1)* %out, i32 %a, i32 %b) {
11entry:
12 %0 = shl i32 %a, 8
13 %a_24 = lshr i32 %0, 8
14 %1 = shl i32 %b, 8
15 %b_24 = lshr i32 %1, 8
16 %2 = mul i32 %a_24, %b_24
17 store i32 %2, i32 addrspace(1)* %out
18 ret void
19}
20
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]21; EG-CHECK-LABEL: @i16_mul24
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]22; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
23; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
24; The order of A and B does not matter.
25; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
26; The result must be sign-extended
Matt Arsenaultfae02982014-03-17 18:58:11 +0000[diff] [blame]27; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]28; EG-CHECK: 16
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]29; SI-CHECK-LABEL: @i16_mul24
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame]30; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
Matt Arsenaultfae02982014-03-17 18:58:11 +0000[diff] [blame]31; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 16,
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]32define void @i16_mul24(i32 addrspace(1)* %out, i16 %a, i16 %b) {
33entry:
34 %0 = mul i16 %a, %b
35 %1 = sext i16 %0 to i32
36 store i32 %1, i32 addrspace(1)* %out
37 ret void
38}
39
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]40; EG-CHECK-LABEL: @i8_mul24
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]41; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40
42; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44
43; The order of A and B does not matter.
44; EG-CHECK: MUL_UINT24 {{[* ]*}}T{{[0-9]}}.[[MUL_CHAN:[XYZW]]], [[A]], [[B]]
45; The result must be sign-extended
Matt Arsenaultfae02982014-03-17 18:58:11 +0000[diff] [blame]46; EG-CHECK: BFE_INT {{[* ]*}}T{{[0-9]}}.{{[XYZW]}}, PV.[[MUL_CHAN]], 0.0, literal.x
Tom Stellard82166022013-11-13 23:36:37 +0000[diff] [blame]47; SI-CHECK-LABEL: @i8_mul24
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame]48; SI-CHECK: V_MUL_U32_U24_e{{(32|64)}} [[MUL:v[0-9]]], {{[sv][0-9], [sv][0-9]}}
Matt Arsenaultfae02982014-03-17 18:58:11 +0000[diff] [blame]49; SI-CHECK: V_BFE_I32 v{{[0-9]}}, [[MUL]], 0, 8,
Tom Stellard41fc7852013-07-23 01:48:42 +0000[diff] [blame]50
51define void @i8_mul24(i32 addrspace(1)* %out, i8 %a, i8 %b) {
52entry:
53 %0 = mul i8 %a, %b
54 %1 = sext i8 %0 to i32
55 store i32 %1, i32 addrspace(1)* %out
56 ret void
57}