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gerrit-public.fairphone.software / toolchain / llvm-project / d63ac339483a4af48a2a3f445e442a4be1302c3d / . / llvm / test / CodeGen / X86 / fold-rmw-ops.ll
blob: e9457bbf4a657ce930a4fb7ba686f67690010666 [file] [log] [blame]
Chandler Carruth4b611a82017-08-25 22:50:52 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -verify-machineinstrs | FileCheck %s
3
4target triple = "x86_64-unknown-unknown"
5
6@g64 = external global i64, align 8
7@g32 = external global i32, align 4
8@g16 = external global i16, align 2
9@g8 = external global i8, align 1
10
11declare void @a()
12declare void @b()
13
14define void @add64_imm_br() nounwind {
15; CHECK-LABEL: add64_imm_br:
16; CHECK: # BB#0: # %entry
17; CHECK-NEXT: movl $42, %eax
18; CHECK-NEXT: addq %rax, {{.*}}(%rip)
19; CHECK-NEXT: js .LBB0_1
20; CHECK-NEXT: # BB#2: # %b
21; CHECK-NEXT: jmp b # TAILCALL
22; CHECK-NEXT: .LBB0_1: # %a
23; CHECK-NEXT: jmp a # TAILCALL
24entry:
25 %load1 = load i64, i64* @g64
26 %add = add nsw i64 %load1, 42
27 store i64 %add, i64* @g64
28 %cond = icmp slt i64 %add, 0
29 br i1 %cond, label %a, label %b
30
31a:
32 tail call void @a()
33 ret void
34
35b:
36 tail call void @b()
37 ret void
38}
39
40define void @add32_imm_br() nounwind {
41; CHECK-LABEL: add32_imm_br:
42; CHECK: # BB#0: # %entry
43; CHECK-NEXT: movl $42, %eax
44; CHECK-NEXT: addl %eax, {{.*}}(%rip)
45; CHECK-NEXT: js .LBB1_1
46; CHECK-NEXT: # BB#2: # %b
47; CHECK-NEXT: jmp b # TAILCALL
48; CHECK-NEXT: .LBB1_1: # %a
49; CHECK-NEXT: jmp a # TAILCALL
50entry:
51 %load1 = load i32, i32* @g32
52 %add = add nsw i32 %load1, 42
53 store i32 %add, i32* @g32
54 %cond = icmp slt i32 %add, 0
55 br i1 %cond, label %a, label %b
56
57a:
58 tail call void @a()
59 ret void
60
61b:
62 tail call void @b()
63 ret void
64}
65
66define void @add16_imm_br() nounwind {
67; CHECK-LABEL: add16_imm_br:
68; CHECK: # BB#0: # %entry
69; CHECK-NEXT: movw $42, %ax
70; CHECK-NEXT: addw %ax, {{.*}}(%rip)
71; CHECK-NEXT: js .LBB2_1
72; CHECK-NEXT: # BB#2: # %b
73; CHECK-NEXT: jmp b # TAILCALL
74; CHECK-NEXT: .LBB2_1: # %a
75; CHECK-NEXT: jmp a # TAILCALL
76entry:
77 %load1 = load i16, i16* @g16
78 %add = add nsw i16 %load1, 42
79 store i16 %add, i16* @g16
80 %cond = icmp slt i16 %add, 0
81 br i1 %cond, label %a, label %b
82
83a:
84 tail call void @a()
85 ret void
86
87b:
88 tail call void @b()
89 ret void
90}
91
92define void @add8_imm_br() nounwind {
93; CHECK-LABEL: add8_imm_br:
94; CHECK: # BB#0: # %entry
95; CHECK-NEXT: movb $42, %al
96; CHECK-NEXT: addb %al, {{.*}}(%rip)
97; CHECK-NEXT: js .LBB3_1
98; CHECK-NEXT: # BB#2: # %b
99; CHECK-NEXT: jmp b # TAILCALL
100; CHECK-NEXT: .LBB3_1: # %a
101; CHECK-NEXT: jmp a # TAILCALL
102entry:
103 %load1 = load i8, i8* @g8
104 %add = add nsw i8 %load1, 42
105 store i8 %add, i8* @g8
106 %cond = icmp slt i8 %add, 0
107 br i1 %cond, label %a, label %b
108
109a:
110 tail call void @a()
111 ret void
112
113b:
114 tail call void @b()
115 ret void
116}
117
118define void @add64_reg_br(i64 %arg) nounwind {
119; CHECK-LABEL: add64_reg_br:
120; CHECK: # BB#0: # %entry
121; CHECK-NEXT: addq %rdi, {{.*}}(%rip)
122; CHECK-NEXT: js .LBB4_1
123; CHECK-NEXT: # BB#2: # %b
124; CHECK-NEXT: jmp b # TAILCALL
125; CHECK-NEXT: .LBB4_1: # %a
126; CHECK-NEXT: jmp a # TAILCALL
127entry:
128 %load1 = load i64, i64* @g64
129 %add = add nsw i64 %load1, %arg
130 store i64 %add, i64* @g64
131 %cond = icmp slt i64 %add, 0
132 br i1 %cond, label %a, label %b
133
134a:
135 tail call void @a()
136 ret void
137
138b:
139 tail call void @b()
140 ret void
141}
142
143define void @add32_reg_br(i32 %arg) nounwind {
144; CHECK-LABEL: add32_reg_br:
145; CHECK: # BB#0: # %entry
146; CHECK-NEXT: addl %edi, {{.*}}(%rip)
147; CHECK-NEXT: js .LBB5_1
148; CHECK-NEXT: # BB#2: # %b
149; CHECK-NEXT: jmp b # TAILCALL
150; CHECK-NEXT: .LBB5_1: # %a
151; CHECK-NEXT: jmp a # TAILCALL
152entry:
153 %load1 = load i32, i32* @g32
154 %add = add nsw i32 %load1, %arg
155 store i32 %add, i32* @g32
156 %cond = icmp slt i32 %add, 0
157 br i1 %cond, label %a, label %b
158
159a:
160 tail call void @a()
161 ret void
162
163b:
164 tail call void @b()
165 ret void
166}
167
168define void @add16_reg_br(i16 %arg) nounwind {
169; CHECK-LABEL: add16_reg_br:
170; CHECK: # BB#0: # %entry
171; CHECK-NEXT: addw %di, {{.*}}(%rip)
172; CHECK-NEXT: js .LBB6_1
173; CHECK-NEXT: # BB#2: # %b
174; CHECK-NEXT: jmp b # TAILCALL
175; CHECK-NEXT: .LBB6_1: # %a
176; CHECK-NEXT: jmp a # TAILCALL
177entry:
178 %load1 = load i16, i16* @g16
179 %add = add nsw i16 %load1, %arg
180 store i16 %add, i16* @g16
181 %cond = icmp slt i16 %add, 0
182 br i1 %cond, label %a, label %b
183
184a:
185 tail call void @a()
186 ret void
187
188b:
189 tail call void @b()
190 ret void
191}
192
193define void @add8_reg_br(i8 %arg) nounwind {
194; CHECK-LABEL: add8_reg_br:
195; CHECK: # BB#0: # %entry
196; CHECK-NEXT: addb %dil, {{.*}}(%rip)
197; CHECK-NEXT: js .LBB7_1
198; CHECK-NEXT: # BB#2: # %b
199; CHECK-NEXT: jmp b # TAILCALL
200; CHECK-NEXT: .LBB7_1: # %a
201; CHECK-NEXT: jmp a # TAILCALL
202entry:
203 %load1 = load i8, i8* @g8
204 %add = add nsw i8 %load1, %arg
205 store i8 %add, i8* @g8
206 %cond = icmp slt i8 %add, 0
207 br i1 %cond, label %a, label %b
208
209a:
210 tail call void @a()
211 ret void
212
213b:
214 tail call void @b()
215 ret void
216}
217
218define void @sub64_imm_br() nounwind {
219; CHECK-LABEL: sub64_imm_br:
220; CHECK: # BB#0: # %entry
221; CHECK-NEXT: movq $-42, %rax
222; CHECK-NEXT: addq %rax, {{.*}}(%rip)
223; CHECK-NEXT: js .LBB8_1
224; CHECK-NEXT: # BB#2: # %b
225; CHECK-NEXT: jmp b # TAILCALL
226; CHECK-NEXT: .LBB8_1: # %a
227; CHECK-NEXT: jmp a # TAILCALL
228entry:
229 %load1 = load i64, i64* @g64
230 %sub = sub nsw i64 %load1, 42
231 store i64 %sub, i64* @g64
232 %cond = icmp slt i64 %sub, 0
233 br i1 %cond, label %a, label %b
234
235a:
236 tail call void @a()
237 ret void
238
239b:
240 tail call void @b()
241 ret void
242}
243
244define void @sub32_imm_br() nounwind {
245; CHECK-LABEL: sub32_imm_br:
246; CHECK: # BB#0: # %entry
247; CHECK-NEXT: movl $-42, %eax
248; CHECK-NEXT: addl %eax, {{.*}}(%rip)
249; CHECK-NEXT: js .LBB9_1
250; CHECK-NEXT: # BB#2: # %b
251; CHECK-NEXT: jmp b # TAILCALL
252; CHECK-NEXT: .LBB9_1: # %a
253; CHECK-NEXT: jmp a # TAILCALL
254entry:
255 %load1 = load i32, i32* @g32
256 %sub = sub nsw i32 %load1, 42
257 store i32 %sub, i32* @g32
258 %cond = icmp slt i32 %sub, 0
259 br i1 %cond, label %a, label %b
260
261a:
262 tail call void @a()
263 ret void
264
265b:
266 tail call void @b()
267 ret void
268}
269
270define void @sub16_imm_br() nounwind {
271; CHECK-LABEL: sub16_imm_br:
272; CHECK: # BB#0: # %entry
273; CHECK-NEXT: movw $-42, %ax
274; CHECK-NEXT: addw %ax, {{.*}}(%rip)
275; CHECK-NEXT: js .LBB10_1
276; CHECK-NEXT: # BB#2: # %b
277; CHECK-NEXT: jmp b # TAILCALL
278; CHECK-NEXT: .LBB10_1: # %a
279; CHECK-NEXT: jmp a # TAILCALL
280entry:
281 %load1 = load i16, i16* @g16
282 %sub = sub nsw i16 %load1, 42
283 store i16 %sub, i16* @g16
284 %cond = icmp slt i16 %sub, 0
285 br i1 %cond, label %a, label %b
286
287a:
288 tail call void @a()
289 ret void
290
291b:
292 tail call void @b()
293 ret void
294}
295
296define void @sub8_imm_br() nounwind {
297; CHECK-LABEL: sub8_imm_br:
298; CHECK: # BB#0: # %entry
299; CHECK-NEXT: movb $-42, %al
300; CHECK-NEXT: addb %al, {{.*}}(%rip)
301; CHECK-NEXT: js .LBB11_1
302; CHECK-NEXT: # BB#2: # %b
303; CHECK-NEXT: jmp b # TAILCALL
304; CHECK-NEXT: .LBB11_1: # %a
305; CHECK-NEXT: jmp a # TAILCALL
306entry:
307 %load1 = load i8, i8* @g8
308 %sub = sub nsw i8 %load1, 42
309 store i8 %sub, i8* @g8
310 %cond = icmp slt i8 %sub, 0
311 br i1 %cond, label %a, label %b
312
313a:
314 tail call void @a()
315 ret void
316
317b:
318 tail call void @b()
319 ret void
320}
321
322define void @sub64_reg_br(i64 %arg) nounwind {
323; CHECK-LABEL: sub64_reg_br:
324; CHECK: # BB#0: # %entry
325; CHECK-NEXT: subq %rdi, {{.*}}(%rip)
326; CHECK-NEXT: js .LBB12_1
327; CHECK-NEXT: # BB#2: # %b
328; CHECK-NEXT: jmp b # TAILCALL
329; CHECK-NEXT: .LBB12_1: # %a
330; CHECK-NEXT: jmp a # TAILCALL
331entry:
332 %load1 = load i64, i64* @g64
333 %sub = sub nsw i64 %load1, %arg
334 store i64 %sub, i64* @g64
335 %cond = icmp slt i64 %sub, 0
336 br i1 %cond, label %a, label %b
337
338a:
339 tail call void @a()
340 ret void
341
342b:
343 tail call void @b()
344 ret void
345}
346
347define void @sub32_reg_br(i32 %arg) nounwind {
348; CHECK-LABEL: sub32_reg_br:
349; CHECK: # BB#0: # %entry
350; CHECK-NEXT: subl %edi, {{.*}}(%rip)
351; CHECK-NEXT: js .LBB13_1
352; CHECK-NEXT: # BB#2: # %b
353; CHECK-NEXT: jmp b # TAILCALL
354; CHECK-NEXT: .LBB13_1: # %a
355; CHECK-NEXT: jmp a # TAILCALL
356entry:
357 %load1 = load i32, i32* @g32
358 %sub = sub nsw i32 %load1, %arg
359 store i32 %sub, i32* @g32
360 %cond = icmp slt i32 %sub, 0
361 br i1 %cond, label %a, label %b
362
363a:
364 tail call void @a()
365 ret void
366
367b:
368 tail call void @b()
369 ret void
370}
371
372define void @sub16_reg_br(i16 %arg) nounwind {
373; CHECK-LABEL: sub16_reg_br:
374; CHECK: # BB#0: # %entry
375; CHECK-NEXT: subw %di, {{.*}}(%rip)
376; CHECK-NEXT: js .LBB14_1
377; CHECK-NEXT: # BB#2: # %b
378; CHECK-NEXT: jmp b # TAILCALL
379; CHECK-NEXT: .LBB14_1: # %a
380; CHECK-NEXT: jmp a # TAILCALL
381entry:
382 %load1 = load i16, i16* @g16
383 %sub = sub nsw i16 %load1, %arg
384 store i16 %sub, i16* @g16
385 %cond = icmp slt i16 %sub, 0
386 br i1 %cond, label %a, label %b
387
388a:
389 tail call void @a()
390 ret void
391
392b:
393 tail call void @b()
394 ret void
395}
396
397define void @sub8_reg_br(i8 %arg) nounwind {
398; CHECK-LABEL: sub8_reg_br:
399; CHECK: # BB#0: # %entry
400; CHECK-NEXT: subb %dil, {{.*}}(%rip)
401; CHECK-NEXT: js .LBB15_1
402; CHECK-NEXT: # BB#2: # %b
403; CHECK-NEXT: jmp b # TAILCALL
404; CHECK-NEXT: .LBB15_1: # %a
405; CHECK-NEXT: jmp a # TAILCALL
406entry:
407 %load1 = load i8, i8* @g8
408 %sub = sub nsw i8 %load1, %arg
409 store i8 %sub, i8* @g8
410 %cond = icmp slt i8 %sub, 0
411 br i1 %cond, label %a, label %b
412
413a:
414 tail call void @a()
415 ret void
416
417b:
418 tail call void @b()
419 ret void
420}