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gerrit-public.fairphone.software / toolchain / llvm-project / 698e08f4cf4898c5966217b706d43fb2f764a7f5 / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: 25fda29c92ae11341338abbba82882bfe33947ac [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet09377232014-10-08 23:25:31 +0000[diff] [blame]82
83 // A vector type of the same width with element type i32. This is used to
84 // create the canonical constant zero node ImmAllZerosV.
85 ValueType i32VT = !cast<ValueType>("v" # !srl(Size, 5) # "i32");
86 dag ImmAllZerosV = (VT (bitconvert (i32VT immAllZerosV)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]87}
88
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]89def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
90def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]91def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
92def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]93def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
94def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]95
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]96// "x" in v32i8x_info means RC = VR256X
97def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
98def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
99def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
100def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
101
102def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
103def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
104def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
105def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
106
107class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
108 X86VectorVTInfo i128> {
109 X86VectorVTInfo info512 = i512;
110 X86VectorVTInfo info256 = i256;
111 X86VectorVTInfo info128 = i128;
112}
113
114def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
115 v16i8x_info>;
116def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
117 v8i16x_info>;
118def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
119 v4i32x_info>;
120def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
121 v2i64x_info>;
122
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]123// This multiclass generates the masking variants from the non-masking
124// variant. It only provides the assembly pieces for the masking variants.
125// It assumes custom ISel patterns for masking which can be provided as
126// template arguments.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]127multiclass AVX512_maskable_custom<bits<8> O, Format F,
128 dag Outs,
129 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
130 string OpcodeStr,
131 string AttSrcAsm, string IntelSrcAsm,
132 list<dag> Pattern,
133 list<dag> MaskingPattern,
134 list<dag> ZeroMaskingPattern,
135 string MaskingConstraint = "",
136 InstrItinClass itin = NoItinerary,
137 bit IsCommutable = 0> {
Adam Nemet52bb6cf2014-10-08 23:25:23 +0000[diff] [blame]138 let isCommutable = IsCommutable in
139 def NAME: AVX512<O, F, Outs, Ins,
140 OpcodeStr#"\t{"#AttSrcAsm#", $dst|"#
141 "$dst, "#IntelSrcAsm#"}",
142 Pattern, itin>;
143
144 // Prefer over VMOV*rrk Pat<>
145 let AddedComplexity = 20 in
146 def NAME#k: AVX512<O, F, Outs, MaskingIns,
147 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}}|"#
148 "$dst {${mask}}, "#IntelSrcAsm#"}",
149 MaskingPattern, itin>,
150 EVEX_K {
151 // In case of the 3src subclass this is overridden with a let.
152 string Constraints = MaskingConstraint;
153 }
154 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
155 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
156 OpcodeStr#"\t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
157 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
158 ZeroMaskingPattern,
159 itin>,
160 EVEX_KZ;
161}
162
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]163
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]164// Common base class of AVX512_maskable and AVX512_maskable_3src.
165multiclass AVX512_maskable_common<bits<8> O, Format F, X86VectorVTInfo _,
166 dag Outs,
167 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
168 string OpcodeStr,
169 string AttSrcAsm, string IntelSrcAsm,
170 dag RHS, dag MaskingRHS,
171 string MaskingConstraint = "",
172 InstrItinClass itin = NoItinerary,
173 bit IsCommutable = 0> :
174 AVX512_maskable_custom<O, F, Outs, Ins, MaskingIns, ZeroMaskingIns, OpcodeStr,
175 AttSrcAsm, IntelSrcAsm,
176 [(set _.RC:$dst, RHS)],
177 [(set _.RC:$dst, MaskingRHS)],
178 [(set _.RC:$dst,
179 (vselect _.KRCWM:$mask, RHS, _.ImmAllZerosV))],
180 MaskingConstraint, NoItinerary, IsCommutable>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]181
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]182// This multiclass generates the unconditional/non-masking, the masking and
183// the zero-masking variant of the instruction. In the masking case, the
184// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]185multiclass AVX512_maskable<bits<8> O, Format F, X86VectorVTInfo _,
186 dag Outs, dag Ins, string OpcodeStr,
187 string AttSrcAsm, string IntelSrcAsm,
188 dag RHS, InstrItinClass itin = NoItinerary,
189 bit IsCommutable = 0> :
190 AVX512_maskable_common<O, F, _, Outs, Ins,
191 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
192 !con((ins _.KRCWM:$mask), Ins),
193 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
194 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
195 "$src0 = $dst", itin, IsCommutable>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]196
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]197// Similar to AVX512_maskable but in this case one of the source operands
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]198// ($src1) is already tied to $dst so we just use that for the preserved
199// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
200// $src1.
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]201multiclass AVX512_maskable_3src<bits<8> O, Format F, X86VectorVTInfo _,
202 dag Outs, dag NonTiedIns, string OpcodeStr,
203 string AttSrcAsm, string IntelSrcAsm,
204 dag RHS> :
205 AVX512_maskable_common<O, F, _, Outs,
206 !con((ins _.RC:$src1), NonTiedIns),
207 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
208 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
209 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
210 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]211
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]212
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]213multiclass AVX512_maskable_in_asm<bits<8> O, Format F, X86VectorVTInfo _,
214 dag Outs, dag Ins,
215 string OpcodeStr,
216 string AttSrcAsm, string IntelSrcAsm,
217 list<dag> Pattern> :
218 AVX512_maskable_custom<O, F, Outs, Ins,
219 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
220 !con((ins _.KRCWM:$mask), Ins),
221 OpcodeStr, AttSrcAsm, IntelSrcAsm, Pattern, [], [],
222 "$src0 = $dst">;
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]223
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]224// Bitcasts between 512-bit vector types. Return the original type since
225// no instruction is needed for the conversion
226let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]227 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]228 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]229 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
230 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
231 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]232 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]233 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
234 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
235 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]236 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]237 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]238 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
239 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]240 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]241 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
242 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]243 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]244 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
245 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]246 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]247 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
248 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
249 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
250 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
251 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
252 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
253 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
254 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
255 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
256 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
257 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]258
259 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
260 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
261 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
262 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
263 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
264 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
265 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
266 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
267 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
268 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
269 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
270 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
271 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
272 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
273 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
274 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
275 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
276 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
277 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
278 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
279 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
280 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
281 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
282 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
283 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
284 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
285 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
286 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
287 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
288 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
289
290// Bitcasts between 256-bit vector types. Return the original type since
291// no instruction is needed for the conversion
292 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
293 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
294 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
295 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
296 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
297 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
298 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
299 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
300 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
301 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
302 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
303 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
304 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
305 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
306 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
307 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
308 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
309 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
310 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
311 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
312 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
313 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
314 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
315 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
316 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
317 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
318 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
319 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
320 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
321 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
322}
323
324//
325// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
326//
327
328let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
329 isPseudo = 1, Predicates = [HasAVX512] in {
330def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
331 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
332}
333
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]334let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]335def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
336def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
337def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]338}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]339
340//===----------------------------------------------------------------------===//
341// AVX-512 - VECTOR INSERT
342//
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]343
344multiclass vinsert_for_size<int Opcode,
345 X86VectorVTInfo From, X86VectorVTInfo To,
346 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
347 PatFrag vinsert_insert,
348 SDNodeXForm INSERT_get_vinsert_imm> {
349 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
350 def rr : AVX512AIi8<Opcode, MRMSrcReg, (outs VR512:$dst),
351 (ins VR512:$src1, From.RC:$src2, i8imm:$src3),
352 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
353 "$dst, $src1, $src2, $src3}",
Adam Nemet4dca3ce2014-10-02 23:18:30 +0000[diff] [blame]354 [(set To.RC:$dst, (vinsert_insert:$src3 (To.VT VR512:$src1),
355 (From.VT From.RC:$src2),
356 (iPTR imm)))]>,
357 EVEX_4V, EVEX_V512;
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]358
359 let mayLoad = 1 in
360 def rm : AVX512AIi8<Opcode, MRMSrcMem, (outs VR512:$dst),
361 (ins VR512:$src1, From.MemOp:$src2, i8imm:$src3),
362 "vinsert" # From.EltTypeName # "x4\t{$src3, $src2, $src1, $dst|"
363 "$dst, $src1, $src2, $src3}",
364 []>, EVEX_4V, EVEX_V512, EVEX_CD8<From.EltSize, CD8VT4>;
365 }
366
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]367 // Codegen pattern with the alternative types, e.g. v2i64 -> v8i64 for
368 // vinserti32x4
369 def : Pat<(vinsert_insert:$ins
370 (AltTo.VT VR512:$src1), (AltFrom.VT From.RC:$src2), (iPTR imm)),
371 (AltTo.VT (!cast<Instruction>(NAME # From.EltSize # "x4rr")
372 VR512:$src1, From.RC:$src2,
373 (INSERT_get_vinsert_imm VR512:$ins)))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]374}
375
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]376multiclass vinsert_for_type<ValueType EltVT32, int Opcode32,
377 ValueType EltVT64, int Opcode64> {
378 defm NAME # "32x4" : vinsert_for_size<Opcode32,
379 X86VectorVTInfo< 4, EltVT32, VR128X>,
380 X86VectorVTInfo<16, EltVT32, VR512>,
381 X86VectorVTInfo< 2, EltVT64, VR128X>,
382 X86VectorVTInfo< 8, EltVT64, VR512>,
383 vinsert128_insert,
384 INSERT_get_vinsert128_imm>;
385 defm NAME # "64x4" : vinsert_for_size<Opcode64,
386 X86VectorVTInfo< 4, EltVT64, VR256X>,
387 X86VectorVTInfo< 8, EltVT64, VR512>,
388 X86VectorVTInfo< 8, EltVT32, VR256>,
389 X86VectorVTInfo<16, EltVT32, VR512>,
390 vinsert256_insert,
391 INSERT_get_vinsert256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]392}
393
Adam Nemet4e2ef472014-10-02 23:18:28 +0000[diff] [blame]394defm VINSERTF : vinsert_for_type<f32, 0x18, f64, 0x1a>;
395defm VINSERTI : vinsert_for_type<i32, 0x38, i64, 0x3a>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]396
397// vinsertps - insert f32 to XMM
398def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]399 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]400 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]401 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]402 EVEX_4V;
403def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]404 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]405 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]406 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]407 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
408 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
409
410//===----------------------------------------------------------------------===//
411// AVX-512 VECTOR EXTRACT
412//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]413
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]414multiclass vextract_for_size<int Opcode,
415 X86VectorVTInfo From, X86VectorVTInfo To,
416 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
417 PatFrag vextract_extract,
418 SDNodeXForm EXTRACT_get_vextract_imm> {
419 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]420 defm rr : AVX512_maskable_in_asm<Opcode, MRMDestReg, To, (outs To.RC:$dst),
Adam Nemet2b5cdbb2014-10-08 23:25:33 +0000[diff] [blame]421 (ins VR512:$src1, i8imm:$idx),
422 "vextract" # To.EltTypeName # "x4",
423 "$idx, $src1", "$src1, $idx",
424 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
425 (iPTR imm)))]>,
426 AVX512AIi8Base, EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]427 let mayStore = 1 in
428 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
429 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
430 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
431 "$dst, $src1, $src2}",
432 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
433 }
434
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]435 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
436 // vextracti32x4
437 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
438 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
439 VR512:$src1,
440 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
441
442 // A 128/256-bit subvector extract from the first 512-bit vector position is
443 // a subregister copy that needs no instruction.
444 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
445 (To.VT
446 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
447
448 // And for the alternative types.
449 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
450 (AltTo.VT
451 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Adam Nemet47b2d5f2014-10-08 23:25:37 +0000[diff] [blame]452
453 // Intrinsic call with masking.
454 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
455 "x4_512")
456 VR512:$src1, (iPTR imm:$idx), To.RC:$src0, GR8:$mask),
457 (!cast<Instruction>(NAME # To.EltSize # "x4rrk") To.RC:$src0,
458 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
459 VR512:$src1, imm:$idx)>;
460
461 // Intrinsic call with zero-masking.
462 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
463 "x4_512")
464 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, GR8:$mask),
465 (!cast<Instruction>(NAME # To.EltSize # "x4rrkz")
466 (v4i1 (COPY_TO_REGCLASS GR8:$mask, VK4WM)),
467 VR512:$src1, imm:$idx)>;
468
469 // Intrinsic call without masking.
470 def : Pat<(!cast<Intrinsic>("int_x86_avx512_mask_vextract" # To.EltTypeName #
471 "x4_512")
472 VR512:$src1, (iPTR imm:$idx), To.ImmAllZerosV, (i8 -1)),
473 (!cast<Instruction>(NAME # To.EltSize # "x4rr")
474 VR512:$src1, imm:$idx)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]475}
476
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]477multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
478 ValueType EltVT64, int Opcode64> {
479 defm NAME # "32x4" : vextract_for_size<Opcode32,
480 X86VectorVTInfo<16, EltVT32, VR512>,
481 X86VectorVTInfo< 4, EltVT32, VR128X>,
482 X86VectorVTInfo< 8, EltVT64, VR512>,
483 X86VectorVTInfo< 2, EltVT64, VR128X>,
484 vextract128_extract,
485 EXTRACT_get_vextract128_imm>;
486 defm NAME # "64x4" : vextract_for_size<Opcode64,
487 X86VectorVTInfo< 8, EltVT64, VR512>,
488 X86VectorVTInfo< 4, EltVT64, VR256X>,
489 X86VectorVTInfo<16, EltVT32, VR512>,
490 X86VectorVTInfo< 8, EltVT32, VR256>,
491 vextract256_extract,
492 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]493}
494
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]495defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
496defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]497
498// A 128-bit subvector insert to the first 512-bit vector position
499// is a subregister copy that needs no instruction.
500def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
501 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
502 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
503 sub_ymm)>;
504def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
505 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
506 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
507 sub_ymm)>;
508def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
509 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
510 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
511 sub_ymm)>;
512def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
513 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
514 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
515 sub_ymm)>;
516
517def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
518 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
519def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
520 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
521def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
522 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
523def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
524 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
525
526// vextractps - extract 32 bits from XMM
527def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]528 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]529 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]530 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
531 EVEX;
532
533def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]534 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]535 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]536 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]537 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]538
539//===---------------------------------------------------------------------===//
540// AVX-512 BROADCAST
541//---
542multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
543 RegisterClass DestRC,
544 RegisterClass SrcRC, X86MemOperand x86memop> {
545 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]546 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]547 []>, EVEX;
548 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]549 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]550}
551let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]552 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]553 VR128X, f32mem>,
554 EVEX_V512, EVEX_CD8<32, CD8VT1>;
555}
556
557let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]558 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]559 VR128X, f64mem>,
560 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
561}
562
563def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
564 (VBROADCASTSSZrm addr:$src)>;
565def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
566 (VBROADCASTSDZrm addr:$src)>;
567
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]568def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
569 (VBROADCASTSSZrm addr:$src)>;
570def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
571 (VBROADCASTSDZrm addr:$src)>;
572
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]573multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
574 RegisterClass SrcRC, RegisterClass KRC> {
575 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]576 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]577 []>, EVEX, EVEX_V512;
578 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
579 (ins KRC:$mask, SrcRC:$src),
580 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]581 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]582 []>, EVEX, EVEX_V512, EVEX_KZ;
583}
584
585defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
586defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
587 VEX_W;
588
589def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
590 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
591
592def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
593 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
594
595def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
596 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]597def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
598 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]599def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
600 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]601def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
602 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]603
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]604def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
605 (VPBROADCASTDrZrr GR32:$src)>;
606def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
607 (VPBROADCASTQrZrr GR64:$src)>;
608
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]609def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
610 (v16i32 immAllZerosV), (i16 GR16:$mask))),
611 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
612def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
613 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
614 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
615
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]616multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
617 X86MemOperand x86memop, PatFrag ld_frag,
618 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
619 RegisterClass KRC> {
620 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]621 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]622 [(set DstRC:$dst,
623 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
624 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
625 VR128X:$src),
626 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]627 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]628 [(set DstRC:$dst,
629 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
630 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]631 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]632 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]633 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]634 [(set DstRC:$dst,
635 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
636 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
637 x86memop:$src),
638 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]639 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]640 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
641 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]642 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]643}
644
645defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
646 loadi32, VR512, v16i32, v4i32, VK16WM>,
647 EVEX_V512, EVEX_CD8<32, CD8VT1>;
648defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
649 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
650 EVEX_CD8<64, CD8VT1>;
651
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]652multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
653 X86MemOperand x86memop, PatFrag ld_frag,
654 RegisterClass KRC> {
655 let mayLoad = 1 in {
656 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
657 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
658 []>, EVEX;
659 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
660 x86memop:$src),
661 !strconcat(OpcodeStr,
662 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
663 []>, EVEX, EVEX_KZ;
664 }
665}
666
667defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
668 i128mem, loadv2i64, VK16WM>,
669 EVEX_V512, EVEX_CD8<32, CD8VT4>;
670defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
671 i256mem, loadv4i64, VK16WM>, VEX_W,
672 EVEX_V512, EVEX_CD8<64, CD8VT4>;
673
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]674def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
675 (VPBROADCASTDZrr VR128X:$src)>;
676def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
677 (VPBROADCASTQZrr VR128X:$src)>;
678
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]679def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
680 (VBROADCASTSSZrr VR128X:$src)>;
681def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
682 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]683
684def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
685 (VBROADCASTSSZrr VR128X:$src)>;
686def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
687 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]688
689// Provide fallback in case the load node that is used in the patterns above
690// is used by additional users, which prevents the pattern selection.
691def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
692 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
693def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
694 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
695
696
697let Predicates = [HasAVX512] in {
698def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
699 (EXTRACT_SUBREG
700 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
701 addr:$src)), sub_ymm)>;
702}
703//===----------------------------------------------------------------------===//
704// AVX-512 BROADCAST MASK TO VECTOR REGISTER
705//---
706
707multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
708 RegisterClass DstRC, RegisterClass KRC,
709 ValueType OpVT, ValueType SrcVT> {
710def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]711 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]712 []>, EVEX;
713}
714
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]715let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]716defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
717 VK16, v16i32, v16i1>, EVEX_V512;
718defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
719 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]720}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]721
722//===----------------------------------------------------------------------===//
723// AVX-512 - VPERM
724//
725// -- immediate form --
726multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
727 SDNode OpNode, PatFrag mem_frag,
728 X86MemOperand x86memop, ValueType OpVT> {
729 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
730 (ins RC:$src1, i8imm:$src2),
731 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]732 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]733 [(set RC:$dst,
734 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
735 EVEX;
736 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
737 (ins x86memop:$src1, i8imm:$src2),
738 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]739 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]740 [(set RC:$dst,
741 (OpVT (OpNode (mem_frag addr:$src1),
742 (i8 imm:$src2))))]>, EVEX;
743}
744
745defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
746 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
747let ExeDomain = SSEPackedDouble in
748defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
749 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
750
751// -- VPERM - register form --
752multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
753 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
754
755 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
756 (ins RC:$src1, RC:$src2),
757 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]758 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]759 [(set RC:$dst,
760 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
761
762 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
763 (ins RC:$src1, x86memop:$src2),
764 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]765 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]766 [(set RC:$dst,
767 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
768 EVEX_4V;
769}
770
771defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
772 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
773defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
774 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
775let ExeDomain = SSEPackedSingle in
776defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
777 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
778let ExeDomain = SSEPackedDouble in
779defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
780 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
781
782// -- VPERM2I - 3 source operands form --
783multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
784 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]785 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]786let Constraints = "$src1 = $dst" in {
787 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
788 (ins RC:$src1, RC:$src2, RC:$src3),
789 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]790 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]791 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]792 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]793 EVEX_4V;
794
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]795 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
796 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
797 !strconcat(OpcodeStr,
798 " \t{$src3, $src2, $dst {${mask}}|"
799 "$dst {${mask}}, $src2, $src3}"),
800 [(set RC:$dst, (OpVT (vselect KRC:$mask,
801 (OpNode RC:$src1, RC:$src2,
802 RC:$src3),
803 RC:$src1)))]>,
804 EVEX_4V, EVEX_K;
805
806 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
807 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
808 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
809 !strconcat(OpcodeStr,
810 " \t{$src3, $src2, $dst {${mask}} {z} |",
811 "$dst {${mask}} {z}, $src2, $src3}"),
812 [(set RC:$dst, (OpVT (vselect KRC:$mask,
813 (OpNode RC:$src1, RC:$src2,
814 RC:$src3),
815 (OpVT (bitconvert
816 (v16i32 immAllZerosV))))))]>,
817 EVEX_4V, EVEX_KZ;
818
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]819 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
820 (ins RC:$src1, RC:$src2, x86memop:$src3),
821 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]822 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]823 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]824 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]825 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]826
827 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
828 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
829 !strconcat(OpcodeStr,
830 " \t{$src3, $src2, $dst {${mask}}|"
831 "$dst {${mask}}, $src2, $src3}"),
832 [(set RC:$dst,
833 (OpVT (vselect KRC:$mask,
834 (OpNode RC:$src1, RC:$src2,
835 (mem_frag addr:$src3)),
836 RC:$src1)))]>,
837 EVEX_4V, EVEX_K;
838
839 let AddedComplexity = 10 in // Prefer over the rrkz variant
840 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
841 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
842 !strconcat(OpcodeStr,
843 " \t{$src3, $src2, $dst {${mask}} {z}|"
844 "$dst {${mask}} {z}, $src2, $src3}"),
845 [(set RC:$dst,
846 (OpVT (vselect KRC:$mask,
847 (OpNode RC:$src1, RC:$src2,
848 (mem_frag addr:$src3)),
849 (OpVT (bitconvert
850 (v16i32 immAllZerosV))))))]>,
851 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]852 }
853}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]854defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
855 i512mem, X86VPermiv3, v16i32, VK16WM>,
856 EVEX_V512, EVEX_CD8<32, CD8VF>;
857defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
858 i512mem, X86VPermiv3, v8i64, VK8WM>,
859 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
860defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
861 i512mem, X86VPermiv3, v16f32, VK16WM>,
862 EVEX_V512, EVEX_CD8<32, CD8VF>;
863defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
864 i512mem, X86VPermiv3, v8f64, VK8WM>,
865 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]866
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]867multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
868 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]869 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
870 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]871 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
872 OpVT, KRC> {
873 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
874 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
875 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]876
877 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
878 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
879 (!cast<Instruction>(NAME#rrk) VR512:$src1,
880 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]881}
882
883defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]884 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
885 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]886defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]887 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
888 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]889defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]890 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
891 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]892defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]893 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
894 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]895
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]896//===----------------------------------------------------------------------===//
897// AVX-512 - BLEND using mask
898//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]899multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]900 RegisterClass KRC, RegisterClass RC,
901 X86MemOperand x86memop, PatFrag mem_frag,
902 SDNode OpNode, ValueType vt> {
903 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]904 (ins KRC:$mask, RC:$src1, RC:$src2),
905 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]906 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]907 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]908 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]909 let mayLoad = 1 in
910 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
911 (ins KRC:$mask, RC:$src1, x86memop:$src2),
912 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]913 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]914 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]915}
916
917let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]918defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]919 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]920 memopv16f32, vselect, v16f32>,
921 EVEX_CD8<32, CD8VF>, EVEX_V512;
922let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]923defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]924 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]925 memopv8f64, vselect, v8f64>,
926 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
927
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]928def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
929 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]930 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]931 VR512:$src1, VR512:$src2)>;
932
933def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
934 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]935 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]936 VR512:$src1, VR512:$src2)>;
937
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]938defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]939 VK16WM, VR512, f512mem,
940 memopv16i32, vselect, v16i32>,
941 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]942
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]943defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]944 VK8WM, VR512, f512mem,
945 memopv8i64, vselect, v8i64>,
946 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]947
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]948def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
949 (v16i32 VR512:$src2), (i16 GR16:$mask))),
950 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
951 VR512:$src1, VR512:$src2)>;
952
953def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
954 (v8i64 VR512:$src2), (i8 GR8:$mask))),
955 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
956 VR512:$src1, VR512:$src2)>;
957
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]958let Predicates = [HasAVX512] in {
959def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
960 (v8f32 VR256X:$src2))),
961 (EXTRACT_SUBREG
962 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
963 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
964 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
965
966def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
967 (v8i32 VR256X:$src2))),
968 (EXTRACT_SUBREG
969 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
970 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
971 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
972}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]973//===----------------------------------------------------------------------===//
974// Compare Instructions
975//===----------------------------------------------------------------------===//
976
977// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
978multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
979 Operand CC, SDNode OpNode, ValueType VT,
980 PatFrag ld_frag, string asm, string asm_alt> {
981 def rr : AVX512Ii8<0xC2, MRMSrcReg,
982 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
983 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
984 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
985 def rm : AVX512Ii8<0xC2, MRMSrcMem,
986 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
987 [(set VK1:$dst, (OpNode (VT RC:$src1),
988 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]989 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]990 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
991 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
992 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
993 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
994 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
995 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
996 }
997}
998
999let Predicates = [HasAVX512] in {
1000defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
1001 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1002 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1003 XS;
1004defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
1005 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1006 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
1007 XD, VEX_W;
1008}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1009
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1010multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
1011 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1012 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1013 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1014 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1015 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1016 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1017 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1018 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1019 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1021 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1022 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1023 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1024 def rrk : AVX512BI<opc, MRMSrcReg,
1025 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1026 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1027 "$dst {${mask}}, $src1, $src2}"),
1028 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1029 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1030 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1031 let mayLoad = 1 in
1032 def rmk : AVX512BI<opc, MRMSrcMem,
1033 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1034 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1035 "$dst {${mask}}, $src1, $src2}"),
1036 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1037 (OpNode (_.VT _.RC:$src1),
1038 (_.VT (bitconvert
1039 (_.LdFrag addr:$src2))))))],
1040 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1041}
1042
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1043multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1044 X86VectorVTInfo _> :
1045 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1046 let mayLoad = 1 in {
1047 def rmb : AVX512BI<opc, MRMSrcMem,
1048 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1049 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1050 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1051 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1052 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1053 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1054 def rmbk : AVX512BI<opc, MRMSrcMem,
1055 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1056 _.ScalarMemOp:$src2),
1057 !strconcat(OpcodeStr,
1058 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1059 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1060 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1061 (OpNode (_.VT _.RC:$src1),
1062 (X86VBroadcast
1063 (_.ScalarLdFrag addr:$src2)))))],
1064 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1065 }
1066}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1067
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1068multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1069 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1070 let Predicates = [prd] in
1071 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1072 EVEX_V512;
1073
1074 let Predicates = [prd, HasVLX] in {
1075 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1076 EVEX_V256;
1077 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1078 EVEX_V128;
1079 }
1080}
1081
1082multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1083 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1084 Predicate prd> {
1085 let Predicates = [prd] in
1086 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1087 EVEX_V512;
1088
1089 let Predicates = [prd, HasVLX] in {
1090 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1091 EVEX_V256;
1092 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1093 EVEX_V128;
1094 }
1095}
1096
1097defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1098 avx512vl_i8_info, HasBWI>,
1099 EVEX_CD8<8, CD8VF>;
1100
1101defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1102 avx512vl_i16_info, HasBWI>,
1103 EVEX_CD8<16, CD8VF>;
1104
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1105defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1106 avx512vl_i32_info, HasAVX512>,
1107 EVEX_CD8<32, CD8VF>;
1108
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1109defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1110 avx512vl_i64_info, HasAVX512>,
1111 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1112
1113defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1114 avx512vl_i8_info, HasBWI>,
1115 EVEX_CD8<8, CD8VF>;
1116
1117defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1118 avx512vl_i16_info, HasBWI>,
1119 EVEX_CD8<16, CD8VF>;
1120
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1121defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1122 avx512vl_i32_info, HasAVX512>,
1123 EVEX_CD8<32, CD8VF>;
1124
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1125defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1126 avx512vl_i64_info, HasAVX512>,
1127 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1128
1129def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1130 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1131 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1132 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1133
1134def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1135 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1136 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1137 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1138
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1139multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1140 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1141 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1142 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1143 !strconcat("vpcmp${cc}", Suffix,
1144 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1145 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1146 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1147 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1148 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1149 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1150 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1151 !strconcat("vpcmp${cc}", Suffix,
1152 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1153 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1154 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1155 imm:$cc))],
1156 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1157 def rrik : AVX512AIi8<opc, MRMSrcReg,
1158 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1159 AVXCC:$cc),
1160 !strconcat("vpcmp${cc}", Suffix,
1161 "\t{$src2, $src1, $dst {${mask}}|",
1162 "$dst {${mask}}, $src1, $src2}"),
1163 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1164 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1165 imm:$cc)))],
1166 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1167 let mayLoad = 1 in
1168 def rmik : AVX512AIi8<opc, MRMSrcMem,
1169 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1170 AVXCC:$cc),
1171 !strconcat("vpcmp${cc}", Suffix,
1172 "\t{$src2, $src1, $dst {${mask}}|",
1173 "$dst {${mask}}, $src1, $src2}"),
1174 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1175 (OpNode (_.VT _.RC:$src1),
1176 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1177 imm:$cc)))],
1178 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1179
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1180 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1181 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1182 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1183 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1184 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1185 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1186 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1187 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1188 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1189 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1190 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1191 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1192 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1193 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1194 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1195 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1196 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1197 "$dst {${mask}}, $src1, $src2, $cc}"),
1198 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1199 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1200 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1201 i8imm:$cc),
1202 !strconcat("vpcmp", Suffix,
1203 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1204 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1205 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1206 }
1207}
1208
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1209multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1210 X86VectorVTInfo _> :
1211 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1212 let mayLoad = 1 in {
1213 def rmib : AVX512AIi8<opc, MRMSrcMem,
1214 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1215 AVXCC:$cc),
1216 !strconcat("vpcmp${cc}", Suffix,
1217 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1218 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1219 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1220 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1221 imm:$cc))],
1222 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1223 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1224 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1225 _.ScalarMemOp:$src2, AVXCC:$cc),
1226 !strconcat("vpcmp${cc}", Suffix,
1227 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1228 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1229 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1230 (OpNode (_.VT _.RC:$src1),
1231 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1232 imm:$cc)))],
1233 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1234 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1235
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1236 // Accept explicit immediate argument form instead of comparison code.
1237 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1238 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1239 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1240 i8imm:$cc),
1241 !strconcat("vpcmp", Suffix,
1242 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1243 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1244 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1245 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1246 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1247 _.ScalarMemOp:$src2, i8imm:$cc),
1248 !strconcat("vpcmp", Suffix,
1249 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1250 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1251 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1252 }
1253}
1254
1255multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1256 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1257 let Predicates = [prd] in
1258 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1259
1260 let Predicates = [prd, HasVLX] in {
1261 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1262 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1263 }
1264}
1265
1266multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1267 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1268 let Predicates = [prd] in
1269 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1270 EVEX_V512;
1271
1272 let Predicates = [prd, HasVLX] in {
1273 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1274 EVEX_V256;
1275 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1276 EVEX_V128;
1277 }
1278}
1279
1280defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1281 HasBWI>, EVEX_CD8<8, CD8VF>;
1282defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1283 HasBWI>, EVEX_CD8<8, CD8VF>;
1284
1285defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1286 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1287defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1288 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1289
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1290defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1291 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1292defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1293 HasAVX512>, EVEX_CD8<32, CD8VF>;
1294
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1295defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1296 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1297defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1298 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1299
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1300// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1301multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1302 X86MemOperand x86memop, ValueType vt,
1303 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1304 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1305 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1306 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1307 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1308 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1309 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1310 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1311 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1312 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1313 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1314 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1315 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1316 !strconcat("vcmp${cc}", suffix,
1317 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1318 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1319 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1320
1321 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1322 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1323 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1324 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1325 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1326 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1327 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1328 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1329 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1330 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1331 }
1332}
1333
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1334defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1335 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1336 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1337defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1338 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1339 EVEX_CD8<64, CD8VF>;
1340
1341def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1342 (COPY_TO_REGCLASS (VCMPPSZrri
1343 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1344 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1345 imm:$cc), VK8)>;
1346def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1347 (COPY_TO_REGCLASS (VPCMPDZrri
1348 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1349 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1350 imm:$cc), VK8)>;
1351def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1352 (COPY_TO_REGCLASS (VPCMPUDZrri
1353 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1354 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1355 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1356
1357def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1358 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1359 FROUND_NO_EXC)),
1360 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1361 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1362
1363def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1364 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1365 FROUND_NO_EXC)),
1366 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1367 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1368
1369def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1370 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1371 FROUND_CURRENT)),
1372 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1373 (I8Imm imm:$cc)), GR16)>;
1374
1375def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1376 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1377 FROUND_CURRENT)),
1378 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1379 (I8Imm imm:$cc)), GR8)>;
1380
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1381// Mask register copy, including
1382// - copy between mask registers
1383// - load/store mask registers
1384// - copy from GPR to mask register and vice versa
1385//
1386multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1387 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1388 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1389 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1390 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1391 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1392 let mayLoad = 1 in
1393 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1394 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1395 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1396 let mayStore = 1 in
1397 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1398 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1399 }
1400}
1401
1402multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1403 string OpcodeStr,
1404 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1405 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1406 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1407 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1408 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1409 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1410 }
1411}
1412
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1413let Predicates = [HasDQI] in
1414 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1415 i8mem>,
1416 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1417 VEX, PD;
1418
1419let Predicates = [HasAVX512] in
1420 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1421 i16mem>,
1422 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1423 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1424
1425let Predicates = [HasBWI] in {
1426 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1427 i32mem>, VEX, PD, VEX_W;
1428 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1429 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1430}
1431
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1432let Predicates = [HasBWI] in {
1433 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1434 i64mem>, VEX, PS, VEX_W;
1435 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1436 VEX, XD, VEX_W;
1437}
1438
1439// GR from/to mask register
1440let Predicates = [HasDQI] in {
1441 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1442 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1443 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1444 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1445}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1446let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1447 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1448 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1449 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1450 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1451}
1452let Predicates = [HasBWI] in {
1453 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1454 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1455}
1456let Predicates = [HasBWI] in {
1457 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1458 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1459}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1460
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1461// Load/store kreg
1462let Predicates = [HasDQI] in {
1463 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1464 (KMOVBmk addr:$dst, VK8:$src)>;
1465}
1466let Predicates = [HasAVX512] in {
1467 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1468 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1469 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1470 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1471 def : Pat<(i1 (load addr:$src)),
1472 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1473 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1474 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1475}
1476let Predicates = [HasBWI] in {
1477 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1478 (KMOVDmk addr:$dst, VK32:$src)>;
1479}
1480let Predicates = [HasBWI] in {
1481 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1482 (KMOVQmk addr:$dst, VK64:$src)>;
1483}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1484
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1485let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1486 def : Pat<(i1 (trunc (i64 GR64:$src))),
1487 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1488 (i32 1))), VK1)>;
1489
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1490 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1491 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1492
1493 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1494 (COPY_TO_REGCLASS
1495 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1496 VK1)>;
1497 def : Pat<(i1 (trunc (i16 GR16:$src))),
1498 (COPY_TO_REGCLASS
1499 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1500 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1501
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1502 def : Pat<(i32 (zext VK1:$src)),
1503 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1504 def : Pat<(i8 (zext VK1:$src)),
1505 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1506 (AND32ri (KMOVWrk
1507 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1508 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1509 (AND64ri8 (SUBREG_TO_REG (i64 0),
1510 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1511 def : Pat<(i16 (zext VK1:$src)),
1512 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1513 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1514 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1515 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1516 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1517 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1518 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1519}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1520let Predicates = [HasBWI] in {
1521 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1522 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1523 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1524 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1525}
1526
1527
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1528// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1529let Predicates = [HasAVX512] in {
1530 // GR from/to 8-bit mask without native support
1531 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1532 (COPY_TO_REGCLASS
1533 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1534 VK8)>;
1535 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1536 (EXTRACT_SUBREG
1537 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1538 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1539
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1540 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1541 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1542 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1543 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1544}
1545let Predicates = [HasBWI] in {
1546 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1547 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1548 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1549 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1550}
1551
1552// Mask unary operation
1553// - KNOT
1554multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1555 RegisterClass KRC, SDPatternOperator OpNode,
1556 Predicate prd> {
1557 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1558 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1559 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1560 [(set KRC:$dst, (OpNode KRC:$src))]>;
1561}
1562
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1563multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1564 SDPatternOperator OpNode> {
1565 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1566 HasDQI>, VEX, PD;
1567 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1568 HasAVX512>, VEX, PS;
1569 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1570 HasBWI>, VEX, PD, VEX_W;
1571 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1572 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1573}
1574
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1575defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1576
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1577multiclass avx512_mask_unop_int<string IntName, string InstName> {
1578 let Predicates = [HasAVX512] in
1579 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1580 (i16 GR16:$src)),
1581 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1582 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1583}
1584defm : avx512_mask_unop_int<"knot", "KNOT">;
1585
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1586let Predicates = [HasDQI] in
1587def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1588let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1589def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1590let Predicates = [HasBWI] in
1591def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1592let Predicates = [HasBWI] in
1593def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1594
1595// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1596let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1597def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1598 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1599
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1600def : Pat<(not VK8:$src),
1601 (COPY_TO_REGCLASS
1602 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1603}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1604
1605// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1606// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1607multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1608 RegisterClass KRC, SDPatternOperator OpNode,
1609 Predicate prd> {
1610 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1611 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1612 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1613 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1614 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1615}
1616
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1617multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1618 SDPatternOperator OpNode> {
1619 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1620 HasDQI>, VEX_4V, VEX_L, PD;
1621 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1622 HasAVX512>, VEX_4V, VEX_L, PS;
1623 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1624 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1625 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1626 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1627}
1628
1629def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1630def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1631
1632let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1633 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1634 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1635 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1636 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1637}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1638let isCommutable = 0 in
1639 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1640
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1641def : Pat<(xor VK1:$src1, VK1:$src2),
1642 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1643 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1644
1645def : Pat<(or VK1:$src1, VK1:$src2),
1646 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1647 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1648
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1649def : Pat<(and VK1:$src1, VK1:$src2),
1650 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1651 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1652
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1653multiclass avx512_mask_binop_int<string IntName, string InstName> {
1654 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1655 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1656 (i16 GR16:$src1), (i16 GR16:$src2)),
1657 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1658 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1659 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1660}
1661
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1662defm : avx512_mask_binop_int<"kand", "KAND">;
1663defm : avx512_mask_binop_int<"kandn", "KANDN">;
1664defm : avx512_mask_binop_int<"kor", "KOR">;
1665defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1666defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1667
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1668// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1669multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1670 let Predicates = [HasAVX512] in
1671 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1672 (COPY_TO_REGCLASS
1673 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1674 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1675}
1676
1677defm : avx512_binop_pat<and, KANDWrr>;
1678defm : avx512_binop_pat<andn, KANDNWrr>;
1679defm : avx512_binop_pat<or, KORWrr>;
1680defm : avx512_binop_pat<xnor, KXNORWrr>;
1681defm : avx512_binop_pat<xor, KXORWrr>;
1682
1683// Mask unpacking
1684multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1685 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1686 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1687 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1688 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1689 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1690}
1691
1692multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1693 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1694 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1695}
1696
1697defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1698def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1699 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1700 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1701
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1702
1703multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1704 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1705 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1706 (i16 GR16:$src1), (i16 GR16:$src2)),
1707 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1708 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1709 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1710}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1711defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1712
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1713// Mask bit testing
1714multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1715 SDNode OpNode> {
1716 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1717 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1718 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1719 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1720}
1721
1722multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1723 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1724 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1725}
1726
1727defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1728
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1729def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1730 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1731 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1732
1733// Mask shift
1734multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1735 SDNode OpNode> {
1736 let Predicates = [HasAVX512] in
1737 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1738 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1739 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1740 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1741}
1742
1743multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1744 SDNode OpNode> {
1745 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1746 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1747}
1748
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1749defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1750defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1751
1752// Mask setting all 0s or 1s
1753multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1754 let Predicates = [HasAVX512] in
1755 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1756 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1757 [(set KRC:$dst, (VT Val))]>;
1758}
1759
1760multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1761 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1762 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1763}
1764
1765defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1766defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1767
1768// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1769let Predicates = [HasAVX512] in {
1770 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1771 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1772 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1773 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1774 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1775}
1776def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1777 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1778
1779def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1780 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1781
1782def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1783 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1784
Robert Khasanov5aa44452014-09-30 11:41:54 +0000[diff] [blame]1785let Predicates = [HasVLX] in {
1786 def : Pat<(v8i1 (insert_subvector undef, (v4i1 VK4:$src), (iPTR 0))),
1787 (v8i1 (COPY_TO_REGCLASS VK4:$src, VK8))>;
1788 def : Pat<(v8i1 (insert_subvector undef, (v2i1 VK2:$src), (iPTR 0))),
1789 (v8i1 (COPY_TO_REGCLASS VK2:$src, VK8))>;
1790 def : Pat<(v4i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1791 (v4i1 (COPY_TO_REGCLASS VK8:$src, VK4))>;
1792 def : Pat<(v2i1 (extract_subvector (v8i1 VK8:$src), (iPTR 0))),
1793 (v2i1 (COPY_TO_REGCLASS VK8:$src, VK2))>;
1794}
1795
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1796def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1797 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1798
1799def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1800 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1801//===----------------------------------------------------------------------===//
1802// AVX-512 - Aligned and unaligned load and store
1803//
1804
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1805multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1806 RegisterClass KRC, RegisterClass RC,
1807 ValueType vt, ValueType zvt, X86MemOperand memop,
1808 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1809let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1810 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1811 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1812 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1813 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1814 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1815 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1816 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1817 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1818 SchedRW = [WriteLoad] in
1819 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1820 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1821 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1822 d>, EVEX;
1823
1824 let AddedComplexity = 20 in {
1825 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1826 let hasSideEffects = 0 in
1827 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1828 (ins RC:$src0, KRC:$mask, RC:$src1),
1829 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1830 "${dst} {${mask}}, $src1}"),
1831 [(set RC:$dst, (vt (vselect KRC:$mask,
1832 (vt RC:$src1),
1833 (vt RC:$src0))))],
1834 d>, EVEX, EVEX_K;
1835 let mayLoad = 1, SchedRW = [WriteLoad] in
1836 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1837 (ins RC:$src0, KRC:$mask, memop:$src1),
1838 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1839 "${dst} {${mask}}, $src1}"),
1840 [(set RC:$dst, (vt
1841 (vselect KRC:$mask,
1842 (vt (bitconvert (ld_frag addr:$src1))),
1843 (vt RC:$src0))))],
1844 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1845 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1846 let mayLoad = 1, SchedRW = [WriteLoad] in
1847 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1848 (ins KRC:$mask, memop:$src),
1849 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1850 "${dst} {${mask}} {z}, $src}"),
1851 [(set RC:$dst, (vt
1852 (vselect KRC:$mask,
1853 (vt (bitconvert (ld_frag addr:$src))),
1854 (vt (bitconvert (zvt immAllZerosV))))))],
1855 d>, EVEX, EVEX_KZ;
1856 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1857}
1858
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1859multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1860 string elty, string elsz, string vsz512,
1861 string vsz256, string vsz128, Domain d,
1862 Predicate prd, bit IsReMaterializable = 1> {
1863 let Predicates = [prd] in
1864 defm Z : avx512_load<opc, OpcodeStr,
1865 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1866 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1867 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1868 !cast<X86MemOperand>(elty##"512mem"), d,
1869 IsReMaterializable>, EVEX_V512;
1870
1871 let Predicates = [prd, HasVLX] in {
1872 defm Z256 : avx512_load<opc, OpcodeStr,
1873 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1874 "v"##vsz256##elty##elsz, "v4i64")),
1875 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1876 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1877 !cast<X86MemOperand>(elty##"256mem"), d,
1878 IsReMaterializable>, EVEX_V256;
1879
1880 defm Z128 : avx512_load<opc, OpcodeStr,
1881 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1882 "v"##vsz128##elty##elsz, "v2i64")),
1883 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1884 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1885 !cast<X86MemOperand>(elty##"128mem"), d,
1886 IsReMaterializable>, EVEX_V128;
1887 }
1888}
1889
1890
1891multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1892 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1893 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1894 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1895 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1896 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1897 EVEX;
1898 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1899 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1900 (ins RC:$src1, KRC:$mask, RC:$src2),
1901 !strconcat(OpcodeStr,
1902 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1903 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1904 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1905 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1906 !strconcat(OpcodeStr,
1907 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1908 [], d>, EVEX, EVEX_KZ;
1909 }
1910 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1911 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1912 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1913 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1914 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1915 (ins memop:$dst, KRC:$mask, RC:$src),
1916 !strconcat(OpcodeStr,
1917 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1918 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1919 }
1920}
1921
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1922
1923multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1924 string st_suff_512, string st_suff_256,
1925 string st_suff_128, string elty, string elsz,
1926 string vsz512, string vsz256, string vsz128,
1927 Domain d, Predicate prd> {
1928 let Predicates = [prd] in
1929 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1930 !cast<ValueType>("v"##vsz512##elty##elsz),
1931 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1932 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1933
1934 let Predicates = [prd, HasVLX] in {
1935 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1936 !cast<ValueType>("v"##vsz256##elty##elsz),
1937 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1938 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1939
1940 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1941 !cast<ValueType>("v"##vsz128##elty##elsz),
1942 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1943 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1944 }
1945}
1946
1947defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1948 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1949 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1950 "512", "256", "", "f", "32", "16", "8", "4",
1951 SSEPackedSingle, HasAVX512>,
1952 PS, EVEX_CD8<32, CD8VF>;
1953
1954defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1955 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1956 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1957 "512", "256", "", "f", "64", "8", "4", "2",
1958 SSEPackedDouble, HasAVX512>,
1959 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1960
1961defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1962 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1963 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1964 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1965 PS, EVEX_CD8<32, CD8VF>;
1966
1967defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1968 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1969 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1970 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1971 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1972
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1973def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1974 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1975 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1976
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1977def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1978 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1979 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1980
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1981def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1982 GR16:$mask),
1983 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1984 VR512:$src)>;
1985def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1986 GR8:$mask),
1987 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1988 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1989
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1990defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1991 "16", "8", "4", SSEPackedInt, HasAVX512>,
1992 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1993 "512", "256", "", "i", "32", "16", "8", "4",
1994 SSEPackedInt, HasAVX512>,
1995 PD, EVEX_CD8<32, CD8VF>;
1996
1997defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1998 "8", "4", "2", SSEPackedInt, HasAVX512>,
1999 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
2000 "512", "256", "", "i", "64", "8", "4", "2",
2001 SSEPackedInt, HasAVX512>,
2002 PD, VEX_W, EVEX_CD8<64, CD8VF>;
2003
2004defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
2005 "64", "32", "16", SSEPackedInt, HasBWI>,
2006 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
2007 "i", "8", "64", "32", "16", SSEPackedInt,
2008 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
2009
2010defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
2011 "32", "16", "8", SSEPackedInt, HasBWI>,
2012 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
2013 "i", "16", "32", "16", "8", SSEPackedInt,
2014 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
2015
2016defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
2017 "16", "8", "4", SSEPackedInt, HasAVX512>,
2018 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
2019 "i", "32", "16", "8", "4", SSEPackedInt,
2020 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
2021
2022defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
2023 "8", "4", "2", SSEPackedInt, HasAVX512>,
2024 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2025 "i", "64", "8", "4", "2", SSEPackedInt,
2026 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2027
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2028def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2029 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2030 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2031
2032def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2033 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2034 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2035
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2036def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2037 GR16:$mask),
2038 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2039 VR512:$src)>;
2040def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2041 GR8:$mask),
2042 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2043 VR512:$src)>;
2044
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2045let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2046def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2047 (bc_v8i64 (v16i32 immAllZerosV)))),
2048 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2049
2050def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2051 (v8i64 VR512:$src))),
2052 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2053 VK8), VR512:$src)>;
2054
2055def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2056 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2057 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2058
2059def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2060 (v16i32 VR512:$src))),
2061 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2062}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2063
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2064// Move Int Doubleword to Packed Double Int
2065//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2066def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2067 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2068 [(set VR128X:$dst,
2069 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2070 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2071def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2072 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2073 [(set VR128X:$dst,
2074 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2075 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2076def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2077 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2078 [(set VR128X:$dst,
2079 (v2i64 (scalar_to_vector GR64:$src)))],
2080 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2081let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2082def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2083 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2084 [(set FR64:$dst, (bitconvert GR64:$src))],
2085 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2086def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2087 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2088 [(set GR64:$dst, (bitconvert FR64:$src))],
2089 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2090}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2091def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2092 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2093 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2094 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2095 EVEX_CD8<64, CD8VT1>;
2096
2097// Move Int Doubleword to Single Scalar
2098//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2099let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2100def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2101 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2102 [(set FR32X:$dst, (bitconvert GR32:$src))],
2103 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2104
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2105def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2106 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2107 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2108 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2109}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2110
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2111// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2112//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2113def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2114 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2115 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2116 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2117 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2118def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2119 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2120 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2121 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2122 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2123 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2124
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2125// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2126//
2127def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2128 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2129 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2130 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2131 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2132 Requires<[HasAVX512, In64BitMode]>;
2133
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2134def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2135 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2136 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2137 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2138 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2139 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2140 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2141
2142// Move Scalar Single to Double Int
2143//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2144let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2145def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2146 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2147 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2148 [(set GR32:$dst, (bitconvert FR32X:$src))],
2149 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2150def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2151 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2152 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2153 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2154 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2155}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2156
2157// Move Quadword Int to Packed Quadword Int
2158//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2159def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2160 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2161 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2162 [(set VR128X:$dst,
2163 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2164 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2165
2166//===----------------------------------------------------------------------===//
2167// AVX-512 MOVSS, MOVSD
2168//===----------------------------------------------------------------------===//
2169
2170multiclass avx512_move_scalar <string asm, RegisterClass RC,
2171 SDNode OpNode, ValueType vt,
2172 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2173 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2174 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2175 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2176 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2177 (scalar_to_vector RC:$src2))))],
2178 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2179 let Constraints = "$src1 = $dst" in
2180 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2181 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2182 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2183 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2184 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2185 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2186 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2187 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2188 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2189 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2190 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2191 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2192 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2193 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2194 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2195 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2196 [], IIC_SSE_MOV_S_MR>,
2197 EVEX, VEX_LIG, EVEX_K;
2198 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2199 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2200}
2201
2202let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2203defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2204 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2205
2206let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2207defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2208 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2209
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2210def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2211 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2212 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2213
2214def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2215 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2216 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2217
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2218def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2219 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2220 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2221
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2222// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2223let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2224 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2225 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2226 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2227 IIC_SSE_MOV_S_RR>,
2228 XS, EVEX_4V, VEX_LIG;
2229 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2230 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2231 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2232 IIC_SSE_MOV_S_RR>,
2233 XD, EVEX_4V, VEX_LIG, VEX_W;
2234}
2235
2236let Predicates = [HasAVX512] in {
2237 let AddedComplexity = 15 in {
2238 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2239 // MOVS{S,D} to the lower bits.
2240 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2241 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2242 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2243 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2244 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2245 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2246 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2247 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2248
2249 // Move low f32 and clear high bits.
2250 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2251 (SUBREG_TO_REG (i32 0),
2252 (VMOVSSZrr (v4f32 (V_SET0)),
2253 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2254 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2255 (SUBREG_TO_REG (i32 0),
2256 (VMOVSSZrr (v4i32 (V_SET0)),
2257 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2258 }
2259
2260 let AddedComplexity = 20 in {
2261 // MOVSSrm zeros the high parts of the register; represent this
2262 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2263 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2264 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2265 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2266 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2267 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2268 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2269
2270 // MOVSDrm zeros the high parts of the register; represent this
2271 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2272 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2273 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2274 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2275 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2276 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2277 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2278 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2279 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2280 def : Pat<(v2f64 (X86vzload addr:$src)),
2281 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2282
2283 // Represent the same patterns above but in the form they appear for
2284 // 256-bit types
2285 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2286 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2287 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2288 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2289 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2290 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2291 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2292 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2293 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2294 }
2295 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2296 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2297 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2298 FR32X:$src)), sub_xmm)>;
2299 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2300 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2301 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2302 FR64X:$src)), sub_xmm)>;
2303 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2304 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2305 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2306
2307 // Move low f64 and clear high bits.
2308 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2309 (SUBREG_TO_REG (i32 0),
2310 (VMOVSDZrr (v2f64 (V_SET0)),
2311 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2312
2313 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2314 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2315 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2316
2317 // Extract and store.
2318 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2319 addr:$dst),
2320 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2321 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2322 addr:$dst),
2323 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2324
2325 // Shuffle with VMOVSS
2326 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2327 (VMOVSSZrr (v4i32 VR128X:$src1),
2328 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2329 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2330 (VMOVSSZrr (v4f32 VR128X:$src1),
2331 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2332
2333 // 256-bit variants
2334 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2335 (SUBREG_TO_REG (i32 0),
2336 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2337 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2338 sub_xmm)>;
2339 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2340 (SUBREG_TO_REG (i32 0),
2341 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2342 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2343 sub_xmm)>;
2344
2345 // Shuffle with VMOVSD
2346 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2347 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2348 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2349 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2350 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2351 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2352 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2353 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2354
2355 // 256-bit variants
2356 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2357 (SUBREG_TO_REG (i32 0),
2358 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2359 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2360 sub_xmm)>;
2361 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2362 (SUBREG_TO_REG (i32 0),
2363 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2364 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2365 sub_xmm)>;
2366
2367 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2368 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2369 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2370 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2371 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2372 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2373 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2374 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2375}
2376
2377let AddedComplexity = 15 in
2378def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2379 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2380 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2381 [(set VR128X:$dst, (v2i64 (X86vzmovl
2382 (v2i64 VR128X:$src))))],
2383 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2384
2385let AddedComplexity = 20 in
2386def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2387 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2388 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2389 [(set VR128X:$dst, (v2i64 (X86vzmovl
2390 (loadv2i64 addr:$src))))],
2391 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2392 EVEX_CD8<8, CD8VT8>;
2393
2394let Predicates = [HasAVX512] in {
2395 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2396 let AddedComplexity = 20 in {
2397 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2398 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2399 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2400 (VMOV64toPQIZrr GR64:$src)>;
2401 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2402 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2403
2404 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2405 (VMOVDI2PDIZrm addr:$src)>;
2406 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2407 (VMOVDI2PDIZrm addr:$src)>;
2408 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2409 (VMOVZPQILo2PQIZrm addr:$src)>;
2410 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2411 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2412 def : Pat<(v2i64 (X86vzload addr:$src)),
2413 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2414 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2415
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2416 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2417 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2418 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2419 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2420 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2421 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2422 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2423}
2424
2425def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2426 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2427
2428def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2429 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2430
2431def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2432 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2433
2434def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2435 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2436
2437//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2438// AVX-512 - Non-temporals
2439//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2440let SchedRW = [WriteLoad] in {
2441 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2442 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2443 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2444 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2445 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2446
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2447 let Predicates = [HasAVX512, HasVLX] in {
2448 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2449 (ins i256mem:$src),
2450 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2451 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2452 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2453
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2454 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2455 (ins i128mem:$src),
2456 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2457 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2458 EVEX_CD8<64, CD8VF>;
2459 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2460}
2461
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2462multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2463 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2464 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2465 let SchedRW = [WriteStore], mayStore = 1,
2466 AddedComplexity = 400 in
2467 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2468 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2469 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2470}
2471
2472multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2473 string elty, string elsz, string vsz512,
2474 string vsz256, string vsz128, Domain d,
2475 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2476 let Predicates = [prd] in
2477 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2478 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2479 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2480 EVEX_V512;
2481
2482 let Predicates = [prd, HasVLX] in {
2483 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2484 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2485 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2486 EVEX_V256;
2487
2488 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2489 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2490 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2491 EVEX_V128;
2492 }
2493}
2494
2495defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2496 "i", "64", "8", "4", "2", SSEPackedInt,
2497 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2498
2499defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2500 "f", "64", "8", "4", "2", SSEPackedDouble,
2501 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2502
2503defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2504 "f", "32", "16", "8", "4", SSEPackedSingle,
2505 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2506
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2507//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2508// AVX-512 - Integer arithmetic
2509//
2510multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2511 X86VectorVTInfo _, OpndItins itins,
2512 bit IsCommutable = 0> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2513 defm rr : AVX512_maskable<opc, MRMSrcReg, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2514 (ins _.RC:$src1, _.RC:$src2), OpcodeStr##_.Suffix,
2515 "$src2, $src1", "$src1, $src2",
2516 (_.VT (OpNode _.RC:$src1, _.RC:$src2)),
2517 itins.rr, IsCommutable>,
2518 AVX512BIBase, EVEX_4V;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2519
2520 let mayLoad = 1 in {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2521 defm rm : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2522 (ins _.RC:$src1, _.MemOp:$src2), OpcodeStr##_.Suffix,
2523 "$src2, $src1", "$src1, $src2",
2524 (_.VT (OpNode _.RC:$src1,
2525 (bitconvert (_.LdFrag addr:$src2)))),
2526 itins.rm>,
2527 AVX512BIBase, EVEX_4V;
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]2528 defm rmb : AVX512_maskable<opc, MRMSrcMem, _, (outs _.RC:$dst),
Robert Khasanov44241442014-10-08 14:37:45 +0000[diff] [blame]2529 (ins _.RC:$src1, _.ScalarMemOp:$src2), OpcodeStr##_.Suffix,
2530 "${src2}"##_.BroadcastStr##", $src1",
2531 "$src1, ${src2}"##_.BroadcastStr,
2532 (_.VT (OpNode _.RC:$src1,
2533 (X86VBroadcast
2534 (_.ScalarLdFrag addr:$src2)))),
2535 itins.rm>,
2536 AVX512BIBase, EVEX_4V, EVEX_B;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2537 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2538}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2539
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2540multiclass avx512_binop_rm_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
2541 AVX512VLVectorVTInfo VTInfo, OpndItins itins,
2542 Predicate prd, bit IsCommutable = 0> {
2543 let Predicates = [prd] in
2544 defm Z : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info512, itins,
2545 IsCommutable>, EVEX_V512;
2546
2547 let Predicates = [prd, HasVLX] in {
2548 defm Z256 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info256, itins,
2549 IsCommutable>, EVEX_V256;
2550 defm Z128 : avx512_binop_rm<opc, OpcodeStr, OpNode, VTInfo.info128, itins,
2551 IsCommutable>, EVEX_V128;
2552 }
2553}
2554
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2555multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2556 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2557 PatFrag memop_frag, X86MemOperand x86memop,
2558 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2559 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2560 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2561 {
2562 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2563 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2564 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2565 []>, EVEX_4V;
2566 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2567 (ins KRC:$mask, RC:$src1, RC:$src2),
2568 !strconcat(OpcodeStr,
2569 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2570 [], itins.rr>, EVEX_4V, EVEX_K;
2571 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2572 (ins KRC:$mask, RC:$src1, RC:$src2),
2573 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2574 "|$dst {${mask}} {z}, $src1, $src2}"),
2575 [], itins.rr>, EVEX_4V, EVEX_KZ;
2576 }
2577 let mayLoad = 1 in {
2578 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2579 (ins RC:$src1, x86memop:$src2),
2580 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2581 []>, EVEX_4V;
2582 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2583 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2584 !strconcat(OpcodeStr,
2585 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2586 [], itins.rm>, EVEX_4V, EVEX_K;
2587 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2588 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2589 !strconcat(OpcodeStr,
2590 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2591 [], itins.rm>, EVEX_4V, EVEX_KZ;
2592 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2593 (ins RC:$src1, x86scalar_mop:$src2),
2594 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2595 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2596 [], itins.rm>, EVEX_4V, EVEX_B;
2597 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2598 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2599 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2600 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2601 BrdcstStr, "}"),
2602 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2603 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2604 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2605 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2606 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2607 BrdcstStr, "}"),
2608 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2609 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2610}
2611
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2612defm VPADDD : avx512_binop_rm_vl<0xFE, "vpadd", add, avx512vl_i32_info,
2613 SSE_INTALU_ITINS_P, HasAVX512, 1>, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2614
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2615defm VPSUBD : avx512_binop_rm_vl<0xFA, "vpsub", sub, avx512vl_i32_info,
2616 SSE_INTALU_ITINS_P, HasAVX512, 0>, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2617
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2618defm VPMULLD : avx512_binop_rm_vl<0x40, "vpmull", mul, avx512vl_i32_info,
2619 SSE_INTALU_ITINS_P, HasAVX512, 1>, T8PD, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2620
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2621defm VPADDQ : avx512_binop_rm_vl<0xD4, "vpadd", add, avx512vl_i64_info,
2622 SSE_INTALU_ITINS_P, HasAVX512, 1>, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2623
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2624defm VPSUBQ : avx512_binop_rm_vl<0xFB, "vpsub", sub, avx512vl_i64_info,
2625 SSE_INTALU_ITINS_P, HasAVX512, 0>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2626
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2627defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2628 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2629 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2630 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2631
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2632defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2633 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2634 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2635
2636def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2637 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2638
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2639def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2640 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2641 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2642def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2643 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2644 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2645
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2646defm VPMAXUD : avx512_binop_rm_vl<0x3F, "vpmaxu", X86umax, avx512vl_i32_info,
2647 SSE_INTALU_ITINS_P, HasAVX512, 1>,
2648 T8PD, EVEX_CD8<32, CD8VF>;
2649defm VPMAXUQ : avx512_binop_rm_vl<0x3F, "vpmaxu", X86umax, avx512vl_i64_info,
2650 SSE_INTALU_ITINS_P, HasAVX512, 0>,
2651 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2652
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2653defm VPMAXSD : avx512_binop_rm_vl<0x3D, "vpmaxs", X86smax, avx512vl_i32_info,
2654 SSE_INTALU_ITINS_P, HasAVX512, 1>,
2655 T8PD, EVEX_CD8<32, CD8VF>;
2656defm VPMAXSQ : avx512_binop_rm_vl<0x3D, "vpmaxs", X86smax, avx512vl_i64_info,
2657 SSE_INTALU_ITINS_P, HasAVX512, 0>,
2658 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2659
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2660defm VPMINUD : avx512_binop_rm_vl<0x3B, "vpminu", X86umin, avx512vl_i32_info,
2661 SSE_INTALU_ITINS_P, HasAVX512, 1>,
2662 T8PD, EVEX_CD8<32, CD8VF>;
2663defm VPMINUQ : avx512_binop_rm_vl<0x3B, "vpminu", X86umin, avx512vl_i64_info,
2664 SSE_INTALU_ITINS_P, HasAVX512, 0>,
2665 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2666
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2667defm VPMINSD : avx512_binop_rm_vl<0x39, "vpmins", X86smin, avx512vl_i32_info,
2668 SSE_INTALU_ITINS_P, HasAVX512, 1>,
2669 T8PD, EVEX_CD8<32, CD8VF>;
2670defm VPMINSQ : avx512_binop_rm_vl<0x39, "vpmins", X86smin, avx512vl_i64_info,
2671 SSE_INTALU_ITINS_P, HasAVX512, 0>,
2672 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2673
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2674def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2675 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2676 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2677def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2678 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2679 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2680def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2681 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2682 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2683def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2684 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2685 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2686def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2687 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2688 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2689def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2690 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2691 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2692def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2693 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2694 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2695def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2696 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2697 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2698//===----------------------------------------------------------------------===//
2699// AVX-512 - Unpack Instructions
2700//===----------------------------------------------------------------------===//
2701
2702multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2703 PatFrag mem_frag, RegisterClass RC,
2704 X86MemOperand x86memop, string asm,
2705 Domain d> {
2706 def rr : AVX512PI<opc, MRMSrcReg,
2707 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2708 asm, [(set RC:$dst,
2709 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2710 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2711 def rm : AVX512PI<opc, MRMSrcMem,
2712 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2713 asm, [(set RC:$dst,
2714 (vt (OpNode RC:$src1,
2715 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2716 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2717}
2718
2719defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2720 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2721 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2722defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2723 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2724 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2725defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2726 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2727 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2728defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2729 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2730 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2731
2732multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2733 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2734 X86MemOperand x86memop> {
2735 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2736 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2737 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2738 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2739 IIC_SSE_UNPCK>, EVEX_4V;
2740 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2741 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2742 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2743 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2744 (bitconvert (memop_frag addr:$src2)))))],
2745 IIC_SSE_UNPCK>, EVEX_4V;
2746}
2747defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2748 VR512, memopv16i32, i512mem>, EVEX_V512,
2749 EVEX_CD8<32, CD8VF>;
2750defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2751 VR512, memopv8i64, i512mem>, EVEX_V512,
2752 VEX_W, EVEX_CD8<64, CD8VF>;
2753defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2754 VR512, memopv16i32, i512mem>, EVEX_V512,
2755 EVEX_CD8<32, CD8VF>;
2756defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2757 VR512, memopv8i64, i512mem>, EVEX_V512,
2758 VEX_W, EVEX_CD8<64, CD8VF>;
2759//===----------------------------------------------------------------------===//
2760// AVX-512 - PSHUFD
2761//
2762
2763multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2764 SDNode OpNode, PatFrag mem_frag,
2765 X86MemOperand x86memop, ValueType OpVT> {
2766 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2767 (ins RC:$src1, i8imm:$src2),
2768 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2769 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2770 [(set RC:$dst,
2771 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2772 EVEX;
2773 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2774 (ins x86memop:$src1, i8imm:$src2),
2775 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2776 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2777 [(set RC:$dst,
2778 (OpVT (OpNode (mem_frag addr:$src1),
2779 (i8 imm:$src2))))]>, EVEX;
2780}
2781
2782defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2783 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2784
2785let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2786defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2787 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2788 EVEX_CD8<32, CD8VF>;
2789let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2790defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2791 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2792 VEX_W, EVEX_CD8<32, CD8VF>;
2793
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2794def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2795 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2796def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2797 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2798
2799//===----------------------------------------------------------------------===//
2800// AVX-512 Logical Instructions
2801//===----------------------------------------------------------------------===//
2802
Robert Khasanovd5b14f72014-10-09 08:38:48 +0000[diff] [blame]2803defm VPANDD : avx512_binop_rm_vl<0xDB, "vpand", and, avx512vl_i32_info,
2804 SSE_BIT_ITINS_P, HasAVX512, 1>,
2805 EVEX_CD8<32, CD8VF>;
2806defm VPANDQ : avx512_binop_rm_vl<0xDB, "vpand", and, avx512vl_i64_info,
2807 SSE_BIT_ITINS_P, HasAVX512, 1>,
2808 VEX_W, EVEX_CD8<64, CD8VF>;
2809defm VPORD : avx512_binop_rm_vl<0xEB, "vpor", or, avx512vl_i32_info,
2810 SSE_BIT_ITINS_P, HasAVX512, 1>,
2811 EVEX_CD8<32, CD8VF>;
2812defm VPORQ : avx512_binop_rm_vl<0xEB, "vpor", or, avx512vl_i64_info,
2813 SSE_BIT_ITINS_P, HasAVX512, 1>,
2814 VEX_W, EVEX_CD8<64, CD8VF>;
2815defm VPXORD : avx512_binop_rm_vl<0xEF, "vpxor", xor, avx512vl_i32_info,
2816 SSE_BIT_ITINS_P, HasAVX512, 1>,
2817 EVEX_CD8<32, CD8VF>;
2818defm VPXORQ : avx512_binop_rm_vl<0xEF, "vpxor", xor, avx512vl_i64_info,
2819 SSE_BIT_ITINS_P, HasAVX512, 1>,
2820 VEX_W, EVEX_CD8<64, CD8VF>;
2821defm VPANDND : avx512_binop_rm_vl<0xDF, "vpandn", X86andnp, avx512vl_i32_info,
2822 SSE_BIT_ITINS_P, HasAVX512, 0>,
2823 EVEX_CD8<32, CD8VF>;
2824defm VPANDNQ : avx512_binop_rm_vl<0xDF, "vpandn", X86andnp, avx512vl_i64_info,
2825 SSE_BIT_ITINS_P, HasAVX512, 0>,
2826 VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2827
2828//===----------------------------------------------------------------------===//
2829// AVX-512 FP arithmetic
2830//===----------------------------------------------------------------------===//
2831
2832multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2833 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2834 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2835 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2836 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2837 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2838 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2839 EVEX_CD8<64, CD8VT1>;
2840}
2841
2842let isCommutable = 1 in {
2843defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2844defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2845defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2846defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2847}
2848let isCommutable = 0 in {
2849defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2850defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2851}
2852
2853multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2854 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2855 RegisterClass RC, ValueType vt,
2856 X86MemOperand x86memop, PatFrag mem_frag,
2857 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2858 string BrdcstStr,
2859 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2860 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2861 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2862 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2863 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2864 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2865
2866 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2867 !strconcat(OpcodeStr,
2868 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2869 [], itins.rr, d>, EVEX_4V, EVEX_K;
2870
2871 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2872 !strconcat(OpcodeStr,
2873 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2874 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2875 }
2876
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2877 let mayLoad = 1 in {
2878 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2879 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2880 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2881 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2882
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2883 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2884 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2885 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2886 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2887 [(set RC:$dst, (OpNode RC:$src1,
2888 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2889 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2890
2891 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2892 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2893 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2894 [], itins.rm, d>, EVEX_4V, EVEX_K;
2895
2896 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2897 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2898 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2899 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2900
2901 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2902 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2903 " \t{${src2}", BrdcstStr,
2904 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2905 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2906
2907 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2908 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2909 " \t{${src2}", BrdcstStr,
2910 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2911 BrdcstStr, "}"),
2912 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2913 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2914}
2915
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2916defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2917 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2918 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2919
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2920defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2921 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2922 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2923 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2924
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2925defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2926 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2927 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2928defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2929 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2930 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2931 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2932
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2933defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2934 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2935 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2936 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2937defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2938 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2939 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2940 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2941
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2942defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2943 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2944 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2945 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2946defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2947 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2948 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2949 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2950
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2951defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2952 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2953 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2954defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2955 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2956 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2957
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2958defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2959 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2960 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2961 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2962defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2963 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2964 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2965 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2966
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]2967def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
2968 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2969 (i16 -1), FROUND_CURRENT)),
2970 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
2971
2972def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
2973 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2974 (i8 -1), FROUND_CURRENT)),
2975 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
2976
2977def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
2978 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
2979 (i16 -1), FROUND_CURRENT)),
2980 (VMINPSZrr VR512:$src1, VR512:$src2)>;
2981
2982def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
2983 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
2984 (i8 -1), FROUND_CURRENT)),
2985 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2986//===----------------------------------------------------------------------===//
2987// AVX-512 VPTESTM instructions
2988//===----------------------------------------------------------------------===//
2989
2990multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
2991 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
2992 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2993 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2994 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2995 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2996 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
2997 SSEPackedInt>, EVEX_4V;
2998 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2999 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3000 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3001 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3002 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3003}
3004
3005defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3006 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3007 EVEX_CD8<32, CD8VF>;
3008defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3009 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3010 EVEX_CD8<64, CD8VF>;
3011
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3012let Predicates = [HasCDI] in {
3013defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3014 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3015 EVEX_CD8<32, CD8VF>;
3016defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3017 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3018 EVEX_CD8<64, CD8VF>;
3019}
3020
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3021def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3022 (v16i32 VR512:$src2), (i16 -1))),
3023 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3024
3025def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3026 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3027 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3028//===----------------------------------------------------------------------===//
3029// AVX-512 Shift instructions
3030//===----------------------------------------------------------------------===//
3031multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3032 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3033 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3034 RegisterClass KRC> {
3035 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3036 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3037 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3038 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3039 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3040 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3041 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3042 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3043 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3044 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3045 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3046 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3047 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3048 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3049 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3050 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3051 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3052 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3053 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3054 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3055}
3056
3057multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3058 RegisterClass RC, ValueType vt, ValueType SrcVT,
3059 PatFrag bc_frag, RegisterClass KRC> {
3060 // src2 is always 128-bit
3061 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3062 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3063 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3064 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3065 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3066 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3067 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3068 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3069 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3070 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3071 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3072 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3073 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3074 [(set RC:$dst, (vt (OpNode RC:$src1,
3075 (bc_frag (memopv2i64 addr:$src2)))))],
3076 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3077 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3078 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3079 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3080 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3081 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3082}
3083
3084defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3085 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3086 EVEX_V512, EVEX_CD8<32, CD8VF>;
3087defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3088 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3089 EVEX_CD8<32, CD8VQ>;
3090
3091defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3092 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3093 EVEX_CD8<64, CD8VF>, VEX_W;
3094defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3095 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3096 EVEX_CD8<64, CD8VQ>, VEX_W;
3097
3098defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3099 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3100 EVEX_CD8<32, CD8VF>;
3101defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3102 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3103 EVEX_CD8<32, CD8VQ>;
3104
3105defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3106 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3107 EVEX_CD8<64, CD8VF>, VEX_W;
3108defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3109 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3110 EVEX_CD8<64, CD8VQ>, VEX_W;
3111
3112defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3113 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3114 EVEX_V512, EVEX_CD8<32, CD8VF>;
3115defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3116 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3117 EVEX_CD8<32, CD8VQ>;
3118
3119defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3120 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3121 EVEX_CD8<64, CD8VF>, VEX_W;
3122defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3123 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3124 EVEX_CD8<64, CD8VQ>, VEX_W;
3125
3126//===-------------------------------------------------------------------===//
3127// Variable Bit Shifts
3128//===-------------------------------------------------------------------===//
3129multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3130 RegisterClass RC, ValueType vt,
3131 X86MemOperand x86memop, PatFrag mem_frag> {
3132 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3133 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3134 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3135 [(set RC:$dst,
3136 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3137 EVEX_4V;
3138 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3139 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3140 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3141 [(set RC:$dst,
3142 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3143 EVEX_4V;
3144}
3145
3146defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3147 i512mem, memopv16i32>, EVEX_V512,
3148 EVEX_CD8<32, CD8VF>;
3149defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3150 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3151 EVEX_CD8<64, CD8VF>;
3152defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3153 i512mem, memopv16i32>, EVEX_V512,
3154 EVEX_CD8<32, CD8VF>;
3155defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3156 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3157 EVEX_CD8<64, CD8VF>;
3158defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3159 i512mem, memopv16i32>, EVEX_V512,
3160 EVEX_CD8<32, CD8VF>;
3161defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3162 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3163 EVEX_CD8<64, CD8VF>;
3164
3165//===----------------------------------------------------------------------===//
3166// AVX-512 - MOVDDUP
3167//===----------------------------------------------------------------------===//
3168
3169multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3170 X86MemOperand x86memop, PatFrag memop_frag> {
3171def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3172 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3173 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3174def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3175 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3176 [(set RC:$dst,
3177 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3178}
3179
3180defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3181 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3182def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3183 (VMOVDDUPZrm addr:$src)>;
3184
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3185//===---------------------------------------------------------------------===//
3186// Replicate Single FP - MOVSHDUP and MOVSLDUP
3187//===---------------------------------------------------------------------===//
3188multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3189 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3190 X86MemOperand x86memop> {
3191 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3192 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3193 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3194 let mayLoad = 1 in
3195 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3196 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3197 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3198}
3199
3200defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3201 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3202 EVEX_CD8<32, CD8VF>;
3203defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3204 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3205 EVEX_CD8<32, CD8VF>;
3206
3207def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3208def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3209 (VMOVSHDUPZrm addr:$src)>;
3210def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3211def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3212 (VMOVSLDUPZrm addr:$src)>;
3213
3214//===----------------------------------------------------------------------===//
3215// Move Low to High and High to Low packed FP Instructions
3216//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3217def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3218 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3219 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3220 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3221 IIC_SSE_MOV_LH>, EVEX_4V;
3222def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3223 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3224 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3225 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3226 IIC_SSE_MOV_LH>, EVEX_4V;
3227
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3228let Predicates = [HasAVX512] in {
3229 // MOVLHPS patterns
3230 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3231 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3232 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3233 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3234
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3235 // MOVHLPS patterns
3236 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3237 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3238}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3239
3240//===----------------------------------------------------------------------===//
3241// FMA - Fused Multiply Operations
3242//
3243let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3244multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3245 X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]3246 defm r: AVX512_maskable_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3247 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3248 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3249 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3250 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3251
3252 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3253 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3254 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3255 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3256 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3257 (_.MemOpFrag addr:$src3))))]>;
3258 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3259 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3260 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3261 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3262 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3263 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3264}
3265} // Constraints = "$src1 = $dst"
3266
3267let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3268 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3269 v16f32_info>,
3270 EVEX_V512, EVEX_CD8<32, CD8VF>;
3271 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3272 v16f32_info>,
3273 EVEX_V512, EVEX_CD8<32, CD8VF>;
3274 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3275 v16f32_info>,
3276 EVEX_V512, EVEX_CD8<32, CD8VF>;
3277 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3278 v16f32_info>,
3279 EVEX_V512, EVEX_CD8<32, CD8VF>;
3280 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3281 v16f32_info>,
3282 EVEX_V512, EVEX_CD8<32, CD8VF>;
3283 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3284 v16f32_info>,
3285 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3286}
3287let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3288 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3289 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3290 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3291 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3292 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3293 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3294 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3295 v8f64_info>,
3296 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3297 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3298 v8f64_info>,
3299 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3300 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3301 v8f64_info>,
3302 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3303 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3304 v8f64_info>,
3305 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3306}
3307
3308let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3309multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3310 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3311 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3312 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3313 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3314 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3315 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3316 _.RC:$src3)))]>;
3317 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3318 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3319 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3320 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3321 [(set _.RC:$dst,
3322 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3323 (_.ScalarLdFrag addr:$src2))),
3324 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3325}
3326} // Constraints = "$src1 = $dst"
3327
3328
3329let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3330 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3331 v16f32_info>,
3332 EVEX_V512, EVEX_CD8<32, CD8VF>;
3333 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3334 v16f32_info>,
3335 EVEX_V512, EVEX_CD8<32, CD8VF>;
3336 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3337 v16f32_info>,
3338 EVEX_V512, EVEX_CD8<32, CD8VF>;
3339 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3340 v16f32_info>,
3341 EVEX_V512, EVEX_CD8<32, CD8VF>;
3342 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3343 v16f32_info>,
3344 EVEX_V512, EVEX_CD8<32, CD8VF>;
3345 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3346 v16f32_info>,
3347 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3348}
3349let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]3350 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3351 v8f64_info>,
3352 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3353 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3354 v8f64_info>,
3355 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3356 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3357 v8f64_info>,
3358 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3359 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3360 v8f64_info>,
3361 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3362 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3363 v8f64_info>,
3364 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3365 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3366 v8f64_info>,
3367 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3368}
3369
3370// Scalar FMA
3371let Constraints = "$src1 = $dst" in {
3372multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3373 RegisterClass RC, ValueType OpVT,
3374 X86MemOperand x86memop, Operand memop,
3375 PatFrag mem_frag> {
3376 let isCommutable = 1 in
3377 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3378 (ins RC:$src1, RC:$src2, RC:$src3),
3379 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3380 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3381 [(set RC:$dst,
3382 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3383 let mayLoad = 1 in
3384 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3385 (ins RC:$src1, RC:$src2, f128mem:$src3),
3386 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3387 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3388 [(set RC:$dst,
3389 (OpVT (OpNode RC:$src2, RC:$src1,
3390 (mem_frag addr:$src3))))]>;
3391}
3392
3393} // Constraints = "$src1 = $dst"
3394
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3395defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3396 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3397defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3398 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3399defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3400 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3401defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3402 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3403defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3404 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3405defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3406 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3407defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3408 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3409defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3410 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3411
3412//===----------------------------------------------------------------------===//
3413// AVX-512 Scalar convert from sign integer to float/double
3414//===----------------------------------------------------------------------===//
3415
3416multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3417 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3418let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3419 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3420 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3421 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3422 let mayLoad = 1 in
3423 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3424 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3425 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3426 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3427} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3428}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3429let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3430defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3431 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3432defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3433 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3434defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3435 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3436defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3437 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3438
3439def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3440 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3441def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3442 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3443def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3444 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3445def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3446 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3447
3448def : Pat<(f32 (sint_to_fp GR32:$src)),
3449 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3450def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3451 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3452def : Pat<(f64 (sint_to_fp GR32:$src)),
3453 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3454def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3455 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3456
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3457defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3458 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3459defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3460 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3461defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3462 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3463defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3464 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3465
3466def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3467 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3468def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3469 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3470def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3471 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3472def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3473 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3474
3475def : Pat<(f32 (uint_to_fp GR32:$src)),
3476 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3477def : Pat<(f32 (uint_to_fp GR64:$src)),
3478 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3479def : Pat<(f64 (uint_to_fp GR32:$src)),
3480 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3481def : Pat<(f64 (uint_to_fp GR64:$src)),
3482 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3483}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3484
3485//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3486// AVX-512 Scalar convert from float/double to integer
3487//===----------------------------------------------------------------------===//
3488multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3489 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3490 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3491let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3492 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3493 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3494 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3495 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3496 let mayLoad = 1 in
3497 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3498 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3499 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3500} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3501}
3502let Predicates = [HasAVX512] in {
3503// Convert float/double to signed/unsigned int 32/64
3504defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3505 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3506 XS, EVEX_CD8<32, CD8VT1>;
3507defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3508 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3509 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3510defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3511 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3512 XS, EVEX_CD8<32, CD8VT1>;
3513defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3514 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3515 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3516 EVEX_CD8<32, CD8VT1>;
3517defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3518 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3519 XD, EVEX_CD8<64, CD8VT1>;
3520defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3521 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3522 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3523defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3524 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3525 XD, EVEX_CD8<64, CD8VT1>;
3526defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3527 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3528 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3529 EVEX_CD8<64, CD8VT1>;
3530
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3531let isCodeGenOnly = 1 in {
3532 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3533 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3534 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3535 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3536 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3537 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3538 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3539 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3540 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3541 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3542 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3543 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3544
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3545 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3546 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3547 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3548 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3549 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3550 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3551 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3552 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3553 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3554 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3555 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3556 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3557} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3558
3559// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3560let isCodeGenOnly = 1 in {
3561 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3562 ssmem, sse_load_f32, "cvttss2si">,
3563 XS, EVEX_CD8<32, CD8VT1>;
3564 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3565 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3566 "cvttss2si">, XS, VEX_W,
3567 EVEX_CD8<32, CD8VT1>;
3568 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3569 sdmem, sse_load_f64, "cvttsd2si">, XD,
3570 EVEX_CD8<64, CD8VT1>;
3571 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3572 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3573 "cvttsd2si">, XD, VEX_W,
3574 EVEX_CD8<64, CD8VT1>;
3575 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3576 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3577 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3578 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3579 int_x86_avx512_cvttss2usi64, ssmem,
3580 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3581 EVEX_CD8<32, CD8VT1>;
3582 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3583 int_x86_avx512_cvttsd2usi,
3584 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3585 EVEX_CD8<64, CD8VT1>;
3586 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3587 int_x86_avx512_cvttsd2usi64, sdmem,
3588 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3589 EVEX_CD8<64, CD8VT1>;
3590} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3591
3592multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3593 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3594 string asm> {
3595 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3596 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3597 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3598 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3599 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3600 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3601}
3602
3603defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3604 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3605 EVEX_CD8<32, CD8VT1>;
3606defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3607 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3608 EVEX_CD8<32, CD8VT1>;
3609defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3610 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3611 EVEX_CD8<32, CD8VT1>;
3612defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3613 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3614 EVEX_CD8<32, CD8VT1>;
3615defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3616 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3617 EVEX_CD8<64, CD8VT1>;
3618defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3619 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3620 EVEX_CD8<64, CD8VT1>;
3621defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3622 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3623 EVEX_CD8<64, CD8VT1>;
3624defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3625 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3626 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3627} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3628//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3629// AVX-512 Convert form float to double and back
3630//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3631let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3632def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3633 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3634 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3635 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3636let mayLoad = 1 in
3637def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3638 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3639 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3640 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3641 EVEX_CD8<32, CD8VT1>;
3642
3643// Convert scalar double to scalar single
3644def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3645 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3646 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3647 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3648let mayLoad = 1 in
3649def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3650 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3651 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3652 []>, EVEX_4V, VEX_LIG, VEX_W,
3653 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3654}
3655
3656def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3657 Requires<[HasAVX512]>;
3658def : Pat<(fextend (loadf32 addr:$src)),
3659 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3660
3661def : Pat<(extloadf32 addr:$src),
3662 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3663 Requires<[HasAVX512, OptForSize]>;
3664
3665def : Pat<(extloadf32 addr:$src),
3666 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3667 Requires<[HasAVX512, OptForSpeed]>;
3668
3669def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3670 Requires<[HasAVX512]>;
3671
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3672multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3673 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3674 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3675 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3676let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3677 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3678 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3679 [(set DstRC:$dst,
3680 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3681 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3682 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3683 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3684 let mayLoad = 1 in
3685 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3686 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3687 [(set DstRC:$dst,
3688 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3689} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3690}
3691
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3692multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3693 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3694 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3695 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3696let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3697 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3698 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3699 [(set DstRC:$dst,
3700 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3701 let mayLoad = 1 in
3702 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3703 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3704 [(set DstRC:$dst,
3705 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3706} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3707}
3708
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3709defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3710 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3711 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3712 EVEX_CD8<64, CD8VF>;
3713
3714defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3715 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3716 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3717 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3718def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3719 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3720
3721def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3722 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3723 (VCVTPD2PSZrr VR512:$src)>;
3724
3725def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3726 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3727 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3728
3729//===----------------------------------------------------------------------===//
3730// AVX-512 Vector convert from sign integer to float/double
3731//===----------------------------------------------------------------------===//
3732
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3733defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3734 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3735 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3736 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3737
3738defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3739 memopv4i64, i256mem, v8f64, v8i32,
3740 SSEPackedDouble>, EVEX_V512, XS,
3741 EVEX_CD8<32, CD8VH>;
3742
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3743defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3744 memopv16f32, f512mem, v16i32, v16f32,
3745 SSEPackedSingle>, EVEX_V512, XS,
3746 EVEX_CD8<32, CD8VF>;
3747
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3748defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3749 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3750 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3751 EVEX_CD8<64, CD8VF>;
3752
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3753defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3754 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3755 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3756 EVEX_CD8<32, CD8VF>;
3757
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3758// cvttps2udq (src, 0, mask-all-ones, sae-current)
3759def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3760 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3761 (VCVTTPS2UDQZrr VR512:$src)>;
3762
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3763defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3764 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3765 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3766 EVEX_CD8<64, CD8VF>;
3767
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3768// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3769def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3770 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3771 (VCVTTPD2UDQZrr VR512:$src)>;
3772
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3773defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3774 memopv4i64, f256mem, v8f64, v8i32,
3775 SSEPackedDouble>, EVEX_V512, XS,
3776 EVEX_CD8<32, CD8VH>;
3777
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3778defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3779 memopv16i32, f512mem, v16f32, v16i32,
3780 SSEPackedSingle>, EVEX_V512, XD,
3781 EVEX_CD8<32, CD8VF>;
3782
3783def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3784 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3785 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3786
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3787def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3788 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3789 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3790
3791def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3792 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3793 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3794
3795def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3796 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3797 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3798
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3799def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3800 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3801 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3802
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3803def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3804 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3805 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3806def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3807 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3808 (VCVTDQ2PDZrr VR256X:$src)>;
3809def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3810 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3811 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3812def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3813 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3814 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3815
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3816multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3817 RegisterClass DstRC, PatFrag mem_frag,
3818 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3819let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3820 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3821 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3822 [], d>, EVEX;
3823 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3824 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3825 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3826 let mayLoad = 1 in
3827 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3828 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3829 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3830} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3831}
3832
3833defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3834 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3835 EVEX_V512, EVEX_CD8<32, CD8VF>;
3836defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3837 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3838 EVEX_V512, EVEX_CD8<64, CD8VF>;
3839
3840def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3841 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3842 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3843
3844def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3845 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3846 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3847
3848defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3849 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3850 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3851defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3852 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3853 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3854
3855def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3856 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3857 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3858
3859def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3860 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3861 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3862
3863let Predicates = [HasAVX512] in {
3864 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3865 (VCVTPD2PSZrm addr:$src)>;
3866 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3867 (VCVTPS2PDZrm addr:$src)>;
3868}
3869
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3870//===----------------------------------------------------------------------===//
3871// Half precision conversion instructions
3872//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3873multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3874 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3875 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3876 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3877 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3878 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3879 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3880 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3881}
3882
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3883multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3884 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3885 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3886 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3887 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3888 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3889 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3890 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3891 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3892 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3893}
3894
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3895defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3896 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3897defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3898 EVEX_CD8<32, CD8VH>;
3899
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3900def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3901 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3902 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3903
3904def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3905 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3906 (VCVTPH2PSZrr VR256X:$src)>;
3907
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3908let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3909 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3910 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3911 EVEX_CD8<32, CD8VT1>;
3912 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3913 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3914 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3915 let Pattern = []<dag> in {
3916 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3917 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3918 EVEX_CD8<32, CD8VT1>;
3919 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3920 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3921 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3922 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3923 let isCodeGenOnly = 1 in {
3924 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3925 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3926 EVEX_CD8<32, CD8VT1>;
3927 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3928 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3929 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3930
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3931 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3932 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3933 EVEX_CD8<32, CD8VT1>;
3934 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3935 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3936 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3937 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3938}
3939
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3940/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3941multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3942 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3943 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3944 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3945 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3946 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3947 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3948 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3949 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3950 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3951 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3952 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3953 }
3954}
3955}
3956
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3957defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3958 EVEX_CD8<32, CD8VT1>;
3959defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3960 VEX_W, EVEX_CD8<64, CD8VT1>;
3961defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3962 EVEX_CD8<32, CD8VT1>;
3963defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3964 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3965
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3966def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
3967 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3968 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3969 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3970
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3971def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
3972 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3973 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3974 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3975
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3976def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
3977 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
3978 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
3979 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3980
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3981def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
3982 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
3983 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
3984 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]3985
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3986/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
3987multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
3988 RegisterClass RC, X86MemOperand x86memop,
3989 PatFrag mem_frag, ValueType OpVt> {
3990 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
3991 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3992 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3993 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
3994 EVEX;
3995 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3996 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3997 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
3998 EVEX;
3999}
4000defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4001 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4002defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4003 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4004defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4005 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4006defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4007 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4008
4009def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4010 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4011 (VRSQRT14PSZr VR512:$src)>;
4012def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4013 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4014 (VRSQRT14PDZr VR512:$src)>;
4015
4016def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4017 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4018 (VRCP14PSZr VR512:$src)>;
4019def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4020 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4021 (VRCP14PDZr VR512:$src)>;
4022
4023/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4024multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4025 X86MemOperand x86memop> {
4026 let hasSideEffects = 0, Predicates = [HasERI] in {
4027 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4028 (ins RC:$src1, RC:$src2),
4029 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4030 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4031 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4032 (ins RC:$src1, RC:$src2),
4033 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4034 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4035 []>, EVEX_4V, EVEX_B;
4036 let mayLoad = 1 in {
4037 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4038 (ins RC:$src1, x86memop:$src2),
4039 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4040 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4041 }
4042}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4043}
4044
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4045defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4046 EVEX_CD8<32, CD8VT1>;
4047defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4048 VEX_W, EVEX_CD8<64, CD8VT1>;
4049defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4050 EVEX_CD8<32, CD8VT1>;
4051defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4052 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4053
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4054def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4055 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4056 FROUND_NO_EXC)),
4057 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4058 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4059
4060def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4061 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4062 FROUND_NO_EXC)),
4063 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4064 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4065
4066def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4067 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4068 FROUND_NO_EXC)),
4069 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4070 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4071
4072def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4073 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4074 FROUND_NO_EXC)),
4075 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4076 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4077
4078/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4079multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4080 RegisterClass RC, X86MemOperand x86memop> {
4081 let hasSideEffects = 0, Predicates = [HasERI] in {
4082 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4083 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4084 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4085 []>, EVEX;
4086 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4087 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4088 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4089 []>, EVEX, EVEX_B;
4090 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4091 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4092 []>, EVEX;
4093 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4094}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4095defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4096 EVEX_V512, EVEX_CD8<32, CD8VF>;
4097defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4098 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4099defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4100 EVEX_V512, EVEX_CD8<32, CD8VF>;
4101defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4102 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4103
4104def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4105 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4106 (VRSQRT28PSZrb VR512:$src)>;
4107def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4108 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4109 (VRSQRT28PDZrb VR512:$src)>;
4110
4111def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4112 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4113 (VRCP28PSZrb VR512:$src)>;
4114def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4115 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4116 (VRCP28PDZrb VR512:$src)>;
4117
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4118multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4119 OpndItins itins_s, OpndItins itins_d> {
4120 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4121 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4122 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4123 EVEX, EVEX_V512;
4124
4125 let mayLoad = 1 in
4126 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4127 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4128 [(set VR512:$dst,
4129 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4130 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4131
4132 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4133 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4134 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4135 EVEX, EVEX_V512;
4136
4137 let mayLoad = 1 in
4138 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4139 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4140 [(set VR512:$dst, (OpNode
4141 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4142 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4143
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4144}
4145
4146multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4147 Intrinsic F32Int, Intrinsic F64Int,
4148 OpndItins itins_s, OpndItins itins_d> {
4149 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4150 (ins FR32X:$src1, FR32X:$src2),
4151 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4152 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4153 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4154 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4155 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4156 (ins VR128X:$src1, VR128X:$src2),
4157 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4158 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4159 [(set VR128X:$dst,
4160 (F32Int VR128X:$src1, VR128X:$src2))],
4161 itins_s.rr>, XS, EVEX_4V;
4162 let mayLoad = 1 in {
4163 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4164 (ins FR32X:$src1, f32mem:$src2),
4165 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4166 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4167 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4168 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4169 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4170 (ins VR128X:$src1, ssmem:$src2),
4171 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4172 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4173 [(set VR128X:$dst,
4174 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4175 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4176 }
4177 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4178 (ins FR64X:$src1, FR64X:$src2),
4179 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4180 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4181 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4182 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4183 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4184 (ins VR128X:$src1, VR128X:$src2),
4185 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4186 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4187 [(set VR128X:$dst,
4188 (F64Int VR128X:$src1, VR128X:$src2))],
4189 itins_s.rr>, XD, EVEX_4V, VEX_W;
4190 let mayLoad = 1 in {
4191 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4192 (ins FR64X:$src1, f64mem:$src2),
4193 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4194 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4195 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4196 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4197 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4198 (ins VR128X:$src1, sdmem:$src2),
4199 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4200 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4201 [(set VR128X:$dst,
4202 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4203 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4204 }
4205}
4206
4207
4208defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4209 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4210 SSE_SQRTSS, SSE_SQRTSD>,
4211 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4212 SSE_SQRTPS, SSE_SQRTPD>;
4213
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4214let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4215 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4216 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4217 (VSQRTPSZrr VR512:$src1)>;
4218 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4219 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4220 (VSQRTPDZrr VR512:$src1)>;
4221
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4222 def : Pat<(f32 (fsqrt FR32X:$src)),
4223 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4224 def : Pat<(f32 (fsqrt (load addr:$src))),
4225 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4226 Requires<[OptForSize]>;
4227 def : Pat<(f64 (fsqrt FR64X:$src)),
4228 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4229 def : Pat<(f64 (fsqrt (load addr:$src))),
4230 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4231 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4232
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4233 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4234 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4235 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4236 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4237 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4238
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4239 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4240 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4241 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4242 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4243 Requires<[OptForSize]>;
4244
4245 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4246 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4247 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4248 VR128X)>;
4249 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4250 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4251
4252 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4253 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4254 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4255 VR128X)>;
4256 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4257 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4258}
4259
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4260
4261multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4262 X86MemOperand x86memop, RegisterClass RC,
4263 PatFrag mem_frag32, PatFrag mem_frag64,
4264 Intrinsic V4F32Int, Intrinsic V2F64Int,
4265 CD8VForm VForm> {
4266let ExeDomain = SSEPackedSingle in {
4267 // Intrinsic operation, reg.
4268 // Vector intrinsic operation, reg
4269 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4270 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4271 !strconcat(OpcodeStr,
4272 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4273 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4274
4275 // Vector intrinsic operation, mem
4276 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4277 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4278 !strconcat(OpcodeStr,
4279 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4280 [(set RC:$dst,
4281 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4282 EVEX_CD8<32, VForm>;
4283} // ExeDomain = SSEPackedSingle
4284
4285let ExeDomain = SSEPackedDouble in {
4286 // Vector intrinsic operation, reg
4287 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4288 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4289 !strconcat(OpcodeStr,
4290 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4291 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4292
4293 // Vector intrinsic operation, mem
4294 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4295 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4296 !strconcat(OpcodeStr,
4297 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4298 [(set RC:$dst,
4299 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4300 EVEX_CD8<64, VForm>;
4301} // ExeDomain = SSEPackedDouble
4302}
4303
4304multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4305 string OpcodeStr,
4306 Intrinsic F32Int,
4307 Intrinsic F64Int> {
4308let ExeDomain = GenericDomain in {
4309 // Operation, reg.
4310 let hasSideEffects = 0 in
4311 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4312 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4313 !strconcat(OpcodeStr,
4314 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4315 []>;
4316
4317 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4318 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4319 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4320 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4321 !strconcat(OpcodeStr,
4322 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4323 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4324
4325 // Intrinsic operation, mem.
4326 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4327 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4328 !strconcat(OpcodeStr,
4329 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4330 [(set VR128X:$dst, (F32Int VR128X:$src1,
4331 sse_load_f32:$src2, imm:$src3))]>,
4332 EVEX_CD8<32, CD8VT1>;
4333
4334 // Operation, reg.
4335 let hasSideEffects = 0 in
4336 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4337 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4338 !strconcat(OpcodeStr,
4339 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4340 []>, VEX_W;
4341
4342 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4343 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4344 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4345 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4346 !strconcat(OpcodeStr,
4347 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4348 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4349 VEX_W;
4350
4351 // Intrinsic operation, mem.
4352 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4353 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4354 !strconcat(OpcodeStr,
4355 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4356 [(set VR128X:$dst,
4357 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4358 VEX_W, EVEX_CD8<64, CD8VT1>;
4359} // ExeDomain = GenericDomain
4360}
4361
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4362multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4363 X86MemOperand x86memop, RegisterClass RC,
4364 PatFrag mem_frag, Domain d> {
4365let ExeDomain = d in {
4366 // Intrinsic operation, reg.
4367 // Vector intrinsic operation, reg
4368 def r : AVX512AIi8<opc, MRMSrcReg,
4369 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4370 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4371 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4372 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4373
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4374 // Vector intrinsic operation, mem
4375 def m : AVX512AIi8<opc, MRMSrcMem,
4376 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4377 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4378 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4379 []>, EVEX;
4380} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4381}
4382
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4383
4384defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4385 memopv16f32, SSEPackedSingle>, EVEX_V512,
4386 EVEX_CD8<32, CD8VF>;
4387
4388def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4389 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4390 FROUND_CURRENT)),
4391 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4392
4393
4394defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4395 memopv8f64, SSEPackedDouble>, EVEX_V512,
4396 VEX_W, EVEX_CD8<64, CD8VF>;
4397
4398def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4399 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4400 FROUND_CURRENT)),
4401 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4402
4403multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4404 Operand x86memop, RegisterClass RC, Domain d> {
4405let ExeDomain = d in {
4406 def r : AVX512AIi8<opc, MRMSrcReg,
4407 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4408 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4409 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4410 []>, EVEX_4V;
4411
4412 def m : AVX512AIi8<opc, MRMSrcMem,
4413 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4414 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4415 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4416 []>, EVEX_4V;
4417} // ExeDomain
4418}
4419
4420defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4421 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4422
4423defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4424 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4425
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4426def : Pat<(ffloor FR32X:$src),
4427 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4428def : Pat<(f64 (ffloor FR64X:$src)),
4429 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4430def : Pat<(f32 (fnearbyint FR32X:$src)),
4431 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4432def : Pat<(f64 (fnearbyint FR64X:$src)),
4433 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4434def : Pat<(f32 (fceil FR32X:$src)),
4435 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4436def : Pat<(f64 (fceil FR64X:$src)),
4437 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4438def : Pat<(f32 (frint FR32X:$src)),
4439 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4440def : Pat<(f64 (frint FR64X:$src)),
4441 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4442def : Pat<(f32 (ftrunc FR32X:$src)),
4443 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4444def : Pat<(f64 (ftrunc FR64X:$src)),
4445 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4446
4447def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4448 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4449def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4450 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4451def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4452 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4453def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4454 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4455def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4456 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4457
4458def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4459 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4460def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4461 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4462def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4463 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4464def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4465 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4466def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4467 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4468
4469//-------------------------------------------------
4470// Integer truncate and extend operations
4471//-------------------------------------------------
4472
4473multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4474 RegisterClass dstRC, RegisterClass srcRC,
4475 RegisterClass KRC, X86MemOperand x86memop> {
4476 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4477 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4478 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4479 []>, EVEX;
4480
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4481 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4482 (ins KRC:$mask, srcRC:$src),
4483 !strconcat(OpcodeStr,
4484 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4485 []>, EVEX, EVEX_K;
4486
4487 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4488 (ins KRC:$mask, srcRC:$src),
4489 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4490 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4491 []>, EVEX, EVEX_KZ;
4492
4493 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4494 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4495 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4496
4497 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4498 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4499 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4500 []>, EVEX, EVEX_K;
4501
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4502}
4503defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4504 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4505defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4506 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4507defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4508 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4509defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4510 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4511defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4512 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4513defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4514 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4515defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4516 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4517defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4518 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4519defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4520 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4521defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4522 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4523defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4524 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4525defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4526 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4527defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4528 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4529defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4530 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4531defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4532 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4533
4534def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4535def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4536def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4537def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4538def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4539
4540def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4541 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4542def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4543 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4544def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4545 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4546def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4547 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4548
4549
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4550multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4551 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4552 PatFrag mem_frag, X86MemOperand x86memop,
4553 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4554
4555 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4556 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4557 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4558 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4559
4560 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4561 (ins KRC:$mask, SrcRC:$src),
4562 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4563 []>, EVEX, EVEX_K;
4564
4565 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4566 (ins KRC:$mask, SrcRC:$src),
4567 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4568 []>, EVEX, EVEX_KZ;
4569
4570 let mayLoad = 1 in {
4571 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4572 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4573 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4574 [(set DstRC:$dst,
4575 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4576 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4577
4578 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4579 (ins KRC:$mask, x86memop:$src),
4580 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4581 []>,
4582 EVEX, EVEX_K;
4583
4584 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4585 (ins KRC:$mask, x86memop:$src),
4586 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4587 []>,
4588 EVEX, EVEX_KZ;
4589 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4590}
4591
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4592defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4593 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4594 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4595defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4596 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4597 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4598defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4599 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4600 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4601defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4602 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4603 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4604defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4605 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4606 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4607
4608defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4609 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4610 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4611defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4612 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4613 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4614defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4615 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4616 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4617defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4618 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4619 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4620defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4621 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4622 EVEX_CD8<32, CD8VH>;
4623
4624//===----------------------------------------------------------------------===//
4625// GATHER - SCATTER Operations
4626
4627multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4628 RegisterClass RC, X86MemOperand memop> {
4629let mayLoad = 1,
4630 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4631 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4632 (ins RC:$src1, KRC:$mask, memop:$src2),
4633 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4634 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4635 []>, EVEX, EVEX_K;
4636}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4637
4638let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4639defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4640 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4641defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4642 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4643}
4644
4645let ExeDomain = SSEPackedSingle in {
4646defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4647 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4648defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4649 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4650}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4651
4652defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4653 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4654defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4655 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4656
4657defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4658 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4659defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4660 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4661
4662multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4663 RegisterClass RC, X86MemOperand memop> {
4664let mayStore = 1, Constraints = "$mask = $mask_wb" in
4665 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4666 (ins memop:$dst, KRC:$mask, RC:$src2),
4667 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4668 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4669 []>, EVEX, EVEX_K;
4670}
4671
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4672let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4673defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4674 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4675defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4676 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4677}
4678
4679let ExeDomain = SSEPackedSingle in {
4680defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4681 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4682defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4683 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4684}
4685
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4686defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4687 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4688defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4689 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4690
4691defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4692 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4693defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4694 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4695
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4696// prefetch
4697multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4698 RegisterClass KRC, X86MemOperand memop> {
4699 let Predicates = [HasPFI], hasSideEffects = 1 in
4700 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4701 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4702 []>, EVEX, EVEX_K;
4703}
4704
4705defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4706 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4707
4708defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4709 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4710
4711defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4712 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4713
4714defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4715 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4716
4717defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4718 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4719
4720defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4721 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4722
4723defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4724 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4725
4726defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4727 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4728
4729defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4730 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4731
4732defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4733 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4734
4735defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4736 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4737
4738defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4739 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4740
4741defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4742 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4743
4744defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4745 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4746
4747defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4748 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4749
4750defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4751 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4752//===----------------------------------------------------------------------===//
4753// VSHUFPS - VSHUFPD Operations
4754
4755multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4756 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4757 Domain d> {
4758 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4759 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4760 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4761 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4762 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4763 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4764 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4765 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4766 (ins RC:$src1, RC:$src2, i8imm:$src3),
4767 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4768 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4769 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4770 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4771 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4772}
4773
4774defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4775 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4776defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4777 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4778
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4779def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4780 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4781def : Pat<(v16i32 (X86Shufp VR512:$src1,
4782 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4783 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4784
4785def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4786 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4787def : Pat<(v8i64 (X86Shufp VR512:$src1,
4788 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4789 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4790
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4791multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet34801422014-10-08 23:25:39 +0000[diff] [blame]4792 defm rri : AVX512_maskable<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4793 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4794 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4795 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4796 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame]4797 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4798 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4799
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4800 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4801 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4802 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4803
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4804 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4805 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4806 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4807 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4808 " \t{$src3, $src2, $src1, $dst|"
4809 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4810 []>, EVEX_4V;
4811}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4812defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4813defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4814
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4815// Helper fragments to match sext vXi1 to vXiY.
4816def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4817def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4818
4819multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4820 RegisterClass KRC, RegisterClass RC,
4821 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4822 string BrdcstStr> {
4823 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4824 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4825 []>, EVEX;
4826 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4827 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4828 []>, EVEX, EVEX_K;
4829 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4830 !strconcat(OpcodeStr,
4831 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4832 []>, EVEX, EVEX_KZ;
4833 let mayLoad = 1 in {
4834 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4835 (ins x86memop:$src),
4836 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4837 []>, EVEX;
4838 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4839 (ins KRC:$mask, x86memop:$src),
4840 !strconcat(OpcodeStr,
4841 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4842 []>, EVEX, EVEX_K;
4843 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4844 (ins KRC:$mask, x86memop:$src),
4845 !strconcat(OpcodeStr,
4846 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4847 []>, EVEX, EVEX_KZ;
4848 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4849 (ins x86scalar_mop:$src),
4850 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4851 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4852 []>, EVEX, EVEX_B;
4853 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4854 (ins KRC:$mask, x86scalar_mop:$src),
4855 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4856 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4857 []>, EVEX, EVEX_B, EVEX_K;
4858 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4859 (ins KRC:$mask, x86scalar_mop:$src),
4860 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4861 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4862 BrdcstStr, "}"),
4863 []>, EVEX, EVEX_B, EVEX_KZ;
4864 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4865}
4866
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4867defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4868 i512mem, i32mem, "{1to16}">, EVEX_V512,
4869 EVEX_CD8<32, CD8VF>;
4870defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4871 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4872 EVEX_CD8<64, CD8VF>;
4873
4874def : Pat<(xor
4875 (bc_v16i32 (v16i1sextv16i32)),
4876 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4877 (VPABSDZrr VR512:$src)>;
4878def : Pat<(xor
4879 (bc_v8i64 (v8i1sextv8i64)),
4880 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4881 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4882
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4883def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4884 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4885 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4886def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4887 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4888 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4889
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4890multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4891 RegisterClass RC, RegisterClass KRC,
4892 X86MemOperand x86memop,
4893 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4894 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4895 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4896 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4897 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4898 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4899 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4900 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4901 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4902 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4903 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4904 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4905 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4906 []>, EVEX, EVEX_B;
4907 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4908 (ins KRC:$mask, RC:$src),
4909 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4910 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4911 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4912 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4913 (ins KRC:$mask, x86memop:$src),
4914 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4915 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4916 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4917 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4918 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4919 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4920 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4921 BrdcstStr, "}"),
4922 []>, EVEX, EVEX_KZ, EVEX_B;
4923
4924 let Constraints = "$src1 = $dst" in {
4925 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4926 (ins RC:$src1, KRC:$mask, RC:$src2),
4927 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4928 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4929 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4930 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4931 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4932 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4933 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4934 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4935 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4936 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4937 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4938 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4939 []>, EVEX, EVEX_K, EVEX_B;
4940 }
4941}
4942
4943let Predicates = [HasCDI] in {
4944defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4945 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4946 EVEX_V512, EVEX_CD8<32, CD8VF>;
4947
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4948
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4949defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4950 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4951 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4952
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4953}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4954
4955def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4956 GR16:$mask),
4957 (VPCONFLICTDrrk VR512:$src1,
4958 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4959
4960def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4961 GR8:$mask),
4962 (VPCONFLICTQrrk VR512:$src1,
4963 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4964
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4965let Predicates = [HasCDI] in {
4966defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
4967 i512mem, i32mem, "{1to16}">,
4968 EVEX_V512, EVEX_CD8<32, CD8VF>;
4969
4970
4971defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
4972 i512mem, i64mem, "{1to8}">,
4973 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
4974
4975}
4976
4977def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
4978 GR16:$mask),
4979 (VPLZCNTDrrk VR512:$src1,
4980 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4981
4982def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
4983 GR8:$mask),
4984 (VPLZCNTQrrk VR512:$src1,
4985 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
4986
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]4987def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
4988 (VPLZCNTDrm addr:$src)>;
4989def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
4990 (VPLZCNTDrr VR512:$src)>;
4991def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
4992 (VPLZCNTQrm addr:$src)>;
4993def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
4994 (VPLZCNTQrr VR512:$src)>;
4995
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4996def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4997def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
4998def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]4999
5000def : Pat<(store VK1:$src, addr:$dst),
5001 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5002
5003def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5004 (truncstore node:$val, node:$ptr), [{
5005 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5006}]>;
5007
5008def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5009 (MOV8mr addr:$dst, GR8:$src)>;
5010
Elena Demikhovsky44bf0632014-10-05 14:11:08 +0000[diff] [blame]5011multiclass cvt_by_vec_width<bits<8> opc, X86VectorVTInfo Vec, string OpcodeStr > {
5012def rr : AVX512XS8I<opc, MRMDestReg, (outs Vec.RC:$dst), (ins Vec.KRC:$src),
5013 !strconcat(OpcodeStr##Vec.Suffix, " \t{$src, $dst|$dst, $src}"),
5014 [(set Vec.RC:$dst, (Vec.VT (X86vsext Vec.KRC:$src)))]>, EVEX;
5015}
5016
5017multiclass cvt_mask_by_elt_width<bits<8> opc, AVX512VLVectorVTInfo VTInfo,
5018 string OpcodeStr, Predicate prd> {
5019let Predicates = [prd] in
5020 defm Z : cvt_by_vec_width<opc, VTInfo.info512, OpcodeStr>, EVEX_V512;
5021
5022 let Predicates = [prd, HasVLX] in {
5023 defm Z256 : cvt_by_vec_width<opc, VTInfo.info256, OpcodeStr>, EVEX_V256;
5024 defm Z128 : cvt_by_vec_width<opc, VTInfo.info128, OpcodeStr>, EVEX_V128;
5025 }
5026}
5027
5028multiclass avx512_convert_mask_to_vector<string OpcodeStr> {
5029 defm NAME##B : cvt_mask_by_elt_width<0x28, avx512vl_i8_info, OpcodeStr,
5030 HasBWI>;
5031 defm NAME##W : cvt_mask_by_elt_width<0x28, avx512vl_i16_info, OpcodeStr,
5032 HasBWI>, VEX_W;
5033 defm NAME##D : cvt_mask_by_elt_width<0x38, avx512vl_i32_info, OpcodeStr,
5034 HasDQI>;
5035 defm NAME##Q : cvt_mask_by_elt_width<0x38, avx512vl_i64_info, OpcodeStr,
5036 HasDQI>, VEX_W;
5037}
5038
5039defm VPMOVM2 : avx512_convert_mask_to_vector<"vpmovm2">;