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gerrit-public.fairphone.software / toolchain / llvm-project / 56228dabfa51a3c810d258fcc1f2a8773c499c4d / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 88a0415f279a5a20d49898a048ab8d03c33b1d4e [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]41static cl::opt<bool> JumpIsExpensiveOverride(
42 "jump-is-expensive", cl::init(false),
43 cl::desc("Do not create extra branches to split comparison logic."),
44 cl::Hidden);
45
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]46/// InitLibcallNames - Set default libcall names.
47///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]48static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]49 Names[RTLIB::SHL_I16] = "__ashlhi3";
50 Names[RTLIB::SHL_I32] = "__ashlsi3";
51 Names[RTLIB::SHL_I64] = "__ashldi3";
52 Names[RTLIB::SHL_I128] = "__ashlti3";
53 Names[RTLIB::SRL_I16] = "__lshrhi3";
54 Names[RTLIB::SRL_I32] = "__lshrsi3";
55 Names[RTLIB::SRL_I64] = "__lshrdi3";
56 Names[RTLIB::SRL_I128] = "__lshrti3";
57 Names[RTLIB::SRA_I16] = "__ashrhi3";
58 Names[RTLIB::SRA_I32] = "__ashrsi3";
59 Names[RTLIB::SRA_I64] = "__ashrdi3";
60 Names[RTLIB::SRA_I128] = "__ashrti3";
61 Names[RTLIB::MUL_I8] = "__mulqi3";
62 Names[RTLIB::MUL_I16] = "__mulhi3";
63 Names[RTLIB::MUL_I32] = "__mulsi3";
64 Names[RTLIB::MUL_I64] = "__muldi3";
65 Names[RTLIB::MUL_I128] = "__multi3";
66 Names[RTLIB::MULO_I32] = "__mulosi4";
67 Names[RTLIB::MULO_I64] = "__mulodi4";
68 Names[RTLIB::MULO_I128] = "__muloti4";
69 Names[RTLIB::SDIV_I8] = "__divqi3";
70 Names[RTLIB::SDIV_I16] = "__divhi3";
71 Names[RTLIB::SDIV_I32] = "__divsi3";
72 Names[RTLIB::SDIV_I64] = "__divdi3";
73 Names[RTLIB::SDIV_I128] = "__divti3";
74 Names[RTLIB::UDIV_I8] = "__udivqi3";
75 Names[RTLIB::UDIV_I16] = "__udivhi3";
76 Names[RTLIB::UDIV_I32] = "__udivsi3";
77 Names[RTLIB::UDIV_I64] = "__udivdi3";
78 Names[RTLIB::UDIV_I128] = "__udivti3";
79 Names[RTLIB::SREM_I8] = "__modqi3";
80 Names[RTLIB::SREM_I16] = "__modhi3";
81 Names[RTLIB::SREM_I32] = "__modsi3";
82 Names[RTLIB::SREM_I64] = "__moddi3";
83 Names[RTLIB::SREM_I128] = "__modti3";
84 Names[RTLIB::UREM_I8] = "__umodqi3";
85 Names[RTLIB::UREM_I16] = "__umodhi3";
86 Names[RTLIB::UREM_I32] = "__umodsi3";
87 Names[RTLIB::UREM_I64] = "__umoddi3";
88 Names[RTLIB::UREM_I128] = "__umodti3";
89
90 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]91 Names[RTLIB::SDIVREM_I8] = nullptr;
92 Names[RTLIB::SDIVREM_I16] = nullptr;
93 Names[RTLIB::SDIVREM_I32] = nullptr;
94 Names[RTLIB::SDIVREM_I64] = nullptr;
95 Names[RTLIB::SDIVREM_I128] = nullptr;
96 Names[RTLIB::UDIVREM_I8] = nullptr;
97 Names[RTLIB::UDIVREM_I16] = nullptr;
98 Names[RTLIB::UDIVREM_I32] = nullptr;
99 Names[RTLIB::UDIVREM_I64] = nullptr;
100 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]101
102 Names[RTLIB::NEG_I32] = "__negsi2";
103 Names[RTLIB::NEG_I64] = "__negdi2";
104 Names[RTLIB::ADD_F32] = "__addsf3";
105 Names[RTLIB::ADD_F64] = "__adddf3";
106 Names[RTLIB::ADD_F80] = "__addxf3";
107 Names[RTLIB::ADD_F128] = "__addtf3";
108 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
109 Names[RTLIB::SUB_F32] = "__subsf3";
110 Names[RTLIB::SUB_F64] = "__subdf3";
111 Names[RTLIB::SUB_F80] = "__subxf3";
112 Names[RTLIB::SUB_F128] = "__subtf3";
113 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
114 Names[RTLIB::MUL_F32] = "__mulsf3";
115 Names[RTLIB::MUL_F64] = "__muldf3";
116 Names[RTLIB::MUL_F80] = "__mulxf3";
117 Names[RTLIB::MUL_F128] = "__multf3";
118 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
119 Names[RTLIB::DIV_F32] = "__divsf3";
120 Names[RTLIB::DIV_F64] = "__divdf3";
121 Names[RTLIB::DIV_F80] = "__divxf3";
122 Names[RTLIB::DIV_F128] = "__divtf3";
123 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
124 Names[RTLIB::REM_F32] = "fmodf";
125 Names[RTLIB::REM_F64] = "fmod";
126 Names[RTLIB::REM_F80] = "fmodl";
127 Names[RTLIB::REM_F128] = "fmodl";
128 Names[RTLIB::REM_PPCF128] = "fmodl";
129 Names[RTLIB::FMA_F32] = "fmaf";
130 Names[RTLIB::FMA_F64] = "fma";
131 Names[RTLIB::FMA_F80] = "fmal";
132 Names[RTLIB::FMA_F128] = "fmal";
133 Names[RTLIB::FMA_PPCF128] = "fmal";
134 Names[RTLIB::POWI_F32] = "__powisf2";
135 Names[RTLIB::POWI_F64] = "__powidf2";
136 Names[RTLIB::POWI_F80] = "__powixf2";
137 Names[RTLIB::POWI_F128] = "__powitf2";
138 Names[RTLIB::POWI_PPCF128] = "__powitf2";
139 Names[RTLIB::SQRT_F32] = "sqrtf";
140 Names[RTLIB::SQRT_F64] = "sqrt";
141 Names[RTLIB::SQRT_F80] = "sqrtl";
142 Names[RTLIB::SQRT_F128] = "sqrtl";
143 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
144 Names[RTLIB::LOG_F32] = "logf";
145 Names[RTLIB::LOG_F64] = "log";
146 Names[RTLIB::LOG_F80] = "logl";
147 Names[RTLIB::LOG_F128] = "logl";
148 Names[RTLIB::LOG_PPCF128] = "logl";
149 Names[RTLIB::LOG2_F32] = "log2f";
150 Names[RTLIB::LOG2_F64] = "log2";
151 Names[RTLIB::LOG2_F80] = "log2l";
152 Names[RTLIB::LOG2_F128] = "log2l";
153 Names[RTLIB::LOG2_PPCF128] = "log2l";
154 Names[RTLIB::LOG10_F32] = "log10f";
155 Names[RTLIB::LOG10_F64] = "log10";
156 Names[RTLIB::LOG10_F80] = "log10l";
157 Names[RTLIB::LOG10_F128] = "log10l";
158 Names[RTLIB::LOG10_PPCF128] = "log10l";
159 Names[RTLIB::EXP_F32] = "expf";
160 Names[RTLIB::EXP_F64] = "exp";
161 Names[RTLIB::EXP_F80] = "expl";
162 Names[RTLIB::EXP_F128] = "expl";
163 Names[RTLIB::EXP_PPCF128] = "expl";
164 Names[RTLIB::EXP2_F32] = "exp2f";
165 Names[RTLIB::EXP2_F64] = "exp2";
166 Names[RTLIB::EXP2_F80] = "exp2l";
167 Names[RTLIB::EXP2_F128] = "exp2l";
168 Names[RTLIB::EXP2_PPCF128] = "exp2l";
169 Names[RTLIB::SIN_F32] = "sinf";
170 Names[RTLIB::SIN_F64] = "sin";
171 Names[RTLIB::SIN_F80] = "sinl";
172 Names[RTLIB::SIN_F128] = "sinl";
173 Names[RTLIB::SIN_PPCF128] = "sinl";
174 Names[RTLIB::COS_F32] = "cosf";
175 Names[RTLIB::COS_F64] = "cos";
176 Names[RTLIB::COS_F80] = "cosl";
177 Names[RTLIB::COS_F128] = "cosl";
178 Names[RTLIB::COS_PPCF128] = "cosl";
179 Names[RTLIB::POW_F32] = "powf";
180 Names[RTLIB::POW_F64] = "pow";
181 Names[RTLIB::POW_F80] = "powl";
182 Names[RTLIB::POW_F128] = "powl";
183 Names[RTLIB::POW_PPCF128] = "powl";
184 Names[RTLIB::CEIL_F32] = "ceilf";
185 Names[RTLIB::CEIL_F64] = "ceil";
186 Names[RTLIB::CEIL_F80] = "ceill";
187 Names[RTLIB::CEIL_F128] = "ceill";
188 Names[RTLIB::CEIL_PPCF128] = "ceill";
189 Names[RTLIB::TRUNC_F32] = "truncf";
190 Names[RTLIB::TRUNC_F64] = "trunc";
191 Names[RTLIB::TRUNC_F80] = "truncl";
192 Names[RTLIB::TRUNC_F128] = "truncl";
193 Names[RTLIB::TRUNC_PPCF128] = "truncl";
194 Names[RTLIB::RINT_F32] = "rintf";
195 Names[RTLIB::RINT_F64] = "rint";
196 Names[RTLIB::RINT_F80] = "rintl";
197 Names[RTLIB::RINT_F128] = "rintl";
198 Names[RTLIB::RINT_PPCF128] = "rintl";
199 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
200 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
201 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
202 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
203 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]204 Names[RTLIB::ROUND_F32] = "roundf";
205 Names[RTLIB::ROUND_F64] = "round";
206 Names[RTLIB::ROUND_F80] = "roundl";
207 Names[RTLIB::ROUND_F128] = "roundl";
208 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]209 Names[RTLIB::FLOOR_F32] = "floorf";
210 Names[RTLIB::FLOOR_F64] = "floor";
211 Names[RTLIB::FLOOR_F80] = "floorl";
212 Names[RTLIB::FLOOR_F128] = "floorl";
213 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]214 Names[RTLIB::FMIN_F32] = "fminf";
215 Names[RTLIB::FMIN_F64] = "fmin";
216 Names[RTLIB::FMIN_F80] = "fminl";
217 Names[RTLIB::FMIN_F128] = "fminl";
218 Names[RTLIB::FMIN_PPCF128] = "fminl";
219 Names[RTLIB::FMAX_F32] = "fmaxf";
220 Names[RTLIB::FMAX_F64] = "fmax";
221 Names[RTLIB::FMAX_F80] = "fmaxl";
222 Names[RTLIB::FMAX_F128] = "fmaxl";
223 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]224 Names[RTLIB::ROUND_F32] = "roundf";
225 Names[RTLIB::ROUND_F64] = "round";
226 Names[RTLIB::ROUND_F80] = "roundl";
227 Names[RTLIB::ROUND_F128] = "roundl";
228 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]229 Names[RTLIB::COPYSIGN_F32] = "copysignf";
230 Names[RTLIB::COPYSIGN_F64] = "copysign";
231 Names[RTLIB::COPYSIGN_F80] = "copysignl";
232 Names[RTLIB::COPYSIGN_F128] = "copysignl";
233 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
234 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
235 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
236 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
237 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
238 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]239 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
240 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
241 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
242 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]243 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
244 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
245 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
246 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
247 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
248 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
249 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
250 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
251 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
252 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
253 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
254 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
255 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
256 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
257 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
258 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
259 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
260 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
261 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
262 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
263 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
264 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
265 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
266 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
267 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
268 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
269 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
270 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
271 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
272 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
273 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
274 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
275 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
276 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
277 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
278 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
279 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
280 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
281 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
282 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
283 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
284 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
285 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
286 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
287 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
288 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
289 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
290 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
291 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
292 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
293 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
294 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
295 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
296 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
297 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
298 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
299 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
300 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
301 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
302 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
303 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
304 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
305 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
306 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
307 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
308 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
309 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
310 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
311 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
312 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
313 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
314 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
315 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
316 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
317 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
318 Names[RTLIB::OEQ_F32] = "__eqsf2";
319 Names[RTLIB::OEQ_F64] = "__eqdf2";
320 Names[RTLIB::OEQ_F128] = "__eqtf2";
321 Names[RTLIB::UNE_F32] = "__nesf2";
322 Names[RTLIB::UNE_F64] = "__nedf2";
323 Names[RTLIB::UNE_F128] = "__netf2";
324 Names[RTLIB::OGE_F32] = "__gesf2";
325 Names[RTLIB::OGE_F64] = "__gedf2";
326 Names[RTLIB::OGE_F128] = "__getf2";
327 Names[RTLIB::OLT_F32] = "__ltsf2";
328 Names[RTLIB::OLT_F64] = "__ltdf2";
329 Names[RTLIB::OLT_F128] = "__lttf2";
330 Names[RTLIB::OLE_F32] = "__lesf2";
331 Names[RTLIB::OLE_F64] = "__ledf2";
332 Names[RTLIB::OLE_F128] = "__letf2";
333 Names[RTLIB::OGT_F32] = "__gtsf2";
334 Names[RTLIB::OGT_F64] = "__gtdf2";
335 Names[RTLIB::OGT_F128] = "__gttf2";
336 Names[RTLIB::UO_F32] = "__unordsf2";
337 Names[RTLIB::UO_F64] = "__unorddf2";
338 Names[RTLIB::UO_F128] = "__unordtf2";
339 Names[RTLIB::O_F32] = "__unordsf2";
340 Names[RTLIB::O_F64] = "__unorddf2";
341 Names[RTLIB::O_F128] = "__unordtf2";
342 Names[RTLIB::MEMCPY] = "memcpy";
343 Names[RTLIB::MEMMOVE] = "memmove";
344 Names[RTLIB::MEMSET] = "memset";
345 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
346 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
347 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
348 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
349 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]350 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]351 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
352 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
353 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
354 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]355 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]356 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
357 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
358 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
359 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
362 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
363 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
364 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
367 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
368 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
369 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]371 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
372 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
373 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
374 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]375 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]376 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
377 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
378 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
379 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]380 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]381 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
382 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
383 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
384 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]385 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]386 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
387 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
388 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
389 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
390 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
391 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
392 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
393 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
394 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
395 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
396 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
397 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
398 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
399 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
400 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
401 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
402 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
403 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
404 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
405 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]406
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]407 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]408 Names[RTLIB::SINCOS_F32] = "sincosf";
409 Names[RTLIB::SINCOS_F64] = "sincos";
410 Names[RTLIB::SINCOS_F80] = "sincosl";
411 Names[RTLIB::SINCOS_F128] = "sincosl";
412 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
413 } else {
414 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]415 Names[RTLIB::SINCOS_F32] = nullptr;
416 Names[RTLIB::SINCOS_F64] = nullptr;
417 Names[RTLIB::SINCOS_F80] = nullptr;
418 Names[RTLIB::SINCOS_F128] = nullptr;
419 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]420 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]421
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]422 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]423 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
424 } else {
425 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]426 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]427 }
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame]428
429 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
430 // of the gnueabi-style __gnu_*_ieee.
431 // FIXME: What about other targets?
432 if (TT.isOSDarwin()) {
433 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
434 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
435 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]436}
437
438/// InitLibcallCallingConvs - Set default libcall CallingConvs.
439///
440static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
441 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
442 CCs[i] = CallingConv::C;
443 }
444}
445
446/// getFPEXT - Return the FPEXT_*_* value for the given types, or
447/// UNKNOWN_LIBCALL if there is none.
448RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]449 if (OpVT == MVT::f16) {
450 if (RetVT == MVT::f32)
451 return FPEXT_F16_F32;
452 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]453 if (RetVT == MVT::f64)
454 return FPEXT_F32_F64;
455 if (RetVT == MVT::f128)
456 return FPEXT_F32_F128;
457 } else if (OpVT == MVT::f64) {
458 if (RetVT == MVT::f128)
459 return FPEXT_F64_F128;
460 }
461
462 return UNKNOWN_LIBCALL;
463}
464
465/// getFPROUND - Return the FPROUND_*_* value for the given types, or
466/// UNKNOWN_LIBCALL if there is none.
467RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]468 if (RetVT == MVT::f16) {
469 if (OpVT == MVT::f32)
470 return FPROUND_F32_F16;
471 if (OpVT == MVT::f64)
472 return FPROUND_F64_F16;
473 if (OpVT == MVT::f80)
474 return FPROUND_F80_F16;
475 if (OpVT == MVT::f128)
476 return FPROUND_F128_F16;
477 if (OpVT == MVT::ppcf128)
478 return FPROUND_PPCF128_F16;
479 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]480 if (OpVT == MVT::f64)
481 return FPROUND_F64_F32;
482 if (OpVT == MVT::f80)
483 return FPROUND_F80_F32;
484 if (OpVT == MVT::f128)
485 return FPROUND_F128_F32;
486 if (OpVT == MVT::ppcf128)
487 return FPROUND_PPCF128_F32;
488 } else if (RetVT == MVT::f64) {
489 if (OpVT == MVT::f80)
490 return FPROUND_F80_F64;
491 if (OpVT == MVT::f128)
492 return FPROUND_F128_F64;
493 if (OpVT == MVT::ppcf128)
494 return FPROUND_PPCF128_F64;
495 }
496
497 return UNKNOWN_LIBCALL;
498}
499
500/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
501/// UNKNOWN_LIBCALL if there is none.
502RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
503 if (OpVT == MVT::f32) {
504 if (RetVT == MVT::i8)
505 return FPTOSINT_F32_I8;
506 if (RetVT == MVT::i16)
507 return FPTOSINT_F32_I16;
508 if (RetVT == MVT::i32)
509 return FPTOSINT_F32_I32;
510 if (RetVT == MVT::i64)
511 return FPTOSINT_F32_I64;
512 if (RetVT == MVT::i128)
513 return FPTOSINT_F32_I128;
514 } else if (OpVT == MVT::f64) {
515 if (RetVT == MVT::i8)
516 return FPTOSINT_F64_I8;
517 if (RetVT == MVT::i16)
518 return FPTOSINT_F64_I16;
519 if (RetVT == MVT::i32)
520 return FPTOSINT_F64_I32;
521 if (RetVT == MVT::i64)
522 return FPTOSINT_F64_I64;
523 if (RetVT == MVT::i128)
524 return FPTOSINT_F64_I128;
525 } else if (OpVT == MVT::f80) {
526 if (RetVT == MVT::i32)
527 return FPTOSINT_F80_I32;
528 if (RetVT == MVT::i64)
529 return FPTOSINT_F80_I64;
530 if (RetVT == MVT::i128)
531 return FPTOSINT_F80_I128;
532 } else if (OpVT == MVT::f128) {
533 if (RetVT == MVT::i32)
534 return FPTOSINT_F128_I32;
535 if (RetVT == MVT::i64)
536 return FPTOSINT_F128_I64;
537 if (RetVT == MVT::i128)
538 return FPTOSINT_F128_I128;
539 } else if (OpVT == MVT::ppcf128) {
540 if (RetVT == MVT::i32)
541 return FPTOSINT_PPCF128_I32;
542 if (RetVT == MVT::i64)
543 return FPTOSINT_PPCF128_I64;
544 if (RetVT == MVT::i128)
545 return FPTOSINT_PPCF128_I128;
546 }
547 return UNKNOWN_LIBCALL;
548}
549
550/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
551/// UNKNOWN_LIBCALL if there is none.
552RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
553 if (OpVT == MVT::f32) {
554 if (RetVT == MVT::i8)
555 return FPTOUINT_F32_I8;
556 if (RetVT == MVT::i16)
557 return FPTOUINT_F32_I16;
558 if (RetVT == MVT::i32)
559 return FPTOUINT_F32_I32;
560 if (RetVT == MVT::i64)
561 return FPTOUINT_F32_I64;
562 if (RetVT == MVT::i128)
563 return FPTOUINT_F32_I128;
564 } else if (OpVT == MVT::f64) {
565 if (RetVT == MVT::i8)
566 return FPTOUINT_F64_I8;
567 if (RetVT == MVT::i16)
568 return FPTOUINT_F64_I16;
569 if (RetVT == MVT::i32)
570 return FPTOUINT_F64_I32;
571 if (RetVT == MVT::i64)
572 return FPTOUINT_F64_I64;
573 if (RetVT == MVT::i128)
574 return FPTOUINT_F64_I128;
575 } else if (OpVT == MVT::f80) {
576 if (RetVT == MVT::i32)
577 return FPTOUINT_F80_I32;
578 if (RetVT == MVT::i64)
579 return FPTOUINT_F80_I64;
580 if (RetVT == MVT::i128)
581 return FPTOUINT_F80_I128;
582 } else if (OpVT == MVT::f128) {
583 if (RetVT == MVT::i32)
584 return FPTOUINT_F128_I32;
585 if (RetVT == MVT::i64)
586 return FPTOUINT_F128_I64;
587 if (RetVT == MVT::i128)
588 return FPTOUINT_F128_I128;
589 } else if (OpVT == MVT::ppcf128) {
590 if (RetVT == MVT::i32)
591 return FPTOUINT_PPCF128_I32;
592 if (RetVT == MVT::i64)
593 return FPTOUINT_PPCF128_I64;
594 if (RetVT == MVT::i128)
595 return FPTOUINT_PPCF128_I128;
596 }
597 return UNKNOWN_LIBCALL;
598}
599
600/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
601/// UNKNOWN_LIBCALL if there is none.
602RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
603 if (OpVT == MVT::i32) {
604 if (RetVT == MVT::f32)
605 return SINTTOFP_I32_F32;
606 if (RetVT == MVT::f64)
607 return SINTTOFP_I32_F64;
608 if (RetVT == MVT::f80)
609 return SINTTOFP_I32_F80;
610 if (RetVT == MVT::f128)
611 return SINTTOFP_I32_F128;
612 if (RetVT == MVT::ppcf128)
613 return SINTTOFP_I32_PPCF128;
614 } else if (OpVT == MVT::i64) {
615 if (RetVT == MVT::f32)
616 return SINTTOFP_I64_F32;
617 if (RetVT == MVT::f64)
618 return SINTTOFP_I64_F64;
619 if (RetVT == MVT::f80)
620 return SINTTOFP_I64_F80;
621 if (RetVT == MVT::f128)
622 return SINTTOFP_I64_F128;
623 if (RetVT == MVT::ppcf128)
624 return SINTTOFP_I64_PPCF128;
625 } else if (OpVT == MVT::i128) {
626 if (RetVT == MVT::f32)
627 return SINTTOFP_I128_F32;
628 if (RetVT == MVT::f64)
629 return SINTTOFP_I128_F64;
630 if (RetVT == MVT::f80)
631 return SINTTOFP_I128_F80;
632 if (RetVT == MVT::f128)
633 return SINTTOFP_I128_F128;
634 if (RetVT == MVT::ppcf128)
635 return SINTTOFP_I128_PPCF128;
636 }
637 return UNKNOWN_LIBCALL;
638}
639
640/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
641/// UNKNOWN_LIBCALL if there is none.
642RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
643 if (OpVT == MVT::i32) {
644 if (RetVT == MVT::f32)
645 return UINTTOFP_I32_F32;
646 if (RetVT == MVT::f64)
647 return UINTTOFP_I32_F64;
648 if (RetVT == MVT::f80)
649 return UINTTOFP_I32_F80;
650 if (RetVT == MVT::f128)
651 return UINTTOFP_I32_F128;
652 if (RetVT == MVT::ppcf128)
653 return UINTTOFP_I32_PPCF128;
654 } else if (OpVT == MVT::i64) {
655 if (RetVT == MVT::f32)
656 return UINTTOFP_I64_F32;
657 if (RetVT == MVT::f64)
658 return UINTTOFP_I64_F64;
659 if (RetVT == MVT::f80)
660 return UINTTOFP_I64_F80;
661 if (RetVT == MVT::f128)
662 return UINTTOFP_I64_F128;
663 if (RetVT == MVT::ppcf128)
664 return UINTTOFP_I64_PPCF128;
665 } else if (OpVT == MVT::i128) {
666 if (RetVT == MVT::f32)
667 return UINTTOFP_I128_F32;
668 if (RetVT == MVT::f64)
669 return UINTTOFP_I128_F64;
670 if (RetVT == MVT::f80)
671 return UINTTOFP_I128_F80;
672 if (RetVT == MVT::f128)
673 return UINTTOFP_I128_F128;
674 if (RetVT == MVT::ppcf128)
675 return UINTTOFP_I128_PPCF128;
676 }
677 return UNKNOWN_LIBCALL;
678}
679
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]680RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) {
681#define OP_TO_LIBCALL(Name, Enum) \
682 case Name: \
683 switch (VT.SimpleTy) { \
684 default: \
685 return UNKNOWN_LIBCALL; \
686 case MVT::i8: \
687 return Enum##_1; \
688 case MVT::i16: \
689 return Enum##_2; \
690 case MVT::i32: \
691 return Enum##_4; \
692 case MVT::i64: \
693 return Enum##_8; \
694 case MVT::i128: \
695 return Enum##_16; \
696 }
697
698 switch (Opc) {
699 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
700 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
701 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
702 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
703 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
704 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
705 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
706 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
707 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
708 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
709 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
710 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
711 }
712
713#undef OP_TO_LIBCALL
714
715 return UNKNOWN_LIBCALL;
716}
717
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]718/// InitCmpLibcallCCs - Set default comparison libcall CC.
719///
720static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
721 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
722 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
723 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
724 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
725 CCs[RTLIB::UNE_F32] = ISD::SETNE;
726 CCs[RTLIB::UNE_F64] = ISD::SETNE;
727 CCs[RTLIB::UNE_F128] = ISD::SETNE;
728 CCs[RTLIB::OGE_F32] = ISD::SETGE;
729 CCs[RTLIB::OGE_F64] = ISD::SETGE;
730 CCs[RTLIB::OGE_F128] = ISD::SETGE;
731 CCs[RTLIB::OLT_F32] = ISD::SETLT;
732 CCs[RTLIB::OLT_F64] = ISD::SETLT;
733 CCs[RTLIB::OLT_F128] = ISD::SETLT;
734 CCs[RTLIB::OLE_F32] = ISD::SETLE;
735 CCs[RTLIB::OLE_F64] = ISD::SETLE;
736 CCs[RTLIB::OLE_F128] = ISD::SETLE;
737 CCs[RTLIB::OGT_F32] = ISD::SETGT;
738 CCs[RTLIB::OGT_F64] = ISD::SETGT;
739 CCs[RTLIB::OGT_F128] = ISD::SETGT;
740 CCs[RTLIB::UO_F32] = ISD::SETNE;
741 CCs[RTLIB::UO_F64] = ISD::SETNE;
742 CCs[RTLIB::UO_F128] = ISD::SETNE;
743 CCs[RTLIB::O_F32] = ISD::SETEQ;
744 CCs[RTLIB::O_F64] = ISD::SETEQ;
745 CCs[RTLIB::O_F128] = ISD::SETEQ;
746}
747
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]748/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]749TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]750 initActions();
751
752 // Perform these initializations only once.
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]753 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
754 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
755 = MaxStoresPerMemmoveOptSize = 4;
756 UseUnderscoreSetJmp = false;
757 UseUnderscoreLongJmp = false;
758 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]759 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]760 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]761 IntDivIsCheap = false;
Matt Arsenaultbf0db912015-01-13 20:53:23 +0000[diff] [blame]762 FsqrtIsCheap = false;
Sanjay Patel2cdea4c2014-08-21 22:31:48 +0000[diff] [blame]763 Pow2SDivIsCheap = false;
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]764 JumpIsExpensive = JumpIsExpensiveOverride;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]765 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]766 MaskAndBranchFoldingIsLegal = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]767 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]768 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]769 StackPointerRegisterToSaveRestore = 0;
770 ExceptionPointerRegister = 0;
771 ExceptionSelectorRegister = 0;
772 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]773 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]774 BooleanVectorContents = UndefinedBooleanContent;
775 SchedPreferenceInfo = Sched::ILP;
776 JumpBufSize = 0;
777 JumpBufAlignment = 0;
778 MinFunctionAlignment = 0;
779 PrefFunctionAlignment = 0;
780 PrefLoopAlignment = 0;
781 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]782 InsertFencesForAtomic = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]783 MinimumJumpTableEntries = 4;
784
Daniel Sanders110bf6d2015-06-24 13:25:57 +0000[diff] [blame]785 InitLibcallNames(LibcallRoutineNames, TM.getTargetTriple());
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]786 InitCmpLibcallCCs(CmpLibcallCCs);
787 InitLibcallCallingConvs(LibcallCallingConvs);
788}
789
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]790void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]791 // All operations default to being supported.
792 memset(OpActions, 0, sizeof(OpActions));
793 memset(LoadExtActions, 0, sizeof(LoadExtActions));
794 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
795 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
796 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]797 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
798 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]799
800 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]801 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]802 // Default all indexed load / store to expand.
803 for (unsigned IM = (unsigned)ISD::PRE_INC;
804 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]805 setIndexedLoadAction(IM, VT, Expand);
806 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]807 }
808
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]809 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]810 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]811
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]812 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]813 setOperationAction(ISD::FGETSIGN, VT, Expand);
814 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
815 setOperationAction(ISD::FMINNUM, VT, Expand);
816 setOperationAction(ISD::FMAXNUM, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]817 setOperationAction(ISD::FMAD, VT, Expand);
James Molloy7e9776b2015-05-15 09:03:15 +0000[diff] [blame]818 setOperationAction(ISD::SMIN, VT, Expand);
819 setOperationAction(ISD::SMAX, VT, Expand);
820 setOperationAction(ISD::UMIN, VT, Expand);
821 setOperationAction(ISD::UMAX, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]822
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]823 // Overflow operations default to expand
824 setOperationAction(ISD::SADDO, VT, Expand);
825 setOperationAction(ISD::SSUBO, VT, Expand);
826 setOperationAction(ISD::UADDO, VT, Expand);
827 setOperationAction(ISD::USUBO, VT, Expand);
828 setOperationAction(ISD::SMULO, VT, Expand);
829 setOperationAction(ISD::UMULO, VT, Expand);
830
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]831 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]832 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]833
834 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]835 if (VT.isVector()) {
836 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
837 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
838 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
839 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]840 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]841 }
842
843 // Most targets ignore the @llvm.prefetch intrinsic.
844 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
845
846 // ConstantFP nodes default to expand. Targets can either change this to
847 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
848 // to optimize expansions for certain constants.
849 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
850 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
851 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
852 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
853 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
854
855 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]856 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
857 setOperationAction(ISD::FLOG , VT, Expand);
858 setOperationAction(ISD::FLOG2, VT, Expand);
859 setOperationAction(ISD::FLOG10, VT, Expand);
860 setOperationAction(ISD::FEXP , VT, Expand);
861 setOperationAction(ISD::FEXP2, VT, Expand);
862 setOperationAction(ISD::FFLOOR, VT, Expand);
863 setOperationAction(ISD::FMINNUM, VT, Expand);
864 setOperationAction(ISD::FMAXNUM, VT, Expand);
865 setOperationAction(ISD::FNEARBYINT, VT, Expand);
866 setOperationAction(ISD::FCEIL, VT, Expand);
867 setOperationAction(ISD::FRINT, VT, Expand);
868 setOperationAction(ISD::FTRUNC, VT, Expand);
869 setOperationAction(ISD::FROUND, VT, Expand);
870 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]871
872 // Default ISD::TRAP to expand (which turns it into abort).
873 setOperationAction(ISD::TRAP, MVT::Other, Expand);
874
875 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
876 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
877 //
878 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]879}
880
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]881MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
882 return MVT::getIntegerVT(getPointerSizeInBits(AS));
883}
884
885unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]886 return getDataLayout()->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]887}
888
889unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
890 assert(Ty->isPointerTy());
891 return getPointerSizeInBits(Ty->getPointerAddressSpace());
892}
893
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]894MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]895 return MVT::getIntegerVT(8 * getDataLayout()->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]896}
897
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]898EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
899 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
900 if (LHSTy.isVector())
901 return LHSTy;
902 return getScalarShiftAmountTy(LHSTy);
903}
904
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]905/// canOpTrap - Returns true if the operation can trap for the value type.
906/// VT must be a legal type.
907bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
908 assert(isTypeLegal(VT));
909 switch (Op) {
910 default:
911 return false;
912 case ISD::FDIV:
913 case ISD::FREM:
914 case ISD::SDIV:
915 case ISD::UDIV:
916 case ISD::SREM:
917 case ISD::UREM:
918 return true;
919 }
920}
921
Sanjay Patel943829a2015-07-01 18:10:20 +0000[diff] [blame]922void TargetLoweringBase::setJumpIsExpensive(bool isExpensive) {
923 // If the command-line option was specified, ignore this request.
924 if (!JumpIsExpensiveOverride.getNumOccurrences())
925 JumpIsExpensive = isExpensive;
926}
927
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]928TargetLoweringBase::LegalizeKind
929TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
930 // If this is a simple type, use the ComputeRegisterProp mechanism.
931 if (VT.isSimple()) {
932 MVT SVT = VT.getSimpleVT();
933 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
934 MVT NVT = TransformToType[SVT.SimpleTy];
935 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
936
937 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
938 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
939 "Promote may not follow Expand or Promote");
940
941 if (LA == TypeSplitVector)
942 return LegalizeKind(LA,
943 EVT::getVectorVT(Context, SVT.getVectorElementType(),
944 SVT.getVectorNumElements() / 2));
945 if (LA == TypeScalarizeVector)
946 return LegalizeKind(LA, SVT.getVectorElementType());
947 return LegalizeKind(LA, NVT);
948 }
949
950 // Handle Extended Scalar Types.
951 if (!VT.isVector()) {
952 assert(VT.isInteger() && "Float types must be simple");
953 unsigned BitSize = VT.getSizeInBits();
954 // First promote to a power-of-two size, then expand if necessary.
955 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
956 EVT NVT = VT.getRoundIntegerType(Context);
957 assert(NVT != VT && "Unable to round integer VT");
958 LegalizeKind NextStep = getTypeConversion(Context, NVT);
959 // Avoid multi-step promotion.
960 if (NextStep.first == TypePromoteInteger)
961 return NextStep;
962 // Return rounded integer type.
963 return LegalizeKind(TypePromoteInteger, NVT);
964 }
965
966 return LegalizeKind(TypeExpandInteger,
967 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
968 }
969
970 // Handle vector types.
971 unsigned NumElts = VT.getVectorNumElements();
972 EVT EltVT = VT.getVectorElementType();
973
974 // Vectors with only one element are always scalarized.
975 if (NumElts == 1)
976 return LegalizeKind(TypeScalarizeVector, EltVT);
977
978 // Try to widen vector elements until the element type is a power of two and
979 // promote it to a legal type later on, for example:
980 // <3 x i8> -> <4 x i8> -> <4 x i32>
981 if (EltVT.isInteger()) {
982 // Vectors with a number of elements that is not a power of two are always
983 // widened, for example <3 x i8> -> <4 x i8>.
984 if (!VT.isPow2VectorType()) {
985 NumElts = (unsigned)NextPowerOf2(NumElts);
986 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
987 return LegalizeKind(TypeWidenVector, NVT);
988 }
989
990 // Examine the element type.
991 LegalizeKind LK = getTypeConversion(Context, EltVT);
992
993 // If type is to be expanded, split the vector.
994 // <4 x i140> -> <2 x i140>
995 if (LK.first == TypeExpandInteger)
996 return LegalizeKind(TypeSplitVector,
997 EVT::getVectorVT(Context, EltVT, NumElts / 2));
998
999 // Promote the integer element types until a legal vector type is found
1000 // or until the element integer type is too big. If a legal type was not
1001 // found, fallback to the usual mechanism of widening/splitting the
1002 // vector.
1003 EVT OldEltVT = EltVT;
1004 while (1) {
1005 // Increase the bitwidth of the element to the next pow-of-two
1006 // (which is greater than 8 bits).
1007 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
1008 .getRoundIntegerType(Context);
1009
1010 // Stop trying when getting a non-simple element type.
1011 // Note that vector elements may be greater than legal vector element
1012 // types. Example: X86 XMM registers hold 64bit element on 32bit
1013 // systems.
1014 if (!EltVT.isSimple())
1015 break;
1016
1017 // Build a new vector type and check if it is legal.
1018 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1019 // Found a legal promoted vector type.
1020 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1021 return LegalizeKind(TypePromoteInteger,
1022 EVT::getVectorVT(Context, EltVT, NumElts));
1023 }
1024
1025 // Reset the type to the unexpanded type if we did not find a legal vector
1026 // type with a promoted vector element type.
1027 EltVT = OldEltVT;
1028 }
1029
1030 // Try to widen the vector until a legal type is found.
1031 // If there is no wider legal type, split the vector.
1032 while (1) {
1033 // Round up to the next power of 2.
1034 NumElts = (unsigned)NextPowerOf2(NumElts);
1035
1036 // If there is no simple vector type with this many elements then there
1037 // cannot be a larger legal vector type. Note that this assumes that
1038 // there are no skipped intermediate vector types in the simple types.
1039 if (!EltVT.isSimple())
1040 break;
1041 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1042 if (LargerVector == MVT())
1043 break;
1044
1045 // If this type is legal then widen the vector.
1046 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1047 return LegalizeKind(TypeWidenVector, LargerVector);
1048 }
1049
1050 // Widen odd vectors to next power of two.
1051 if (!VT.isPow2VectorType()) {
1052 EVT NVT = VT.getPow2VectorType(Context);
1053 return LegalizeKind(TypeWidenVector, NVT);
1054 }
1055
1056 // Vectors with illegal element types are expanded.
1057 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1058 return LegalizeKind(TypeSplitVector, NVT);
1059}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1060
1061static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1062 unsigned &NumIntermediates,
1063 MVT &RegisterVT,
1064 TargetLoweringBase *TLI) {
1065 // Figure out the right, legal destination reg to copy into.
1066 unsigned NumElts = VT.getVectorNumElements();
1067 MVT EltTy = VT.getVectorElementType();
1068
1069 unsigned NumVectorRegs = 1;
1070
1071 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1072 // could break down into LHS/RHS like LegalizeDAG does.
1073 if (!isPowerOf2_32(NumElts)) {
1074 NumVectorRegs = NumElts;
1075 NumElts = 1;
1076 }
1077
1078 // Divide the input until we get to a supported size. This will always
1079 // end with a scalar if the target doesn't support vectors.
1080 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1081 NumElts >>= 1;
1082 NumVectorRegs <<= 1;
1083 }
1084
1085 NumIntermediates = NumVectorRegs;
1086
1087 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1088 if (!TLI->isTypeLegal(NewVT))
1089 NewVT = EltTy;
1090 IntermediateVT = NewVT;
1091
1092 unsigned NewVTSize = NewVT.getSizeInBits();
1093
1094 // Convert sizes such as i33 to i64.
1095 if (!isPowerOf2_32(NewVTSize))
1096 NewVTSize = NextPowerOf2(NewVTSize);
1097
1098 MVT DestVT = TLI->getRegisterType(NewVT);
1099 RegisterVT = DestVT;
1100 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1101 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1102
1103 // Otherwise, promotion or legal types use the same number of registers as
1104 // the vector decimated to the appropriate level.
1105 return NumVectorRegs;
1106}
1107
1108/// isLegalRC - Return true if the value types that can be represented by the
1109/// specified register class are all legal.
1110bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
1111 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1112 I != E; ++I) {
1113 if (isTypeLegal(*I))
1114 return true;
1115 }
1116 return false;
1117}
1118
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1119/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1120/// sequence of memory operands that is recognized by PrologEpilogInserter.
1121MachineBasicBlock*
1122TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
1123 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1124 MachineFunction &MF = *MI->getParent()->getParent();
1125
1126 // MI changes inside this loop as we grow operands.
1127 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1128 MachineOperand &MO = MI->getOperand(OperIdx);
1129 if (!MO.isFI())
1130 continue;
1131
1132 // foldMemoryOperand builds a new MI after replacing a single FI operand
1133 // with the canonical set of five x86 addressing-mode operands.
1134 int FI = MO.getIndex();
1135 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1136
1137 // Copy operands before the frame-index.
1138 for (unsigned i = 0; i < OperIdx; ++i)
1139 MIB.addOperand(MI->getOperand(i));
1140 // Add frame index operands: direct-mem-ref tag, #FI, offset.
1141 MIB.addImm(StackMaps::DirectMemRefOp);
1142 MIB.addOperand(MI->getOperand(OperIdx));
1143 MIB.addImm(0);
1144 // Copy the operands after the frame index.
1145 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1146 MIB.addOperand(MI->getOperand(i));
1147
1148 // Inherit previous memory operands.
1149 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1150 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1151
1152 // Add a new memory operand for this FI.
1153 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1154 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1155
1156 unsigned Flags = MachineMemOperand::MOLoad;
1157 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1158 Flags |= MachineMemOperand::MOStore;
1159 Flags |= MachineMemOperand::MOVolatile;
1160 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1161 MachineMemOperand *MMO = MF.getMachineMemOperand(
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1162 MachinePointerInfo::getFixedStack(FI), Flags,
Eric Christopher8b770652015-01-26 19:03:15 +0000[diff] [blame]1163 TM.getDataLayout()->getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1164 MIB->addMemOperand(MF, MMO);
1165
1166 // Replace the instruction and update the operand index.
1167 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1168 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1169 MI->eraseFromParent();
1170 MI = MIB;
1171 }
1172 return MBB;
1173}
1174
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1175/// findRepresentativeClass - Return the largest legal super-reg register class
1176/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1177// This function is in TargetLowering because it uses RegClassForVT which would
1178// need to be moved to TargetRegisterInfo and would necessitate moving
1179// isTypeLegal over as well - a massive change that would just require
1180// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1181std::pair<const TargetRegisterClass *, uint8_t>
1182TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1183 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1184 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1185 if (!RC)
1186 return std::make_pair(RC, 0);
1187
1188 // Compute the set of all super-register classes.
1189 BitVector SuperRegRC(TRI->getNumRegClasses());
1190 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1191 SuperRegRC.setBitsInMask(RCI.getMask());
1192
1193 // Find the first legal register class with the largest spill size.
1194 const TargetRegisterClass *BestRC = RC;
1195 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1196 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1197 // We want the largest possible spill size.
1198 if (SuperRC->getSize() <= BestRC->getSize())
1199 continue;
1200 if (!isLegalRC(SuperRC))
1201 continue;
1202 BestRC = SuperRC;
1203 }
1204 return std::make_pair(BestRC, 1);
1205}
1206
1207/// computeRegisterProperties - Once all of the register classes are added,
1208/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1209void TargetLoweringBase::computeRegisterProperties(
1210 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1211 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1212 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1213
1214 // Everything defaults to needing one register.
1215 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1216 NumRegistersForVT[i] = 1;
1217 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1218 }
1219 // ...except isVoid, which doesn't need any registers.
1220 NumRegistersForVT[MVT::isVoid] = 0;
1221
1222 // Find the largest integer register class.
1223 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1224 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1225 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1226
1227 // Every integer value type larger than this largest register takes twice as
1228 // many registers to represent as the previous ValueType.
1229 for (unsigned ExpandedReg = LargestIntReg + 1;
1230 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1231 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1232 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1233 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1234 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1235 TypeExpandInteger);
1236 }
1237
1238 // Inspect all of the ValueType's smaller than the largest integer
1239 // register to see which ones need promotion.
1240 unsigned LegalIntReg = LargestIntReg;
1241 for (unsigned IntReg = LargestIntReg - 1;
1242 IntReg >= (unsigned)MVT::i1; --IntReg) {
1243 MVT IVT = (MVT::SimpleValueType)IntReg;
1244 if (isTypeLegal(IVT)) {
1245 LegalIntReg = IntReg;
1246 } else {
1247 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1248 (const MVT::SimpleValueType)LegalIntReg;
1249 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1250 }
1251 }
1252
1253 // ppcf128 type is really two f64's.
1254 if (!isTypeLegal(MVT::ppcf128)) {
1255 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1256 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1257 TransformToType[MVT::ppcf128] = MVT::f64;
1258 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1259 }
1260
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1261 // Decide how to handle f128. If the target does not have native f128 support,
1262 // expand it to i128 and we will be generating soft float library calls.
1263 if (!isTypeLegal(MVT::f128)) {
1264 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1265 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1266 TransformToType[MVT::f128] = MVT::i128;
1267 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1268 }
1269
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1270 // Decide how to handle f64. If the target does not have native f64 support,
1271 // expand it to i64 and we will be generating soft float library calls.
1272 if (!isTypeLegal(MVT::f64)) {
1273 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1274 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1275 TransformToType[MVT::f64] = MVT::i64;
1276 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1277 }
1278
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1279 // Decide how to handle f32. If the target does not have native f32 support,
1280 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1281 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1282 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1283 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1284 TransformToType[MVT::f32] = MVT::i32;
1285 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1286 }
1287
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1288 if (!isTypeLegal(MVT::f16)) {
Pirama Arumuga Nainardb7c07e22015-04-17 18:36:25 +0000[diff] [blame]1289 // If the target has native f32 support, promote f16 operations to f32. If
1290 // f32 is not supported, generate soft float library calls.
1291 if (isTypeLegal(MVT::f32)) {
1292 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1293 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1294 TransformToType[MVT::f16] = MVT::f32;
1295 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1296 } else {
1297 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1298 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1299 TransformToType[MVT::f16] = MVT::i16;
1300 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1301 }
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1302 }
1303
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1304 // Loop over all of the vector value types to see which need transformations.
1305 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1306 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1307 MVT VT = (MVT::SimpleValueType) i;
1308 if (isTypeLegal(VT))
1309 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1310
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1311 MVT EltVT = VT.getVectorElementType();
1312 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1313 bool IsLegalWiderType = false;
1314 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1315 switch (PreferredAction) {
1316 case TypePromoteInteger: {
1317 // Try to promote the elements of integer vectors. If no legal
1318 // promotion was found, fall through to the widen-vector method.
1319 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1320 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1321 // Promote vectors of integers to vectors with the same number
1322 // of elements, with a wider element type.
1323 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1324 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1325 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1326 TransformToType[i] = SVT;
1327 RegisterTypeForVT[i] = SVT;
1328 NumRegistersForVT[i] = 1;
1329 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1330 IsLegalWiderType = true;
1331 break;
1332 }
1333 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1334 if (IsLegalWiderType)
1335 break;
1336 }
1337 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1338 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1339 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1340 MVT SVT = (MVT::SimpleValueType) nVT;
1341 if (SVT.getVectorElementType() == EltVT
1342 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1343 TransformToType[i] = SVT;
1344 RegisterTypeForVT[i] = SVT;
1345 NumRegistersForVT[i] = 1;
1346 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1347 IsLegalWiderType = true;
1348 break;
1349 }
1350 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1351 if (IsLegalWiderType)
1352 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1353 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1354 case TypeSplitVector:
1355 case TypeScalarizeVector: {
1356 MVT IntermediateVT;
1357 MVT RegisterVT;
1358 unsigned NumIntermediates;
1359 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1360 NumIntermediates, RegisterVT, this);
1361 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1362
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1363 MVT NVT = VT.getPow2VectorType();
1364 if (NVT == VT) {
1365 // Type is already a power of 2. The default action is to split.
1366 TransformToType[i] = MVT::Other;
1367 if (PreferredAction == TypeScalarizeVector)
1368 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1369 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1370 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1371 else
1372 // Set type action according to the number of elements.
1373 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1374 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1375 } else {
1376 TransformToType[i] = NVT;
1377 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1378 }
1379 break;
1380 }
1381 default:
1382 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1383 }
1384 }
1385
1386 // Determine the 'representative' register class for each value type.
1387 // An representative register class is the largest (meaning one which is
1388 // not a sub-register class / subreg register class) legal register class for
1389 // a group of value types. For example, on i386, i8, i16, and i32
1390 // representative would be GR32; while on x86_64 it's GR64.
1391 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1392 const TargetRegisterClass* RRC;
1393 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1394 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1395 RepRegClassForVT[i] = RRC;
1396 RepRegClassCostForVT[i] = Cost;
1397 }
1398}
1399
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1400EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1401 assert(!VT.isVector() && "No default SetCC type for vectors!");
1402 return getPointerTy(0).SimpleTy;
1403}
1404
1405MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1406 return MVT::i32; // return the default value
1407}
1408
1409/// getVectorTypeBreakdown - Vector types are broken down into some number of
1410/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1411/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1412/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1413///
1414/// This method returns the number of registers needed, and the VT for each
1415/// register. It also returns the VT and quantity of the intermediate values
1416/// before they are promoted/expanded.
1417///
1418unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1419 EVT &IntermediateVT,
1420 unsigned &NumIntermediates,
1421 MVT &RegisterVT) const {
1422 unsigned NumElts = VT.getVectorNumElements();
1423
1424 // If there is a wider vector type with the same element type as this one,
1425 // or a promoted vector type that has the same number of elements which
1426 // are wider, then we should convert to that legal vector type.
1427 // This handles things like <2 x float> -> <4 x float> and
1428 // <4 x i1> -> <4 x i32>.
1429 LegalizeTypeAction TA = getTypeAction(Context, VT);
1430 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1431 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1432 if (isTypeLegal(RegisterEVT)) {
1433 IntermediateVT = RegisterEVT;
1434 RegisterVT = RegisterEVT.getSimpleVT();
1435 NumIntermediates = 1;
1436 return 1;
1437 }
1438 }
1439
1440 // Figure out the right, legal destination reg to copy into.
1441 EVT EltTy = VT.getVectorElementType();
1442
1443 unsigned NumVectorRegs = 1;
1444
1445 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1446 // could break down into LHS/RHS like LegalizeDAG does.
1447 if (!isPowerOf2_32(NumElts)) {
1448 NumVectorRegs = NumElts;
1449 NumElts = 1;
1450 }
1451
1452 // Divide the input until we get to a supported size. This will always
1453 // end with a scalar if the target doesn't support vectors.
1454 while (NumElts > 1 && !isTypeLegal(
1455 EVT::getVectorVT(Context, EltTy, NumElts))) {
1456 NumElts >>= 1;
1457 NumVectorRegs <<= 1;
1458 }
1459
1460 NumIntermediates = NumVectorRegs;
1461
1462 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1463 if (!isTypeLegal(NewVT))
1464 NewVT = EltTy;
1465 IntermediateVT = NewVT;
1466
1467 MVT DestVT = getRegisterType(Context, NewVT);
1468 RegisterVT = DestVT;
1469 unsigned NewVTSize = NewVT.getSizeInBits();
1470
1471 // Convert sizes such as i33 to i64.
1472 if (!isPowerOf2_32(NewVTSize))
1473 NewVTSize = NextPowerOf2(NewVTSize);
1474
1475 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1476 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1477
1478 // Otherwise, promotion or legal types use the same number of registers as
1479 // the vector decimated to the appropriate level.
1480 return NumVectorRegs;
1481}
1482
1483/// Get the EVTs and ArgFlags collections that represent the legalized return
1484/// type of the given function. This does not require a DAG or a return value,
1485/// and is suitable for use before any DAGs for the function are constructed.
1486/// TODO: Move this out of TargetLowering.cpp.
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame^]1487void llvm::GetReturnInfo(Type *ReturnType, AttributeSet attr,
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1488 SmallVectorImpl<ISD::OutputArg> &Outs,
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame^]1489 const TargetLowering &TLI, const DataLayout &DL) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1490 SmallVector<EVT, 4> ValueVTs;
Mehdi Amini56228da2015-07-09 01:57:34 +0000[diff] [blame^]1491 ComputeValueVTs(TLI, DL, ReturnType, ValueVTs);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1492 unsigned NumValues = ValueVTs.size();
1493 if (NumValues == 0) return;
1494
1495 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1496 EVT VT = ValueVTs[j];
1497 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1498
1499 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1500 ExtendKind = ISD::SIGN_EXTEND;
1501 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1502 ExtendKind = ISD::ZERO_EXTEND;
1503
1504 // FIXME: C calling convention requires the return type to be promoted to
1505 // at least 32-bit. But this is not necessary for non-C calling
1506 // conventions. The frontend should mark functions whose return values
1507 // require promoting with signext or zeroext attributes.
1508 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1509 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1510 if (VT.bitsLT(MinVT))
1511 VT = MinVT;
1512 }
1513
1514 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1515 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1516
1517 // 'inreg' on function refers to return value
1518 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1519 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1520 Flags.setInReg();
1521
1522 // Propagate extension type if any
1523 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1524 Flags.setSExt();
1525 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1526 Flags.setZExt();
1527
1528 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1529 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1530 }
1531}
1532
1533/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1534/// function arguments in the caller parameter area. This is the actual
1535/// alignment, not its logarithm.
1536unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]1537 return getDataLayout()->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1538}
1539
1540//===----------------------------------------------------------------------===//
1541// TargetTransformInfo Helpers
1542//===----------------------------------------------------------------------===//
1543
1544int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1545 enum InstructionOpcodes {
1546#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1547#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1548#include "llvm/IR/Instruction.def"
1549 };
1550 switch (static_cast<InstructionOpcodes>(Opcode)) {
1551 case Ret: return 0;
1552 case Br: return 0;
1553 case Switch: return 0;
1554 case IndirectBr: return 0;
1555 case Invoke: return 0;
1556 case Resume: return 0;
1557 case Unreachable: return 0;
1558 case Add: return ISD::ADD;
1559 case FAdd: return ISD::FADD;
1560 case Sub: return ISD::SUB;
1561 case FSub: return ISD::FSUB;
1562 case Mul: return ISD::MUL;
1563 case FMul: return ISD::FMUL;
1564 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1565 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1566 case FDiv: return ISD::FDIV;
1567 case URem: return ISD::UREM;
1568 case SRem: return ISD::SREM;
1569 case FRem: return ISD::FREM;
1570 case Shl: return ISD::SHL;
1571 case LShr: return ISD::SRL;
1572 case AShr: return ISD::SRA;
1573 case And: return ISD::AND;
1574 case Or: return ISD::OR;
1575 case Xor: return ISD::XOR;
1576 case Alloca: return 0;
1577 case Load: return ISD::LOAD;
1578 case Store: return ISD::STORE;
1579 case GetElementPtr: return 0;
1580 case Fence: return 0;
1581 case AtomicCmpXchg: return 0;
1582 case AtomicRMW: return 0;
1583 case Trunc: return ISD::TRUNCATE;
1584 case ZExt: return ISD::ZERO_EXTEND;
1585 case SExt: return ISD::SIGN_EXTEND;
1586 case FPToUI: return ISD::FP_TO_UINT;
1587 case FPToSI: return ISD::FP_TO_SINT;
1588 case UIToFP: return ISD::UINT_TO_FP;
1589 case SIToFP: return ISD::SINT_TO_FP;
1590 case FPTrunc: return ISD::FP_ROUND;
1591 case FPExt: return ISD::FP_EXTEND;
1592 case PtrToInt: return ISD::BITCAST;
1593 case IntToPtr: return ISD::BITCAST;
1594 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1595 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1596 case ICmp: return ISD::SETCC;
1597 case FCmp: return ISD::SETCC;
1598 case PHI: return 0;
1599 case Call: return 0;
1600 case Select: return ISD::SELECT;
1601 case UserOp1: return 0;
1602 case UserOp2: return 0;
1603 case VAArg: return 0;
1604 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1605 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1606 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1607 case ExtractValue: return ISD::MERGE_VALUES;
1608 case InsertValue: return ISD::MERGE_VALUES;
1609 case LandingPad: return 0;
1610 }
1611
1612 llvm_unreachable("Unknown instruction type encountered!");
1613}
1614
1615std::pair<unsigned, MVT>
1616TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1617 LLVMContext &C = Ty->getContext();
1618 EVT MTy = getValueType(Ty);
1619
1620 unsigned Cost = 1;
1621 // We keep legalizing the type until we find a legal kind. We assume that
1622 // the only operation that costs anything is the split. After splitting
1623 // we need to handle two types.
1624 while (true) {
1625 LegalizeKind LK = getTypeConversion(C, MTy);
1626
1627 if (LK.first == TypeLegal)
1628 return std::make_pair(Cost, MTy.getSimpleVT());
1629
1630 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1631 Cost *= 2;
1632
1633 // Keep legalizing the type.
1634 MTy = LK.second;
1635 }
1636}
1637
1638//===----------------------------------------------------------------------===//
1639// Loop Strength Reduction hooks
1640//===----------------------------------------------------------------------===//
1641
1642/// isLegalAddressingMode - Return true if the addressing mode represented
1643/// by AM is legal for this target, for a load/store of the specified type.
1644bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
Matt Arsenaultbd7d80a2015-06-01 05:31:59 +0000[diff] [blame]1645 Type *Ty,
1646 unsigned AS) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1647 // The default implementation of this implements a conservative RISCy, r+r and
1648 // r+i addr mode.
1649
1650 // Allows a sign-extended 16-bit immediate field.
1651 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1652 return false;
1653
1654 // No global is ever allowed as a base.
1655 if (AM.BaseGV)
1656 return false;
1657
1658 // Only support r+r,
1659 switch (AM.Scale) {
1660 case 0: // "r+i" or just "i", depending on HasBaseReg.
1661 break;
1662 case 1:
1663 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1664 return false;
1665 // Otherwise we have r+r or r+i.
1666 break;
1667 case 2:
1668 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1669 return false;
1670 // Allow 2*r as r+r.
1671 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1672 default: // Don't allow n * r
1673 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1674 }
1675
1676 return true;
1677}