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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000011#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
Tom Stellard75aadc22012-12-11 21:25:42 +000013
Matt Arsenault678e1112017-04-10 17:58:06 +000014#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Konstantin Zhuravlyov60a83732016-10-03 18:47:26 +000015#include "llvm/Target/TargetMachine.h"
16
Tom Stellard75aadc22012-12-11 21:25:42 +000017namespace llvm {
18
Tom Stellard75aadc22012-12-11 21:25:42 +000019class AMDGPUTargetMachine;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000020class FunctionPass;
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +000021class GCNTargetMachine;
Matt Arsenault2ffe8fd2016-08-11 19:18:50 +000022class ModulePass;
23class Pass;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000024class Target;
25class TargetMachine;
Matt Arsenault2ffe8fd2016-08-11 19:18:50 +000026class PassRegistry;
Yaxun Liu1a14bfa2017-03-27 14:04:01 +000027class Module;
Tom Stellard75aadc22012-12-11 21:25:42 +000028
29// R600 Passes
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +000030FunctionPass *createR600VectorRegMerger();
31FunctionPass *createR600ExpandSpecialInstrsPass();
Tom Stellard1de55822013-12-11 17:51:41 +000032FunctionPass *createR600EmitClauseMarkers();
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +000033FunctionPass *createR600ClauseMergePass();
34FunctionPass *createR600Packetizer();
35FunctionPass *createR600ControlFlowFinalizer();
Tom Stellardf2ba9722013-12-11 17:51:47 +000036FunctionPass *createAMDGPUCFGStructurizerPass();
Tom Stellard20287692017-08-08 04:57:55 +000037FunctionPass *createR600ISelDag(TargetMachine *TM, CodeGenOpt::Level OptLevel);
Tom Stellard75aadc22012-12-11 21:25:42 +000038
39// SI Passes
Tom Stellardf8794352012-12-19 22:10:31 +000040FunctionPass *createSIAnnotateControlFlowPass();
Tom Stellard6596ba72014-11-21 22:06:37 +000041FunctionPass *createSIFoldOperandsPass();
Sam Koltonf60ad582017-03-21 12:51:34 +000042FunctionPass *createSIPeepholeSDWAPass();
Tom Stellard1bd80722014-04-30 15:31:33 +000043FunctionPass *createSILowerI1CopiesPass();
Tom Stellard1aaad692014-07-21 16:55:33 +000044FunctionPass *createSIShrinkInstructionsPass();
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +000045FunctionPass *createSILoadStoreOptimizerPass();
Nicolai Haehnle213e87f2016-03-21 20:28:33 +000046FunctionPass *createSIWholeQuadModePass();
Tom Stellard28d13a42015-05-12 17:13:02 +000047FunctionPass *createSIFixControlFlowLiveIntervalsPass();
Stanislav Mekhanoshin37e7f952017-08-01 23:14:32 +000048FunctionPass *createSIOptimizeExecMaskingPreRAPass();
Matt Arsenault782c03b2015-11-03 22:30:13 +000049FunctionPass *createSIFixSGPRCopiesPass();
Konstantin Zhuravlyove9a5a772017-07-21 21:19:23 +000050FunctionPass *createSIMemoryLegalizerPass();
Konstantin Zhuravlyova7919322016-05-10 18:33:41 +000051FunctionPass *createSIDebuggerInsertNopsPass();
Tom Stellard6e1967e2016-02-05 17:42:38 +000052FunctionPass *createSIInsertWaitsPass();
Kannan Narayananacb089e2017-04-12 03:25:12 +000053FunctionPass *createSIInsertWaitcntsPass();
Connor Abbott92638ab2017-08-04 18:36:52 +000054FunctionPass *createSIFixWWMLivenessPass();
Stanislav Mekhanoshin7f377942017-08-11 16:42:09 +000055FunctionPass *createAMDGPUSimplifyLibCallsPass();
56FunctionPass *createAMDGPUUseNativeCallsPass();
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +000057FunctionPass *createAMDGPUCodeGenPreparePass();
Jan Sjodina06bfe02017-05-15 20:18:37 +000058FunctionPass *createAMDGPUMachineCFGStructurizerPass();
Matt Arsenaultc06574f2017-07-28 18:40:05 +000059FunctionPass *createAMDGPURewriteOutArgumentsPass();
Jan Sjodina06bfe02017-05-15 20:18:37 +000060
Matt Arsenault7016f132017-08-03 22:30:46 +000061void initializeAMDGPUDAGToDAGISelPass(PassRegistry&);
62
Jan Sjodina06bfe02017-05-15 20:18:37 +000063void initializeAMDGPUMachineCFGStructurizerPass(PassRegistry&);
64extern char &AMDGPUMachineCFGStructurizerID;
Tom Stellard75aadc22012-12-11 21:25:42 +000065
Matt Arsenault746e0652017-06-02 18:02:42 +000066void initializeAMDGPUAlwaysInlinePass(PassRegistry&);
67
Matt Arsenault6b930462017-07-13 21:43:42 +000068Pass *createAMDGPUAnnotateKernelFeaturesPass();
Matt Arsenault39319482015-11-06 18:01:57 +000069void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
70extern char &AMDGPUAnnotateKernelFeaturesID;
71
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +000072ModulePass *createAMDGPULowerIntrinsicsPass();
Matt Arsenault0699ef32017-02-09 22:00:42 +000073void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
74extern char &AMDGPULowerIntrinsicsID;
75
Matt Arsenaultc06574f2017-07-28 18:40:05 +000076void initializeAMDGPURewriteOutArgumentsPass(PassRegistry &);
77extern char &AMDGPURewriteOutArgumentsID;
78
Tom Stellarda2f57be2017-08-02 22:19:45 +000079void initializeR600ClauseMergePassPass(PassRegistry &);
80extern char &R600ClauseMergePassID;
81
82void initializeR600ControlFlowFinalizerPass(PassRegistry &);
83extern char &R600ControlFlowFinalizerID;
84
85void initializeR600ExpandSpecialInstrsPassPass(PassRegistry &);
86extern char &R600ExpandSpecialInstrsPassID;
87
88void initializeR600VectorRegMergerPass(PassRegistry &);
89extern char &R600VectorRegMergerID;
90
91void initializeR600PacketizerPass(PassRegistry &);
92extern char &R600PacketizerID;
93
Tom Stellard6596ba72014-11-21 22:06:37 +000094void initializeSIFoldOperandsPass(PassRegistry &);
95extern char &SIFoldOperandsID;
96
Sam Koltonf60ad582017-03-21 12:51:34 +000097void initializeSIPeepholeSDWAPass(PassRegistry &);
98extern char &SIPeepholeSDWAID;
99
Matt Arsenaultc3a01ec2016-06-09 23:18:47 +0000100void initializeSIShrinkInstructionsPass(PassRegistry&);
101extern char &SIShrinkInstructionsID;
102
Matt Arsenault782c03b2015-11-03 22:30:13 +0000103void initializeSIFixSGPRCopiesPass(PassRegistry &);
104extern char &SIFixSGPRCopiesID;
105
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +0000106void initializeSIFixVGPRCopiesPass(PassRegistry &);
107extern char &SIFixVGPRCopiesID;
108
Tom Stellard1bd80722014-04-30 15:31:33 +0000109void initializeSILowerI1CopiesPass(PassRegistry &);
110extern char &SILowerI1CopiesID;
111
Matt Arsenault41033282014-10-10 22:01:59 +0000112void initializeSILoadStoreOptimizerPass(PassRegistry &);
113extern char &SILoadStoreOptimizerID;
114
Nicolai Haehnle213e87f2016-03-21 20:28:33 +0000115void initializeSIWholeQuadModePass(PassRegistry &);
116extern char &SIWholeQuadModeID;
117
Matt Arsenault55d49cf2016-02-12 02:16:10 +0000118void initializeSILowerControlFlowPass(PassRegistry &);
Matt Arsenault78fc9da2016-08-22 19:33:16 +0000119extern char &SILowerControlFlowID;
Matt Arsenault55d49cf2016-02-12 02:16:10 +0000120
Matt Arsenault78fc9da2016-08-22 19:33:16 +0000121void initializeSIInsertSkipsPass(PassRegistry &);
122extern char &SIInsertSkipsPassID;
Matt Arsenault55d49cf2016-02-12 02:16:10 +0000123
Matt Arsenaulte6740752016-09-29 01:44:16 +0000124void initializeSIOptimizeExecMaskingPass(PassRegistry &);
125extern char &SIOptimizeExecMaskingID;
126
Connor Abbott92638ab2017-08-04 18:36:52 +0000127void initializeSIFixWWMLivenessPass(PassRegistry &);
128extern char &SIFixWWMLivenessID;
129
Stanislav Mekhanoshin7f377942017-08-11 16:42:09 +0000130void initializeAMDGPUSimplifyLibCallsPass(PassRegistry &);
131extern char &AMDGPUSimplifyLibCallsID;
132
133void initializeAMDGPUUseNativeCallsPass(PassRegistry &);
134extern char &AMDGPUUseNativeCallsID;
135
Tom Stellard75aadc22012-12-11 21:25:42 +0000136// Passes common to R600 and SI
Francis Visoiu Mistrih8b617642017-05-18 17:21:13 +0000137FunctionPass *createAMDGPUPromoteAlloca();
Matt Arsenaulte0132462016-01-30 05:19:45 +0000138void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
139extern char &AMDGPUPromoteAllocaID;
140
Tom Stellardf8794352012-12-19 22:10:31 +0000141Pass *createAMDGPUStructurizeCFGPass();
Matt Arsenault7016f132017-08-03 22:30:46 +0000142FunctionPass *createAMDGPUISelDag(
143 TargetMachine *TM = nullptr,
144 CodeGenOpt::Level OptLevel = CodeGenOpt::Default);
Stanislav Mekhanoshin89653df2017-03-30 20:16:02 +0000145ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
Tom Stellardfd253952015-08-07 23:19:30 +0000146ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
Tom Stellarda6f24c62015-12-15 20:55:55 +0000147FunctionPass *createAMDGPUAnnotateUniformValues();
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000148
Stanislav Mekhanoshinf6c1feb2017-01-27 16:38:10 +0000149ModulePass* createAMDGPUUnifyMetadataPass();
Stanislav Mekhanoshin50ea93a2016-12-08 19:46:04 +0000150void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
151extern char &AMDGPUUnifyMetadataID;
152
Stanislav Mekhanoshin37e7f952017-08-01 23:14:32 +0000153void initializeSIOptimizeExecMaskingPreRAPass(PassRegistry&);
154extern char &SIOptimizeExecMaskingPreRAID;
155
Tom Stellarda6f24c62015-12-15 20:55:55 +0000156void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
157extern char &AMDGPUAnnotateUniformValuesPassID;
Tom Stellardb2de94e2014-07-02 20:53:48 +0000158
Matt Arsenault86de4862016-06-24 07:07:55 +0000159void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
160extern char &AMDGPUCodeGenPrepareID;
161
Tom Stellard77a17772016-01-20 15:48:27 +0000162void initializeSIAnnotateControlFlowPass(PassRegistry&);
163extern char &SIAnnotateControlFlowPassID;
164
Konstantin Zhuravlyove9a5a772017-07-21 21:19:23 +0000165void initializeSIMemoryLegalizerPass(PassRegistry&);
166extern char &SIMemoryLegalizerID;
167
Konstantin Zhuravlyova7919322016-05-10 18:33:41 +0000168void initializeSIDebuggerInsertNopsPass(PassRegistry&);
169extern char &SIDebuggerInsertNopsID;
Tom Stellardcc7067a62016-03-03 03:53:29 +0000170
Tom Stellard6e1967e2016-02-05 17:42:38 +0000171void initializeSIInsertWaitsPass(PassRegistry&);
172extern char &SIInsertWaitsID;
173
Kannan Narayananacb089e2017-04-12 03:25:12 +0000174void initializeSIInsertWaitcntsPass(PassRegistry&);
175extern char &SIInsertWaitcntsID;
176
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +0000177void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
178extern char &AMDGPUUnifyDivergentExitNodesID;
179
Stanislav Mekhanoshin8e45acf2017-03-17 23:56:58 +0000180ImmutablePass *createAMDGPUAAWrapperPass();
181void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
182
Matt Arsenault7016f132017-08-03 22:30:46 +0000183void initializeAMDGPUArgumentUsageInfoPass(PassRegistry &);
184
Mehdi Aminif42454b2016-10-09 23:00:34 +0000185Target &getTheAMDGPUTarget();
186Target &getTheGCNTarget();
Tom Stellard75aadc22012-12-11 21:25:42 +0000187
Tom Stellard067c8152014-07-21 14:01:14 +0000188namespace AMDGPU {
189enum TargetIndex {
Tom Stellard95292bb2015-01-20 17:49:47 +0000190 TI_CONSTDATA_START,
191 TI_SCRATCH_RSRC_DWORD0,
192 TI_SCRATCH_RSRC_DWORD1,
193 TI_SCRATCH_RSRC_DWORD2,
194 TI_SCRATCH_RSRC_DWORD3
Tom Stellard067c8152014-07-21 14:01:14 +0000195};
196}
197
Tom Stellard75aadc22012-12-11 21:25:42 +0000198} // End namespace llvm
199
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000200/// OpenCL uses address spaces to differentiate between
201/// various memory regions on the hardware. On the CPU
202/// all of the address spaces point to the same memory,
203/// however on the GPU, each address space points to
Alp Tokercb402912014-01-24 17:20:08 +0000204/// a separate piece of memory that is unique from other
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000205/// memory locations.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000206struct AMDGPUAS {
207 // The following address space values depend on the triple environment.
208 unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000209 unsigned FLAT_ADDRESS; ///< Address space for flat memory.
210 unsigned REGION_ADDRESS; ///< Address space for region memory.
211
212 // The maximum value for flat, generic, local, private, constant and region.
213 const static unsigned MAX_COMMON_ADDRESS = 5;
214
215 const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0).
Yaxun Liu76ae47c2017-04-06 19:17:32 +0000216 const static unsigned CONSTANT_ADDRESS = 2; ///< Address space for constant memory (VTX2)
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000217 const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory.
218 const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0)
219 const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1)
Tom Stellard1e803092013-07-23 01:48:18 +0000220
221 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
222 // order to be able to dynamically index a constant buffer, for example:
223 //
224 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
225
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000226 const static unsigned CONSTANT_BUFFER_0 = 8;
227 const static unsigned CONSTANT_BUFFER_1 = 9;
228 const static unsigned CONSTANT_BUFFER_2 = 10;
229 const static unsigned CONSTANT_BUFFER_3 = 11;
230 const static unsigned CONSTANT_BUFFER_4 = 12;
231 const static unsigned CONSTANT_BUFFER_5 = 13;
232 const static unsigned CONSTANT_BUFFER_6 = 14;
233 const static unsigned CONSTANT_BUFFER_7 = 15;
234 const static unsigned CONSTANT_BUFFER_8 = 16;
235 const static unsigned CONSTANT_BUFFER_9 = 17;
236 const static unsigned CONSTANT_BUFFER_10 = 18;
237 const static unsigned CONSTANT_BUFFER_11 = 19;
238 const static unsigned CONSTANT_BUFFER_12 = 20;
239 const static unsigned CONSTANT_BUFFER_13 = 21;
240 const static unsigned CONSTANT_BUFFER_14 = 22;
241 const static unsigned CONSTANT_BUFFER_15 = 23;
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000242
243 // Some places use this if the address space can't be determined.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000244 const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000245};
246
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000247namespace llvm {
248namespace AMDGPU {
249AMDGPUAS getAMDGPUAS(const Module &M);
250AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
251AMDGPUAS getAMDGPUAS(Triple T);
252} // namespace AMDGPU
253} // namespace llvm
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000254
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000255#endif