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Matt Davis712db512018-06-18 21:38:38 +00001//===--------------------- InstructionInfoView.cpp --------------*- C++ -*-===//
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10///
Matt Davis712db512018-06-18 21:38:38 +000011/// This file implements the InstructionInfoView API.
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000012///
13//===----------------------------------------------------------------------===//
14
Matt Davis10aa09f2018-08-24 20:24:53 +000015#include "Views/InstructionInfoView.h"
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000016
17namespace mca {
18
19using namespace llvm;
20
21void InstructionInfoView::printView(raw_ostream &OS) const {
22 std::string Buffer;
23 raw_string_ostream TempStream(Buffer);
24 const MCSchedModel &SM = STI.getSchedModel();
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000025
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000026 std::string Instruction;
27 raw_string_ostream InstrStream(Instruction);
28
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000029 TempStream << "\n\nInstruction Info:\n";
30 TempStream << "[1]: #uOps\n[2]: Latency\n[3]: RThroughput\n"
Andrea Di Biagiod2e2c052018-07-11 12:44:44 +000031 << "[4]: MayLoad\n[5]: MayStore\n[6]: HasSideEffects (U)\n\n";
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000032
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000033 TempStream << "[1] [2] [3] [4] [5] [6] Instructions:\n";
Andrea Di Biagio7be45b0f2018-10-24 15:06:27 +000034 for (const MCInst &Inst : Source) {
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000035 const MCInstrDesc &MCDesc = MCII.get(Inst.getOpcode());
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000036
Andrea Di Biagio39e5a562018-06-04 15:43:09 +000037 // Obtain the scheduling class information from the instruction.
38 unsigned SchedClassID = MCDesc.getSchedClass();
39 unsigned CPUID = SM.getProcessorID();
40
41 // Try to solve variant scheduling classes.
42 while (SchedClassID && SM.getSchedClassDesc(SchedClassID)->isVariant())
43 SchedClassID = STI.resolveVariantSchedClass(SchedClassID, &Inst, CPUID);
44
45 const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID);
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000046 unsigned NumMicroOpcodes = SCDesc.NumMicroOps;
47 unsigned Latency = MCSchedModel::computeInstrLatency(STI, SCDesc);
48 Optional<double> RThroughput =
49 MCSchedModel::getReciprocalThroughput(STI, SCDesc);
50
51 TempStream << ' ' << NumMicroOpcodes << " ";
52 if (NumMicroOpcodes < 10)
53 TempStream << " ";
54 else if (NumMicroOpcodes < 100)
55 TempStream << ' ';
56 TempStream << Latency << " ";
57 if (Latency < 10)
58 TempStream << " ";
59 else if (Latency < 100)
60 TempStream << ' ';
61
62 if (RThroughput.hasValue()) {
63 double RT = RThroughput.getValue();
64 TempStream << format("%.2f", RT) << ' ';
65 if (RT < 10.0)
66 TempStream << " ";
67 else if (RT < 100.0)
68 TempStream << ' ';
69 } else {
70 TempStream << " - ";
71 }
72 TempStream << (MCDesc.mayLoad() ? " * " : " ");
73 TempStream << (MCDesc.mayStore() ? " * " : " ");
Andrea Di Biagiod2e2c052018-07-11 12:44:44 +000074 TempStream << (MCDesc.hasUnmodeledSideEffects() ? " U " : " ");
Andrea Di Biagioa7c3c452018-05-15 15:18:05 +000075
76 MCIP.printInst(&Inst, InstrStream, "", STI);
77 InstrStream.flush();
78
79 // Consume any tabs or spaces at the beginning of the string.
80 StringRef Str(Instruction);
81 Str = Str.ltrim();
82 TempStream << " " << Str << '\n';
83 Instruction = "";
Andrea Di Biagiodf5d9482018-03-23 19:40:04 +000084 }
85
86 TempStream.flush();
87 OS << Buffer;
88}
89} // namespace mca.