Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 6402ad27c01c9503a12d41d7e40646cf0d1f919f / . / llvm / lib / CodeGen / TargetLoweringBase.cpp
blob: 1ca453aa09c26814d35c25b90032f6319e40dd1f [file] [log] [blame]
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1//===-- TargetLoweringBase.cpp - Implement the TargetLoweringBase class ---===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This implements the TargetLoweringBase class.
11//
12//===----------------------------------------------------------------------===//
13
14#include "llvm/Target/TargetLowering.h"
15#include "llvm/ADT/BitVector.h"
16#include "llvm/ADT/STLExtras.h"
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]17#include "llvm/ADT/Triple.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]18#include "llvm/CodeGen/Analysis.h"
19#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]21#include "llvm/CodeGen/MachineInstrBuilder.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]22#include "llvm/CodeGen/MachineJumpTableInfo.h"
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]23#include "llvm/CodeGen/StackMaps.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]24#include "llvm/IR/DataLayout.h"
25#include "llvm/IR/DerivedTypes.h"
26#include "llvm/IR/GlobalVariable.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]27#include "llvm/IR/Mangler.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]28#include "llvm/MC/MCAsmInfo.h"
Rafael Espindoladaeafb42014-02-19 17:23:20 +0000[diff] [blame]29#include "llvm/MC/MCContext.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]30#include "llvm/MC/MCExpr.h"
31#include "llvm/Support/CommandLine.h"
32#include "llvm/Support/ErrorHandling.h"
33#include "llvm/Support/MathExtras.h"
34#include "llvm/Target/TargetLoweringObjectFile.h"
35#include "llvm/Target/TargetMachine.h"
36#include "llvm/Target/TargetRegisterInfo.h"
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]37#include "llvm/Target/TargetSubtargetInfo.h"
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]38#include <cctype>
39using namespace llvm;
40
41/// InitLibcallNames - Set default libcall names.
42///
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]43static void InitLibcallNames(const char **Names, const Triple &TT) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]44 Names[RTLIB::SHL_I16] = "__ashlhi3";
45 Names[RTLIB::SHL_I32] = "__ashlsi3";
46 Names[RTLIB::SHL_I64] = "__ashldi3";
47 Names[RTLIB::SHL_I128] = "__ashlti3";
48 Names[RTLIB::SRL_I16] = "__lshrhi3";
49 Names[RTLIB::SRL_I32] = "__lshrsi3";
50 Names[RTLIB::SRL_I64] = "__lshrdi3";
51 Names[RTLIB::SRL_I128] = "__lshrti3";
52 Names[RTLIB::SRA_I16] = "__ashrhi3";
53 Names[RTLIB::SRA_I32] = "__ashrsi3";
54 Names[RTLIB::SRA_I64] = "__ashrdi3";
55 Names[RTLIB::SRA_I128] = "__ashrti3";
56 Names[RTLIB::MUL_I8] = "__mulqi3";
57 Names[RTLIB::MUL_I16] = "__mulhi3";
58 Names[RTLIB::MUL_I32] = "__mulsi3";
59 Names[RTLIB::MUL_I64] = "__muldi3";
60 Names[RTLIB::MUL_I128] = "__multi3";
61 Names[RTLIB::MULO_I32] = "__mulosi4";
62 Names[RTLIB::MULO_I64] = "__mulodi4";
63 Names[RTLIB::MULO_I128] = "__muloti4";
64 Names[RTLIB::SDIV_I8] = "__divqi3";
65 Names[RTLIB::SDIV_I16] = "__divhi3";
66 Names[RTLIB::SDIV_I32] = "__divsi3";
67 Names[RTLIB::SDIV_I64] = "__divdi3";
68 Names[RTLIB::SDIV_I128] = "__divti3";
69 Names[RTLIB::UDIV_I8] = "__udivqi3";
70 Names[RTLIB::UDIV_I16] = "__udivhi3";
71 Names[RTLIB::UDIV_I32] = "__udivsi3";
72 Names[RTLIB::UDIV_I64] = "__udivdi3";
73 Names[RTLIB::UDIV_I128] = "__udivti3";
74 Names[RTLIB::SREM_I8] = "__modqi3";
75 Names[RTLIB::SREM_I16] = "__modhi3";
76 Names[RTLIB::SREM_I32] = "__modsi3";
77 Names[RTLIB::SREM_I64] = "__moddi3";
78 Names[RTLIB::SREM_I128] = "__modti3";
79 Names[RTLIB::UREM_I8] = "__umodqi3";
80 Names[RTLIB::UREM_I16] = "__umodhi3";
81 Names[RTLIB::UREM_I32] = "__umodsi3";
82 Names[RTLIB::UREM_I64] = "__umoddi3";
83 Names[RTLIB::UREM_I128] = "__umodti3";
84
85 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]86 Names[RTLIB::SDIVREM_I8] = nullptr;
87 Names[RTLIB::SDIVREM_I16] = nullptr;
88 Names[RTLIB::SDIVREM_I32] = nullptr;
89 Names[RTLIB::SDIVREM_I64] = nullptr;
90 Names[RTLIB::SDIVREM_I128] = nullptr;
91 Names[RTLIB::UDIVREM_I8] = nullptr;
92 Names[RTLIB::UDIVREM_I16] = nullptr;
93 Names[RTLIB::UDIVREM_I32] = nullptr;
94 Names[RTLIB::UDIVREM_I64] = nullptr;
95 Names[RTLIB::UDIVREM_I128] = nullptr;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]96
97 Names[RTLIB::NEG_I32] = "__negsi2";
98 Names[RTLIB::NEG_I64] = "__negdi2";
99 Names[RTLIB::ADD_F32] = "__addsf3";
100 Names[RTLIB::ADD_F64] = "__adddf3";
101 Names[RTLIB::ADD_F80] = "__addxf3";
102 Names[RTLIB::ADD_F128] = "__addtf3";
103 Names[RTLIB::ADD_PPCF128] = "__gcc_qadd";
104 Names[RTLIB::SUB_F32] = "__subsf3";
105 Names[RTLIB::SUB_F64] = "__subdf3";
106 Names[RTLIB::SUB_F80] = "__subxf3";
107 Names[RTLIB::SUB_F128] = "__subtf3";
108 Names[RTLIB::SUB_PPCF128] = "__gcc_qsub";
109 Names[RTLIB::MUL_F32] = "__mulsf3";
110 Names[RTLIB::MUL_F64] = "__muldf3";
111 Names[RTLIB::MUL_F80] = "__mulxf3";
112 Names[RTLIB::MUL_F128] = "__multf3";
113 Names[RTLIB::MUL_PPCF128] = "__gcc_qmul";
114 Names[RTLIB::DIV_F32] = "__divsf3";
115 Names[RTLIB::DIV_F64] = "__divdf3";
116 Names[RTLIB::DIV_F80] = "__divxf3";
117 Names[RTLIB::DIV_F128] = "__divtf3";
118 Names[RTLIB::DIV_PPCF128] = "__gcc_qdiv";
119 Names[RTLIB::REM_F32] = "fmodf";
120 Names[RTLIB::REM_F64] = "fmod";
121 Names[RTLIB::REM_F80] = "fmodl";
122 Names[RTLIB::REM_F128] = "fmodl";
123 Names[RTLIB::REM_PPCF128] = "fmodl";
124 Names[RTLIB::FMA_F32] = "fmaf";
125 Names[RTLIB::FMA_F64] = "fma";
126 Names[RTLIB::FMA_F80] = "fmal";
127 Names[RTLIB::FMA_F128] = "fmal";
128 Names[RTLIB::FMA_PPCF128] = "fmal";
129 Names[RTLIB::POWI_F32] = "__powisf2";
130 Names[RTLIB::POWI_F64] = "__powidf2";
131 Names[RTLIB::POWI_F80] = "__powixf2";
132 Names[RTLIB::POWI_F128] = "__powitf2";
133 Names[RTLIB::POWI_PPCF128] = "__powitf2";
134 Names[RTLIB::SQRT_F32] = "sqrtf";
135 Names[RTLIB::SQRT_F64] = "sqrt";
136 Names[RTLIB::SQRT_F80] = "sqrtl";
137 Names[RTLIB::SQRT_F128] = "sqrtl";
138 Names[RTLIB::SQRT_PPCF128] = "sqrtl";
139 Names[RTLIB::LOG_F32] = "logf";
140 Names[RTLIB::LOG_F64] = "log";
141 Names[RTLIB::LOG_F80] = "logl";
142 Names[RTLIB::LOG_F128] = "logl";
143 Names[RTLIB::LOG_PPCF128] = "logl";
144 Names[RTLIB::LOG2_F32] = "log2f";
145 Names[RTLIB::LOG2_F64] = "log2";
146 Names[RTLIB::LOG2_F80] = "log2l";
147 Names[RTLIB::LOG2_F128] = "log2l";
148 Names[RTLIB::LOG2_PPCF128] = "log2l";
149 Names[RTLIB::LOG10_F32] = "log10f";
150 Names[RTLIB::LOG10_F64] = "log10";
151 Names[RTLIB::LOG10_F80] = "log10l";
152 Names[RTLIB::LOG10_F128] = "log10l";
153 Names[RTLIB::LOG10_PPCF128] = "log10l";
154 Names[RTLIB::EXP_F32] = "expf";
155 Names[RTLIB::EXP_F64] = "exp";
156 Names[RTLIB::EXP_F80] = "expl";
157 Names[RTLIB::EXP_F128] = "expl";
158 Names[RTLIB::EXP_PPCF128] = "expl";
159 Names[RTLIB::EXP2_F32] = "exp2f";
160 Names[RTLIB::EXP2_F64] = "exp2";
161 Names[RTLIB::EXP2_F80] = "exp2l";
162 Names[RTLIB::EXP2_F128] = "exp2l";
163 Names[RTLIB::EXP2_PPCF128] = "exp2l";
164 Names[RTLIB::SIN_F32] = "sinf";
165 Names[RTLIB::SIN_F64] = "sin";
166 Names[RTLIB::SIN_F80] = "sinl";
167 Names[RTLIB::SIN_F128] = "sinl";
168 Names[RTLIB::SIN_PPCF128] = "sinl";
169 Names[RTLIB::COS_F32] = "cosf";
170 Names[RTLIB::COS_F64] = "cos";
171 Names[RTLIB::COS_F80] = "cosl";
172 Names[RTLIB::COS_F128] = "cosl";
173 Names[RTLIB::COS_PPCF128] = "cosl";
174 Names[RTLIB::POW_F32] = "powf";
175 Names[RTLIB::POW_F64] = "pow";
176 Names[RTLIB::POW_F80] = "powl";
177 Names[RTLIB::POW_F128] = "powl";
178 Names[RTLIB::POW_PPCF128] = "powl";
179 Names[RTLIB::CEIL_F32] = "ceilf";
180 Names[RTLIB::CEIL_F64] = "ceil";
181 Names[RTLIB::CEIL_F80] = "ceill";
182 Names[RTLIB::CEIL_F128] = "ceill";
183 Names[RTLIB::CEIL_PPCF128] = "ceill";
184 Names[RTLIB::TRUNC_F32] = "truncf";
185 Names[RTLIB::TRUNC_F64] = "trunc";
186 Names[RTLIB::TRUNC_F80] = "truncl";
187 Names[RTLIB::TRUNC_F128] = "truncl";
188 Names[RTLIB::TRUNC_PPCF128] = "truncl";
189 Names[RTLIB::RINT_F32] = "rintf";
190 Names[RTLIB::RINT_F64] = "rint";
191 Names[RTLIB::RINT_F80] = "rintl";
192 Names[RTLIB::RINT_F128] = "rintl";
193 Names[RTLIB::RINT_PPCF128] = "rintl";
194 Names[RTLIB::NEARBYINT_F32] = "nearbyintf";
195 Names[RTLIB::NEARBYINT_F64] = "nearbyint";
196 Names[RTLIB::NEARBYINT_F80] = "nearbyintl";
197 Names[RTLIB::NEARBYINT_F128] = "nearbyintl";
198 Names[RTLIB::NEARBYINT_PPCF128] = "nearbyintl";
Hal Finkel171817e2013-08-07 22:49:12 +0000[diff] [blame]199 Names[RTLIB::ROUND_F32] = "roundf";
200 Names[RTLIB::ROUND_F64] = "round";
201 Names[RTLIB::ROUND_F80] = "roundl";
202 Names[RTLIB::ROUND_F128] = "roundl";
203 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]204 Names[RTLIB::FLOOR_F32] = "floorf";
205 Names[RTLIB::FLOOR_F64] = "floor";
206 Names[RTLIB::FLOOR_F80] = "floorl";
207 Names[RTLIB::FLOOR_F128] = "floorl";
208 Names[RTLIB::FLOOR_PPCF128] = "floorl";
Matt Arsenault7c936902014-10-21 23:01:01 +0000[diff] [blame]209 Names[RTLIB::FMIN_F32] = "fminf";
210 Names[RTLIB::FMIN_F64] = "fmin";
211 Names[RTLIB::FMIN_F80] = "fminl";
212 Names[RTLIB::FMIN_F128] = "fminl";
213 Names[RTLIB::FMIN_PPCF128] = "fminl";
214 Names[RTLIB::FMAX_F32] = "fmaxf";
215 Names[RTLIB::FMAX_F64] = "fmax";
216 Names[RTLIB::FMAX_F80] = "fmaxl";
217 Names[RTLIB::FMAX_F128] = "fmaxl";
218 Names[RTLIB::FMAX_PPCF128] = "fmaxl";
Tim Northover753eca02014-03-29 09:03:18 +0000[diff] [blame]219 Names[RTLIB::ROUND_F32] = "roundf";
220 Names[RTLIB::ROUND_F64] = "round";
221 Names[RTLIB::ROUND_F80] = "roundl";
222 Names[RTLIB::ROUND_F128] = "roundl";
223 Names[RTLIB::ROUND_PPCF128] = "roundl";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]224 Names[RTLIB::COPYSIGN_F32] = "copysignf";
225 Names[RTLIB::COPYSIGN_F64] = "copysign";
226 Names[RTLIB::COPYSIGN_F80] = "copysignl";
227 Names[RTLIB::COPYSIGN_F128] = "copysignl";
228 Names[RTLIB::COPYSIGN_PPCF128] = "copysignl";
229 Names[RTLIB::FPEXT_F64_F128] = "__extenddftf2";
230 Names[RTLIB::FPEXT_F32_F128] = "__extendsftf2";
231 Names[RTLIB::FPEXT_F32_F64] = "__extendsfdf2";
232 Names[RTLIB::FPEXT_F16_F32] = "__gnu_h2f_ieee";
233 Names[RTLIB::FPROUND_F32_F16] = "__gnu_f2h_ieee";
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]234 Names[RTLIB::FPROUND_F64_F16] = "__truncdfhf2";
235 Names[RTLIB::FPROUND_F80_F16] = "__truncxfhf2";
236 Names[RTLIB::FPROUND_F128_F16] = "__trunctfhf2";
237 Names[RTLIB::FPROUND_PPCF128_F16] = "__trunctfhf2";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]238 Names[RTLIB::FPROUND_F64_F32] = "__truncdfsf2";
239 Names[RTLIB::FPROUND_F80_F32] = "__truncxfsf2";
240 Names[RTLIB::FPROUND_F128_F32] = "__trunctfsf2";
241 Names[RTLIB::FPROUND_PPCF128_F32] = "__trunctfsf2";
242 Names[RTLIB::FPROUND_F80_F64] = "__truncxfdf2";
243 Names[RTLIB::FPROUND_F128_F64] = "__trunctfdf2";
244 Names[RTLIB::FPROUND_PPCF128_F64] = "__trunctfdf2";
245 Names[RTLIB::FPTOSINT_F32_I8] = "__fixsfqi";
246 Names[RTLIB::FPTOSINT_F32_I16] = "__fixsfhi";
247 Names[RTLIB::FPTOSINT_F32_I32] = "__fixsfsi";
248 Names[RTLIB::FPTOSINT_F32_I64] = "__fixsfdi";
249 Names[RTLIB::FPTOSINT_F32_I128] = "__fixsfti";
250 Names[RTLIB::FPTOSINT_F64_I8] = "__fixdfqi";
251 Names[RTLIB::FPTOSINT_F64_I16] = "__fixdfhi";
252 Names[RTLIB::FPTOSINT_F64_I32] = "__fixdfsi";
253 Names[RTLIB::FPTOSINT_F64_I64] = "__fixdfdi";
254 Names[RTLIB::FPTOSINT_F64_I128] = "__fixdfti";
255 Names[RTLIB::FPTOSINT_F80_I32] = "__fixxfsi";
256 Names[RTLIB::FPTOSINT_F80_I64] = "__fixxfdi";
257 Names[RTLIB::FPTOSINT_F80_I128] = "__fixxfti";
258 Names[RTLIB::FPTOSINT_F128_I32] = "__fixtfsi";
259 Names[RTLIB::FPTOSINT_F128_I64] = "__fixtfdi";
260 Names[RTLIB::FPTOSINT_F128_I128] = "__fixtfti";
261 Names[RTLIB::FPTOSINT_PPCF128_I32] = "__fixtfsi";
262 Names[RTLIB::FPTOSINT_PPCF128_I64] = "__fixtfdi";
263 Names[RTLIB::FPTOSINT_PPCF128_I128] = "__fixtfti";
264 Names[RTLIB::FPTOUINT_F32_I8] = "__fixunssfqi";
265 Names[RTLIB::FPTOUINT_F32_I16] = "__fixunssfhi";
266 Names[RTLIB::FPTOUINT_F32_I32] = "__fixunssfsi";
267 Names[RTLIB::FPTOUINT_F32_I64] = "__fixunssfdi";
268 Names[RTLIB::FPTOUINT_F32_I128] = "__fixunssfti";
269 Names[RTLIB::FPTOUINT_F64_I8] = "__fixunsdfqi";
270 Names[RTLIB::FPTOUINT_F64_I16] = "__fixunsdfhi";
271 Names[RTLIB::FPTOUINT_F64_I32] = "__fixunsdfsi";
272 Names[RTLIB::FPTOUINT_F64_I64] = "__fixunsdfdi";
273 Names[RTLIB::FPTOUINT_F64_I128] = "__fixunsdfti";
274 Names[RTLIB::FPTOUINT_F80_I32] = "__fixunsxfsi";
275 Names[RTLIB::FPTOUINT_F80_I64] = "__fixunsxfdi";
276 Names[RTLIB::FPTOUINT_F80_I128] = "__fixunsxfti";
277 Names[RTLIB::FPTOUINT_F128_I32] = "__fixunstfsi";
278 Names[RTLIB::FPTOUINT_F128_I64] = "__fixunstfdi";
279 Names[RTLIB::FPTOUINT_F128_I128] = "__fixunstfti";
280 Names[RTLIB::FPTOUINT_PPCF128_I32] = "__fixunstfsi";
281 Names[RTLIB::FPTOUINT_PPCF128_I64] = "__fixunstfdi";
282 Names[RTLIB::FPTOUINT_PPCF128_I128] = "__fixunstfti";
283 Names[RTLIB::SINTTOFP_I32_F32] = "__floatsisf";
284 Names[RTLIB::SINTTOFP_I32_F64] = "__floatsidf";
285 Names[RTLIB::SINTTOFP_I32_F80] = "__floatsixf";
286 Names[RTLIB::SINTTOFP_I32_F128] = "__floatsitf";
287 Names[RTLIB::SINTTOFP_I32_PPCF128] = "__floatsitf";
288 Names[RTLIB::SINTTOFP_I64_F32] = "__floatdisf";
289 Names[RTLIB::SINTTOFP_I64_F64] = "__floatdidf";
290 Names[RTLIB::SINTTOFP_I64_F80] = "__floatdixf";
291 Names[RTLIB::SINTTOFP_I64_F128] = "__floatditf";
292 Names[RTLIB::SINTTOFP_I64_PPCF128] = "__floatditf";
293 Names[RTLIB::SINTTOFP_I128_F32] = "__floattisf";
294 Names[RTLIB::SINTTOFP_I128_F64] = "__floattidf";
295 Names[RTLIB::SINTTOFP_I128_F80] = "__floattixf";
296 Names[RTLIB::SINTTOFP_I128_F128] = "__floattitf";
297 Names[RTLIB::SINTTOFP_I128_PPCF128] = "__floattitf";
298 Names[RTLIB::UINTTOFP_I32_F32] = "__floatunsisf";
299 Names[RTLIB::UINTTOFP_I32_F64] = "__floatunsidf";
300 Names[RTLIB::UINTTOFP_I32_F80] = "__floatunsixf";
301 Names[RTLIB::UINTTOFP_I32_F128] = "__floatunsitf";
302 Names[RTLIB::UINTTOFP_I32_PPCF128] = "__floatunsitf";
303 Names[RTLIB::UINTTOFP_I64_F32] = "__floatundisf";
304 Names[RTLIB::UINTTOFP_I64_F64] = "__floatundidf";
305 Names[RTLIB::UINTTOFP_I64_F80] = "__floatundixf";
306 Names[RTLIB::UINTTOFP_I64_F128] = "__floatunditf";
307 Names[RTLIB::UINTTOFP_I64_PPCF128] = "__floatunditf";
308 Names[RTLIB::UINTTOFP_I128_F32] = "__floatuntisf";
309 Names[RTLIB::UINTTOFP_I128_F64] = "__floatuntidf";
310 Names[RTLIB::UINTTOFP_I128_F80] = "__floatuntixf";
311 Names[RTLIB::UINTTOFP_I128_F128] = "__floatuntitf";
312 Names[RTLIB::UINTTOFP_I128_PPCF128] = "__floatuntitf";
313 Names[RTLIB::OEQ_F32] = "__eqsf2";
314 Names[RTLIB::OEQ_F64] = "__eqdf2";
315 Names[RTLIB::OEQ_F128] = "__eqtf2";
316 Names[RTLIB::UNE_F32] = "__nesf2";
317 Names[RTLIB::UNE_F64] = "__nedf2";
318 Names[RTLIB::UNE_F128] = "__netf2";
319 Names[RTLIB::OGE_F32] = "__gesf2";
320 Names[RTLIB::OGE_F64] = "__gedf2";
321 Names[RTLIB::OGE_F128] = "__getf2";
322 Names[RTLIB::OLT_F32] = "__ltsf2";
323 Names[RTLIB::OLT_F64] = "__ltdf2";
324 Names[RTLIB::OLT_F128] = "__lttf2";
325 Names[RTLIB::OLE_F32] = "__lesf2";
326 Names[RTLIB::OLE_F64] = "__ledf2";
327 Names[RTLIB::OLE_F128] = "__letf2";
328 Names[RTLIB::OGT_F32] = "__gtsf2";
329 Names[RTLIB::OGT_F64] = "__gtdf2";
330 Names[RTLIB::OGT_F128] = "__gttf2";
331 Names[RTLIB::UO_F32] = "__unordsf2";
332 Names[RTLIB::UO_F64] = "__unorddf2";
333 Names[RTLIB::UO_F128] = "__unordtf2";
334 Names[RTLIB::O_F32] = "__unordsf2";
335 Names[RTLIB::O_F64] = "__unorddf2";
336 Names[RTLIB::O_F128] = "__unordtf2";
337 Names[RTLIB::MEMCPY] = "memcpy";
338 Names[RTLIB::MEMMOVE] = "memmove";
339 Names[RTLIB::MEMSET] = "memset";
340 Names[RTLIB::UNWIND_RESUME] = "_Unwind_Resume";
341 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_1] = "__sync_val_compare_and_swap_1";
342 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_2] = "__sync_val_compare_and_swap_2";
343 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_4] = "__sync_val_compare_and_swap_4";
344 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_8] = "__sync_val_compare_and_swap_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]345 Names[RTLIB::SYNC_VAL_COMPARE_AND_SWAP_16] = "__sync_val_compare_and_swap_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]346 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_1] = "__sync_lock_test_and_set_1";
347 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_2] = "__sync_lock_test_and_set_2";
348 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_4] = "__sync_lock_test_and_set_4";
349 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_8] = "__sync_lock_test_and_set_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]350 Names[RTLIB::SYNC_LOCK_TEST_AND_SET_16] = "__sync_lock_test_and_set_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]351 Names[RTLIB::SYNC_FETCH_AND_ADD_1] = "__sync_fetch_and_add_1";
352 Names[RTLIB::SYNC_FETCH_AND_ADD_2] = "__sync_fetch_and_add_2";
353 Names[RTLIB::SYNC_FETCH_AND_ADD_4] = "__sync_fetch_and_add_4";
354 Names[RTLIB::SYNC_FETCH_AND_ADD_8] = "__sync_fetch_and_add_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]355 Names[RTLIB::SYNC_FETCH_AND_ADD_16] = "__sync_fetch_and_add_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]356 Names[RTLIB::SYNC_FETCH_AND_SUB_1] = "__sync_fetch_and_sub_1";
357 Names[RTLIB::SYNC_FETCH_AND_SUB_2] = "__sync_fetch_and_sub_2";
358 Names[RTLIB::SYNC_FETCH_AND_SUB_4] = "__sync_fetch_and_sub_4";
359 Names[RTLIB::SYNC_FETCH_AND_SUB_8] = "__sync_fetch_and_sub_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]360 Names[RTLIB::SYNC_FETCH_AND_SUB_16] = "__sync_fetch_and_sub_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]361 Names[RTLIB::SYNC_FETCH_AND_AND_1] = "__sync_fetch_and_and_1";
362 Names[RTLIB::SYNC_FETCH_AND_AND_2] = "__sync_fetch_and_and_2";
363 Names[RTLIB::SYNC_FETCH_AND_AND_4] = "__sync_fetch_and_and_4";
364 Names[RTLIB::SYNC_FETCH_AND_AND_8] = "__sync_fetch_and_and_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]365 Names[RTLIB::SYNC_FETCH_AND_AND_16] = "__sync_fetch_and_and_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]366 Names[RTLIB::SYNC_FETCH_AND_OR_1] = "__sync_fetch_and_or_1";
367 Names[RTLIB::SYNC_FETCH_AND_OR_2] = "__sync_fetch_and_or_2";
368 Names[RTLIB::SYNC_FETCH_AND_OR_4] = "__sync_fetch_and_or_4";
369 Names[RTLIB::SYNC_FETCH_AND_OR_8] = "__sync_fetch_and_or_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]370 Names[RTLIB::SYNC_FETCH_AND_OR_16] = "__sync_fetch_and_or_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]371 Names[RTLIB::SYNC_FETCH_AND_XOR_1] = "__sync_fetch_and_xor_1";
372 Names[RTLIB::SYNC_FETCH_AND_XOR_2] = "__sync_fetch_and_xor_2";
373 Names[RTLIB::SYNC_FETCH_AND_XOR_4] = "__sync_fetch_and_xor_4";
374 Names[RTLIB::SYNC_FETCH_AND_XOR_8] = "__sync_fetch_and_xor_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]375 Names[RTLIB::SYNC_FETCH_AND_XOR_16] = "__sync_fetch_and_xor_16";
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]376 Names[RTLIB::SYNC_FETCH_AND_NAND_1] = "__sync_fetch_and_nand_1";
377 Names[RTLIB::SYNC_FETCH_AND_NAND_2] = "__sync_fetch_and_nand_2";
378 Names[RTLIB::SYNC_FETCH_AND_NAND_4] = "__sync_fetch_and_nand_4";
379 Names[RTLIB::SYNC_FETCH_AND_NAND_8] = "__sync_fetch_and_nand_8";
David Majnemer451b7dd2013-10-18 08:03:43 +0000[diff] [blame]380 Names[RTLIB::SYNC_FETCH_AND_NAND_16] = "__sync_fetch_and_nand_16";
Tim Northovera564d322013-10-25 09:30:20 +0000[diff] [blame]381 Names[RTLIB::SYNC_FETCH_AND_MAX_1] = "__sync_fetch_and_max_1";
382 Names[RTLIB::SYNC_FETCH_AND_MAX_2] = "__sync_fetch_and_max_2";
383 Names[RTLIB::SYNC_FETCH_AND_MAX_4] = "__sync_fetch_and_max_4";
384 Names[RTLIB::SYNC_FETCH_AND_MAX_8] = "__sync_fetch_and_max_8";
385 Names[RTLIB::SYNC_FETCH_AND_MAX_16] = "__sync_fetch_and_max_16";
386 Names[RTLIB::SYNC_FETCH_AND_UMAX_1] = "__sync_fetch_and_umax_1";
387 Names[RTLIB::SYNC_FETCH_AND_UMAX_2] = "__sync_fetch_and_umax_2";
388 Names[RTLIB::SYNC_FETCH_AND_UMAX_4] = "__sync_fetch_and_umax_4";
389 Names[RTLIB::SYNC_FETCH_AND_UMAX_8] = "__sync_fetch_and_umax_8";
390 Names[RTLIB::SYNC_FETCH_AND_UMAX_16] = "__sync_fetch_and_umax_16";
391 Names[RTLIB::SYNC_FETCH_AND_MIN_1] = "__sync_fetch_and_min_1";
392 Names[RTLIB::SYNC_FETCH_AND_MIN_2] = "__sync_fetch_and_min_2";
393 Names[RTLIB::SYNC_FETCH_AND_MIN_4] = "__sync_fetch_and_min_4";
394 Names[RTLIB::SYNC_FETCH_AND_MIN_8] = "__sync_fetch_and_min_8";
395 Names[RTLIB::SYNC_FETCH_AND_MIN_16] = "__sync_fetch_and_min_16";
396 Names[RTLIB::SYNC_FETCH_AND_UMIN_1] = "__sync_fetch_and_umin_1";
397 Names[RTLIB::SYNC_FETCH_AND_UMIN_2] = "__sync_fetch_and_umin_2";
398 Names[RTLIB::SYNC_FETCH_AND_UMIN_4] = "__sync_fetch_and_umin_4";
399 Names[RTLIB::SYNC_FETCH_AND_UMIN_8] = "__sync_fetch_and_umin_8";
400 Names[RTLIB::SYNC_FETCH_AND_UMIN_16] = "__sync_fetch_and_umin_16";
Evan Cheng0e88c7d2013-01-29 02:32:37 +0000[diff] [blame]401
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]402 if (TT.getEnvironment() == Triple::GNU) {
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]403 Names[RTLIB::SINCOS_F32] = "sincosf";
404 Names[RTLIB::SINCOS_F64] = "sincos";
405 Names[RTLIB::SINCOS_F80] = "sincosl";
406 Names[RTLIB::SINCOS_F128] = "sincosl";
407 Names[RTLIB::SINCOS_PPCF128] = "sincosl";
408 } else {
409 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]410 Names[RTLIB::SINCOS_F32] = nullptr;
411 Names[RTLIB::SINCOS_F64] = nullptr;
412 Names[RTLIB::SINCOS_F80] = nullptr;
413 Names[RTLIB::SINCOS_F128] = nullptr;
414 Names[RTLIB::SINCOS_PPCF128] = nullptr;
Paul Redmondf29ddfe2013-02-15 18:45:18 +0000[diff] [blame]415 }
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]416
Simon Pilgrim2bfd9122014-11-29 19:18:21 +0000[diff] [blame]417 if (!TT.isOSOpenBSD()) {
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]418 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = "__stack_chk_fail";
419 } else {
420 // These are generally not available.
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]421 Names[RTLIB::STACKPROTECTOR_CHECK_FAIL] = nullptr;
Michael Gottesman7dce16f2013-08-12 18:45:38 +0000[diff] [blame]422 }
Ahmed Bougacha6402ad22015-05-14 01:00:51 +0000[diff] [blame^]423
424 // For f16/f32 conversions, Darwin uses the standard naming scheme, instead
425 // of the gnueabi-style __gnu_*_ieee.
426 // FIXME: What about other targets?
427 if (TT.isOSDarwin()) {
428 Names[RTLIB::FPEXT_F16_F32] = "__extendhfsf2";
429 Names[RTLIB::FPROUND_F32_F16] = "__truncsfhf2";
430 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]431}
432
433/// InitLibcallCallingConvs - Set default libcall CallingConvs.
434///
435static void InitLibcallCallingConvs(CallingConv::ID *CCs) {
436 for (int i = 0; i < RTLIB::UNKNOWN_LIBCALL; ++i) {
437 CCs[i] = CallingConv::C;
438 }
439}
440
441/// getFPEXT - Return the FPEXT_*_* value for the given types, or
442/// UNKNOWN_LIBCALL if there is none.
443RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
Tim Northoverf7a02c12014-07-21 09:13:56 +0000[diff] [blame]444 if (OpVT == MVT::f16) {
445 if (RetVT == MVT::f32)
446 return FPEXT_F16_F32;
447 } else if (OpVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]448 if (RetVT == MVT::f64)
449 return FPEXT_F32_F64;
450 if (RetVT == MVT::f128)
451 return FPEXT_F32_F128;
452 } else if (OpVT == MVT::f64) {
453 if (RetVT == MVT::f128)
454 return FPEXT_F64_F128;
455 }
456
457 return UNKNOWN_LIBCALL;
458}
459
460/// getFPROUND - Return the FPROUND_*_* value for the given types, or
461/// UNKNOWN_LIBCALL if there is none.
462RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
Tim Northover84ce0a62014-07-17 11:12:12 +0000[diff] [blame]463 if (RetVT == MVT::f16) {
464 if (OpVT == MVT::f32)
465 return FPROUND_F32_F16;
466 if (OpVT == MVT::f64)
467 return FPROUND_F64_F16;
468 if (OpVT == MVT::f80)
469 return FPROUND_F80_F16;
470 if (OpVT == MVT::f128)
471 return FPROUND_F128_F16;
472 if (OpVT == MVT::ppcf128)
473 return FPROUND_PPCF128_F16;
474 } else if (RetVT == MVT::f32) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]475 if (OpVT == MVT::f64)
476 return FPROUND_F64_F32;
477 if (OpVT == MVT::f80)
478 return FPROUND_F80_F32;
479 if (OpVT == MVT::f128)
480 return FPROUND_F128_F32;
481 if (OpVT == MVT::ppcf128)
482 return FPROUND_PPCF128_F32;
483 } else if (RetVT == MVT::f64) {
484 if (OpVT == MVT::f80)
485 return FPROUND_F80_F64;
486 if (OpVT == MVT::f128)
487 return FPROUND_F128_F64;
488 if (OpVT == MVT::ppcf128)
489 return FPROUND_PPCF128_F64;
490 }
491
492 return UNKNOWN_LIBCALL;
493}
494
495/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
496/// UNKNOWN_LIBCALL if there is none.
497RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
498 if (OpVT == MVT::f32) {
499 if (RetVT == MVT::i8)
500 return FPTOSINT_F32_I8;
501 if (RetVT == MVT::i16)
502 return FPTOSINT_F32_I16;
503 if (RetVT == MVT::i32)
504 return FPTOSINT_F32_I32;
505 if (RetVT == MVT::i64)
506 return FPTOSINT_F32_I64;
507 if (RetVT == MVT::i128)
508 return FPTOSINT_F32_I128;
509 } else if (OpVT == MVT::f64) {
510 if (RetVT == MVT::i8)
511 return FPTOSINT_F64_I8;
512 if (RetVT == MVT::i16)
513 return FPTOSINT_F64_I16;
514 if (RetVT == MVT::i32)
515 return FPTOSINT_F64_I32;
516 if (RetVT == MVT::i64)
517 return FPTOSINT_F64_I64;
518 if (RetVT == MVT::i128)
519 return FPTOSINT_F64_I128;
520 } else if (OpVT == MVT::f80) {
521 if (RetVT == MVT::i32)
522 return FPTOSINT_F80_I32;
523 if (RetVT == MVT::i64)
524 return FPTOSINT_F80_I64;
525 if (RetVT == MVT::i128)
526 return FPTOSINT_F80_I128;
527 } else if (OpVT == MVT::f128) {
528 if (RetVT == MVT::i32)
529 return FPTOSINT_F128_I32;
530 if (RetVT == MVT::i64)
531 return FPTOSINT_F128_I64;
532 if (RetVT == MVT::i128)
533 return FPTOSINT_F128_I128;
534 } else if (OpVT == MVT::ppcf128) {
535 if (RetVT == MVT::i32)
536 return FPTOSINT_PPCF128_I32;
537 if (RetVT == MVT::i64)
538 return FPTOSINT_PPCF128_I64;
539 if (RetVT == MVT::i128)
540 return FPTOSINT_PPCF128_I128;
541 }
542 return UNKNOWN_LIBCALL;
543}
544
545/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
546/// UNKNOWN_LIBCALL if there is none.
547RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
548 if (OpVT == MVT::f32) {
549 if (RetVT == MVT::i8)
550 return FPTOUINT_F32_I8;
551 if (RetVT == MVT::i16)
552 return FPTOUINT_F32_I16;
553 if (RetVT == MVT::i32)
554 return FPTOUINT_F32_I32;
555 if (RetVT == MVT::i64)
556 return FPTOUINT_F32_I64;
557 if (RetVT == MVT::i128)
558 return FPTOUINT_F32_I128;
559 } else if (OpVT == MVT::f64) {
560 if (RetVT == MVT::i8)
561 return FPTOUINT_F64_I8;
562 if (RetVT == MVT::i16)
563 return FPTOUINT_F64_I16;
564 if (RetVT == MVT::i32)
565 return FPTOUINT_F64_I32;
566 if (RetVT == MVT::i64)
567 return FPTOUINT_F64_I64;
568 if (RetVT == MVT::i128)
569 return FPTOUINT_F64_I128;
570 } else if (OpVT == MVT::f80) {
571 if (RetVT == MVT::i32)
572 return FPTOUINT_F80_I32;
573 if (RetVT == MVT::i64)
574 return FPTOUINT_F80_I64;
575 if (RetVT == MVT::i128)
576 return FPTOUINT_F80_I128;
577 } else if (OpVT == MVT::f128) {
578 if (RetVT == MVT::i32)
579 return FPTOUINT_F128_I32;
580 if (RetVT == MVT::i64)
581 return FPTOUINT_F128_I64;
582 if (RetVT == MVT::i128)
583 return FPTOUINT_F128_I128;
584 } else if (OpVT == MVT::ppcf128) {
585 if (RetVT == MVT::i32)
586 return FPTOUINT_PPCF128_I32;
587 if (RetVT == MVT::i64)
588 return FPTOUINT_PPCF128_I64;
589 if (RetVT == MVT::i128)
590 return FPTOUINT_PPCF128_I128;
591 }
592 return UNKNOWN_LIBCALL;
593}
594
595/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
596/// UNKNOWN_LIBCALL if there is none.
597RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
598 if (OpVT == MVT::i32) {
599 if (RetVT == MVT::f32)
600 return SINTTOFP_I32_F32;
601 if (RetVT == MVT::f64)
602 return SINTTOFP_I32_F64;
603 if (RetVT == MVT::f80)
604 return SINTTOFP_I32_F80;
605 if (RetVT == MVT::f128)
606 return SINTTOFP_I32_F128;
607 if (RetVT == MVT::ppcf128)
608 return SINTTOFP_I32_PPCF128;
609 } else if (OpVT == MVT::i64) {
610 if (RetVT == MVT::f32)
611 return SINTTOFP_I64_F32;
612 if (RetVT == MVT::f64)
613 return SINTTOFP_I64_F64;
614 if (RetVT == MVT::f80)
615 return SINTTOFP_I64_F80;
616 if (RetVT == MVT::f128)
617 return SINTTOFP_I64_F128;
618 if (RetVT == MVT::ppcf128)
619 return SINTTOFP_I64_PPCF128;
620 } else if (OpVT == MVT::i128) {
621 if (RetVT == MVT::f32)
622 return SINTTOFP_I128_F32;
623 if (RetVT == MVT::f64)
624 return SINTTOFP_I128_F64;
625 if (RetVT == MVT::f80)
626 return SINTTOFP_I128_F80;
627 if (RetVT == MVT::f128)
628 return SINTTOFP_I128_F128;
629 if (RetVT == MVT::ppcf128)
630 return SINTTOFP_I128_PPCF128;
631 }
632 return UNKNOWN_LIBCALL;
633}
634
635/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
636/// UNKNOWN_LIBCALL if there is none.
637RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
638 if (OpVT == MVT::i32) {
639 if (RetVT == MVT::f32)
640 return UINTTOFP_I32_F32;
641 if (RetVT == MVT::f64)
642 return UINTTOFP_I32_F64;
643 if (RetVT == MVT::f80)
644 return UINTTOFP_I32_F80;
645 if (RetVT == MVT::f128)
646 return UINTTOFP_I32_F128;
647 if (RetVT == MVT::ppcf128)
648 return UINTTOFP_I32_PPCF128;
649 } else if (OpVT == MVT::i64) {
650 if (RetVT == MVT::f32)
651 return UINTTOFP_I64_F32;
652 if (RetVT == MVT::f64)
653 return UINTTOFP_I64_F64;
654 if (RetVT == MVT::f80)
655 return UINTTOFP_I64_F80;
656 if (RetVT == MVT::f128)
657 return UINTTOFP_I64_F128;
658 if (RetVT == MVT::ppcf128)
659 return UINTTOFP_I64_PPCF128;
660 } else if (OpVT == MVT::i128) {
661 if (RetVT == MVT::f32)
662 return UINTTOFP_I128_F32;
663 if (RetVT == MVT::f64)
664 return UINTTOFP_I128_F64;
665 if (RetVT == MVT::f80)
666 return UINTTOFP_I128_F80;
667 if (RetVT == MVT::f128)
668 return UINTTOFP_I128_F128;
669 if (RetVT == MVT::ppcf128)
670 return UINTTOFP_I128_PPCF128;
671 }
672 return UNKNOWN_LIBCALL;
673}
674
Benjamin Kramerc54c38e2015-03-05 20:04:29 +0000[diff] [blame]675RTLIB::Libcall RTLIB::getATOMIC(unsigned Opc, MVT VT) {
676#define OP_TO_LIBCALL(Name, Enum) \
677 case Name: \
678 switch (VT.SimpleTy) { \
679 default: \
680 return UNKNOWN_LIBCALL; \
681 case MVT::i8: \
682 return Enum##_1; \
683 case MVT::i16: \
684 return Enum##_2; \
685 case MVT::i32: \
686 return Enum##_4; \
687 case MVT::i64: \
688 return Enum##_8; \
689 case MVT::i128: \
690 return Enum##_16; \
691 }
692
693 switch (Opc) {
694 OP_TO_LIBCALL(ISD::ATOMIC_SWAP, SYNC_LOCK_TEST_AND_SET)
695 OP_TO_LIBCALL(ISD::ATOMIC_CMP_SWAP, SYNC_VAL_COMPARE_AND_SWAP)
696 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_ADD, SYNC_FETCH_AND_ADD)
697 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_SUB, SYNC_FETCH_AND_SUB)
698 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_AND, SYNC_FETCH_AND_AND)
699 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_OR, SYNC_FETCH_AND_OR)
700 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_XOR, SYNC_FETCH_AND_XOR)
701 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_NAND, SYNC_FETCH_AND_NAND)
702 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MAX, SYNC_FETCH_AND_MAX)
703 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMAX, SYNC_FETCH_AND_UMAX)
704 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_MIN, SYNC_FETCH_AND_MIN)
705 OP_TO_LIBCALL(ISD::ATOMIC_LOAD_UMIN, SYNC_FETCH_AND_UMIN)
706 }
707
708#undef OP_TO_LIBCALL
709
710 return UNKNOWN_LIBCALL;
711}
712
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]713/// InitCmpLibcallCCs - Set default comparison libcall CC.
714///
715static void InitCmpLibcallCCs(ISD::CondCode *CCs) {
716 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL);
717 CCs[RTLIB::OEQ_F32] = ISD::SETEQ;
718 CCs[RTLIB::OEQ_F64] = ISD::SETEQ;
719 CCs[RTLIB::OEQ_F128] = ISD::SETEQ;
720 CCs[RTLIB::UNE_F32] = ISD::SETNE;
721 CCs[RTLIB::UNE_F64] = ISD::SETNE;
722 CCs[RTLIB::UNE_F128] = ISD::SETNE;
723 CCs[RTLIB::OGE_F32] = ISD::SETGE;
724 CCs[RTLIB::OGE_F64] = ISD::SETGE;
725 CCs[RTLIB::OGE_F128] = ISD::SETGE;
726 CCs[RTLIB::OLT_F32] = ISD::SETLT;
727 CCs[RTLIB::OLT_F64] = ISD::SETLT;
728 CCs[RTLIB::OLT_F128] = ISD::SETLT;
729 CCs[RTLIB::OLE_F32] = ISD::SETLE;
730 CCs[RTLIB::OLE_F64] = ISD::SETLE;
731 CCs[RTLIB::OLE_F128] = ISD::SETLE;
732 CCs[RTLIB::OGT_F32] = ISD::SETGT;
733 CCs[RTLIB::OGT_F64] = ISD::SETGT;
734 CCs[RTLIB::OGT_F128] = ISD::SETGT;
735 CCs[RTLIB::UO_F32] = ISD::SETNE;
736 CCs[RTLIB::UO_F64] = ISD::SETNE;
737 CCs[RTLIB::UO_F128] = ISD::SETNE;
738 CCs[RTLIB::O_F32] = ISD::SETEQ;
739 CCs[RTLIB::O_F64] = ISD::SETEQ;
740 CCs[RTLIB::O_F128] = ISD::SETEQ;
741}
742
Aditya Nandakumar30531552014-11-13 21:29:21 +0000[diff] [blame]743/// NOTE: The TargetMachine owns TLOF.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]744TargetLoweringBase::TargetLoweringBase(const TargetMachine &tm) : TM(tm) {
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]745 initActions();
746
747 // Perform these initializations only once.
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]748 IsLittleEndian = getDataLayout()->isLittleEndian();
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]749 MaxStoresPerMemset = MaxStoresPerMemcpy = MaxStoresPerMemmove = 8;
750 MaxStoresPerMemsetOptSize = MaxStoresPerMemcpyOptSize
751 = MaxStoresPerMemmoveOptSize = 4;
752 UseUnderscoreSetJmp = false;
753 UseUnderscoreLongJmp = false;
754 SelectIsExpensive = false;
Hal Finkeldecb0242014-01-02 21:13:43 +0000[diff] [blame]755 HasMultipleConditionRegisters = false;
Yi Jiangb23edeb2014-04-21 22:22:44 +0000[diff] [blame]756 HasExtractBitsInsn = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]757 IntDivIsCheap = false;
Matt Arsenaultbf0db912015-01-13 20:53:23 +0000[diff] [blame]758 FsqrtIsCheap = false;
Sanjay Patel2cdea4c2014-08-21 22:31:48 +0000[diff] [blame]759 Pow2SDivIsCheap = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]760 JumpIsExpensive = false;
761 PredictableSelectIsExpensive = false;
Tim Northovercea0abb2014-03-29 08:22:29 +0000[diff] [blame]762 MaskAndBranchFoldingIsLegal = false;
Quentin Colombetfc2201e2014-12-17 01:36:17 +0000[diff] [blame]763 EnableExtLdPromotion = false;
Pedro Artigascaa56582014-08-08 16:46:53 +0000[diff] [blame]764 HasFloatingPointExceptions = true;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]765 StackPointerRegisterToSaveRestore = 0;
766 ExceptionPointerRegister = 0;
767 ExceptionSelectorRegister = 0;
768 BooleanContents = UndefinedBooleanContent;
Daniel Sanderscbd44c52014-07-10 10:18:12 +0000[diff] [blame]769 BooleanFloatContents = UndefinedBooleanContent;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]770 BooleanVectorContents = UndefinedBooleanContent;
771 SchedPreferenceInfo = Sched::ILP;
772 JumpBufSize = 0;
773 JumpBufAlignment = 0;
774 MinFunctionAlignment = 0;
775 PrefFunctionAlignment = 0;
776 PrefLoopAlignment = 0;
777 MinStackArgumentAlignment = 1;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]778 InsertFencesForAtomic = false;
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]779 MinimumJumpTableEntries = 4;
780
Eric Christopherd91d6052014-06-02 20:51:49 +0000[diff] [blame]781 InitLibcallNames(LibcallRoutineNames, Triple(TM.getTargetTriple()));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]782 InitCmpLibcallCCs(CmpLibcallCCs);
783 InitLibcallCallingConvs(LibcallCallingConvs);
784}
785
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]786void TargetLoweringBase::initActions() {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]787 // All operations default to being supported.
788 memset(OpActions, 0, sizeof(OpActions));
789 memset(LoadExtActions, 0, sizeof(LoadExtActions));
790 memset(TruncStoreActions, 0, sizeof(TruncStoreActions));
791 memset(IndexedModeActions, 0, sizeof(IndexedModeActions));
792 memset(CondCodeActions, 0, sizeof(CondCodeActions));
Bill Wendlingeb108ba2013-04-05 21:52:40 +0000[diff] [blame]793 memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
794 memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]795
796 // Set default actions for various operations.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]797 for (MVT VT : MVT::all_valuetypes()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]798 // Default all indexed load / store to expand.
799 for (unsigned IM = (unsigned)ISD::PRE_INC;
800 IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]801 setIndexedLoadAction(IM, VT, Expand);
802 setIndexedStoreAction(IM, VT, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]803 }
804
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]805 // Most backends expect to see the node which just returns the value loaded.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]806 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, VT, Expand);
Tim Northover420a2162014-06-13 14:24:07 +0000[diff] [blame]807
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]808 // These operations default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]809 setOperationAction(ISD::FGETSIGN, VT, Expand);
810 setOperationAction(ISD::CONCAT_VECTORS, VT, Expand);
811 setOperationAction(ISD::FMINNUM, VT, Expand);
812 setOperationAction(ISD::FMAXNUM, VT, Expand);
Matt Arsenault0dc54c42015-02-20 22:10:33 +0000[diff] [blame]813 setOperationAction(ISD::FMAD, VT, Expand);
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]814
Jan Vesely75395482015-04-29 16:30:46 +0000[diff] [blame]815 // Overflow operations default to expand
816 setOperationAction(ISD::SADDO, VT, Expand);
817 setOperationAction(ISD::SSUBO, VT, Expand);
818 setOperationAction(ISD::UADDO, VT, Expand);
819 setOperationAction(ISD::USUBO, VT, Expand);
820 setOperationAction(ISD::SMULO, VT, Expand);
821 setOperationAction(ISD::UMULO, VT, Expand);
822
Hal Finkel8ec43c62013-08-09 04:13:44 +0000[diff] [blame]823 // These library functions default to expand.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]824 setOperationAction(ISD::FROUND, VT, Expand);
Hal Finkel0c5c01aa2013-08-19 23:35:46 +0000[diff] [blame]825
826 // These operations default to expand for vector types.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +0000[diff] [blame]827 if (VT.isVector()) {
828 setOperationAction(ISD::FCOPYSIGN, VT, Expand);
829 setOperationAction(ISD::ANY_EXTEND_VECTOR_INREG, VT, Expand);
830 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Expand);
831 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Expand);
Chandler Carruthd3561f62014-07-09 22:53:04 +0000[diff] [blame]832 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]833 }
834
835 // Most targets ignore the @llvm.prefetch intrinsic.
836 setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
837
838 // ConstantFP nodes default to expand. Targets can either change this to
839 // Legal, in which case all fp constants are legal, or use isFPImmLegal()
840 // to optimize expansions for certain constants.
841 setOperationAction(ISD::ConstantFP, MVT::f16, Expand);
842 setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
843 setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
844 setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
845 setOperationAction(ISD::ConstantFP, MVT::f128, Expand);
846
847 // These library functions default to expand.
Ahmed Bougacha2a20e272015-03-26 23:21:03 +0000[diff] [blame]848 for (MVT VT : {MVT::f32, MVT::f64, MVT::f128}) {
849 setOperationAction(ISD::FLOG , VT, Expand);
850 setOperationAction(ISD::FLOG2, VT, Expand);
851 setOperationAction(ISD::FLOG10, VT, Expand);
852 setOperationAction(ISD::FEXP , VT, Expand);
853 setOperationAction(ISD::FEXP2, VT, Expand);
854 setOperationAction(ISD::FFLOOR, VT, Expand);
855 setOperationAction(ISD::FMINNUM, VT, Expand);
856 setOperationAction(ISD::FMAXNUM, VT, Expand);
857 setOperationAction(ISD::FNEARBYINT, VT, Expand);
858 setOperationAction(ISD::FCEIL, VT, Expand);
859 setOperationAction(ISD::FRINT, VT, Expand);
860 setOperationAction(ISD::FTRUNC, VT, Expand);
861 setOperationAction(ISD::FROUND, VT, Expand);
862 }
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]863
864 // Default ISD::TRAP to expand (which turns it into abort).
865 setOperationAction(ISD::TRAP, MVT::Other, Expand);
866
867 // On most systems, DEBUGTRAP and TRAP have no difference. The "Expand"
868 // here is to inform DAG Legalizer to replace DEBUGTRAP with TRAP.
869 //
870 setOperationAction(ISD::DEBUGTRAP, MVT::Other, Expand);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]871}
872
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]873MVT TargetLoweringBase::getPointerTy(uint32_t AS) const {
874 return MVT::getIntegerVT(getPointerSizeInBits(AS));
875}
876
877unsigned TargetLoweringBase::getPointerSizeInBits(uint32_t AS) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]878 return getDataLayout()->getPointerSizeInBits(AS);
Tom Stellardfd155822013-08-26 15:05:36 +0000[diff] [blame]879}
880
881unsigned TargetLoweringBase::getPointerTypeSizeInBits(Type *Ty) const {
882 assert(Ty->isPointerTy());
883 return getPointerSizeInBits(Ty->getPointerAddressSpace());
884}
885
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]886MVT TargetLoweringBase::getScalarShiftAmountTy(EVT LHSTy) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]887 return MVT::getIntegerVT(8 * getDataLayout()->getPointerSize(0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]888}
889
Michael Liao6af16fc2013-03-01 18:40:30 +0000[diff] [blame]890EVT TargetLoweringBase::getShiftAmountTy(EVT LHSTy) const {
891 assert(LHSTy.isInteger() && "Shift amount is not an integer type!");
892 if (LHSTy.isVector())
893 return LHSTy;
894 return getScalarShiftAmountTy(LHSTy);
895}
896
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]897/// canOpTrap - Returns true if the operation can trap for the value type.
898/// VT must be a legal type.
899bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
900 assert(isTypeLegal(VT));
901 switch (Op) {
902 default:
903 return false;
904 case ISD::FDIV:
905 case ISD::FREM:
906 case ISD::SDIV:
907 case ISD::UDIV:
908 case ISD::SREM:
909 case ISD::UREM:
910 return true;
911 }
912}
913
Eric Christopher75dbd7c2015-02-25 22:41:30 +0000[diff] [blame]914TargetLoweringBase::LegalizeKind
915TargetLoweringBase::getTypeConversion(LLVMContext &Context, EVT VT) const {
916 // If this is a simple type, use the ComputeRegisterProp mechanism.
917 if (VT.isSimple()) {
918 MVT SVT = VT.getSimpleVT();
919 assert((unsigned)SVT.SimpleTy < array_lengthof(TransformToType));
920 MVT NVT = TransformToType[SVT.SimpleTy];
921 LegalizeTypeAction LA = ValueTypeActions.getTypeAction(SVT);
922
923 assert((LA == TypeLegal || LA == TypeSoftenFloat ||
924 ValueTypeActions.getTypeAction(NVT) != TypePromoteInteger) &&
925 "Promote may not follow Expand or Promote");
926
927 if (LA == TypeSplitVector)
928 return LegalizeKind(LA,
929 EVT::getVectorVT(Context, SVT.getVectorElementType(),
930 SVT.getVectorNumElements() / 2));
931 if (LA == TypeScalarizeVector)
932 return LegalizeKind(LA, SVT.getVectorElementType());
933 return LegalizeKind(LA, NVT);
934 }
935
936 // Handle Extended Scalar Types.
937 if (!VT.isVector()) {
938 assert(VT.isInteger() && "Float types must be simple");
939 unsigned BitSize = VT.getSizeInBits();
940 // First promote to a power-of-two size, then expand if necessary.
941 if (BitSize < 8 || !isPowerOf2_32(BitSize)) {
942 EVT NVT = VT.getRoundIntegerType(Context);
943 assert(NVT != VT && "Unable to round integer VT");
944 LegalizeKind NextStep = getTypeConversion(Context, NVT);
945 // Avoid multi-step promotion.
946 if (NextStep.first == TypePromoteInteger)
947 return NextStep;
948 // Return rounded integer type.
949 return LegalizeKind(TypePromoteInteger, NVT);
950 }
951
952 return LegalizeKind(TypeExpandInteger,
953 EVT::getIntegerVT(Context, VT.getSizeInBits() / 2));
954 }
955
956 // Handle vector types.
957 unsigned NumElts = VT.getVectorNumElements();
958 EVT EltVT = VT.getVectorElementType();
959
960 // Vectors with only one element are always scalarized.
961 if (NumElts == 1)
962 return LegalizeKind(TypeScalarizeVector, EltVT);
963
964 // Try to widen vector elements until the element type is a power of two and
965 // promote it to a legal type later on, for example:
966 // <3 x i8> -> <4 x i8> -> <4 x i32>
967 if (EltVT.isInteger()) {
968 // Vectors with a number of elements that is not a power of two are always
969 // widened, for example <3 x i8> -> <4 x i8>.
970 if (!VT.isPow2VectorType()) {
971 NumElts = (unsigned)NextPowerOf2(NumElts);
972 EVT NVT = EVT::getVectorVT(Context, EltVT, NumElts);
973 return LegalizeKind(TypeWidenVector, NVT);
974 }
975
976 // Examine the element type.
977 LegalizeKind LK = getTypeConversion(Context, EltVT);
978
979 // If type is to be expanded, split the vector.
980 // <4 x i140> -> <2 x i140>
981 if (LK.first == TypeExpandInteger)
982 return LegalizeKind(TypeSplitVector,
983 EVT::getVectorVT(Context, EltVT, NumElts / 2));
984
985 // Promote the integer element types until a legal vector type is found
986 // or until the element integer type is too big. If a legal type was not
987 // found, fallback to the usual mechanism of widening/splitting the
988 // vector.
989 EVT OldEltVT = EltVT;
990 while (1) {
991 // Increase the bitwidth of the element to the next pow-of-two
992 // (which is greater than 8 bits).
993 EltVT = EVT::getIntegerVT(Context, 1 + EltVT.getSizeInBits())
994 .getRoundIntegerType(Context);
995
996 // Stop trying when getting a non-simple element type.
997 // Note that vector elements may be greater than legal vector element
998 // types. Example: X86 XMM registers hold 64bit element on 32bit
999 // systems.
1000 if (!EltVT.isSimple())
1001 break;
1002
1003 // Build a new vector type and check if it is legal.
1004 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1005 // Found a legal promoted vector type.
1006 if (NVT != MVT() && ValueTypeActions.getTypeAction(NVT) == TypeLegal)
1007 return LegalizeKind(TypePromoteInteger,
1008 EVT::getVectorVT(Context, EltVT, NumElts));
1009 }
1010
1011 // Reset the type to the unexpanded type if we did not find a legal vector
1012 // type with a promoted vector element type.
1013 EltVT = OldEltVT;
1014 }
1015
1016 // Try to widen the vector until a legal type is found.
1017 // If there is no wider legal type, split the vector.
1018 while (1) {
1019 // Round up to the next power of 2.
1020 NumElts = (unsigned)NextPowerOf2(NumElts);
1021
1022 // If there is no simple vector type with this many elements then there
1023 // cannot be a larger legal vector type. Note that this assumes that
1024 // there are no skipped intermediate vector types in the simple types.
1025 if (!EltVT.isSimple())
1026 break;
1027 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts);
1028 if (LargerVector == MVT())
1029 break;
1030
1031 // If this type is legal then widen the vector.
1032 if (ValueTypeActions.getTypeAction(LargerVector) == TypeLegal)
1033 return LegalizeKind(TypeWidenVector, LargerVector);
1034 }
1035
1036 // Widen odd vectors to next power of two.
1037 if (!VT.isPow2VectorType()) {
1038 EVT NVT = VT.getPow2VectorType(Context);
1039 return LegalizeKind(TypeWidenVector, NVT);
1040 }
1041
1042 // Vectors with illegal element types are expanded.
1043 EVT NVT = EVT::getVectorVT(Context, EltVT, VT.getVectorNumElements() / 2);
1044 return LegalizeKind(TypeSplitVector, NVT);
1045}
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1046
1047static unsigned getVectorTypeBreakdownMVT(MVT VT, MVT &IntermediateVT,
1048 unsigned &NumIntermediates,
1049 MVT &RegisterVT,
1050 TargetLoweringBase *TLI) {
1051 // Figure out the right, legal destination reg to copy into.
1052 unsigned NumElts = VT.getVectorNumElements();
1053 MVT EltTy = VT.getVectorElementType();
1054
1055 unsigned NumVectorRegs = 1;
1056
1057 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1058 // could break down into LHS/RHS like LegalizeDAG does.
1059 if (!isPowerOf2_32(NumElts)) {
1060 NumVectorRegs = NumElts;
1061 NumElts = 1;
1062 }
1063
1064 // Divide the input until we get to a supported size. This will always
1065 // end with a scalar if the target doesn't support vectors.
1066 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
1067 NumElts >>= 1;
1068 NumVectorRegs <<= 1;
1069 }
1070
1071 NumIntermediates = NumVectorRegs;
1072
1073 MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
1074 if (!TLI->isTypeLegal(NewVT))
1075 NewVT = EltTy;
1076 IntermediateVT = NewVT;
1077
1078 unsigned NewVTSize = NewVT.getSizeInBits();
1079
1080 // Convert sizes such as i33 to i64.
1081 if (!isPowerOf2_32(NewVTSize))
1082 NewVTSize = NextPowerOf2(NewVTSize);
1083
1084 MVT DestVT = TLI->getRegisterType(NewVT);
1085 RegisterVT = DestVT;
1086 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1087 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1088
1089 // Otherwise, promotion or legal types use the same number of registers as
1090 // the vector decimated to the appropriate level.
1091 return NumVectorRegs;
1092}
1093
1094/// isLegalRC - Return true if the value types that can be represented by the
1095/// specified register class are all legal.
1096bool TargetLoweringBase::isLegalRC(const TargetRegisterClass *RC) const {
1097 for (TargetRegisterClass::vt_iterator I = RC->vt_begin(), E = RC->vt_end();
1098 I != E; ++I) {
1099 if (isTypeLegal(*I))
1100 return true;
1101 }
1102 return false;
1103}
1104
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1105/// Replace/modify any TargetFrameIndex operands with a targte-dependent
1106/// sequence of memory operands that is recognized by PrologEpilogInserter.
1107MachineBasicBlock*
1108TargetLoweringBase::emitPatchPoint(MachineInstr *MI,
1109 MachineBasicBlock *MBB) const {
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1110 MachineFunction &MF = *MI->getParent()->getParent();
1111
1112 // MI changes inside this loop as we grow operands.
1113 for(unsigned OperIdx = 0; OperIdx != MI->getNumOperands(); ++OperIdx) {
1114 MachineOperand &MO = MI->getOperand(OperIdx);
1115 if (!MO.isFI())
1116 continue;
1117
1118 // foldMemoryOperand builds a new MI after replacing a single FI operand
1119 // with the canonical set of five x86 addressing-mode operands.
1120 int FI = MO.getIndex();
1121 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), MI->getDesc());
1122
1123 // Copy operands before the frame-index.
1124 for (unsigned i = 0; i < OperIdx; ++i)
1125 MIB.addOperand(MI->getOperand(i));
1126 // Add frame index operands: direct-mem-ref tag, #FI, offset.
1127 MIB.addImm(StackMaps::DirectMemRefOp);
1128 MIB.addOperand(MI->getOperand(OperIdx));
1129 MIB.addImm(0);
1130 // Copy the operands after the frame index.
1131 for (unsigned i = OperIdx + 1; i != MI->getNumOperands(); ++i)
1132 MIB.addOperand(MI->getOperand(i));
1133
1134 // Inherit previous memory operands.
1135 MIB->setMemRefs(MI->memoperands_begin(), MI->memoperands_end());
1136 assert(MIB->mayLoad() && "Folded a stackmap use to a non-load!");
1137
1138 // Add a new memory operand for this FI.
1139 const MachineFrameInfo &MFI = *MF.getFrameInfo();
1140 assert(MFI.getObjectOffset(FI) != -1);
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1141
1142 unsigned Flags = MachineMemOperand::MOLoad;
1143 if (MI->getOpcode() == TargetOpcode::STATEPOINT) {
1144 Flags |= MachineMemOperand::MOStore;
1145 Flags |= MachineMemOperand::MOVolatile;
1146 }
Eric Christopherd9134482014-08-04 21:25:23 +0000[diff] [blame]1147 MachineMemOperand *MMO = MF.getMachineMemOperand(
Philip Reames0365f1a2014-12-01 22:52:56 +0000[diff] [blame]1148 MachinePointerInfo::getFixedStack(FI), Flags,
Eric Christopher8b770652015-01-26 19:03:15 +0000[diff] [blame]1149 TM.getDataLayout()->getPointerSize(), MFI.getObjectAlignment(FI));
Lang Hames39609992013-11-29 03:07:54 +0000[diff] [blame]1150 MIB->addMemOperand(MF, MMO);
1151
1152 // Replace the instruction and update the operand index.
1153 MBB->insert(MachineBasicBlock::iterator(MI), MIB);
1154 OperIdx += (MIB->getNumOperands() - MI->getNumOperands()) - 1;
1155 MI->eraseFromParent();
1156 MI = MIB;
1157 }
1158 return MBB;
1159}
1160
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1161/// findRepresentativeClass - Return the largest legal super-reg register class
1162/// of the register class for the specified type and its associated "cost".
Eric Christopher720ab842015-03-03 19:47:14 +0000[diff] [blame]1163// This function is in TargetLowering because it uses RegClassForVT which would
1164// need to be moved to TargetRegisterInfo and would necessitate moving
1165// isTypeLegal over as well - a massive change that would just require
1166// TargetLowering having a TargetRegisterInfo class member that it would use.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1167std::pair<const TargetRegisterClass *, uint8_t>
1168TargetLoweringBase::findRepresentativeClass(const TargetRegisterInfo *TRI,
1169 MVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1170 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
1171 if (!RC)
1172 return std::make_pair(RC, 0);
1173
1174 // Compute the set of all super-register classes.
1175 BitVector SuperRegRC(TRI->getNumRegClasses());
1176 for (SuperRegClassIterator RCI(RC, TRI); RCI.isValid(); ++RCI)
1177 SuperRegRC.setBitsInMask(RCI.getMask());
1178
1179 // Find the first legal register class with the largest spill size.
1180 const TargetRegisterClass *BestRC = RC;
1181 for (int i = SuperRegRC.find_first(); i >= 0; i = SuperRegRC.find_next(i)) {
1182 const TargetRegisterClass *SuperRC = TRI->getRegClass(i);
1183 // We want the largest possible spill size.
1184 if (SuperRC->getSize() <= BestRC->getSize())
1185 continue;
1186 if (!isLegalRC(SuperRC))
1187 continue;
1188 BestRC = SuperRC;
1189 }
1190 return std::make_pair(BestRC, 1);
1191}
1192
1193/// computeRegisterProperties - Once all of the register classes are added,
1194/// this allows us to compute derived properties we expose.
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1195void TargetLoweringBase::computeRegisterProperties(
1196 const TargetRegisterInfo *TRI) {
Craig Topper6438fc32014-11-17 00:26:50 +0000[diff] [blame]1197 static_assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE,
1198 "Too many value types for ValueTypeActions to hold!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1199
1200 // Everything defaults to needing one register.
1201 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1202 NumRegistersForVT[i] = 1;
1203 RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
1204 }
1205 // ...except isVoid, which doesn't need any registers.
1206 NumRegistersForVT[MVT::isVoid] = 0;
1207
1208 // Find the largest integer register class.
1209 unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
Craig Topperc0196b12014-04-14 00:51:57 +0000[diff] [blame]1210 for (; RegClassForVT[LargestIntReg] == nullptr; --LargestIntReg)
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1211 assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
1212
1213 // Every integer value type larger than this largest register takes twice as
1214 // many registers to represent as the previous ValueType.
1215 for (unsigned ExpandedReg = LargestIntReg + 1;
1216 ExpandedReg <= MVT::LAST_INTEGER_VALUETYPE; ++ExpandedReg) {
1217 NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
1218 RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
1219 TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
1220 ValueTypeActions.setTypeAction((MVT::SimpleValueType)ExpandedReg,
1221 TypeExpandInteger);
1222 }
1223
1224 // Inspect all of the ValueType's smaller than the largest integer
1225 // register to see which ones need promotion.
1226 unsigned LegalIntReg = LargestIntReg;
1227 for (unsigned IntReg = LargestIntReg - 1;
1228 IntReg >= (unsigned)MVT::i1; --IntReg) {
1229 MVT IVT = (MVT::SimpleValueType)IntReg;
1230 if (isTypeLegal(IVT)) {
1231 LegalIntReg = IntReg;
1232 } else {
1233 RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
1234 (const MVT::SimpleValueType)LegalIntReg;
1235 ValueTypeActions.setTypeAction(IVT, TypePromoteInteger);
1236 }
1237 }
1238
1239 // ppcf128 type is really two f64's.
1240 if (!isTypeLegal(MVT::ppcf128)) {
1241 NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
1242 RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
1243 TransformToType[MVT::ppcf128] = MVT::f64;
1244 ValueTypeActions.setTypeAction(MVT::ppcf128, TypeExpandFloat);
1245 }
1246
Akira Hatanaka3d055582013-03-01 21:11:44 +0000[diff] [blame]1247 // Decide how to handle f128. If the target does not have native f128 support,
1248 // expand it to i128 and we will be generating soft float library calls.
1249 if (!isTypeLegal(MVT::f128)) {
1250 NumRegistersForVT[MVT::f128] = NumRegistersForVT[MVT::i128];
1251 RegisterTypeForVT[MVT::f128] = RegisterTypeForVT[MVT::i128];
1252 TransformToType[MVT::f128] = MVT::i128;
1253 ValueTypeActions.setTypeAction(MVT::f128, TypeSoftenFloat);
1254 }
1255
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1256 // Decide how to handle f64. If the target does not have native f64 support,
1257 // expand it to i64 and we will be generating soft float library calls.
1258 if (!isTypeLegal(MVT::f64)) {
1259 NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
1260 RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
1261 TransformToType[MVT::f64] = MVT::i64;
1262 ValueTypeActions.setTypeAction(MVT::f64, TypeSoftenFloat);
1263 }
1264
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1265 // Decide how to handle f32. If the target does not have native f32 support,
1266 // expand it to i32 and we will be generating soft float library calls.
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1267 if (!isTypeLegal(MVT::f32)) {
Ahmed Bougachaa0f35592015-03-28 01:22:37 +0000[diff] [blame]1268 NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
1269 RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
1270 TransformToType[MVT::f32] = MVT::i32;
1271 ValueTypeActions.setTypeAction(MVT::f32, TypeSoftenFloat);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1272 }
1273
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1274 if (!isTypeLegal(MVT::f16)) {
Pirama Arumuga Nainardb7c07e22015-04-17 18:36:25 +0000[diff] [blame]1275 // If the target has native f32 support, promote f16 operations to f32. If
1276 // f32 is not supported, generate soft float library calls.
1277 if (isTypeLegal(MVT::f32)) {
1278 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::f32];
1279 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::f32];
1280 TransformToType[MVT::f16] = MVT::f32;
1281 ValueTypeActions.setTypeAction(MVT::f16, TypePromoteFloat);
1282 } else {
1283 NumRegistersForVT[MVT::f16] = NumRegistersForVT[MVT::i16];
1284 RegisterTypeForVT[MVT::f16] = RegisterTypeForVT[MVT::i16];
1285 TransformToType[MVT::f16] = MVT::i16;
1286 ValueTypeActions.setTypeAction(MVT::f16, TypeSoftenFloat);
1287 }
Tim Northover20bd0ce2014-07-18 12:41:46 +0000[diff] [blame]1288 }
1289
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1290 // Loop over all of the vector value types to see which need transformations.
1291 for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
1292 i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1293 MVT VT = (MVT::SimpleValueType) i;
1294 if (isTypeLegal(VT))
1295 continue;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1296
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1297 MVT EltVT = VT.getVectorElementType();
1298 unsigned NElts = VT.getVectorNumElements();
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1299 bool IsLegalWiderType = false;
1300 LegalizeTypeAction PreferredAction = getPreferredVectorAction(VT);
1301 switch (PreferredAction) {
1302 case TypePromoteInteger: {
1303 // Try to promote the elements of integer vectors. If no legal
1304 // promotion was found, fall through to the widen-vector method.
1305 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1306 MVT SVT = (MVT::SimpleValueType) nVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1307 // Promote vectors of integers to vectors with the same number
1308 // of elements, with a wider element type.
1309 if (SVT.getVectorElementType().getSizeInBits() > EltVT.getSizeInBits()
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1310 && SVT.getVectorNumElements() == NElts && isTypeLegal(SVT)
1311 && SVT.getScalarType().isInteger()) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1312 TransformToType[i] = SVT;
1313 RegisterTypeForVT[i] = SVT;
1314 NumRegistersForVT[i] = 1;
1315 ValueTypeActions.setTypeAction(VT, TypePromoteInteger);
1316 IsLegalWiderType = true;
1317 break;
1318 }
1319 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1320 if (IsLegalWiderType)
1321 break;
1322 }
1323 case TypeWidenVector: {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1324 // Try to widen the vector.
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1325 for (unsigned nVT = i + 1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
1326 MVT SVT = (MVT::SimpleValueType) nVT;
1327 if (SVT.getVectorElementType() == EltVT
1328 && SVT.getVectorNumElements() > NElts && isTypeLegal(SVT)) {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1329 TransformToType[i] = SVT;
1330 RegisterTypeForVT[i] = SVT;
1331 NumRegistersForVT[i] = 1;
1332 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1333 IsLegalWiderType = true;
1334 break;
1335 }
1336 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1337 if (IsLegalWiderType)
1338 break;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1339 }
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1340 case TypeSplitVector:
1341 case TypeScalarizeVector: {
1342 MVT IntermediateVT;
1343 MVT RegisterVT;
1344 unsigned NumIntermediates;
1345 NumRegistersForVT[i] = getVectorTypeBreakdownMVT(VT, IntermediateVT,
1346 NumIntermediates, RegisterVT, this);
1347 RegisterTypeForVT[i] = RegisterVT;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1348
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1349 MVT NVT = VT.getPow2VectorType();
1350 if (NVT == VT) {
1351 // Type is already a power of 2. The default action is to split.
1352 TransformToType[i] = MVT::Other;
1353 if (PreferredAction == TypeScalarizeVector)
1354 ValueTypeActions.setTypeAction(VT, TypeScalarizeVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1355 else if (PreferredAction == TypeSplitVector)
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1356 ValueTypeActions.setTypeAction(VT, TypeSplitVector);
Hao Liue02b1a02014-10-31 02:35:34 +0000[diff] [blame]1357 else
1358 // Set type action according to the number of elements.
1359 ValueTypeActions.setTypeAction(VT, NElts == 1 ? TypeScalarizeVector
1360 : TypeSplitVector);
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000[diff] [blame]1361 } else {
1362 TransformToType[i] = NVT;
1363 ValueTypeActions.setTypeAction(VT, TypeWidenVector);
1364 }
1365 break;
1366 }
1367 default:
1368 llvm_unreachable("Unknown vector legalization action!");
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1369 }
1370 }
1371
1372 // Determine the 'representative' register class for each value type.
1373 // An representative register class is the largest (meaning one which is
1374 // not a sub-register class / subreg register class) legal register class for
1375 // a group of value types. For example, on i386, i8, i16, and i32
1376 // representative would be GR32; while on x86_64 it's GR64.
1377 for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
1378 const TargetRegisterClass* RRC;
1379 uint8_t Cost;
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]1380 std::tie(RRC, Cost) = findRepresentativeClass(TRI, (MVT::SimpleValueType)i);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1381 RepRegClassForVT[i] = RRC;
1382 RepRegClassCostForVT[i] = Cost;
1383 }
1384}
1385
Matt Arsenault758659232013-05-18 00:21:46 +0000[diff] [blame]1386EVT TargetLoweringBase::getSetCCResultType(LLVMContext &, EVT VT) const {
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1387 assert(!VT.isVector() && "No default SetCC type for vectors!");
1388 return getPointerTy(0).SimpleTy;
1389}
1390
1391MVT::SimpleValueType TargetLoweringBase::getCmpLibcallReturnType() const {
1392 return MVT::i32; // return the default value
1393}
1394
1395/// getVectorTypeBreakdown - Vector types are broken down into some number of
1396/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
1397/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
1398/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
1399///
1400/// This method returns the number of registers needed, and the VT for each
1401/// register. It also returns the VT and quantity of the intermediate values
1402/// before they are promoted/expanded.
1403///
1404unsigned TargetLoweringBase::getVectorTypeBreakdown(LLVMContext &Context, EVT VT,
1405 EVT &IntermediateVT,
1406 unsigned &NumIntermediates,
1407 MVT &RegisterVT) const {
1408 unsigned NumElts = VT.getVectorNumElements();
1409
1410 // If there is a wider vector type with the same element type as this one,
1411 // or a promoted vector type that has the same number of elements which
1412 // are wider, then we should convert to that legal vector type.
1413 // This handles things like <2 x float> -> <4 x float> and
1414 // <4 x i1> -> <4 x i32>.
1415 LegalizeTypeAction TA = getTypeAction(Context, VT);
1416 if (NumElts != 1 && (TA == TypeWidenVector || TA == TypePromoteInteger)) {
1417 EVT RegisterEVT = getTypeToTransformTo(Context, VT);
1418 if (isTypeLegal(RegisterEVT)) {
1419 IntermediateVT = RegisterEVT;
1420 RegisterVT = RegisterEVT.getSimpleVT();
1421 NumIntermediates = 1;
1422 return 1;
1423 }
1424 }
1425
1426 // Figure out the right, legal destination reg to copy into.
1427 EVT EltTy = VT.getVectorElementType();
1428
1429 unsigned NumVectorRegs = 1;
1430
1431 // FIXME: We don't support non-power-of-2-sized vectors for now. Ideally we
1432 // could break down into LHS/RHS like LegalizeDAG does.
1433 if (!isPowerOf2_32(NumElts)) {
1434 NumVectorRegs = NumElts;
1435 NumElts = 1;
1436 }
1437
1438 // Divide the input until we get to a supported size. This will always
1439 // end with a scalar if the target doesn't support vectors.
1440 while (NumElts > 1 && !isTypeLegal(
1441 EVT::getVectorVT(Context, EltTy, NumElts))) {
1442 NumElts >>= 1;
1443 NumVectorRegs <<= 1;
1444 }
1445
1446 NumIntermediates = NumVectorRegs;
1447
1448 EVT NewVT = EVT::getVectorVT(Context, EltTy, NumElts);
1449 if (!isTypeLegal(NewVT))
1450 NewVT = EltTy;
1451 IntermediateVT = NewVT;
1452
1453 MVT DestVT = getRegisterType(Context, NewVT);
1454 RegisterVT = DestVT;
1455 unsigned NewVTSize = NewVT.getSizeInBits();
1456
1457 // Convert sizes such as i33 to i64.
1458 if (!isPowerOf2_32(NewVTSize))
1459 NewVTSize = NextPowerOf2(NewVTSize);
1460
1461 if (EVT(DestVT).bitsLT(NewVT)) // Value is expanded, e.g. i64 -> i16.
1462 return NumVectorRegs*(NewVTSize/DestVT.getSizeInBits());
1463
1464 // Otherwise, promotion or legal types use the same number of registers as
1465 // the vector decimated to the appropriate level.
1466 return NumVectorRegs;
1467}
1468
1469/// Get the EVTs and ArgFlags collections that represent the legalized return
1470/// type of the given function. This does not require a DAG or a return value,
1471/// and is suitable for use before any DAGs for the function are constructed.
1472/// TODO: Move this out of TargetLowering.cpp.
1473void llvm::GetReturnInfo(Type* ReturnType, AttributeSet attr,
1474 SmallVectorImpl<ISD::OutputArg> &Outs,
1475 const TargetLowering &TLI) {
1476 SmallVector<EVT, 4> ValueVTs;
1477 ComputeValueVTs(TLI, ReturnType, ValueVTs);
1478 unsigned NumValues = ValueVTs.size();
1479 if (NumValues == 0) return;
1480
1481 for (unsigned j = 0, f = NumValues; j != f; ++j) {
1482 EVT VT = ValueVTs[j];
1483 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
1484
1485 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1486 ExtendKind = ISD::SIGN_EXTEND;
1487 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1488 ExtendKind = ISD::ZERO_EXTEND;
1489
1490 // FIXME: C calling convention requires the return type to be promoted to
1491 // at least 32-bit. But this is not necessary for non-C calling
1492 // conventions. The frontend should mark functions whose return values
1493 // require promoting with signext or zeroext attributes.
1494 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
1495 MVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
1496 if (VT.bitsLT(MinVT))
1497 VT = MinVT;
1498 }
1499
1500 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
1501 MVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1502
1503 // 'inreg' on function refers to return value
1504 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1505 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::InReg))
1506 Flags.setInReg();
1507
1508 // Propagate extension type if any
1509 if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::SExt))
1510 Flags.setSExt();
1511 else if (attr.hasAttribute(AttributeSet::ReturnIndex, Attribute::ZExt))
1512 Flags.setZExt();
1513
1514 for (unsigned i = 0; i < NumParts; ++i)
Tom Stellard8d7d4de2013-10-23 00:44:24 +0000[diff] [blame]1515 Outs.push_back(ISD::OutputArg(Flags, PartVT, VT, /*isFixed=*/true, 0, 0));
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1516 }
1517}
1518
1519/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
1520/// function arguments in the caller parameter area. This is the actual
1521/// alignment, not its logarithm.
1522unsigned TargetLoweringBase::getByValTypeAlignment(Type *Ty) const {
Mehdi Aminia28d91d2015-03-10 02:37:25 +0000[diff] [blame]1523 return getDataLayout()->getABITypeAlignment(Ty);
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1524}
1525
1526//===----------------------------------------------------------------------===//
1527// TargetTransformInfo Helpers
1528//===----------------------------------------------------------------------===//
1529
1530int TargetLoweringBase::InstructionOpcodeToISD(unsigned Opcode) const {
1531 enum InstructionOpcodes {
1532#define HANDLE_INST(NUM, OPCODE, CLASS) OPCODE = NUM,
1533#define LAST_OTHER_INST(NUM) InstructionOpcodesCount = NUM
1534#include "llvm/IR/Instruction.def"
1535 };
1536 switch (static_cast<InstructionOpcodes>(Opcode)) {
1537 case Ret: return 0;
1538 case Br: return 0;
1539 case Switch: return 0;
1540 case IndirectBr: return 0;
1541 case Invoke: return 0;
1542 case Resume: return 0;
1543 case Unreachable: return 0;
1544 case Add: return ISD::ADD;
1545 case FAdd: return ISD::FADD;
1546 case Sub: return ISD::SUB;
1547 case FSub: return ISD::FSUB;
1548 case Mul: return ISD::MUL;
1549 case FMul: return ISD::FMUL;
1550 case UDiv: return ISD::UDIV;
Benjamin Kramerce4b3fe2014-04-27 18:47:54 +0000[diff] [blame]1551 case SDiv: return ISD::SDIV;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1552 case FDiv: return ISD::FDIV;
1553 case URem: return ISD::UREM;
1554 case SRem: return ISD::SREM;
1555 case FRem: return ISD::FREM;
1556 case Shl: return ISD::SHL;
1557 case LShr: return ISD::SRL;
1558 case AShr: return ISD::SRA;
1559 case And: return ISD::AND;
1560 case Or: return ISD::OR;
1561 case Xor: return ISD::XOR;
1562 case Alloca: return 0;
1563 case Load: return ISD::LOAD;
1564 case Store: return ISD::STORE;
1565 case GetElementPtr: return 0;
1566 case Fence: return 0;
1567 case AtomicCmpXchg: return 0;
1568 case AtomicRMW: return 0;
1569 case Trunc: return ISD::TRUNCATE;
1570 case ZExt: return ISD::ZERO_EXTEND;
1571 case SExt: return ISD::SIGN_EXTEND;
1572 case FPToUI: return ISD::FP_TO_UINT;
1573 case FPToSI: return ISD::FP_TO_SINT;
1574 case UIToFP: return ISD::UINT_TO_FP;
1575 case SIToFP: return ISD::SINT_TO_FP;
1576 case FPTrunc: return ISD::FP_ROUND;
1577 case FPExt: return ISD::FP_EXTEND;
1578 case PtrToInt: return ISD::BITCAST;
1579 case IntToPtr: return ISD::BITCAST;
1580 case BitCast: return ISD::BITCAST;
Matt Arsenaultb03bd4d2013-11-15 01:34:59 +0000[diff] [blame]1581 case AddrSpaceCast: return ISD::ADDRSPACECAST;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1582 case ICmp: return ISD::SETCC;
1583 case FCmp: return ISD::SETCC;
1584 case PHI: return 0;
1585 case Call: return 0;
1586 case Select: return ISD::SELECT;
1587 case UserOp1: return 0;
1588 case UserOp2: return 0;
1589 case VAArg: return 0;
1590 case ExtractElement: return ISD::EXTRACT_VECTOR_ELT;
1591 case InsertElement: return ISD::INSERT_VECTOR_ELT;
1592 case ShuffleVector: return ISD::VECTOR_SHUFFLE;
1593 case ExtractValue: return ISD::MERGE_VALUES;
1594 case InsertValue: return ISD::MERGE_VALUES;
1595 case LandingPad: return 0;
1596 }
1597
1598 llvm_unreachable("Unknown instruction type encountered!");
1599}
1600
1601std::pair<unsigned, MVT>
1602TargetLoweringBase::getTypeLegalizationCost(Type *Ty) const {
1603 LLVMContext &C = Ty->getContext();
1604 EVT MTy = getValueType(Ty);
1605
1606 unsigned Cost = 1;
1607 // We keep legalizing the type until we find a legal kind. We assume that
1608 // the only operation that costs anything is the split. After splitting
1609 // we need to handle two types.
1610 while (true) {
1611 LegalizeKind LK = getTypeConversion(C, MTy);
1612
1613 if (LK.first == TypeLegal)
1614 return std::make_pair(Cost, MTy.getSimpleVT());
1615
1616 if (LK.first == TypeSplitVector || LK.first == TypeExpandInteger)
1617 Cost *= 2;
1618
1619 // Keep legalizing the type.
1620 MTy = LK.second;
1621 }
1622}
1623
1624//===----------------------------------------------------------------------===//
1625// Loop Strength Reduction hooks
1626//===----------------------------------------------------------------------===//
1627
1628/// isLegalAddressingMode - Return true if the addressing mode represented
1629/// by AM is legal for this target, for a load/store of the specified type.
1630bool TargetLoweringBase::isLegalAddressingMode(const AddrMode &AM,
1631 Type *Ty) const {
1632 // The default implementation of this implements a conservative RISCy, r+r and
1633 // r+i addr mode.
1634
1635 // Allows a sign-extended 16-bit immediate field.
1636 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1)
1637 return false;
1638
1639 // No global is ever allowed as a base.
1640 if (AM.BaseGV)
1641 return false;
1642
1643 // Only support r+r,
1644 switch (AM.Scale) {
1645 case 0: // "r+i" or just "i", depending on HasBaseReg.
1646 break;
1647 case 1:
1648 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed.
1649 return false;
1650 // Otherwise we have r+r or r+i.
1651 break;
1652 case 2:
1653 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed.
1654 return false;
1655 // Allow 2*r as r+r.
1656 break;
Tom Stellard728d4172014-02-14 21:10:34 +0000[diff] [blame]1657 default: // Don't allow n * r
1658 return false;
Benjamin Kramer56b31bd2013-01-11 20:05:37 +0000[diff] [blame]1659 }
1660
1661 return true;
1662}