| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 1 | //===-- R600Intrinsics.td - R600 Instrinsic defs -------*- tablegen -*-----===// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | // |
| 10 | // R600 Intrinsic Definitions |
| 11 | // |
| 12 | //===----------------------------------------------------------------------===// |
| 13 | |
| Matt Arsenault | 59bd301 | 2016-01-22 19:00:09 +0000 | [diff] [blame] | 14 | // FIXME: Should migrate to using TargetPrefix that matches triple arch name. |
| Matt Arsenault | bee7575 | 2016-01-26 04:49:24 +0000 | [diff] [blame] | 15 | let TargetPrefix = "AMDGPU", isTarget = 1 in { |
| 16 | def int_AMDGPU_dp4 : Intrinsic<[llvm_float_ty], [llvm_v4f32_ty, llvm_v4f32_ty], [IntrNoMem]>; |
| 17 | def int_AMDGPU_tex : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 18 | def int_AMDGPU_txb : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 19 | def int_AMDGPU_txf : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 20 | def int_AMDGPU_txq : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 21 | def int_AMDGPU_txd : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_v4f32_ty, llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 22 | def int_AMDGPU_txl : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 23 | def int_AMDGPU_ddx : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 24 | def int_AMDGPU_ddy : Intrinsic<[llvm_v4f32_ty], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| 25 | } |
| 26 | |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 27 | let TargetPrefix = "R600", isTarget = 1 in { |
| Vincent Lejeune | d3eed66 | 2013-05-17 16:50:20 +0000 | [diff] [blame] | 28 | class TextureIntrinsicFloatInput : |
| 29 | Intrinsic<[llvm_v4f32_ty], [ |
| 30 | llvm_v4f32_ty, // Coord |
| 31 | llvm_i32_ty, // offset_x |
| 32 | llvm_i32_ty, // offset_y, |
| 33 | llvm_i32_ty, // offset_z, |
| 34 | llvm_i32_ty, // resource_id |
| 35 | llvm_i32_ty, // samplerid |
| 36 | llvm_i32_ty, // coord_type_x |
| 37 | llvm_i32_ty, // coord_type_y |
| 38 | llvm_i32_ty, // coord_type_z |
| 39 | llvm_i32_ty // coord_type_w |
| 40 | ], [IntrNoMem]>; |
| 41 | class TextureIntrinsicInt32Input : |
| 42 | Intrinsic<[llvm_v4i32_ty], [ |
| 43 | llvm_v4i32_ty, // Coord |
| 44 | llvm_i32_ty, // offset_x |
| 45 | llvm_i32_ty, // offset_y, |
| 46 | llvm_i32_ty, // offset_z, |
| 47 | llvm_i32_ty, // resource_id |
| 48 | llvm_i32_ty, // samplerid |
| 49 | llvm_i32_ty, // coord_type_x |
| 50 | llvm_i32_ty, // coord_type_y |
| 51 | llvm_i32_ty, // coord_type_z |
| 52 | llvm_i32_ty // coord_type_w |
| 53 | ], [IntrNoMem]>; |
| 54 | |
| Matt Arsenault | 59bd301 | 2016-01-22 19:00:09 +0000 | [diff] [blame] | 55 | def int_R600_ldptr : TextureIntrinsicInt32Input; |
| 56 | |
| Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 57 | def int_R600_interp_const : |
| 58 | Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty], [IntrNoMem]>; |
| Matt Arsenault | 59bd301 | 2016-01-22 19:00:09 +0000 | [diff] [blame] | 59 | def int_R600_interp_xy : |
| Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 60 | Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; |
| Matt Arsenault | 59bd301 | 2016-01-22 19:00:09 +0000 | [diff] [blame] | 61 | def int_R600_interp_zw : |
| Vincent Lejeune | f143af3 | 2013-11-11 22:10:24 +0000 | [diff] [blame] | 62 | Intrinsic<[llvm_v2f32_ty], [llvm_i32_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]>; |
| Vincent Lejeune | 6850180 | 2013-02-18 14:11:19 +0000 | [diff] [blame] | 63 | def int_R600_load_texbuf : |
| 64 | Intrinsic<[llvm_v4f32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>; |
| Tom Stellard | 6f1b865 | 2013-01-23 21:39:49 +0000 | [diff] [blame] | 65 | def int_R600_store_swizzle : |
| 66 | Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty], []>; |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 67 | def int_R600_store_stream_output : |
| Tom Stellard | d8ac91d | 2013-01-23 21:39:47 +0000 | [diff] [blame] | 68 | Intrinsic<[], [llvm_v4f32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], []>; |
| Tom Stellard | 75aadc2 | 2012-12-11 21:25:42 +0000 | [diff] [blame] | 69 | def int_R600_store_pixel_depth : |
| 70 | Intrinsic<[], [llvm_float_ty], []>; |
| 71 | def int_R600_store_pixel_stencil : |
| 72 | Intrinsic<[], [llvm_float_ty], []>; |
| Tom Stellard | af1bce7 | 2013-01-31 22:11:46 +0000 | [diff] [blame] | 73 | def int_R600_store_dummy : |
| 74 | Intrinsic<[], [llvm_i32_ty], []>; |
| Matt Arsenault | 59bd301 | 2016-01-22 19:00:09 +0000 | [diff] [blame] | 75 | } // End TargetPrefix = "R600", isTarget = 1 |
| 76 | |
| 77 | let TargetPrefix = "r600", isTarget = 1 in { |
| 78 | def int_r600_tex : TextureIntrinsicFloatInput; |
| 79 | def int_r600_texc : TextureIntrinsicFloatInput; |
| 80 | def int_r600_txl : TextureIntrinsicFloatInput; |
| 81 | def int_r600_txlc : TextureIntrinsicFloatInput; |
| 82 | def int_r600_txb : TextureIntrinsicFloatInput; |
| 83 | def int_r600_txbc : TextureIntrinsicFloatInput; |
| 84 | def int_r600_txf : TextureIntrinsicInt32Input; |
| 85 | def int_r600_txq : TextureIntrinsicInt32Input; |
| 86 | def int_r600_ddx : TextureIntrinsicFloatInput; |
| 87 | def int_r600_ddy : TextureIntrinsicFloatInput; |
| Matt Arsenault | bee7575 | 2016-01-26 04:49:24 +0000 | [diff] [blame] | 88 | } // End TargetPrefix = "r600", isTarget = 1 |