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Amara Emerson836b0f42017-05-10 09:42:49 +00001//===--- ExpandReductions.cpp - Expand experimental reduction intrinsics --===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Amara Emerson836b0f42017-05-10 09:42:49 +00006//
7//===----------------------------------------------------------------------===//
8//
9// This pass implements IR expansion for reduction intrinsics, allowing targets
10// to enable the experimental intrinsics until just before codegen.
11//
12//===----------------------------------------------------------------------===//
13
Amara Emerson836b0f42017-05-10 09:42:49 +000014#include "llvm/CodeGen/ExpandReductions.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000015#include "llvm/Analysis/TargetTransformInfo.h"
Amara Emerson836b0f42017-05-10 09:42:49 +000016#include "llvm/CodeGen/Passes.h"
17#include "llvm/IR/Function.h"
18#include "llvm/IR/IRBuilder.h"
19#include "llvm/IR/InstIterator.h"
Amara Emerson836b0f42017-05-10 09:42:49 +000020#include "llvm/IR/IntrinsicInst.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000021#include "llvm/IR/Intrinsics.h"
Amara Emerson836b0f42017-05-10 09:42:49 +000022#include "llvm/IR/Module.h"
Amara Emerson836b0f42017-05-10 09:42:49 +000023#include "llvm/Pass.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000024#include "llvm/Transforms/Utils/LoopUtils.h"
Amara Emerson836b0f42017-05-10 09:42:49 +000025
26using namespace llvm;
27
28namespace {
29
30unsigned getOpcode(Intrinsic::ID ID) {
31 switch (ID) {
Sander de Smalencbeb5632019-06-11 08:22:10 +000032 case Intrinsic::experimental_vector_reduce_v2_fadd:
Amara Emerson836b0f42017-05-10 09:42:49 +000033 return Instruction::FAdd;
Sander de Smalencbeb5632019-06-11 08:22:10 +000034 case Intrinsic::experimental_vector_reduce_v2_fmul:
Amara Emerson836b0f42017-05-10 09:42:49 +000035 return Instruction::FMul;
36 case Intrinsic::experimental_vector_reduce_add:
37 return Instruction::Add;
38 case Intrinsic::experimental_vector_reduce_mul:
39 return Instruction::Mul;
40 case Intrinsic::experimental_vector_reduce_and:
41 return Instruction::And;
42 case Intrinsic::experimental_vector_reduce_or:
43 return Instruction::Or;
44 case Intrinsic::experimental_vector_reduce_xor:
45 return Instruction::Xor;
46 case Intrinsic::experimental_vector_reduce_smax:
47 case Intrinsic::experimental_vector_reduce_smin:
48 case Intrinsic::experimental_vector_reduce_umax:
49 case Intrinsic::experimental_vector_reduce_umin:
50 return Instruction::ICmp;
51 case Intrinsic::experimental_vector_reduce_fmax:
52 case Intrinsic::experimental_vector_reduce_fmin:
53 return Instruction::FCmp;
54 default:
55 llvm_unreachable("Unexpected ID");
56 }
57}
58
59RecurrenceDescriptor::MinMaxRecurrenceKind getMRK(Intrinsic::ID ID) {
60 switch (ID) {
61 case Intrinsic::experimental_vector_reduce_smax:
62 return RecurrenceDescriptor::MRK_SIntMax;
63 case Intrinsic::experimental_vector_reduce_smin:
64 return RecurrenceDescriptor::MRK_SIntMin;
65 case Intrinsic::experimental_vector_reduce_umax:
66 return RecurrenceDescriptor::MRK_UIntMax;
67 case Intrinsic::experimental_vector_reduce_umin:
68 return RecurrenceDescriptor::MRK_UIntMin;
69 case Intrinsic::experimental_vector_reduce_fmax:
70 return RecurrenceDescriptor::MRK_FloatMax;
71 case Intrinsic::experimental_vector_reduce_fmin:
72 return RecurrenceDescriptor::MRK_FloatMin;
73 default:
74 return RecurrenceDescriptor::MRK_Invalid;
75 }
76}
77
78bool expandReductions(Function &F, const TargetTransformInfo *TTI) {
79 bool Changed = false;
Simon Pilgrim23c21822018-04-09 15:44:20 +000080 SmallVector<IntrinsicInst *, 4> Worklist;
Amara Emerson836b0f42017-05-10 09:42:49 +000081 for (inst_iterator I = inst_begin(F), E = inst_end(F); I != E; ++I)
82 if (auto II = dyn_cast<IntrinsicInst>(&*I))
83 Worklist.push_back(II);
84
85 for (auto *II : Worklist) {
Sander de Smalencbeb5632019-06-11 08:22:10 +000086 if (!TTI->shouldExpandReduction(II))
87 continue;
88
89 FastMathFlags FMF =
90 isa<FPMathOperator>(II) ? II->getFastMathFlags() : FastMathFlags{};
91 Intrinsic::ID ID = II->getIntrinsicID();
92 RecurrenceDescriptor::MinMaxRecurrenceKind MRK = getMRK(ID);
93
94 Value *Rdx = nullptr;
Amara Emerson836b0f42017-05-10 09:42:49 +000095 IRBuilder<> Builder(II);
Sander de Smalencbeb5632019-06-11 08:22:10 +000096 IRBuilder<>::FastMathFlagGuard FMFGuard(Builder);
97 Builder.setFastMathFlags(FMF);
Amara Emerson836b0f42017-05-10 09:42:49 +000098 switch (ID) {
Sander de Smalencbeb5632019-06-11 08:22:10 +000099 case Intrinsic::experimental_vector_reduce_v2_fadd:
100 case Intrinsic::experimental_vector_reduce_v2_fmul: {
Amara Emerson836b0f42017-05-10 09:42:49 +0000101 // FMFs must be attached to the call, otherwise it's an ordered reduction
Simon Pilgrim23c21822018-04-09 15:44:20 +0000102 // and it can't be handled by generating a shuffle sequence.
Sander de Smalencbeb5632019-06-11 08:22:10 +0000103 Value *Acc = II->getArgOperand(0);
104 Value *Vec = II->getArgOperand(1);
105 if (!FMF.allowReassoc())
106 Rdx = getOrderedReduction(Builder, Acc, Vec, getOpcode(ID), MRK);
107 else {
108 Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
109 Rdx = Builder.CreateBinOp((Instruction::BinaryOps)getOpcode(ID),
110 Acc, Rdx, "bin.rdx");
111 }
112 } break;
Amara Emerson836b0f42017-05-10 09:42:49 +0000113 case Intrinsic::experimental_vector_reduce_add:
114 case Intrinsic::experimental_vector_reduce_mul:
115 case Intrinsic::experimental_vector_reduce_and:
116 case Intrinsic::experimental_vector_reduce_or:
117 case Intrinsic::experimental_vector_reduce_xor:
118 case Intrinsic::experimental_vector_reduce_smax:
119 case Intrinsic::experimental_vector_reduce_smin:
120 case Intrinsic::experimental_vector_reduce_umax:
121 case Intrinsic::experimental_vector_reduce_umin:
122 case Intrinsic::experimental_vector_reduce_fmax:
Sander de Smalencbeb5632019-06-11 08:22:10 +0000123 case Intrinsic::experimental_vector_reduce_fmin: {
124 Value *Vec = II->getArgOperand(0);
125 Rdx = getShuffleReduction(Builder, Vec, getOpcode(ID), MRK);
126 } break;
Amara Emerson836b0f42017-05-10 09:42:49 +0000127 default:
128 continue;
129 }
Amara Emerson836b0f42017-05-10 09:42:49 +0000130 II->replaceAllUsesWith(Rdx);
131 II->eraseFromParent();
132 Changed = true;
133 }
134 return Changed;
135}
136
137class ExpandReductions : public FunctionPass {
138public:
139 static char ID;
140 ExpandReductions() : FunctionPass(ID) {
141 initializeExpandReductionsPass(*PassRegistry::getPassRegistry());
142 }
143
144 bool runOnFunction(Function &F) override {
145 const auto *TTI =&getAnalysis<TargetTransformInfoWrapperPass>().getTTI(F);
146 return expandReductions(F, TTI);
147 }
148
149 void getAnalysisUsage(AnalysisUsage &AU) const override {
150 AU.addRequired<TargetTransformInfoWrapperPass>();
151 AU.setPreservesCFG();
152 }
153};
154}
155
156char ExpandReductions::ID;
157INITIALIZE_PASS_BEGIN(ExpandReductions, "expand-reductions",
158 "Expand reduction intrinsics", false, false)
159INITIALIZE_PASS_DEPENDENCY(TargetTransformInfoWrapperPass)
160INITIALIZE_PASS_END(ExpandReductions, "expand-reductions",
161 "Expand reduction intrinsics", false, false)
162
163FunctionPass *llvm::createExpandReductionsPass() {
164 return new ExpandReductions();
165}
166
167PreservedAnalyses ExpandReductionsPass::run(Function &F,
168 FunctionAnalysisManager &AM) {
169 const auto &TTI = AM.getResult<TargetIRAnalysis>(F);
170 if (!expandReductions(F, &TTI))
171 return PreservedAnalyses::all();
172 PreservedAnalyses PA;
173 PA.preserveSet<CFGAnalyses>();
174 return PA;
175}