blob: d0967c102149290cf074312e42592f967c5c35b2 [file] [log] [blame]
Sanjay Patel8f200112017-04-10 23:26:31 +00001; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
3
4; FIXME: add (sext i1 X), 1 -> zext (not i1 X)
5
6define i32 @sext_inc(i1 zeroext %x) nounwind {
7; CHECK-LABEL: sext_inc:
8; CHECK: # BB#0:
9; CHECK-NEXT: movzbl %dil, %ecx
10; CHECK-NEXT: movl $1, %eax
11; CHECK-NEXT: subl %ecx, %eax
12; CHECK-NEXT: retq
13 %ext = sext i1 %x to i32
14 %add = add i32 %ext, 1
15 ret i32 %add
16}
17
18; FIXME: add (sext i1 X), 1 -> zext (not i1 X)
19
20define <4 x i32> @sext_inc_vec(<4 x i1> %x) nounwind {
21; CHECK-LABEL: sext_inc_vec:
22; CHECK: # BB#0:
23; CHECK-NEXT: pslld $31, %xmm0
24; CHECK-NEXT: psrad $31, %xmm0
25; CHECK-NEXT: paddd {{.*}}(%rip), %xmm0
26; CHECK-NEXT: retq
27 %ext = sext <4 x i1> %x to <4 x i32>
28 %add = add <4 x i32> %ext, <i32 1, i32 1, i32 1, i32 1>
29 ret <4 x i32> %add
30}
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