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Andrew Trick87255e32012-07-07 04:00:00 +00001//===- CodeGenSchedule.h - Scheduling Machine Models ------------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Alp Tokercb402912014-01-24 17:20:08 +000010// This file defines structures to encapsulate the machine model as described in
Andrew Trick87255e32012-07-07 04:00:00 +000011// the target description.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +000015#ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
16#define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H
Andrew Trick87255e32012-07-07 04:00:00 +000017
Andrew Trick87255e32012-07-07 04:00:00 +000018#include "llvm/ADT/DenseMap.h"
19#include "llvm/ADT/StringMap.h"
Chandler Carruth91d19d82012-12-04 10:37:14 +000020#include "llvm/Support/ErrorHandling.h"
21#include "llvm/TableGen/Record.h"
James Molloyf1653b52014-06-17 13:10:38 +000022#include "llvm/TableGen/SetTheory.h"
Andrew Trick87255e32012-07-07 04:00:00 +000023
24namespace llvm {
25
26class CodeGenTarget;
Andrew Trick76686492012-09-15 00:19:57 +000027class CodeGenSchedModels;
28class CodeGenInstruction;
Andrew Trick87255e32012-07-07 04:00:00 +000029
Andrew Trick76686492012-09-15 00:19:57 +000030typedef std::vector<Record*> RecVec;
31typedef std::vector<Record*>::const_iterator RecIter;
32
33typedef std::vector<unsigned> IdxVec;
34typedef std::vector<unsigned>::const_iterator IdxIter;
35
36void splitSchedReadWrites(const RecVec &RWDefs,
37 RecVec &WriteDefs, RecVec &ReadDefs);
38
39/// We have two kinds of SchedReadWrites. Explicitly defined and inferred
40/// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41/// may not be empty. TheDef is null for inferred sequences, and Sequence must
42/// be nonempty.
43///
44/// IsVariadic controls whether the variants are expanded into multiple operands
45/// or a sequence of writes on one operand.
46struct CodeGenSchedRW {
Andrew Trickda984b12012-10-03 23:06:28 +000047 unsigned Index;
Andrew Trick76686492012-09-15 00:19:57 +000048 std::string Name;
49 Record *TheDef;
Andrew Trickda984b12012-10-03 23:06:28 +000050 bool IsRead;
Andrew Trick9257b8f2012-09-22 02:24:21 +000051 bool IsAlias;
Andrew Trick76686492012-09-15 00:19:57 +000052 bool HasVariants;
53 bool IsVariadic;
54 bool IsSequence;
55 IdxVec Sequence;
Andrew Trick9257b8f2012-09-22 02:24:21 +000056 RecVec Aliases;
Andrew Trick76686492012-09-15 00:19:57 +000057
Richard Smitha7bb16a2012-12-20 01:05:39 +000058 CodeGenSchedRW()
Craig Topperada08572014-04-16 04:21:27 +000059 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false),
Richard Smitha7bb16a2012-12-20 01:05:39 +000060 HasVariants(false), IsVariadic(false), IsSequence(false) {}
61 CodeGenSchedRW(unsigned Idx, Record *Def)
62 : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) {
Andrew Trick76686492012-09-15 00:19:57 +000063 Name = Def->getName();
Andrew Trickda984b12012-10-03 23:06:28 +000064 IsRead = Def->isSubClassOf("SchedRead");
Andrew Trick76686492012-09-15 00:19:57 +000065 HasVariants = Def->isSubClassOf("SchedVariant");
66 if (HasVariants)
67 IsVariadic = Def->getValueAsBit("Variadic");
68
69 // Read records don't currently have sequences, but it can be easily
70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
71 // (but no record).
72 IsSequence = Def->isSubClassOf("WriteSequence");
73 }
74
Benjamin Kramere1761952015-10-24 12:46:49 +000075 CodeGenSchedRW(unsigned Idx, bool Read, ArrayRef<unsigned> Seq,
Richard Smitha7bb16a2012-12-20 01:05:39 +000076 const std::string &Name)
Benjamin Kramere1761952015-10-24 12:46:49 +000077 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false),
78 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
Andrew Trick76686492012-09-15 00:19:57 +000079 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
80 }
81
82 bool isValid() const {
83 assert((!HasVariants || TheDef) && "Variant write needs record def");
84 assert((!IsVariadic || HasVariants) && "Variadic write needs variants");
85 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
86 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty");
Andrew Trick9257b8f2012-09-22 02:24:21 +000087 assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases");
Andrew Trick76686492012-09-15 00:19:57 +000088 return TheDef || !Sequence.empty();
89 }
90
91#ifndef NDEBUG
92 void dump() const;
93#endif
94};
95
Andrew Trickea28dbd2012-09-18 04:03:30 +000096/// Represent a transition between SchedClasses induced by SchedVariant.
Andrew Trick33401e82012-09-15 00:19:59 +000097struct CodeGenSchedTransition {
98 unsigned ToClassIdx;
99 IdxVec ProcIndices;
100 RecVec PredTerm;
101};
102
Andrew Trick76686492012-09-15 00:19:57 +0000103/// Scheduling class.
104///
105/// Each instruction description will be mapped to a scheduling class. There are
106/// four types of classes:
107///
108/// 1) An explicitly defined itinerary class with ItinClassDef set.
109/// Writes and ReadDefs are empty. ProcIndices contains 0 for any processor.
110///
111/// 2) An implied class with a list of SchedWrites and SchedReads that are
112/// defined in an instruction definition and which are common across all
113/// subtargets. ProcIndices contains 0 for any processor.
114///
115/// 3) An implied class with a list of InstRW records that map instructions to
116/// SchedWrites and SchedReads per-processor. InstrClassMap should map the same
117/// instructions to this class. ProcIndices contains all the processors that
118/// provided InstrRW records for this class. ItinClassDef or Writes/Reads may
119/// still be defined for processors with no InstRW entry.
120///
121/// 4) An inferred class represents a variant of another class that may be
122/// resolved at runtime. ProcIndices contains the set of processors that may
123/// require the class. ProcIndices are propagated through SchedClasses as
124/// variants are expanded. Multiple SchedClasses may be inferred from an
125/// itinerary class. Each inherits the processor index from the ItinRW record
126/// that mapped the itinerary class to the variant Writes or Reads.
Andrew Trick87255e32012-07-07 04:00:00 +0000127struct CodeGenSchedClass {
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000128 unsigned Index;
Andrew Trick87255e32012-07-07 04:00:00 +0000129 std::string Name;
Andrew Trick87255e32012-07-07 04:00:00 +0000130 Record *ItinClassDef;
131
Andrew Trick76686492012-09-15 00:19:57 +0000132 IdxVec Writes;
133 IdxVec Reads;
134 // Sorted list of ProcIdx, where ProcIdx==0 implies any processor.
135 IdxVec ProcIndices;
136
Andrew Trick33401e82012-09-15 00:19:59 +0000137 std::vector<CodeGenSchedTransition> Transitions;
138
Andrew Trick9257b8f2012-09-22 02:24:21 +0000139 // InstRW records associated with this class. These records may refer to an
140 // Instruction no longer mapped to this class by InstrClassMap. These
141 // Instructions should be ignored by this class because they have been split
142 // off to join another inferred class.
Andrew Trick76686492012-09-15 00:19:57 +0000143 RecVec InstRWs;
144
Craig Topperada08572014-04-16 04:21:27 +0000145 CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {}
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000146
Benjamin Kramere1761952015-10-24 12:46:49 +0000147 bool isKeyEqual(Record *IC, ArrayRef<unsigned> W, ArrayRef<unsigned> R) {
148 return ItinClassDef == IC && makeArrayRef(Writes) == W &&
149 makeArrayRef(Reads) == R;
Andrew Trick87255e32012-07-07 04:00:00 +0000150 }
Andrew Trick76686492012-09-15 00:19:57 +0000151
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000152 // Is this class generated from a variants if existing classes? Instructions
153 // are never mapped directly to inferred scheduling classes.
154 bool isInferred() const { return !ItinClassDef; }
155
Andrew Trick76686492012-09-15 00:19:57 +0000156#ifndef NDEBUG
157 void dump(const CodeGenSchedModels *SchedModels) const;
158#endif
Andrew Trick87255e32012-07-07 04:00:00 +0000159};
160
161// Processor model.
162//
163// ModelName is a unique name used to name an instantiation of MCSchedModel.
164//
165// ModelDef is NULL for inferred Models. This happens when a processor defines
Alp Tokercb402912014-01-24 17:20:08 +0000166// an itinerary but no machine model. If the processor defines neither a machine
Andrew Trick87255e32012-07-07 04:00:00 +0000167// model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has
168// the special "NoModel" field set to true.
169//
170// ItinsDef always points to a valid record definition, but may point to the
171// default NoItineraries. NoItineraries has an empty list of InstrItinData
172// records.
173//
174// ItinDefList orders this processor's InstrItinData records by SchedClass idx.
175struct CodeGenProcModel {
Andrew Trick76686492012-09-15 00:19:57 +0000176 unsigned Index;
Andrew Trick87255e32012-07-07 04:00:00 +0000177 std::string ModelName;
178 Record *ModelDef;
179 Record *ItinsDef;
180
Andrew Trick76686492012-09-15 00:19:57 +0000181 // Derived members...
Andrew Trick87255e32012-07-07 04:00:00 +0000182
Andrew Trick76686492012-09-15 00:19:57 +0000183 // Array of InstrItinData records indexed by a CodeGenSchedClass index.
184 // This list is empty if the Processor has no value for Itineraries.
185 // Initialized by collectProcItins().
186 RecVec ItinDefList;
187
188 // Map itinerary classes to per-operand resources.
189 // This list is empty if no ItinRW refers to this Processor.
190 RecVec ItinRWDefs;
191
Andrew Trick1e46d482012-09-15 00:20:02 +0000192 // All read/write resources associated with this processor.
193 RecVec WriteResDefs;
194 RecVec ReadAdvanceDefs;
195
196 // Per-operand machine model resources associated with this processor.
197 RecVec ProcResourceDefs;
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000198 RecVec ProcResGroupDefs;
Andrew Trick1e46d482012-09-15 00:20:02 +0000199
Andrew Trick76686492012-09-15 00:19:57 +0000200 CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef,
201 Record *IDef) :
202 Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {}
203
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000204 bool hasItineraries() const {
205 return !ItinsDef->getValueAsListOfDefs("IID").empty();
206 }
207
Andrew Trick1e46d482012-09-15 00:20:02 +0000208 bool hasInstrSchedModel() const {
209 return !WriteResDefs.empty() || !ItinRWDefs.empty();
210 }
211
212 unsigned getProcResourceIdx(Record *PRDef) const;
213
Andrew Trick76686492012-09-15 00:19:57 +0000214#ifndef NDEBUG
215 void dump() const;
216#endif
Andrew Trick87255e32012-07-07 04:00:00 +0000217};
218
Andrew Trick76686492012-09-15 00:19:57 +0000219/// Top level container for machine model data.
Andrew Trick87255e32012-07-07 04:00:00 +0000220class CodeGenSchedModels {
221 RecordKeeper &Records;
222 const CodeGenTarget &Target;
223
Andrew Trick9e1deb62012-10-03 23:06:32 +0000224 // Map dag expressions to Instruction lists.
225 SetTheory Sets;
226
Andrew Trick76686492012-09-15 00:19:57 +0000227 // List of unique processor models.
228 std::vector<CodeGenProcModel> ProcModels;
229
230 // Map Processor's MachineModel or ProcItin to a CodeGenProcModel index.
231 typedef DenseMap<Record*, unsigned> ProcModelMapTy;
232 ProcModelMapTy ProcModelMap;
233
234 // Per-operand SchedReadWrite types.
235 std::vector<CodeGenSchedRW> SchedWrites;
236 std::vector<CodeGenSchedRW> SchedReads;
237
Andrew Trick87255e32012-07-07 04:00:00 +0000238 // List of unique SchedClasses.
239 std::vector<CodeGenSchedClass> SchedClasses;
240
Andrew Trick76686492012-09-15 00:19:57 +0000241 // Any inferred SchedClass has an index greater than NumInstrSchedClassses.
242 unsigned NumInstrSchedClasses;
Andrew Trick87255e32012-07-07 04:00:00 +0000243
Matthias Braun6b1fd9a2016-06-21 03:24:03 +0000244 RecVec ProcResourceDefs;
245 RecVec ProcResGroups;
246
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000247 // Map each instruction to its unique SchedClass index considering the
248 // combination of it's itinerary class, SchedRW list, and InstRW records.
Andrew Trick76686492012-09-15 00:19:57 +0000249 typedef DenseMap<Record*, unsigned> InstClassMapTy;
250 InstClassMapTy InstrClassMap;
Andrew Trick87255e32012-07-07 04:00:00 +0000251
252public:
253 CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT);
254
Jim Grosbachaf814452014-04-18 02:09:04 +0000255 // iterator access to the scheduling classes.
256 typedef std::vector<CodeGenSchedClass>::iterator class_iterator;
257 typedef std::vector<CodeGenSchedClass>::const_iterator const_class_iterator;
258 class_iterator classes_begin() { return SchedClasses.begin(); }
259 const_class_iterator classes_begin() const { return SchedClasses.begin(); }
260 class_iterator classes_end() { return SchedClasses.end(); }
261 const_class_iterator classes_end() const { return SchedClasses.end(); }
262 iterator_range<class_iterator> classes() {
Craig Topper15576e12015-12-06 05:08:07 +0000263 return make_range(classes_begin(), classes_end());
Jim Grosbachaf814452014-04-18 02:09:04 +0000264 }
265 iterator_range<const_class_iterator> classes() const {
Craig Topper15576e12015-12-06 05:08:07 +0000266 return make_range(classes_begin(), classes_end());
Jim Grosbachaf814452014-04-18 02:09:04 +0000267 }
268 iterator_range<class_iterator> explicit_classes() {
Craig Topper15576e12015-12-06 05:08:07 +0000269 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
Jim Grosbachaf814452014-04-18 02:09:04 +0000270 }
271 iterator_range<const_class_iterator> explicit_classes() const {
Craig Topper15576e12015-12-06 05:08:07 +0000272 return make_range(classes_begin(), classes_begin() + NumInstrSchedClasses);
Jim Grosbachaf814452014-04-18 02:09:04 +0000273 }
274
Andrew Trick76686492012-09-15 00:19:57 +0000275 Record *getModelOrItinDef(Record *ProcDef) const {
276 Record *ModelDef = ProcDef->getValueAsDef("SchedModel");
277 Record *ItinsDef = ProcDef->getValueAsDef("ProcItin");
278 if (!ItinsDef->getValueAsListOfDefs("IID").empty()) {
279 assert(ModelDef->getValueAsBit("NoModel")
280 && "Itineraries must be defined within SchedMachineModel");
281 return ItinsDef;
282 }
283 return ModelDef;
284 }
285
286 const CodeGenProcModel &getModelForProc(Record *ProcDef) const {
287 Record *ModelDef = getModelOrItinDef(ProcDef);
288 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
289 assert(I != ProcModelMap.end() && "missing machine model");
290 return ProcModels[I->second];
291 }
292
Andrew Trick40c4f382013-06-15 04:50:06 +0000293 CodeGenProcModel &getProcModel(Record *ModelDef) {
Andrew Trick76686492012-09-15 00:19:57 +0000294 ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef);
295 assert(I != ProcModelMap.end() && "missing machine model");
296 return ProcModels[I->second];
297 }
Andrew Trick40c4f382013-06-15 04:50:06 +0000298 const CodeGenProcModel &getProcModel(Record *ModelDef) const {
299 return const_cast<CodeGenSchedModels*>(this)->getProcModel(ModelDef);
300 }
Andrew Trick76686492012-09-15 00:19:57 +0000301
302 // Iterate over the unique processor models.
303 typedef std::vector<CodeGenProcModel>::const_iterator ProcIter;
304 ProcIter procModelBegin() const { return ProcModels.begin(); }
305 ProcIter procModelEnd() const { return ProcModels.end(); }
Craig Topper29c55dcb2016-02-13 06:03:32 +0000306 ArrayRef<CodeGenProcModel> procModels() const { return ProcModels; }
Andrew Trick76686492012-09-15 00:19:57 +0000307
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000308 // Return true if any processors have itineraries.
309 bool hasItineraries() const;
310
Andrew Trick76686492012-09-15 00:19:57 +0000311 // Get a SchedWrite from its index.
312 const CodeGenSchedRW &getSchedWrite(unsigned Idx) const {
313 assert(Idx < SchedWrites.size() && "bad SchedWrite index");
314 assert(SchedWrites[Idx].isValid() && "invalid SchedWrite");
315 return SchedWrites[Idx];
316 }
317 // Get a SchedWrite from its index.
318 const CodeGenSchedRW &getSchedRead(unsigned Idx) const {
319 assert(Idx < SchedReads.size() && "bad SchedRead index");
320 assert(SchedReads[Idx].isValid() && "invalid SchedRead");
321 return SchedReads[Idx];
322 }
323
324 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const {
325 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx);
326 }
Andrew Trickda984b12012-10-03 23:06:28 +0000327 CodeGenSchedRW &getSchedRW(Record *Def) {
Andrew Trick9257b8f2012-09-22 02:24:21 +0000328 bool IsRead = Def->isSubClassOf("SchedRead");
Andrew Trickda984b12012-10-03 23:06:28 +0000329 unsigned Idx = getSchedRWIdx(Def, IsRead);
Andrew Trick9257b8f2012-09-22 02:24:21 +0000330 return const_cast<CodeGenSchedRW&>(
331 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx));
332 }
Andrew Trickda984b12012-10-03 23:06:28 +0000333 const CodeGenSchedRW &getSchedRW(Record*Def) const {
334 return const_cast<CodeGenSchedModels&>(*this).getSchedRW(Def);
Andrew Trick9257b8f2012-09-22 02:24:21 +0000335 }
Andrew Trick76686492012-09-15 00:19:57 +0000336
337 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
338
Andrew Trickcfe222c2012-09-19 04:43:19 +0000339 // Return true if the given write record is referenced by a ReadAdvance.
340 bool hasReadOfWrite(Record *WriteDef) const;
341
Andrew Trick87255e32012-07-07 04:00:00 +0000342 // Get a SchedClass from its index.
Andrew Trick76686492012-09-15 00:19:57 +0000343 CodeGenSchedClass &getSchedClass(unsigned Idx) {
344 assert(Idx < SchedClasses.size() && "bad SchedClass index");
345 return SchedClasses[Idx];
346 }
347 const CodeGenSchedClass &getSchedClass(unsigned Idx) const {
Andrew Trick87255e32012-07-07 04:00:00 +0000348 assert(Idx < SchedClasses.size() && "bad SchedClass index");
349 return SchedClasses[Idx];
350 }
351
Andrew Trick76686492012-09-15 00:19:57 +0000352 // Get the SchedClass index for an instruction. Instructions with no
353 // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0
354 // for NoItinerary.
355 unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const;
356
Andrew Trick76686492012-09-15 00:19:57 +0000357 typedef std::vector<CodeGenSchedClass>::const_iterator SchedClassIter;
358 SchedClassIter schedClassBegin() const { return SchedClasses.begin(); }
359 SchedClassIter schedClassEnd() const { return SchedClasses.end(); }
Craig Topper29c55dcb2016-02-13 06:03:32 +0000360 ArrayRef<CodeGenSchedClass> schedClasses() const { return SchedClasses; }
Andrew Trick87255e32012-07-07 04:00:00 +0000361
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000362 unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; }
363
Andrew Trick76686492012-09-15 00:19:57 +0000364 void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const;
365 void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const;
Andrew Trick33401e82012-09-15 00:19:59 +0000366 void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const;
Andrew Trickda984b12012-10-03 23:06:28 +0000367 void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead,
368 const CodeGenProcModel &ProcModel) const;
Andrew Trick76686492012-09-15 00:19:57 +0000369
Benjamin Kramere1761952015-10-24 12:46:49 +0000370 unsigned addSchedClass(Record *ItinDef, ArrayRef<unsigned> OperWrites,
371 ArrayRef<unsigned> OperReads,
372 ArrayRef<unsigned> ProcIndices);
Andrew Trick76686492012-09-15 00:19:57 +0000373
374 unsigned findOrInsertRW(ArrayRef<unsigned> Seq, bool IsRead);
375
Benjamin Kramere1761952015-10-24 12:46:49 +0000376 unsigned findSchedClassIdx(Record *ItinClassDef, ArrayRef<unsigned> Writes,
377 ArrayRef<unsigned> Reads) const;
Andrew Trick87255e32012-07-07 04:00:00 +0000378
Andrew Trick1e46d482012-09-15 00:20:02 +0000379 Record *findProcResUnits(Record *ProcResKind,
380 const CodeGenProcModel &PM) const;
381
Andrew Trick87255e32012-07-07 04:00:00 +0000382private:
Andrew Trick76686492012-09-15 00:19:57 +0000383 void collectProcModels();
Andrew Trick87255e32012-07-07 04:00:00 +0000384
385 // Initialize a new processor model if it is unique.
386 void addProcModel(Record *ProcDef);
387
Andrew Trick76686492012-09-15 00:19:57 +0000388 void collectSchedRW();
389
Benjamin Kramere1761952015-10-24 12:46:49 +0000390 std::string genRWName(ArrayRef<unsigned> Seq, bool IsRead);
391 unsigned findRWForSequence(ArrayRef<unsigned> Seq, bool IsRead);
Andrew Trick76686492012-09-15 00:19:57 +0000392
393 void collectSchedClasses();
394
Andrew Trickbf8a28d2013-03-16 18:58:55 +0000395 std::string createSchedClassName(Record *ItinClassDef,
Benjamin Kramere1761952015-10-24 12:46:49 +0000396 ArrayRef<unsigned> OperWrites,
397 ArrayRef<unsigned> OperReads);
Andrew Trick76686492012-09-15 00:19:57 +0000398 std::string createSchedClassName(const RecVec &InstDefs);
399 void createInstRWClass(Record *InstRWDef);
400
401 void collectProcItins();
402
403 void collectProcItinRW();
Andrew Trick33401e82012-09-15 00:19:59 +0000404
405 void inferSchedClasses();
406
Matthias Braun17cb5792016-03-01 20:03:21 +0000407 void checkCompleteness();
408
Benjamin Kramere1761952015-10-24 12:46:49 +0000409 void inferFromRW(ArrayRef<unsigned> OperWrites, ArrayRef<unsigned> OperReads,
410 unsigned FromClassIdx, ArrayRef<unsigned> ProcIndices);
Andrew Trick33401e82012-09-15 00:19:59 +0000411 void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx);
412 void inferFromInstRWs(unsigned SCIdx);
Andrew Trick1e46d482012-09-15 00:20:02 +0000413
Andrew Trickcf398b22013-04-23 23:45:14 +0000414 bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM);
415 void verifyProcResourceGroups(CodeGenProcModel &PM);
416
Andrew Trick1e46d482012-09-15 00:20:02 +0000417 void collectProcResources();
418
419 void collectItinProcResources(Record *ItinClassDef);
420
Andrew Trickd0b9c442012-10-10 05:43:13 +0000421 void collectRWResources(unsigned RWIdx, bool IsRead,
Benjamin Kramere1761952015-10-24 12:46:49 +0000422 ArrayRef<unsigned> ProcIndices);
Andrew Trickd0b9c442012-10-10 05:43:13 +0000423
Benjamin Kramere1761952015-10-24 12:46:49 +0000424 void collectRWResources(ArrayRef<unsigned> Writes, ArrayRef<unsigned> Reads,
425 ArrayRef<unsigned> ProcIndices);
Andrew Trick1e46d482012-09-15 00:20:02 +0000426
427 void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM);
428
429 void addWriteRes(Record *ProcWriteResDef, unsigned PIdx);
430
431 void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx);
Andrew Trick87255e32012-07-07 04:00:00 +0000432};
433
434} // namespace llvm
435
436#endif