Gitiles
Code Review Sign In
gerrit-public.fairphone.software / toolchain / llvm-project / 6bddb8c3a57ad79849f97c5775479e00bafb0c7e / . / llvm / lib / Target / X86 / X86InstrAVX512.td
blob: c2a95849b6a8c0f021fc39b7866a0fd5cb05327d [file] [log] [blame]
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]1// Group template arguments that can be derived from the vector type (EltNum x
2// EltVT). These are things like the register class for the writemask, etc.
3// The idea is to pass one of these as the template argument rather than the
4// individual arguments.
5class X86VectorVTInfo<int NumElts, ValueType EltVT, RegisterClass rc,
6 string suffix = ""> {
7 RegisterClass RC = rc;
8
9 // Corresponding mask register class.
10 RegisterClass KRC = !cast<RegisterClass>("VK" # NumElts);
11
12 // Corresponding write-mask register class.
13 RegisterClass KRCWM = !cast<RegisterClass>("VK" # NumElts # "WM");
14
15 // The GPR register class that can hold the write mask. Use GR8 for fewer
16 // than 8 elements. Use shift-right and equal to work around the lack of
17 // !lt in tablegen.
18 RegisterClass MRC =
19 !cast<RegisterClass>("GR" #
20 !if (!eq (!srl(NumElts, 3), 0), 8, NumElts));
21
22 // Suffix used in the instruction mnemonic.
23 string Suffix = suffix;
24
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]25 string VTName = "v" # NumElts # EltVT;
26
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]27 // The vector VT.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]28 ValueType VT = !cast<ValueType>(VTName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]29
30 string EltTypeName = !cast<string>(EltVT);
31 // Size of the element type in bits, e.g. 32 for v16i32.
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]32 string EltSizeName = !subst("i", "", !subst("f", "", EltTypeName));
33 int EltSize = EltVT.Size;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]34
35 // "i" for integer types and "f" for floating-point types
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]36 string TypeVariantName = !subst(EltSizeName, "", EltTypeName);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]37
38 // Size of RC in bits, e.g. 512 for VR512.
39 int Size = VT.Size;
40
41 // The corresponding memory operand, e.g. i512mem for VR512.
42 X86MemOperand MemOp = !cast<X86MemOperand>(TypeVariantName # Size # "mem");
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]43 X86MemOperand ScalarMemOp = !cast<X86MemOperand>(EltVT # "mem");
44
45 // Load patterns
46 // Note: For 128/256-bit integer VT we choose loadv2i64/loadv4i64
47 // due to load promotion during legalization
48 PatFrag LdFrag = !cast<PatFrag>("load" #
49 !if (!eq (TypeVariantName, "i"),
50 !if (!eq (Size, 128), "v2i64",
51 !if (!eq (Size, 256), "v4i64",
52 VTName)), VTName));
53 PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]54
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]55 // Load patterns used for memory operands. We only have this defined in
56 // case of i64 element types for sub-512 integer vectors. For now, keep
57 // MemOpFrag undefined in these cases.
58 PatFrag MemOpFrag =
59 !if (!eq (TypeVariantName, "f"), !cast<PatFrag>("memop" # VTName),
60 !if (!eq (EltTypeName, "i64"), !cast<PatFrag>("memop" # VTName),
61 !if (!eq (VTName, "v16i32"), !cast<PatFrag>("memop" # VTName), ?)));
62
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]63 // The corresponding float type, e.g. v16f32 for v16i32
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]64 // Note: For EltSize < 32, FloatVT is illegal and TableGen
65 // fails to compile, so we choose FloatVT = VT
66 ValueType FloatVT = !cast<ValueType>(
67 !if (!eq (!srl(EltSize,5),0),
68 VTName,
69 !if (!eq(TypeVariantName, "i"),
70 "v" # NumElts # "f" # EltSize,
71 VTName)));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]72
73 // The string to specify embedded broadcast in assembly.
74 string BroadcastStr = "{1to" # NumElts # "}";
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]75
76 SubRegIndex SubRegIdx = !if (!eq (Size, 128), sub_xmm,
77 !if (!eq (Size, 256), sub_ymm, ?));
78
79 Domain ExeDomain = !if (!eq (EltTypeName, "f32"), SSEPackedSingle,
80 !if (!eq (EltTypeName, "f64"), SSEPackedDouble,
81 SSEPackedInt));
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]82}
83
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]84def v64i8_info : X86VectorVTInfo<64, i8, VR512, "b">;
85def v32i16_info : X86VectorVTInfo<32, i16, VR512, "w">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]86def v16i32_info : X86VectorVTInfo<16, i32, VR512, "d">;
87def v8i64_info : X86VectorVTInfo<8, i64, VR512, "q">;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]88def v16f32_info : X86VectorVTInfo<16, f32, VR512, "ps">;
89def v8f64_info : X86VectorVTInfo<8, f64, VR512, "pd">;
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]90
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]91// "x" in v32i8x_info means RC = VR256X
92def v32i8x_info : X86VectorVTInfo<32, i8, VR256X, "b">;
93def v16i16x_info : X86VectorVTInfo<16, i16, VR256X, "w">;
94def v8i32x_info : X86VectorVTInfo<8, i32, VR256X, "d">;
95def v4i64x_info : X86VectorVTInfo<4, i64, VR256X, "q">;
96
97def v16i8x_info : X86VectorVTInfo<16, i8, VR128X, "b">;
98def v8i16x_info : X86VectorVTInfo<8, i16, VR128X, "w">;
99def v4i32x_info : X86VectorVTInfo<4, i32, VR128X, "d">;
100def v2i64x_info : X86VectorVTInfo<2, i64, VR128X, "q">;
101
102class AVX512VLVectorVTInfo<X86VectorVTInfo i512, X86VectorVTInfo i256,
103 X86VectorVTInfo i128> {
104 X86VectorVTInfo info512 = i512;
105 X86VectorVTInfo info256 = i256;
106 X86VectorVTInfo info128 = i128;
107}
108
109def avx512vl_i8_info : AVX512VLVectorVTInfo<v64i8_info, v32i8x_info,
110 v16i8x_info>;
111def avx512vl_i16_info : AVX512VLVectorVTInfo<v32i16_info, v16i16x_info,
112 v8i16x_info>;
113def avx512vl_i32_info : AVX512VLVectorVTInfo<v16i32_info, v8i32x_info,
114 v4i32x_info>;
115def avx512vl_i64_info : AVX512VLVectorVTInfo<v8i64_info, v4i64x_info,
116 v2i64x_info>;
117
118
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]119// Common base class of AVX512_masking and AVX512_masking_3src.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]120multiclass AVX512_masking_common<bits<8> O, Format F, X86VectorVTInfo _,
121 dag Outs,
122 dag Ins, dag MaskingIns, dag ZeroMaskingIns,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]123 string OpcodeStr,
124 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]125 dag RHS, dag MaskingRHS,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]126 string MaskingConstraint = ""> {
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]127 def NAME: AVX512<O, F, Outs, Ins,
128 OpcodeStr#" \t{"#AttSrcAsm#", $dst|"#
129 "$dst, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]130 [(set _.RC:$dst, RHS)]>;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]131
Adam Nemetfa1f7202014-08-07 23:18:18 +0000[diff] [blame]132 // Prefer over VMOV*rrk Pat<>
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]133 let AddedComplexity = 20 in
134 def NAME#k: AVX512<O, F, Outs, MaskingIns,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]135 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}}|"#
136 "$dst {${mask}}, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]137 [(set _.RC:$dst, MaskingRHS)]>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]138 EVEX_K {
139 // In case of the 3src subclass this is overridden with a let.
140 string Constraints = MaskingConstraint;
141 }
Adam Nemet7d498622014-08-07 23:53:38 +0000[diff] [blame]142 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]143 def NAME#kz: AVX512<O, F, Outs, ZeroMaskingIns,
Adam Nemet7d498622014-08-07 23:53:38 +0000[diff] [blame]144 OpcodeStr#" \t{"#AttSrcAsm#", $dst {${mask}} {z}|"#
145 "$dst {${mask}} {z}, "#IntelSrcAsm#"}",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]146 [(set _.RC:$dst,
147 (vselect _.KRCWM:$mask, RHS,
148 (_.VT (bitconvert
Adam Nemet7d498622014-08-07 23:53:38 +0000[diff] [blame]149 (v16i32 immAllZerosV)))))]>,
150 EVEX_KZ;
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]151}
152
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]153// This multiclass generates the unconditional/non-masking, the masking and
154// the zero-masking variant of the instruction. In the masking case, the
155// perserved vector elements come from a new dummy input operand tied to $dst.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]156multiclass AVX512_masking<bits<8> O, Format F, X86VectorVTInfo _,
157 dag Outs, dag Ins, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]158 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]159 dag RHS> :
160 AVX512_masking_common<O, F, _, Outs, Ins,
161 !con((ins _.RC:$src0, _.KRCWM:$mask), Ins),
162 !con((ins _.KRCWM:$mask), Ins),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]163 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]164 (vselect _.KRCWM:$mask, RHS, _.RC:$src0),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]165 "$src0 = $dst">;
166
167// Similar to AVX512_masking but in this case one of the source operands
168// ($src1) is already tied to $dst so we just use that for the preserved
169// vector elements. NOTE that the NonTiedIns (the ins dag) should exclude
170// $src1.
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]171multiclass AVX512_masking_3src<bits<8> O, Format F, X86VectorVTInfo _,
172 dag Outs, dag NonTiedIns, string OpcodeStr,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]173 string AttSrcAsm, string IntelSrcAsm,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]174 dag RHS> :
175 AVX512_masking_common<O, F, _, Outs,
176 !con((ins _.RC:$src1), NonTiedIns),
177 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
178 !con((ins _.RC:$src1, _.KRCWM:$mask), NonTiedIns),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]179 OpcodeStr, AttSrcAsm, IntelSrcAsm, RHS,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]180 (vselect _.KRCWM:$mask, RHS, _.RC:$src1)>;
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]181
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]182// Bitcasts between 512-bit vector types. Return the original type since
183// no instruction is needed for the conversion
184let Predicates = [HasAVX512] in {
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]185 def : Pat<(v8f64 (bitconvert (v8i64 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]186 def : Pat<(v8f64 (bitconvert (v16i32 VR512:$src))), (v8f64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]187 def : Pat<(v8f64 (bitconvert (v32i16 VR512:$src))), (v8f64 VR512:$src)>;
188 def : Pat<(v8f64 (bitconvert (v64i8 VR512:$src))), (v8f64 VR512:$src)>;
189 def : Pat<(v8f64 (bitconvert (v16f32 VR512:$src))), (v8f64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]190 def : Pat<(v16f32 (bitconvert (v8i64 VR512:$src))), (v16f32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]191 def : Pat<(v16f32 (bitconvert (v16i32 VR512:$src))), (v16f32 VR512:$src)>;
192 def : Pat<(v16f32 (bitconvert (v32i16 VR512:$src))), (v16f32 VR512:$src)>;
193 def : Pat<(v16f32 (bitconvert (v64i8 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]194 def : Pat<(v16f32 (bitconvert (v8f64 VR512:$src))), (v16f32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]195 def : Pat<(v8i64 (bitconvert (v16i32 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]196 def : Pat<(v8i64 (bitconvert (v32i16 VR512:$src))), (v8i64 VR512:$src)>;
197 def : Pat<(v8i64 (bitconvert (v64i8 VR512:$src))), (v8i64 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]198 def : Pat<(v8i64 (bitconvert (v8f64 VR512:$src))), (v8i64 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]199 def : Pat<(v8i64 (bitconvert (v16f32 VR512:$src))), (v8i64 VR512:$src)>;
200 def : Pat<(v16i32 (bitconvert (v8i64 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovsky40a77142014-08-11 09:59:08 +0000[diff] [blame]201 def : Pat<(v16i32 (bitconvert (v16f32 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]202 def : Pat<(v16i32 (bitconvert (v32i16 VR512:$src))), (v16i32 VR512:$src)>;
203 def : Pat<(v16i32 (bitconvert (v64i8 VR512:$src))), (v16i32 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]204 def : Pat<(v16i32 (bitconvert (v8f64 VR512:$src))), (v16i32 VR512:$src)>;
Robert Khasanovbfa01312014-07-21 14:54:21 +0000[diff] [blame]205 def : Pat<(v32i16 (bitconvert (v8i64 VR512:$src))), (v32i16 VR512:$src)>;
206 def : Pat<(v32i16 (bitconvert (v16i32 VR512:$src))), (v32i16 VR512:$src)>;
207 def : Pat<(v32i16 (bitconvert (v64i8 VR512:$src))), (v32i16 VR512:$src)>;
208 def : Pat<(v32i16 (bitconvert (v8f64 VR512:$src))), (v32i16 VR512:$src)>;
209 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
210 def : Pat<(v32i16 (bitconvert (v16f32 VR512:$src))), (v32i16 VR512:$src)>;
211 def : Pat<(v64i8 (bitconvert (v8i64 VR512:$src))), (v64i8 VR512:$src)>;
212 def : Pat<(v64i8 (bitconvert (v16i32 VR512:$src))), (v64i8 VR512:$src)>;
213 def : Pat<(v64i8 (bitconvert (v32i16 VR512:$src))), (v64i8 VR512:$src)>;
214 def : Pat<(v64i8 (bitconvert (v8f64 VR512:$src))), (v64i8 VR512:$src)>;
215 def : Pat<(v64i8 (bitconvert (v16f32 VR512:$src))), (v64i8 VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]216
217 def : Pat<(v2i64 (bitconvert (v4i32 VR128X:$src))), (v2i64 VR128X:$src)>;
218 def : Pat<(v2i64 (bitconvert (v8i16 VR128X:$src))), (v2i64 VR128X:$src)>;
219 def : Pat<(v2i64 (bitconvert (v16i8 VR128X:$src))), (v2i64 VR128X:$src)>;
220 def : Pat<(v2i64 (bitconvert (v2f64 VR128X:$src))), (v2i64 VR128X:$src)>;
221 def : Pat<(v2i64 (bitconvert (v4f32 VR128X:$src))), (v2i64 VR128X:$src)>;
222 def : Pat<(v4i32 (bitconvert (v2i64 VR128X:$src))), (v4i32 VR128X:$src)>;
223 def : Pat<(v4i32 (bitconvert (v8i16 VR128X:$src))), (v4i32 VR128X:$src)>;
224 def : Pat<(v4i32 (bitconvert (v16i8 VR128X:$src))), (v4i32 VR128X:$src)>;
225 def : Pat<(v4i32 (bitconvert (v2f64 VR128X:$src))), (v4i32 VR128X:$src)>;
226 def : Pat<(v4i32 (bitconvert (v4f32 VR128X:$src))), (v4i32 VR128X:$src)>;
227 def : Pat<(v8i16 (bitconvert (v2i64 VR128X:$src))), (v8i16 VR128X:$src)>;
228 def : Pat<(v8i16 (bitconvert (v4i32 VR128X:$src))), (v8i16 VR128X:$src)>;
229 def : Pat<(v8i16 (bitconvert (v16i8 VR128X:$src))), (v8i16 VR128X:$src)>;
230 def : Pat<(v8i16 (bitconvert (v2f64 VR128X:$src))), (v8i16 VR128X:$src)>;
231 def : Pat<(v8i16 (bitconvert (v4f32 VR128X:$src))), (v8i16 VR128X:$src)>;
232 def : Pat<(v16i8 (bitconvert (v2i64 VR128X:$src))), (v16i8 VR128X:$src)>;
233 def : Pat<(v16i8 (bitconvert (v4i32 VR128X:$src))), (v16i8 VR128X:$src)>;
234 def : Pat<(v16i8 (bitconvert (v8i16 VR128X:$src))), (v16i8 VR128X:$src)>;
235 def : Pat<(v16i8 (bitconvert (v2f64 VR128X:$src))), (v16i8 VR128X:$src)>;
236 def : Pat<(v16i8 (bitconvert (v4f32 VR128X:$src))), (v16i8 VR128X:$src)>;
237 def : Pat<(v4f32 (bitconvert (v2i64 VR128X:$src))), (v4f32 VR128X:$src)>;
238 def : Pat<(v4f32 (bitconvert (v4i32 VR128X:$src))), (v4f32 VR128X:$src)>;
239 def : Pat<(v4f32 (bitconvert (v8i16 VR128X:$src))), (v4f32 VR128X:$src)>;
240 def : Pat<(v4f32 (bitconvert (v16i8 VR128X:$src))), (v4f32 VR128X:$src)>;
241 def : Pat<(v4f32 (bitconvert (v2f64 VR128X:$src))), (v4f32 VR128X:$src)>;
242 def : Pat<(v2f64 (bitconvert (v2i64 VR128X:$src))), (v2f64 VR128X:$src)>;
243 def : Pat<(v2f64 (bitconvert (v4i32 VR128X:$src))), (v2f64 VR128X:$src)>;
244 def : Pat<(v2f64 (bitconvert (v8i16 VR128X:$src))), (v2f64 VR128X:$src)>;
245 def : Pat<(v2f64 (bitconvert (v16i8 VR128X:$src))), (v2f64 VR128X:$src)>;
246 def : Pat<(v2f64 (bitconvert (v4f32 VR128X:$src))), (v2f64 VR128X:$src)>;
247
248// Bitcasts between 256-bit vector types. Return the original type since
249// no instruction is needed for the conversion
250 def : Pat<(v4f64 (bitconvert (v8f32 VR256X:$src))), (v4f64 VR256X:$src)>;
251 def : Pat<(v4f64 (bitconvert (v8i32 VR256X:$src))), (v4f64 VR256X:$src)>;
252 def : Pat<(v4f64 (bitconvert (v4i64 VR256X:$src))), (v4f64 VR256X:$src)>;
253 def : Pat<(v4f64 (bitconvert (v16i16 VR256X:$src))), (v4f64 VR256X:$src)>;
254 def : Pat<(v4f64 (bitconvert (v32i8 VR256X:$src))), (v4f64 VR256X:$src)>;
255 def : Pat<(v8f32 (bitconvert (v8i32 VR256X:$src))), (v8f32 VR256X:$src)>;
256 def : Pat<(v8f32 (bitconvert (v4i64 VR256X:$src))), (v8f32 VR256X:$src)>;
257 def : Pat<(v8f32 (bitconvert (v4f64 VR256X:$src))), (v8f32 VR256X:$src)>;
258 def : Pat<(v8f32 (bitconvert (v32i8 VR256X:$src))), (v8f32 VR256X:$src)>;
259 def : Pat<(v8f32 (bitconvert (v16i16 VR256X:$src))), (v8f32 VR256X:$src)>;
260 def : Pat<(v4i64 (bitconvert (v8f32 VR256X:$src))), (v4i64 VR256X:$src)>;
261 def : Pat<(v4i64 (bitconvert (v8i32 VR256X:$src))), (v4i64 VR256X:$src)>;
262 def : Pat<(v4i64 (bitconvert (v4f64 VR256X:$src))), (v4i64 VR256X:$src)>;
263 def : Pat<(v4i64 (bitconvert (v32i8 VR256X:$src))), (v4i64 VR256X:$src)>;
264 def : Pat<(v4i64 (bitconvert (v16i16 VR256X:$src))), (v4i64 VR256X:$src)>;
265 def : Pat<(v32i8 (bitconvert (v4f64 VR256X:$src))), (v32i8 VR256X:$src)>;
266 def : Pat<(v32i8 (bitconvert (v4i64 VR256X:$src))), (v32i8 VR256X:$src)>;
267 def : Pat<(v32i8 (bitconvert (v8f32 VR256X:$src))), (v32i8 VR256X:$src)>;
268 def : Pat<(v32i8 (bitconvert (v8i32 VR256X:$src))), (v32i8 VR256X:$src)>;
269 def : Pat<(v32i8 (bitconvert (v16i16 VR256X:$src))), (v32i8 VR256X:$src)>;
270 def : Pat<(v8i32 (bitconvert (v32i8 VR256X:$src))), (v8i32 VR256X:$src)>;
271 def : Pat<(v8i32 (bitconvert (v16i16 VR256X:$src))), (v8i32 VR256X:$src)>;
272 def : Pat<(v8i32 (bitconvert (v8f32 VR256X:$src))), (v8i32 VR256X:$src)>;
273 def : Pat<(v8i32 (bitconvert (v4i64 VR256X:$src))), (v8i32 VR256X:$src)>;
274 def : Pat<(v8i32 (bitconvert (v4f64 VR256X:$src))), (v8i32 VR256X:$src)>;
275 def : Pat<(v16i16 (bitconvert (v8f32 VR256X:$src))), (v16i16 VR256X:$src)>;
276 def : Pat<(v16i16 (bitconvert (v8i32 VR256X:$src))), (v16i16 VR256X:$src)>;
277 def : Pat<(v16i16 (bitconvert (v4i64 VR256X:$src))), (v16i16 VR256X:$src)>;
278 def : Pat<(v16i16 (bitconvert (v4f64 VR256X:$src))), (v16i16 VR256X:$src)>;
279 def : Pat<(v16i16 (bitconvert (v32i8 VR256X:$src))), (v16i16 VR256X:$src)>;
280}
281
282//
283// AVX-512: VPXOR instruction writes zero to its upper part, it's safe build zeros.
284//
285
286let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1,
287 isPseudo = 1, Predicates = [HasAVX512] in {
288def AVX512_512_SET0 : I<0, Pseudo, (outs VR512:$dst), (ins), "",
289 [(set VR512:$dst, (v16f32 immAllZerosV))]>;
290}
291
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]292let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]293def : Pat<(v8i64 immAllZerosV), (AVX512_512_SET0)>;
294def : Pat<(v16i32 immAllZerosV), (AVX512_512_SET0)>;
295def : Pat<(v8f64 immAllZerosV), (AVX512_512_SET0)>;
Craig Topperfb1746b2014-01-30 06:03:19 +0000[diff] [blame]296}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]297
298//===----------------------------------------------------------------------===//
299// AVX-512 - VECTOR INSERT
300//
301// -- 32x8 form --
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]302let hasSideEffects = 0, ExeDomain = SSEPackedSingle in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]303def VINSERTF32x4rr : AVX512AIi8<0x18, MRMSrcReg, (outs VR512:$dst),
304 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
305 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
306 []>, EVEX_4V, EVEX_V512;
307let mayLoad = 1 in
308def VINSERTF32x4rm : AVX512AIi8<0x18, MRMSrcMem, (outs VR512:$dst),
309 (ins VR512:$src1, f128mem:$src2, i8imm:$src3),
310 "vinsertf32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
311 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
312}
313
314// -- 64x4 fp form --
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]315let hasSideEffects = 0, ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]316def VINSERTF64x4rr : AVX512AIi8<0x1a, MRMSrcReg, (outs VR512:$dst),
317 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
318 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
319 []>, EVEX_4V, EVEX_V512, VEX_W;
320let mayLoad = 1 in
321def VINSERTF64x4rm : AVX512AIi8<0x1a, MRMSrcMem, (outs VR512:$dst),
322 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
323 "vinsertf64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
324 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
325}
326// -- 32x4 integer form --
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]327let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]328def VINSERTI32x4rr : AVX512AIi8<0x38, MRMSrcReg, (outs VR512:$dst),
329 (ins VR512:$src1, VR128X:$src2, i8imm:$src3),
330 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
331 []>, EVEX_4V, EVEX_V512;
332let mayLoad = 1 in
333def VINSERTI32x4rm : AVX512AIi8<0x38, MRMSrcMem, (outs VR512:$dst),
334 (ins VR512:$src1, i128mem:$src2, i8imm:$src3),
335 "vinserti32x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
336 []>, EVEX_4V, EVEX_V512, EVEX_CD8<32, CD8VT4>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]337}
338
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]339let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]340// -- 64x4 form --
341def VINSERTI64x4rr : AVX512AIi8<0x3a, MRMSrcReg, (outs VR512:$dst),
342 (ins VR512:$src1, VR256X:$src2, i8imm:$src3),
343 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
344 []>, EVEX_4V, EVEX_V512, VEX_W;
345let mayLoad = 1 in
346def VINSERTI64x4rm : AVX512AIi8<0x3a, MRMSrcMem, (outs VR512:$dst),
347 (ins VR512:$src1, i256mem:$src2, i8imm:$src3),
348 "vinserti64x4\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
349 []>, EVEX_4V, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT4>;
350}
351
352def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (v4f32 VR128X:$src2),
353 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
354 (INSERT_get_vinsert128_imm VR512:$ins))>;
355def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (v2f64 VR128X:$src2),
356 (iPTR imm)), (VINSERTF32x4rr VR512:$src1, VR128X:$src2,
357 (INSERT_get_vinsert128_imm VR512:$ins))>;
358def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v2i64 VR128X:$src2),
359 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
360 (INSERT_get_vinsert128_imm VR512:$ins))>;
361def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v4i32 VR128X:$src2),
362 (iPTR imm)), (VINSERTI32x4rr VR512:$src1, VR128X:$src2,
363 (INSERT_get_vinsert128_imm VR512:$ins))>;
Robert Khasanoved0b2e92014-03-31 16:01:38 +0000[diff] [blame]364
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]365def : Pat<(vinsert128_insert:$ins (v16f32 VR512:$src1), (loadv4f32 addr:$src2),
366 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
367 (INSERT_get_vinsert128_imm VR512:$ins))>;
368def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1),
Robert Khasanoved0b2e92014-03-31 16:01:38 +0000[diff] [blame]369 (bc_v4i32 (loadv2i64 addr:$src2)),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]370 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
371 (INSERT_get_vinsert128_imm VR512:$ins))>;
372def : Pat<(vinsert128_insert:$ins (v8f64 VR512:$src1), (loadv2f64 addr:$src2),
373 (iPTR imm)), (VINSERTF32x4rm VR512:$src1, addr:$src2,
374 (INSERT_get_vinsert128_imm VR512:$ins))>;
375def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (loadv2i64 addr:$src2),
376 (iPTR imm)), (VINSERTI32x4rm VR512:$src1, addr:$src2,
377 (INSERT_get_vinsert128_imm VR512:$ins))>;
378
379def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (v8f32 VR256X:$src2),
380 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
381 (INSERT_get_vinsert256_imm VR512:$ins))>;
382def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (v4f64 VR256X:$src2),
383 (iPTR imm)), (VINSERTF64x4rr VR512:$src1, VR256X:$src2,
384 (INSERT_get_vinsert256_imm VR512:$ins))>;
385def : Pat<(vinsert128_insert:$ins (v8i64 VR512:$src1), (v4i64 VR256X:$src2),
386 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
387 (INSERT_get_vinsert256_imm VR512:$ins))>;
388def : Pat<(vinsert128_insert:$ins (v16i32 VR512:$src1), (v8i32 VR256X:$src2),
389 (iPTR imm)), (VINSERTI64x4rr VR512:$src1, VR256X:$src2,
390 (INSERT_get_vinsert256_imm VR512:$ins))>;
391
392def : Pat<(vinsert256_insert:$ins (v16f32 VR512:$src1), (loadv8f32 addr:$src2),
393 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
394 (INSERT_get_vinsert256_imm VR512:$ins))>;
395def : Pat<(vinsert256_insert:$ins (v8f64 VR512:$src1), (loadv4f64 addr:$src2),
396 (iPTR imm)), (VINSERTF64x4rm VR512:$src1, addr:$src2,
397 (INSERT_get_vinsert256_imm VR512:$ins))>;
398def : Pat<(vinsert256_insert:$ins (v8i64 VR512:$src1), (loadv4i64 addr:$src2),
399 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
400 (INSERT_get_vinsert256_imm VR512:$ins))>;
401def : Pat<(vinsert256_insert:$ins (v16i32 VR512:$src1),
402 (bc_v8i32 (loadv4i64 addr:$src2)),
403 (iPTR imm)), (VINSERTI64x4rm VR512:$src1, addr:$src2,
404 (INSERT_get_vinsert256_imm VR512:$ins))>;
405
406// vinsertps - insert f32 to XMM
407def VINSERTPSzrr : AVX512AIi8<0x21, MRMSrcReg, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]408 (ins VR128X:$src1, VR128X:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]409 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]410 [(set VR128X:$dst, (X86insertps VR128X:$src1, VR128X:$src2, imm:$src3))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]411 EVEX_4V;
412def VINSERTPSzrm: AVX512AIi8<0x21, MRMSrcMem, (outs VR128X:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]413 (ins VR128X:$src1, f32mem:$src2, i8imm:$src3),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]414 "vinsertps\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
Filipe Cabecinhas20352212014-04-21 20:07:29 +0000[diff] [blame]415 [(set VR128X:$dst, (X86insertps VR128X:$src1,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]416 (v4f32 (scalar_to_vector (loadf32 addr:$src2))),
417 imm:$src3))]>, EVEX_4V, EVEX_CD8<32, CD8VT1>;
418
419//===----------------------------------------------------------------------===//
420// AVX-512 VECTOR EXTRACT
421//---
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]422
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]423multiclass vextract_for_size<int Opcode,
424 X86VectorVTInfo From, X86VectorVTInfo To,
425 X86VectorVTInfo AltFrom, X86VectorVTInfo AltTo,
426 PatFrag vextract_extract,
427 SDNodeXForm EXTRACT_get_vextract_imm> {
428 let hasSideEffects = 0, ExeDomain = To.ExeDomain in {
429 def rr : AVX512AIi8<Opcode, MRMDestReg, (outs To.RC:$dst),
Adam Nemetf7988d72014-09-25 23:48:49 +0000[diff] [blame]430 (ins VR512:$src1, i8imm:$idx),
431 "vextract" # To.EltTypeName # "x4\t{$idx, $src1, $dst|"
432 "$dst, $src1, $idx}",
433 [(set To.RC:$dst, (vextract_extract:$idx (From.VT VR512:$src1),
434 (iPTR imm)))]>,
435 EVEX, EVEX_V512;
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]436 let mayStore = 1 in
437 def rm : AVX512AIi8<Opcode, MRMDestMem, (outs),
438 (ins To.MemOp:$dst, VR512:$src1, i8imm:$src2),
439 "vextract" # To.EltTypeName # "x4\t{$src2, $src1, $dst|"
440 "$dst, $src1, $src2}",
441 []>, EVEX, EVEX_V512, EVEX_CD8<To.EltSize, CD8VT4>;
442 }
443
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]444 // Codegen pattern with the alternative types, e.g. v8i64 -> v2i64 for
445 // vextracti32x4
446 def : Pat<(vextract_extract:$ext (AltFrom.VT VR512:$src1), (iPTR imm)),
447 (AltTo.VT (!cast<Instruction>(NAME # To.EltSize # "x4rr")
448 VR512:$src1,
449 (EXTRACT_get_vextract_imm To.RC:$ext)))>;
450
451 // A 128/256-bit subvector extract from the first 512-bit vector position is
452 // a subregister copy that needs no instruction.
453 def : Pat<(To.VT (extract_subvector (From.VT VR512:$src), (iPTR 0))),
454 (To.VT
455 (EXTRACT_SUBREG (From.VT VR512:$src), To.SubRegIdx))>;
456
457 // And for the alternative types.
458 def : Pat<(AltTo.VT (extract_subvector (AltFrom.VT VR512:$src), (iPTR 0))),
459 (AltTo.VT
460 (EXTRACT_SUBREG (AltFrom.VT VR512:$src), AltTo.SubRegIdx))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]461}
462
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]463multiclass vextract_for_type<ValueType EltVT32, int Opcode32,
464 ValueType EltVT64, int Opcode64> {
465 defm NAME # "32x4" : vextract_for_size<Opcode32,
466 X86VectorVTInfo<16, EltVT32, VR512>,
467 X86VectorVTInfo< 4, EltVT32, VR128X>,
468 X86VectorVTInfo< 8, EltVT64, VR512>,
469 X86VectorVTInfo< 2, EltVT64, VR128X>,
470 vextract128_extract,
471 EXTRACT_get_vextract128_imm>;
472 defm NAME # "64x4" : vextract_for_size<Opcode64,
473 X86VectorVTInfo< 8, EltVT64, VR512>,
474 X86VectorVTInfo< 4, EltVT64, VR256X>,
475 X86VectorVTInfo<16, EltVT32, VR512>,
476 X86VectorVTInfo< 8, EltVT32, VR256>,
477 vextract256_extract,
478 EXTRACT_get_vextract256_imm>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]479}
480
Adam Nemet55536c62014-09-25 23:48:45 +0000[diff] [blame]481defm VEXTRACTF : vextract_for_type<f32, 0x19, f64, 0x1b>;
482defm VEXTRACTI : vextract_for_type<i32, 0x39, i64, 0x3b>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]483
484// A 128-bit subvector insert to the first 512-bit vector position
485// is a subregister copy that needs no instruction.
486def : Pat<(insert_subvector undef, (v2i64 VR128X:$src), (iPTR 0)),
487 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
488 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
489 sub_ymm)>;
490def : Pat<(insert_subvector undef, (v2f64 VR128X:$src), (iPTR 0)),
491 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
492 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
493 sub_ymm)>;
494def : Pat<(insert_subvector undef, (v4i32 VR128X:$src), (iPTR 0)),
495 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
496 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
497 sub_ymm)>;
498def : Pat<(insert_subvector undef, (v4f32 VR128X:$src), (iPTR 0)),
499 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
500 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
501 sub_ymm)>;
502
503def : Pat<(insert_subvector undef, (v4i64 VR256X:$src), (iPTR 0)),
504 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
505def : Pat<(insert_subvector undef, (v4f64 VR256X:$src), (iPTR 0)),
506 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
507def : Pat<(insert_subvector undef, (v8i32 VR256X:$src), (iPTR 0)),
508 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
509def : Pat<(insert_subvector undef, (v8f32 VR256X:$src), (iPTR 0)),
510 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
511
512// vextractps - extract 32 bits from XMM
513def VEXTRACTPSzrr : AVX512AIi8<0x17, MRMDestReg, (outs GR32:$dst),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]514 (ins VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]515 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]516 [(set GR32:$dst, (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2))]>,
517 EVEX;
518
519def VEXTRACTPSzmr : AVX512AIi8<0x17, MRMDestMem, (outs),
Chandler Carruth373b2b12014-09-06 10:00:01 +0000[diff] [blame]520 (ins f32mem:$dst, VR128X:$src1, i32i8imm:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]521 "vextractps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]522 [(store (extractelt (bc_v4i32 (v4f32 VR128X:$src1)), imm:$src2),
Elena Demikhovsky2aafc222014-02-11 07:25:59 +0000[diff] [blame]523 addr:$dst)]>, EVEX, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]524
525//===---------------------------------------------------------------------===//
526// AVX-512 BROADCAST
527//---
528multiclass avx512_fp_broadcast<bits<8> opc, string OpcodeStr,
529 RegisterClass DestRC,
530 RegisterClass SrcRC, X86MemOperand x86memop> {
531 def rr : AVX5128I<opc, MRMSrcReg, (outs DestRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]532 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]533 []>, EVEX;
534 def rm : AVX5128I<opc, MRMSrcMem, (outs DestRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]535 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),[]>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]536}
537let ExeDomain = SSEPackedSingle in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]538 defm VBROADCASTSSZ : avx512_fp_broadcast<0x18, "vbroadcastss", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]539 VR128X, f32mem>,
540 EVEX_V512, EVEX_CD8<32, CD8VT1>;
541}
542
543let ExeDomain = SSEPackedDouble in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]544 defm VBROADCASTSDZ : avx512_fp_broadcast<0x19, "vbroadcastsd", VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]545 VR128X, f64mem>,
546 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
547}
548
549def : Pat<(v16f32 (X86VBroadcast (loadf32 addr:$src))),
550 (VBROADCASTSSZrm addr:$src)>;
551def : Pat<(v8f64 (X86VBroadcast (loadf64 addr:$src))),
552 (VBROADCASTSDZrm addr:$src)>;
553
Quentin Colombet4bf1c282013-10-25 17:47:18 +0000[diff] [blame]554def : Pat<(int_x86_avx512_vbroadcast_ss_512 addr:$src),
555 (VBROADCASTSSZrm addr:$src)>;
556def : Pat<(int_x86_avx512_vbroadcast_sd_512 addr:$src),
557 (VBROADCASTSDZrm addr:$src)>;
558
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]559multiclass avx512_int_broadcast_reg<bits<8> opc, string OpcodeStr,
560 RegisterClass SrcRC, RegisterClass KRC> {
561 def Zrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]562 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]563 []>, EVEX, EVEX_V512;
564 def Zkrr : AVX5128I<opc, MRMSrcReg, (outs VR512:$dst),
565 (ins KRC:$mask, SrcRC:$src),
566 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]567 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]568 []>, EVEX, EVEX_V512, EVEX_KZ;
569}
570
571defm VPBROADCASTDr : avx512_int_broadcast_reg<0x7C, "vpbroadcastd", GR32, VK16WM>;
572defm VPBROADCASTQr : avx512_int_broadcast_reg<0x7C, "vpbroadcastq", GR64, VK8WM>,
573 VEX_W;
574
575def : Pat <(v16i32 (X86vzext VK16WM:$mask)),
576 (VPBROADCASTDrZkrr VK16WM:$mask, (i32 (MOV32ri 0x1)))>;
577
578def : Pat <(v8i64 (X86vzext VK8WM:$mask)),
579 (VPBROADCASTQrZkrr VK8WM:$mask, (i64 (MOV64ri 0x1)))>;
580
581def : Pat<(v16i32 (X86VBroadcast (i32 GR32:$src))),
582 (VPBROADCASTDrZrr GR32:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]583def : Pat<(v16i32 (X86VBroadcastm VK16WM:$mask, (i32 GR32:$src))),
584 (VPBROADCASTDrZkrr VK16WM:$mask, GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]585def : Pat<(v8i64 (X86VBroadcast (i64 GR64:$src))),
586 (VPBROADCASTQrZrr GR64:$src)>;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]587def : Pat<(v8i64 (X86VBroadcastm VK8WM:$mask, (i64 GR64:$src))),
588 (VPBROADCASTQrZkrr VK8WM:$mask, GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]589
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]590def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_i32_512 (i32 GR32:$src))),
591 (VPBROADCASTDrZrr GR32:$src)>;
592def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_i64_512 (i64 GR64:$src))),
593 (VPBROADCASTQrZrr GR64:$src)>;
594
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]595def : Pat<(v16i32 (int_x86_avx512_mask_pbroadcast_d_gpr_512 (i32 GR32:$src),
596 (v16i32 immAllZerosV), (i16 GR16:$mask))),
597 (VPBROADCASTDrZkrr (COPY_TO_REGCLASS GR16:$mask, VK16WM), GR32:$src)>;
598def : Pat<(v8i64 (int_x86_avx512_mask_pbroadcast_q_gpr_512 (i64 GR64:$src),
599 (bc_v8i64 (v16i32 immAllZerosV)), (i8 GR8:$mask))),
600 (VPBROADCASTQrZkrr (COPY_TO_REGCLASS GR8:$mask, VK8WM), GR64:$src)>;
601
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]602multiclass avx512_int_broadcast_rm<bits<8> opc, string OpcodeStr,
603 X86MemOperand x86memop, PatFrag ld_frag,
604 RegisterClass DstRC, ValueType OpVT, ValueType SrcVT,
605 RegisterClass KRC> {
606 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins VR128X:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]607 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]608 [(set DstRC:$dst,
609 (OpVT (X86VBroadcast (SrcVT VR128X:$src))))]>, EVEX;
610 def krr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst), (ins KRC:$mask,
611 VR128X:$src),
612 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]613 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]614 [(set DstRC:$dst,
615 (OpVT (X86VBroadcastm KRC:$mask, (SrcVT VR128X:$src))))]>,
616 EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]617 let mayLoad = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]618 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]619 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]620 [(set DstRC:$dst,
621 (OpVT (X86VBroadcast (ld_frag addr:$src))))]>, EVEX;
622 def krm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst), (ins KRC:$mask,
623 x86memop:$src),
624 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]625 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]626 [(set DstRC:$dst, (OpVT (X86VBroadcastm KRC:$mask,
627 (ld_frag addr:$src))))]>, EVEX, EVEX_KZ;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]628 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]629}
630
631defm VPBROADCASTDZ : avx512_int_broadcast_rm<0x58, "vpbroadcastd", i32mem,
632 loadi32, VR512, v16i32, v4i32, VK16WM>,
633 EVEX_V512, EVEX_CD8<32, CD8VT1>;
634defm VPBROADCASTQZ : avx512_int_broadcast_rm<0x59, "vpbroadcastq", i64mem,
635 loadi64, VR512, v8i64, v2i64, VK8WM>, EVEX_V512, VEX_W,
636 EVEX_CD8<64, CD8VT1>;
637
Adam Nemet73f72e12014-06-27 00:43:38 +0000[diff] [blame]638multiclass avx512_int_subvec_broadcast_rm<bits<8> opc, string OpcodeStr,
639 X86MemOperand x86memop, PatFrag ld_frag,
640 RegisterClass KRC> {
641 let mayLoad = 1 in {
642 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins x86memop:$src),
643 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
644 []>, EVEX;
645 def krm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst), (ins KRC:$mask,
646 x86memop:$src),
647 !strconcat(OpcodeStr,
648 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
649 []>, EVEX, EVEX_KZ;
650 }
651}
652
653defm VBROADCASTI32X4 : avx512_int_subvec_broadcast_rm<0x5a, "vbroadcasti32x4",
654 i128mem, loadv2i64, VK16WM>,
655 EVEX_V512, EVEX_CD8<32, CD8VT4>;
656defm VBROADCASTI64X4 : avx512_int_subvec_broadcast_rm<0x5b, "vbroadcasti64x4",
657 i256mem, loadv4i64, VK16WM>, VEX_W,
658 EVEX_V512, EVEX_CD8<64, CD8VT4>;
659
Cameron McInally394d5572013-10-31 13:56:31 +0000[diff] [blame]660def : Pat<(v16i32 (int_x86_avx512_pbroadcastd_512 (v4i32 VR128X:$src))),
661 (VPBROADCASTDZrr VR128X:$src)>;
662def : Pat<(v8i64 (int_x86_avx512_pbroadcastq_512 (v2i64 VR128X:$src))),
663 (VPBROADCASTQZrr VR128X:$src)>;
664
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]665def : Pat<(v16f32 (X86VBroadcast (v4f32 VR128X:$src))),
666 (VBROADCASTSSZrr VR128X:$src)>;
667def : Pat<(v8f64 (X86VBroadcast (v2f64 VR128X:$src))),
668 (VBROADCASTSDZrr VR128X:$src)>;
Quentin Colombet8761a8f2013-10-25 18:04:12 +0000[diff] [blame]669
670def : Pat<(v16f32 (int_x86_avx512_vbroadcast_ss_ps_512 (v4f32 VR128X:$src))),
671 (VBROADCASTSSZrr VR128X:$src)>;
672def : Pat<(v8f64 (int_x86_avx512_vbroadcast_sd_pd_512 (v2f64 VR128X:$src))),
673 (VBROADCASTSDZrr VR128X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]674
675// Provide fallback in case the load node that is used in the patterns above
676// is used by additional users, which prevents the pattern selection.
677def : Pat<(v16f32 (X86VBroadcast FR32X:$src)),
678 (VBROADCASTSSZrr (COPY_TO_REGCLASS FR32X:$src, VR128X))>;
679def : Pat<(v8f64 (X86VBroadcast FR64X:$src)),
680 (VBROADCASTSDZrr (COPY_TO_REGCLASS FR64X:$src, VR128X))>;
681
682
683let Predicates = [HasAVX512] in {
684def : Pat<(v8i32 (X86VBroadcastm (v8i1 VK8WM:$mask), (loadi32 addr:$src))),
685 (EXTRACT_SUBREG
686 (v16i32 (VPBROADCASTDZkrm (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
687 addr:$src)), sub_ymm)>;
688}
689//===----------------------------------------------------------------------===//
690// AVX-512 BROADCAST MASK TO VECTOR REGISTER
691//---
692
693multiclass avx512_mask_broadcast<bits<8> opc, string OpcodeStr,
694 RegisterClass DstRC, RegisterClass KRC,
695 ValueType OpVT, ValueType SrcVT> {
696def rr : AVX512XS8I<opc, MRMDestReg, (outs DstRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]697 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]698 []>, EVEX;
699}
700
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]701let Predicates = [HasCDI] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]702defm VPBROADCASTMW2D : avx512_mask_broadcast<0x3A, "vpbroadcastmw2d", VR512,
703 VK16, v16i32, v16i1>, EVEX_V512;
704defm VPBROADCASTMB2Q : avx512_mask_broadcast<0x2A, "vpbroadcastmb2q", VR512,
705 VK8, v8i64, v8i1>, EVEX_V512, VEX_W;
Cameron McInallyc43c8f92014-06-13 11:40:31 +0000[diff] [blame]706}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]707
708//===----------------------------------------------------------------------===//
709// AVX-512 - VPERM
710//
711// -- immediate form --
712multiclass avx512_perm_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
713 SDNode OpNode, PatFrag mem_frag,
714 X86MemOperand x86memop, ValueType OpVT> {
715 def ri : AVX512AIi8<opc, MRMSrcReg, (outs RC:$dst),
716 (ins RC:$src1, i8imm:$src2),
717 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]718 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]719 [(set RC:$dst,
720 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
721 EVEX;
722 def mi : AVX512AIi8<opc, MRMSrcMem, (outs RC:$dst),
723 (ins x86memop:$src1, i8imm:$src2),
724 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]725 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]726 [(set RC:$dst,
727 (OpVT (OpNode (mem_frag addr:$src1),
728 (i8 imm:$src2))))]>, EVEX;
729}
730
731defm VPERMQZ : avx512_perm_imm<0x00, "vpermq", VR512, X86VPermi, memopv8i64,
732 i512mem, v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
733let ExeDomain = SSEPackedDouble in
734defm VPERMPDZ : avx512_perm_imm<0x01, "vpermpd", VR512, X86VPermi, memopv8f64,
735 f512mem, v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
736
737// -- VPERM - register form --
738multiclass avx512_perm<bits<8> opc, string OpcodeStr, RegisterClass RC,
739 PatFrag mem_frag, X86MemOperand x86memop, ValueType OpVT> {
740
741 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
742 (ins RC:$src1, RC:$src2),
743 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]744 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]745 [(set RC:$dst,
746 (OpVT (X86VPermv RC:$src1, RC:$src2)))]>, EVEX_4V;
747
748 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
749 (ins RC:$src1, x86memop:$src2),
750 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]751 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]752 [(set RC:$dst,
753 (OpVT (X86VPermv RC:$src1, (mem_frag addr:$src2))))]>,
754 EVEX_4V;
755}
756
757defm VPERMDZ : avx512_perm<0x36, "vpermd", VR512, memopv16i32, i512mem,
758 v16i32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
759defm VPERMQZ : avx512_perm<0x36, "vpermq", VR512, memopv8i64, i512mem,
760 v8i64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
761let ExeDomain = SSEPackedSingle in
762defm VPERMPSZ : avx512_perm<0x16, "vpermps", VR512, memopv16f32, f512mem,
763 v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
764let ExeDomain = SSEPackedDouble in
765defm VPERMPDZ : avx512_perm<0x16, "vpermpd", VR512, memopv8f64, f512mem,
766 v8f64>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
767
768// -- VPERM2I - 3 source operands form --
769multiclass avx512_perm_3src<bits<8> opc, string OpcodeStr, RegisterClass RC,
770 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]771 SDNode OpNode, ValueType OpVT, RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]772let Constraints = "$src1 = $dst" in {
773 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
774 (ins RC:$src1, RC:$src2, RC:$src3),
775 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]776 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]777 [(set RC:$dst,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]778 (OpVT (OpNode RC:$src1, RC:$src2, RC:$src3)))]>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]779 EVEX_4V;
780
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]781 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
782 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
783 !strconcat(OpcodeStr,
784 " \t{$src3, $src2, $dst {${mask}}|"
785 "$dst {${mask}}, $src2, $src3}"),
786 [(set RC:$dst, (OpVT (vselect KRC:$mask,
787 (OpNode RC:$src1, RC:$src2,
788 RC:$src3),
789 RC:$src1)))]>,
790 EVEX_4V, EVEX_K;
791
792 let AddedComplexity = 30 in // Prefer over VMOV*rrkz Pat<>
793 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
794 (ins RC:$src1, KRC:$mask, RC:$src2, RC:$src3),
795 !strconcat(OpcodeStr,
796 " \t{$src3, $src2, $dst {${mask}} {z} |",
797 "$dst {${mask}} {z}, $src2, $src3}"),
798 [(set RC:$dst, (OpVT (vselect KRC:$mask,
799 (OpNode RC:$src1, RC:$src2,
800 RC:$src3),
801 (OpVT (bitconvert
802 (v16i32 immAllZerosV))))))]>,
803 EVEX_4V, EVEX_KZ;
804
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]805 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
806 (ins RC:$src1, RC:$src2, x86memop:$src3),
807 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]808 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]809 [(set RC:$dst,
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]810 (OpVT (OpNode RC:$src1, RC:$src2,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]811 (mem_frag addr:$src3))))]>, EVEX_4V;
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]812
813 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
814 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
815 !strconcat(OpcodeStr,
816 " \t{$src3, $src2, $dst {${mask}}|"
817 "$dst {${mask}}, $src2, $src3}"),
818 [(set RC:$dst,
819 (OpVT (vselect KRC:$mask,
820 (OpNode RC:$src1, RC:$src2,
821 (mem_frag addr:$src3)),
822 RC:$src1)))]>,
823 EVEX_4V, EVEX_K;
824
825 let AddedComplexity = 10 in // Prefer over the rrkz variant
826 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
827 (ins RC:$src1, KRC:$mask, RC:$src2, x86memop:$src3),
828 !strconcat(OpcodeStr,
829 " \t{$src3, $src2, $dst {${mask}} {z}|"
830 "$dst {${mask}} {z}, $src2, $src3}"),
831 [(set RC:$dst,
832 (OpVT (vselect KRC:$mask,
833 (OpNode RC:$src1, RC:$src2,
834 (mem_frag addr:$src3)),
835 (OpVT (bitconvert
836 (v16i32 immAllZerosV))))))]>,
837 EVEX_4V, EVEX_KZ;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]838 }
839}
Adam Nemet2415a492014-07-02 21:25:54 +0000[diff] [blame]840defm VPERMI2D : avx512_perm_3src<0x76, "vpermi2d", VR512, memopv16i32,
841 i512mem, X86VPermiv3, v16i32, VK16WM>,
842 EVEX_V512, EVEX_CD8<32, CD8VF>;
843defm VPERMI2Q : avx512_perm_3src<0x76, "vpermi2q", VR512, memopv8i64,
844 i512mem, X86VPermiv3, v8i64, VK8WM>,
845 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
846defm VPERMI2PS : avx512_perm_3src<0x77, "vpermi2ps", VR512, memopv16f32,
847 i512mem, X86VPermiv3, v16f32, VK16WM>,
848 EVEX_V512, EVEX_CD8<32, CD8VF>;
849defm VPERMI2PD : avx512_perm_3src<0x77, "vpermi2pd", VR512, memopv8f64,
850 i512mem, X86VPermiv3, v8f64, VK8WM>,
851 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]852
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]853multiclass avx512_perm_table_3src<bits<8> opc, string Suffix, RegisterClass RC,
854 PatFrag mem_frag, X86MemOperand x86memop,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]855 SDNode OpNode, ValueType OpVT, RegisterClass KRC,
856 ValueType MaskVT, RegisterClass MRC> :
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]857 avx512_perm_3src<opc, "vpermt2"##Suffix, RC, mem_frag, x86memop, OpNode,
858 OpVT, KRC> {
859 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
860 VR512:$idx, VR512:$src1, VR512:$src2, -1)),
861 (!cast<Instruction>(NAME#rr) VR512:$src1, VR512:$idx, VR512:$src2)>;
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]862
863 def : Pat<(OpVT (!cast<Intrinsic>("int_x86_avx512_mask_vpermt_"##Suffix##"_512")
864 VR512:$idx, VR512:$src1, VR512:$src2, MRC:$mask)),
865 (!cast<Instruction>(NAME#rrk) VR512:$src1,
866 (MaskVT (COPY_TO_REGCLASS MRC:$mask, KRC)), VR512:$idx, VR512:$src2)>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]867}
868
869defm VPERMT2D : avx512_perm_table_3src<0x7E, "d", VR512, memopv16i32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]870 X86VPermv3, v16i32, VK16WM, v16i1, GR16>,
871 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]872defm VPERMT2Q : avx512_perm_table_3src<0x7E, "q", VR512, memopv8i64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]873 X86VPermv3, v8i64, VK8WM, v8i1, GR8>,
874 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]875defm VPERMT2PS : avx512_perm_table_3src<0x7F, "ps", VR512, memopv16f32, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]876 X86VPermv3, v16f32, VK16WM, v16i1, GR16>,
877 EVEX_V512, EVEX_CD8<32, CD8VF>;
Adam Nemetefe9c982014-07-02 21:25:58 +0000[diff] [blame]878defm VPERMT2PD : avx512_perm_table_3src<0x7F, "pd", VR512, memopv8f64, i512mem,
Adam Nemet11dd5cf2014-07-02 21:26:01 +0000[diff] [blame]879 X86VPermv3, v8f64, VK8WM, v8i1, GR8>,
880 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky299cf5112014-04-29 09:09:15 +0000[diff] [blame]881
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]882//===----------------------------------------------------------------------===//
883// AVX-512 - BLEND using mask
884//
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]885multiclass avx512_blendmask<bits<8> opc, string OpcodeStr,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]886 RegisterClass KRC, RegisterClass RC,
887 X86MemOperand x86memop, PatFrag mem_frag,
888 SDNode OpNode, ValueType vt> {
889 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]890 (ins KRC:$mask, RC:$src1, RC:$src2),
891 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]892 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]893 [(set RC:$dst, (OpNode KRC:$mask, (vt RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]894 (vt RC:$src1)))]>, EVEX_4V, EVEX_K;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]895 let mayLoad = 1 in
896 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
897 (ins KRC:$mask, RC:$src1, x86memop:$src2),
898 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]899 " \t{$src2, $src1, ${dst} {${mask}}|${dst} {${mask}}, $src1, $src2}"),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]900 []>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]901}
902
903let ExeDomain = SSEPackedSingle in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]904defm VBLENDMPSZ : avx512_blendmask<0x65, "vblendmps",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]905 VK16WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]906 memopv16f32, vselect, v16f32>,
907 EVEX_CD8<32, CD8VF>, EVEX_V512;
908let ExeDomain = SSEPackedDouble in
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]909defm VBLENDMPDZ : avx512_blendmask<0x65, "vblendmpd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]910 VK8WM, VR512, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]911 memopv8f64, vselect, v8f64>,
912 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
913
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]914def : Pat<(v16f32 (int_x86_avx512_mask_blend_ps_512 (v16f32 VR512:$src1),
915 (v16f32 VR512:$src2), (i16 GR16:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]916 (VBLENDMPSZrr (COPY_TO_REGCLASS GR16:$mask, VK16WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]917 VR512:$src1, VR512:$src2)>;
918
919def : Pat<(v8f64 (int_x86_avx512_mask_blend_pd_512 (v8f64 VR512:$src1),
920 (v8f64 VR512:$src2), (i8 GR8:$mask))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]921 (VBLENDMPDZrr (COPY_TO_REGCLASS GR8:$mask, VK8WM),
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]922 VR512:$src1, VR512:$src2)>;
923
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]924defm VPBLENDMDZ : avx512_blendmask<0x64, "vpblendmd",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]925 VK16WM, VR512, f512mem,
926 memopv16i32, vselect, v16i32>,
927 EVEX_CD8<32, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]928
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]929defm VPBLENDMQZ : avx512_blendmask<0x64, "vpblendmq",
Cameron McInallyd80f7d32013-11-04 19:14:56 +0000[diff] [blame]930 VK8WM, VR512, f512mem,
931 memopv8i64, vselect, v8i64>,
932 VEX_W, EVEX_CD8<64, CD8VF>, EVEX_V512;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]933
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]934def : Pat<(v16i32 (int_x86_avx512_mask_blend_d_512 (v16i32 VR512:$src1),
935 (v16i32 VR512:$src2), (i16 GR16:$mask))),
936 (VPBLENDMDZrr (COPY_TO_REGCLASS GR16:$mask, VK16),
937 VR512:$src1, VR512:$src2)>;
938
939def : Pat<(v8i64 (int_x86_avx512_mask_blend_q_512 (v8i64 VR512:$src1),
940 (v8i64 VR512:$src2), (i8 GR8:$mask))),
941 (VPBLENDMQZrr (COPY_TO_REGCLASS GR8:$mask, VK8),
942 VR512:$src1, VR512:$src2)>;
943
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]944let Predicates = [HasAVX512] in {
945def : Pat<(v8f32 (vselect (v8i1 VK8WM:$mask), (v8f32 VR256X:$src1),
946 (v8f32 VR256X:$src2))),
947 (EXTRACT_SUBREG
948 (v16f32 (VBLENDMPSZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
949 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
950 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
951
952def : Pat<(v8i32 (vselect (v8i1 VK8WM:$mask), (v8i32 VR256X:$src1),
953 (v8i32 VR256X:$src2))),
954 (EXTRACT_SUBREG
955 (v16i32 (VPBLENDMDZrr (COPY_TO_REGCLASS VK8WM:$mask, VK16WM),
956 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
957 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
958}
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]959//===----------------------------------------------------------------------===//
960// Compare Instructions
961//===----------------------------------------------------------------------===//
962
963// avx512_cmp_scalar - AVX512 CMPSS and CMPSD
964multiclass avx512_cmp_scalar<RegisterClass RC, X86MemOperand x86memop,
965 Operand CC, SDNode OpNode, ValueType VT,
966 PatFrag ld_frag, string asm, string asm_alt> {
967 def rr : AVX512Ii8<0xC2, MRMSrcReg,
968 (outs VK1:$dst), (ins RC:$src1, RC:$src2, CC:$cc), asm,
969 [(set VK1:$dst, (OpNode (VT RC:$src1), RC:$src2, imm:$cc))],
970 IIC_SSE_ALU_F32S_RR>, EVEX_4V;
971 def rm : AVX512Ii8<0xC2, MRMSrcMem,
972 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, CC:$cc), asm,
973 [(set VK1:$dst, (OpNode (VT RC:$src1),
974 (ld_frag addr:$src2), imm:$cc))], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]975 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]976 def rri_alt : AVX512Ii8<0xC2, MRMSrcReg,
977 (outs VK1:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
978 asm_alt, [], IIC_SSE_ALU_F32S_RR>, EVEX_4V;
979 def rmi_alt : AVX512Ii8<0xC2, MRMSrcMem,
980 (outs VK1:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
981 asm_alt, [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
982 }
983}
984
985let Predicates = [HasAVX512] in {
986defm VCMPSSZ : avx512_cmp_scalar<FR32X, f32mem, AVXCC, X86cmpms, f32, loadf32,
987 "vcmp${cc}ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
988 "vcmpss\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
989 XS;
990defm VCMPSDZ : avx512_cmp_scalar<FR64X, f64mem, AVXCC, X86cmpms, f64, loadf64,
991 "vcmp${cc}sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
992 "vcmpsd\t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}">,
993 XD, VEX_W;
994}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]995
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]996multiclass avx512_icmp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
997 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]998 def rr : AVX512BI<opc, MRMSrcReg,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]999 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2),
1000 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1001 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2)))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1002 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1003 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1004 def rm : AVX512BI<opc, MRMSrcMem,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1005 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2),
1006 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
1007 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1008 (_.VT (bitconvert (_.LdFrag addr:$src2)))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1009 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1010 def rrk : AVX512BI<opc, MRMSrcReg,
1011 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2),
1012 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1013 "$dst {${mask}}, $src1, $src2}"),
1014 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1015 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2))))],
1016 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1017 let mayLoad = 1 in
1018 def rmk : AVX512BI<opc, MRMSrcMem,
1019 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2),
1020 !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|",
1021 "$dst {${mask}}, $src1, $src2}"),
1022 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1023 (OpNode (_.VT _.RC:$src1),
1024 (_.VT (bitconvert
1025 (_.LdFrag addr:$src2))))))],
1026 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1027}
1028
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1029multiclass avx512_icmp_packed_rmb<bits<8> opc, string OpcodeStr, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1030 X86VectorVTInfo _> :
1031 avx512_icmp_packed<opc, OpcodeStr, OpNode, _> {
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1032 let mayLoad = 1 in {
1033 def rmb : AVX512BI<opc, MRMSrcMem,
1034 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2),
1035 !strconcat(OpcodeStr, "\t{${src2}", _.BroadcastStr, ", $src1, $dst",
1036 "|$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1037 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1038 (X86VBroadcast (_.ScalarLdFrag addr:$src2))))],
1039 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1040 def rmbk : AVX512BI<opc, MRMSrcMem,
1041 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1042 _.ScalarMemOp:$src2),
1043 !strconcat(OpcodeStr,
1044 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1045 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1046 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1047 (OpNode (_.VT _.RC:$src1),
1048 (X86VBroadcast
1049 (_.ScalarLdFrag addr:$src2)))))],
1050 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1051 }
1052}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1053
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1054multiclass avx512_icmp_packed_vl<bits<8> opc, string OpcodeStr, SDNode OpNode,
1055 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1056 let Predicates = [prd] in
1057 defm Z : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info512>,
1058 EVEX_V512;
1059
1060 let Predicates = [prd, HasVLX] in {
1061 defm Z256 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info256>,
1062 EVEX_V256;
1063 defm Z128 : avx512_icmp_packed<opc, OpcodeStr, OpNode, VTInfo.info128>,
1064 EVEX_V128;
1065 }
1066}
1067
1068multiclass avx512_icmp_packed_rmb_vl<bits<8> opc, string OpcodeStr,
1069 SDNode OpNode, AVX512VLVectorVTInfo VTInfo,
1070 Predicate prd> {
1071 let Predicates = [prd] in
1072 defm Z : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info512>,
1073 EVEX_V512;
1074
1075 let Predicates = [prd, HasVLX] in {
1076 defm Z256 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info256>,
1077 EVEX_V256;
1078 defm Z128 : avx512_icmp_packed_rmb<opc, OpcodeStr, OpNode, VTInfo.info128>,
1079 EVEX_V128;
1080 }
1081}
1082
1083defm VPCMPEQB : avx512_icmp_packed_vl<0x74, "vpcmpeqb", X86pcmpeqm,
1084 avx512vl_i8_info, HasBWI>,
1085 EVEX_CD8<8, CD8VF>;
1086
1087defm VPCMPEQW : avx512_icmp_packed_vl<0x75, "vpcmpeqw", X86pcmpeqm,
1088 avx512vl_i16_info, HasBWI>,
1089 EVEX_CD8<16, CD8VF>;
1090
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1091defm VPCMPEQD : avx512_icmp_packed_rmb_vl<0x76, "vpcmpeqd", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1092 avx512vl_i32_info, HasAVX512>,
1093 EVEX_CD8<32, CD8VF>;
1094
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1095defm VPCMPEQQ : avx512_icmp_packed_rmb_vl<0x29, "vpcmpeqq", X86pcmpeqm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1096 avx512vl_i64_info, HasAVX512>,
1097 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
1098
1099defm VPCMPGTB : avx512_icmp_packed_vl<0x64, "vpcmpgtb", X86pcmpgtm,
1100 avx512vl_i8_info, HasBWI>,
1101 EVEX_CD8<8, CD8VF>;
1102
1103defm VPCMPGTW : avx512_icmp_packed_vl<0x65, "vpcmpgtw", X86pcmpgtm,
1104 avx512vl_i16_info, HasBWI>,
1105 EVEX_CD8<16, CD8VF>;
1106
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1107defm VPCMPGTD : avx512_icmp_packed_rmb_vl<0x66, "vpcmpgtd", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1108 avx512vl_i32_info, HasAVX512>,
1109 EVEX_CD8<32, CD8VF>;
1110
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1111defm VPCMPGTQ : avx512_icmp_packed_rmb_vl<0x37, "vpcmpgtq", X86pcmpgtm,
Robert Khasanov2ea081d2014-08-25 14:49:34 +0000[diff] [blame]1112 avx512vl_i64_info, HasAVX512>,
1113 T8PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1114
1115def : Pat<(v8i1 (X86pcmpgtm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1116 (COPY_TO_REGCLASS (VPCMPGTDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1117 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1118 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1119
1120def : Pat<(v8i1 (X86pcmpeqm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2))),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1121 (COPY_TO_REGCLASS (VPCMPEQDZrr
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1122 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1123 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm))), VK8)>;
1124
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1125multiclass avx512_icmp_cc<bits<8> opc, string Suffix, SDNode OpNode,
1126 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1127 def rri : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1128 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1129 !strconcat("vpcmp${cc}", Suffix,
1130 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1131 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1132 imm:$cc))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1133 IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1134 let mayLoad = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1135 def rmi : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1136 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, AVXCC:$cc),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1137 !strconcat("vpcmp${cc}", Suffix,
1138 "\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1139 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1140 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1141 imm:$cc))],
1142 IIC_SSE_ALU_F32P_RM>, EVEX_4V;
1143 def rrik : AVX512AIi8<opc, MRMSrcReg,
1144 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1145 AVXCC:$cc),
1146 !strconcat("vpcmp${cc}", Suffix,
1147 "\t{$src2, $src1, $dst {${mask}}|",
1148 "$dst {${mask}}, $src1, $src2}"),
1149 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1150 (OpNode (_.VT _.RC:$src1), (_.VT _.RC:$src2),
1151 imm:$cc)))],
1152 IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1153 let mayLoad = 1 in
1154 def rmik : AVX512AIi8<opc, MRMSrcMem,
1155 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1156 AVXCC:$cc),
1157 !strconcat("vpcmp${cc}", Suffix,
1158 "\t{$src2, $src1, $dst {${mask}}|",
1159 "$dst {${mask}}, $src1, $src2}"),
1160 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1161 (OpNode (_.VT _.RC:$src1),
1162 (_.VT (bitconvert (_.LdFrag addr:$src2))),
1163 imm:$cc)))],
1164 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
1165
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1166 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1167 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1168 def rri_alt : AVX512AIi8<opc, MRMSrcReg,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1169 (outs _.KRC:$dst), (ins _.RC:$src1, _.RC:$src2, i8imm:$cc),
1170 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1171 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1172 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1173 def rmi_alt : AVX512AIi8<opc, MRMSrcMem,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1174 (outs _.KRC:$dst), (ins _.RC:$src1, _.MemOp:$src2, i8imm:$cc),
1175 !strconcat("vpcmp", Suffix, "\t{$cc, $src2, $src1, $dst|",
1176 "$dst, $src1, $src2, $cc}"),
Adam Nemet1efcb902014-07-01 18:03:43 +0000[diff] [blame]1177 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V;
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1178 def rrik_alt : AVX512AIi8<opc, MRMSrcReg,
1179 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.RC:$src2,
1180 i8imm:$cc),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1181 !strconcat("vpcmp", Suffix,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1182 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1183 "$dst {${mask}}, $src1, $src2, $cc}"),
1184 [], IIC_SSE_ALU_F32P_RR>, EVEX_4V, EVEX_K;
1185 def rmik_alt : AVX512AIi8<opc, MRMSrcMem,
1186 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1, _.MemOp:$src2,
1187 i8imm:$cc),
1188 !strconcat("vpcmp", Suffix,
1189 "\t{$cc, $src2, $src1, $dst {${mask}}|",
1190 "$dst {${mask}}, $src1, $src2, $cc}"),
Adam Nemet16de2482014-07-01 18:03:45 +0000[diff] [blame]1191 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1192 }
1193}
1194
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1195multiclass avx512_icmp_cc_rmb<bits<8> opc, string Suffix, SDNode OpNode,
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1196 X86VectorVTInfo _> :
1197 avx512_icmp_cc<opc, Suffix, OpNode, _> {
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1198 let mayLoad = 1 in {
1199 def rmib : AVX512AIi8<opc, MRMSrcMem,
1200 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1201 AVXCC:$cc),
1202 !strconcat("vpcmp${cc}", Suffix,
1203 "\t{${src2}", _.BroadcastStr, ", $src1, $dst|",
1204 "$dst, $src1, ${src2}", _.BroadcastStr, "}"),
1205 [(set _.KRC:$dst, (OpNode (_.VT _.RC:$src1),
1206 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1207 imm:$cc))],
1208 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1209 def rmibk : AVX512AIi8<opc, MRMSrcMem,
1210 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1211 _.ScalarMemOp:$src2, AVXCC:$cc),
1212 !strconcat("vpcmp${cc}", Suffix,
1213 "\t{${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1214 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, "}"),
1215 [(set _.KRC:$dst, (and _.KRCWM:$mask,
1216 (OpNode (_.VT _.RC:$src1),
1217 (X86VBroadcast (_.ScalarLdFrag addr:$src2)),
1218 imm:$cc)))],
1219 IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1220 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1221
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1222 // Accept explicit immediate argument form instead of comparison code.
1223 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1224 def rmib_alt : AVX512AIi8<opc, MRMSrcMem,
1225 (outs _.KRC:$dst), (ins _.RC:$src1, _.ScalarMemOp:$src2,
1226 i8imm:$cc),
1227 !strconcat("vpcmp", Suffix,
1228 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst|",
1229 "$dst, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1230 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_B;
1231 def rmibk_alt : AVX512AIi8<opc, MRMSrcMem,
1232 (outs _.KRC:$dst), (ins _.KRCWM:$mask, _.RC:$src1,
1233 _.ScalarMemOp:$src2, i8imm:$cc),
1234 !strconcat("vpcmp", Suffix,
1235 "\t{$cc, ${src2}", _.BroadcastStr, ", $src1, $dst {${mask}}|",
1236 "$dst {${mask}}, $src1, ${src2}", _.BroadcastStr, ", $cc}"),
1237 [], IIC_SSE_ALU_F32P_RM>, EVEX_4V, EVEX_K, EVEX_B;
1238 }
1239}
1240
1241multiclass avx512_icmp_cc_vl<bits<8> opc, string Suffix, SDNode OpNode,
1242 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1243 let Predicates = [prd] in
1244 defm Z : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info512>, EVEX_V512;
1245
1246 let Predicates = [prd, HasVLX] in {
1247 defm Z256 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info256>, EVEX_V256;
1248 defm Z128 : avx512_icmp_cc<opc, Suffix, OpNode, VTInfo.info128>, EVEX_V128;
1249 }
1250}
1251
1252multiclass avx512_icmp_cc_rmb_vl<bits<8> opc, string Suffix, SDNode OpNode,
1253 AVX512VLVectorVTInfo VTInfo, Predicate prd> {
1254 let Predicates = [prd] in
1255 defm Z : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info512>,
1256 EVEX_V512;
1257
1258 let Predicates = [prd, HasVLX] in {
1259 defm Z256 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info256>,
1260 EVEX_V256;
1261 defm Z128 : avx512_icmp_cc_rmb<opc, Suffix, OpNode, VTInfo.info128>,
1262 EVEX_V128;
1263 }
1264}
1265
1266defm VPCMPB : avx512_icmp_cc_vl<0x3F, "b", X86cmpm, avx512vl_i8_info,
1267 HasBWI>, EVEX_CD8<8, CD8VF>;
1268defm VPCMPUB : avx512_icmp_cc_vl<0x3E, "ub", X86cmpmu, avx512vl_i8_info,
1269 HasBWI>, EVEX_CD8<8, CD8VF>;
1270
1271defm VPCMPW : avx512_icmp_cc_vl<0x3F, "w", X86cmpm, avx512vl_i16_info,
1272 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1273defm VPCMPUW : avx512_icmp_cc_vl<0x3E, "uw", X86cmpmu, avx512vl_i16_info,
1274 HasBWI>, VEX_W, EVEX_CD8<16, CD8VF>;
1275
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1276defm VPCMPD : avx512_icmp_cc_rmb_vl<0x1F, "d", X86cmpm, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1277 HasAVX512>, EVEX_CD8<32, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1278defm VPCMPUD : avx512_icmp_cc_rmb_vl<0x1E, "ud", X86cmpmu, avx512vl_i32_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1279 HasAVX512>, EVEX_CD8<32, CD8VF>;
1280
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1281defm VPCMPQ : avx512_icmp_cc_rmb_vl<0x1F, "q", X86cmpm, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1282 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Robert Khasanovf70f7982014-09-18 14:06:55 +0000[diff] [blame]1283defm VPCMPUQ : avx512_icmp_cc_rmb_vl<0x1E, "uq", X86cmpmu, avx512vl_i64_info,
Robert Khasanov29e3b962014-08-27 09:34:37 +0000[diff] [blame]1284 HasAVX512>, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1285
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1286// avx512_cmp_packed - compare packed instructions
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1287multiclass avx512_cmp_packed<RegisterClass KRC, RegisterClass RC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1288 X86MemOperand x86memop, ValueType vt,
1289 string suffix, Domain d> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1290 def rri : AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1291 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
1292 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1293 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1294 [(set KRC:$dst, (X86cmpm (vt RC:$src1), (vt RC:$src2), imm:$cc))], d>;
1295 def rrib: AVX512PIi8<0xC2, MRMSrcReg,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1296 (outs KRC:$dst), (ins RC:$src1, RC:$src2, AVXCC:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1297 !strconcat("vcmp${cc}", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1298 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1299 [], d>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1300 def rmi : AVX512PIi8<0xC2, MRMSrcMem,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1301 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, AVXCC:$cc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1302 !strconcat("vcmp${cc}", suffix,
1303 " \t{$src2, $src1, $dst|$dst, $src1, $src2, $cc}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1304 [(set KRC:$dst,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1305 (X86cmpm (vt RC:$src1), (memop addr:$src2), imm:$cc))], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1306
1307 // Accept explicit immediate argument form instead of comparison code.
Craig Topper0550ce72014-01-05 04:55:55 +0000[diff] [blame]1308 let isAsmParserOnly = 1, hasSideEffects = 0 in {
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1309 def rri_alt : AVX512PIi8<0xC2, MRMSrcReg,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1310 (outs KRC:$dst), (ins RC:$src1, RC:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1311 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1312 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Craig Toppera328ee42013-10-09 04:24:38 +0000[diff] [blame]1313 def rmi_alt : AVX512PIi8<0xC2, MRMSrcMem,
Adam Nemet905832b2014-06-26 00:21:12 +0000[diff] [blame]1314 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2, i8imm:$cc),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1315 !strconcat("vcmp", suffix,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1316 " \t{$cc, $src2, $src1, $dst|$dst, $src1, $src2, $cc}"), [], d>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1317 }
1318}
1319
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1320defm VCMPPSZ : avx512_cmp_packed<VK16, VR512, f512mem, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1321 "ps", SSEPackedSingle>, PS, EVEX_4V, EVEX_V512,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]1322 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1323defm VCMPPDZ : avx512_cmp_packed<VK8, VR512, f512mem, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1324 "pd", SSEPackedDouble>, PD, EVEX_4V, VEX_W, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1325 EVEX_CD8<64, CD8VF>;
1326
1327def : Pat<(v8i1 (X86cmpm (v8f32 VR256X:$src1), (v8f32 VR256X:$src2), imm:$cc)),
1328 (COPY_TO_REGCLASS (VCMPPSZrri
1329 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1330 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1331 imm:$cc), VK8)>;
1332def : Pat<(v8i1 (X86cmpm (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1333 (COPY_TO_REGCLASS (VPCMPDZrri
1334 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1335 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1336 imm:$cc), VK8)>;
1337def : Pat<(v8i1 (X86cmpmu (v8i32 VR256X:$src1), (v8i32 VR256X:$src2), imm:$cc)),
1338 (COPY_TO_REGCLASS (VPCMPUDZrri
1339 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)),
1340 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src2, sub_ymm)),
1341 imm:$cc), VK8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1342
1343def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1344 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1345 FROUND_NO_EXC)),
1346 (COPY_TO_REGCLASS (VCMPPSZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1347 (I8Imm imm:$cc)), GR16)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1348
1349def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1350 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1351 FROUND_NO_EXC)),
1352 (COPY_TO_REGCLASS (VCMPPDZrrib VR512:$src1, VR512:$src2,
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1353 (I8Imm imm:$cc)), GR8)>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]1354
1355def : Pat<(i16 (int_x86_avx512_mask_cmp_ps_512 (v16f32 VR512:$src1),
1356 (v16f32 VR512:$src2), imm:$cc, (i16 -1),
1357 FROUND_CURRENT)),
1358 (COPY_TO_REGCLASS (VCMPPSZrri VR512:$src1, VR512:$src2,
1359 (I8Imm imm:$cc)), GR16)>;
1360
1361def : Pat<(i8 (int_x86_avx512_mask_cmp_pd_512 (v8f64 VR512:$src1),
1362 (v8f64 VR512:$src2), imm:$cc, (i8 -1),
1363 FROUND_CURRENT)),
1364 (COPY_TO_REGCLASS (VCMPPDZrri VR512:$src1, VR512:$src2,
1365 (I8Imm imm:$cc)), GR8)>;
1366
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1367// Mask register copy, including
1368// - copy between mask registers
1369// - load/store mask registers
1370// - copy from GPR to mask register and vice versa
1371//
1372multiclass avx512_mask_mov<bits<8> opc_kk, bits<8> opc_km, bits<8> opc_mk,
1373 string OpcodeStr, RegisterClass KRC,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1374 ValueType vvt, ValueType ivt, X86MemOperand x86memop> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1375 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1376 def kk : I<opc_kk, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1377 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1378 let mayLoad = 1 in
1379 def km : I<opc_km, MRMSrcMem, (outs KRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1380 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1381 [(set KRC:$dst, (vvt (bitconvert (ivt (load addr:$src)))))]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1382 let mayStore = 1 in
1383 def mk : I<opc_mk, MRMDestMem, (outs), (ins x86memop:$dst, KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1384 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1385 }
1386}
1387
1388multiclass avx512_mask_mov_gpr<bits<8> opc_kr, bits<8> opc_rk,
1389 string OpcodeStr,
1390 RegisterClass KRC, RegisterClass GRC> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]1391 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1392 def kr : I<opc_kr, MRMSrcReg, (outs KRC:$dst), (ins GRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1393 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1394 def rk : I<opc_rk, MRMSrcReg, (outs GRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1395 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1396 }
1397}
1398
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1399let Predicates = [HasDQI] in
1400 defm KMOVB : avx512_mask_mov<0x90, 0x90, 0x91, "kmovb", VK8, v8i1, i8,
1401 i8mem>,
1402 avx512_mask_mov_gpr<0x92, 0x93, "kmovb", VK8, GR32>,
1403 VEX, PD;
1404
1405let Predicates = [HasAVX512] in
1406 defm KMOVW : avx512_mask_mov<0x90, 0x90, 0x91, "kmovw", VK16, v16i1, i16,
1407 i16mem>,
1408 avx512_mask_mov_gpr<0x92, 0x93, "kmovw", VK16, GR32>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1409 VEX, PS;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1410
1411let Predicates = [HasBWI] in {
1412 defm KMOVD : avx512_mask_mov<0x90, 0x90, 0x91, "kmovd", VK32, v32i1, i32,
1413 i32mem>, VEX, PD, VEX_W;
1414 defm KMOVD : avx512_mask_mov_gpr<0x92, 0x93, "kmovd", VK32, GR32>,
1415 VEX, XD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1416}
1417
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1418let Predicates = [HasBWI] in {
1419 defm KMOVQ : avx512_mask_mov<0x90, 0x90, 0x91, "kmovq", VK64, v64i1, i64,
1420 i64mem>, VEX, PS, VEX_W;
1421 defm KMOVQ : avx512_mask_mov_gpr<0x92, 0x93, "kmovq", VK64, GR64>,
1422 VEX, XD, VEX_W;
1423}
1424
1425// GR from/to mask register
1426let Predicates = [HasDQI] in {
1427 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1428 (KMOVBkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit))>;
1429 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1430 (EXTRACT_SUBREG (KMOVBrk VK8:$src), sub_8bit)>;
1431}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1432let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1433 def : Pat<(v16i1 (bitconvert (i16 GR16:$src))),
1434 (KMOVWkr (SUBREG_TO_REG (i32 0), GR16:$src, sub_16bit))>;
1435 def : Pat<(i16 (bitconvert (v16i1 VK16:$src))),
1436 (EXTRACT_SUBREG (KMOVWrk VK16:$src), sub_16bit)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1437}
1438let Predicates = [HasBWI] in {
1439 def : Pat<(v32i1 (bitconvert (i32 GR32:$src))), (KMOVDkr GR32:$src)>;
1440 def : Pat<(i32 (bitconvert (v32i1 VK32:$src))), (KMOVDrk VK32:$src)>;
1441}
1442let Predicates = [HasBWI] in {
1443 def : Pat<(v64i1 (bitconvert (i64 GR64:$src))), (KMOVQkr GR64:$src)>;
1444 def : Pat<(i64 (bitconvert (v64i1 VK64:$src))), (KMOVQrk VK64:$src)>;
1445}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1446
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1447// Load/store kreg
1448let Predicates = [HasDQI] in {
1449 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
1450 (KMOVBmk addr:$dst, VK8:$src)>;
1451}
1452let Predicates = [HasAVX512] in {
1453 def : Pat<(store (i16 (bitconvert (v16i1 VK16:$src))), addr:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1454 (KMOVWmk addr:$dst, VK16:$src)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1455 def : Pat<(store (i8 (bitconvert (v8i1 VK8:$src))), addr:$dst),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1456 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK8:$src, VK16))>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1457 def : Pat<(i1 (load addr:$src)),
1458 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1459 def : Pat<(v8i1 (bitconvert (i8 (load addr:$src)))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1460 (COPY_TO_REGCLASS (KMOVWkm addr:$src), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1461}
1462let Predicates = [HasBWI] in {
1463 def : Pat<(store (i32 (bitconvert (v32i1 VK32:$src))), addr:$dst),
1464 (KMOVDmk addr:$dst, VK32:$src)>;
1465}
1466let Predicates = [HasBWI] in {
1467 def : Pat<(store (i64 (bitconvert (v64i1 VK64:$src))), addr:$dst),
1468 (KMOVQmk addr:$dst, VK64:$src)>;
1469}
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1470
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1471let Predicates = [HasAVX512] in {
Elena Demikhovsky34d2d762014-08-18 11:59:06 +0000[diff] [blame]1472 def : Pat<(i1 (trunc (i64 GR64:$src))),
1473 (COPY_TO_REGCLASS (KMOVWkr (AND32ri (EXTRACT_SUBREG $src, sub_32bit),
1474 (i32 1))), VK1)>;
1475
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1476 def : Pat<(i1 (trunc (i32 GR32:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1477 (COPY_TO_REGCLASS (KMOVWkr (AND32ri $src, (i32 1))), VK1)>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1478
1479 def : Pat<(i1 (trunc (i8 GR8:$src))),
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000[diff] [blame]1480 (COPY_TO_REGCLASS
1481 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit), (i32 1))),
1482 VK1)>;
1483 def : Pat<(i1 (trunc (i16 GR16:$src))),
1484 (COPY_TO_REGCLASS
1485 (KMOVWkr (AND32ri (SUBREG_TO_REG (i32 0), $src, sub_16bit), (i32 1))),
1486 VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1487
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1488 def : Pat<(i32 (zext VK1:$src)),
1489 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1))>;
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1490 def : Pat<(i8 (zext VK1:$src)),
1491 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1492 (AND32ri (KMOVWrk
1493 (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)), sub_8bit)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1494 def : Pat<(i64 (zext VK1:$src)),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1495 (AND64ri8 (SUBREG_TO_REG (i64 0),
1496 (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), sub_32bit), (i64 1))>;
Elena Demikhovsky750498c2014-02-17 07:29:33 +0000[diff] [blame]1497 def : Pat<(i16 (zext VK1:$src)),
1498 (EXTRACT_SUBREG
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]1499 (AND32ri (KMOVWrk (COPY_TO_REGCLASS VK1:$src, VK16)), (i32 1)),
1500 sub_16bit)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]1501 def : Pat<(v16i1 (scalar_to_vector VK1:$src)),
1502 (COPY_TO_REGCLASS VK1:$src, VK16)>;
1503 def : Pat<(v8i1 (scalar_to_vector VK1:$src)),
1504 (COPY_TO_REGCLASS VK1:$src, VK8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1505}
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1506let Predicates = [HasBWI] in {
1507 def : Pat<(v32i1 (scalar_to_vector VK1:$src)),
1508 (COPY_TO_REGCLASS VK1:$src, VK32)>;
1509 def : Pat<(v64i1 (scalar_to_vector VK1:$src)),
1510 (COPY_TO_REGCLASS VK1:$src, VK64)>;
1511}
1512
1513
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1514// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1515let Predicates = [HasAVX512] in {
1516 // GR from/to 8-bit mask without native support
1517 def : Pat<(v8i1 (bitconvert (i8 GR8:$src))),
1518 (COPY_TO_REGCLASS
1519 (KMOVWkr (SUBREG_TO_REG (i32 0), GR8:$src, sub_8bit)),
1520 VK8)>;
1521 def : Pat<(i8 (bitconvert (v8i1 VK8:$src))),
1522 (EXTRACT_SUBREG
1523 (KMOVWrk (COPY_TO_REGCLASS VK8:$src, VK16)),
1524 sub_8bit)>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1525
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1526 def : Pat<(i1 (X86Vextract VK16:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1527 (COPY_TO_REGCLASS VK16:$src, VK1)>;
Elena Demikhovsky9f423d62014-02-10 07:02:39 +0000[diff] [blame]1528 def : Pat<(i1 (X86Vextract VK8:$src, (iPTR 0))),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1529 (COPY_TO_REGCLASS VK8:$src, VK1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1530}
1531let Predicates = [HasBWI] in {
1532 def : Pat<(i1 (X86Vextract VK32:$src, (iPTR 0))),
1533 (COPY_TO_REGCLASS VK32:$src, VK1)>;
1534 def : Pat<(i1 (X86Vextract VK64:$src, (iPTR 0))),
1535 (COPY_TO_REGCLASS VK64:$src, VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1536}
1537
1538// Mask unary operation
1539// - KNOT
1540multiclass avx512_mask_unop<bits<8> opc, string OpcodeStr,
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1541 RegisterClass KRC, SDPatternOperator OpNode,
1542 Predicate prd> {
1543 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1544 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1545 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1546 [(set KRC:$dst, (OpNode KRC:$src))]>;
1547}
1548
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1549multiclass avx512_mask_unop_all<bits<8> opc, string OpcodeStr,
1550 SDPatternOperator OpNode> {
1551 defm B : avx512_mask_unop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1552 HasDQI>, VEX, PD;
1553 defm W : avx512_mask_unop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1554 HasAVX512>, VEX, PS;
1555 defm D : avx512_mask_unop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1556 HasBWI>, VEX, PD, VEX_W;
1557 defm Q : avx512_mask_unop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1558 HasBWI>, VEX, PS, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1559}
1560
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1561defm KNOT : avx512_mask_unop_all<0x44, "knot", not>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1562
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1563multiclass avx512_mask_unop_int<string IntName, string InstName> {
1564 let Predicates = [HasAVX512] in
1565 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1566 (i16 GR16:$src)),
1567 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1568 (v16i1 (COPY_TO_REGCLASS GR16:$src, VK16))), GR16)>;
1569}
1570defm : avx512_mask_unop_int<"knot", "KNOT">;
1571
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1572let Predicates = [HasDQI] in
1573def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)), (KNOTBrr VK8:$src1)>;
1574let Predicates = [HasAVX512] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1575def : Pat<(xor VK16:$src1, (v16i1 immAllOnesV)), (KNOTWrr VK16:$src1)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1576let Predicates = [HasBWI] in
1577def : Pat<(xor VK32:$src1, (v32i1 immAllOnesV)), (KNOTDrr VK32:$src1)>;
1578let Predicates = [HasBWI] in
1579def : Pat<(xor VK64:$src1, (v64i1 immAllOnesV)), (KNOTQrr VK64:$src1)>;
1580
1581// KNL does not support KMOVB, 8-bit mask is promoted to 16-bit
1582let Predicates = [HasAVX512] in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1583def : Pat<(xor VK8:$src1, (v8i1 immAllOnesV)),
1584 (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$src1, VK16)), VK8)>;
1585
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1586def : Pat<(not VK8:$src),
1587 (COPY_TO_REGCLASS
1588 (KNOTWrr (COPY_TO_REGCLASS VK8:$src, VK16)), VK8)>;
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]1589}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1590
1591// Mask binary operation
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1592// - KAND, KANDN, KOR, KXNOR, KXOR
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1593multiclass avx512_mask_binop<bits<8> opc, string OpcodeStr,
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1594 RegisterClass KRC, SDPatternOperator OpNode,
1595 Predicate prd> {
1596 let Predicates = [prd] in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1597 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
1598 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1599 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1600 [(set KRC:$dst, (OpNode KRC:$src1, KRC:$src2))]>;
1601}
1602
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1603multiclass avx512_mask_binop_all<bits<8> opc, string OpcodeStr,
1604 SDPatternOperator OpNode> {
1605 defm B : avx512_mask_binop<opc, !strconcat(OpcodeStr, "b"), VK8, OpNode,
1606 HasDQI>, VEX_4V, VEX_L, PD;
1607 defm W : avx512_mask_binop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode,
1608 HasAVX512>, VEX_4V, VEX_L, PS;
1609 defm D : avx512_mask_binop<opc, !strconcat(OpcodeStr, "d"), VK32, OpNode,
1610 HasBWI>, VEX_4V, VEX_L, VEX_W, PD;
1611 defm Q : avx512_mask_binop<opc, !strconcat(OpcodeStr, "q"), VK64, OpNode,
1612 HasBWI>, VEX_4V, VEX_L, VEX_W, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1613}
1614
1615def andn : PatFrag<(ops node:$i0, node:$i1), (and (not node:$i0), node:$i1)>;
1616def xnor : PatFrag<(ops node:$i0, node:$i1), (not (xor node:$i0, node:$i1))>;
1617
1618let isCommutable = 1 in {
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1619 defm KAND : avx512_mask_binop_all<0x41, "kand", and>;
1620 defm KOR : avx512_mask_binop_all<0x45, "kor", or>;
1621 defm KXNOR : avx512_mask_binop_all<0x46, "kxnor", xnor>;
1622 defm KXOR : avx512_mask_binop_all<0x47, "kxor", xor>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1623}
Robert Khasanov595683d2014-07-28 13:46:45 +0000[diff] [blame]1624let isCommutable = 0 in
1625 defm KANDN : avx512_mask_binop_all<0x42, "kandn", andn>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1626
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1627def : Pat<(xor VK1:$src1, VK1:$src2),
1628 (COPY_TO_REGCLASS (KXORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1629 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1630
1631def : Pat<(or VK1:$src1, VK1:$src2),
1632 (COPY_TO_REGCLASS (KORWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1633 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1634
Elena Demikhovskyb64d7e82013-12-25 10:06:40 +0000[diff] [blame]1635def : Pat<(and VK1:$src1, VK1:$src2),
1636 (COPY_TO_REGCLASS (KANDWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
1637 (COPY_TO_REGCLASS VK1:$src2, VK16)), VK1)>;
1638
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1639multiclass avx512_mask_binop_int<string IntName, string InstName> {
1640 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1641 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_w")
1642 (i16 GR16:$src1), (i16 GR16:$src2)),
1643 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"Wrr")
1644 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1645 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1646}
1647
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1648defm : avx512_mask_binop_int<"kand", "KAND">;
1649defm : avx512_mask_binop_int<"kandn", "KANDN">;
1650defm : avx512_mask_binop_int<"kor", "KOR">;
1651defm : avx512_mask_binop_int<"kxnor", "KXNOR">;
1652defm : avx512_mask_binop_int<"kxor", "KXOR">;
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1653
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1654// With AVX-512, 8-bit mask is promoted to 16-bit mask.
1655multiclass avx512_binop_pat<SDPatternOperator OpNode, Instruction Inst> {
1656 let Predicates = [HasAVX512] in
1657 def : Pat<(OpNode VK8:$src1, VK8:$src2),
1658 (COPY_TO_REGCLASS
1659 (Inst (COPY_TO_REGCLASS VK8:$src1, VK16),
1660 (COPY_TO_REGCLASS VK8:$src2, VK16)), VK8)>;
1661}
1662
1663defm : avx512_binop_pat<and, KANDWrr>;
1664defm : avx512_binop_pat<andn, KANDNWrr>;
1665defm : avx512_binop_pat<or, KORWrr>;
1666defm : avx512_binop_pat<xnor, KXNORWrr>;
1667defm : avx512_binop_pat<xor, KXORWrr>;
1668
1669// Mask unpacking
1670multiclass avx512_mask_unpck<bits<8> opc, string OpcodeStr,
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1671 RegisterClass KRC> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1672 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1673 def rr : I<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1674 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1675 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1676}
1677
1678multiclass avx512_mask_unpck_bw<bits<8> opc, string OpcodeStr> {
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1679 defm BW : avx512_mask_unpck<opc, !strconcat(OpcodeStr, "bw"), VK16>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1680 VEX_4V, VEX_L, PD;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1681}
1682
1683defm KUNPCK : avx512_mask_unpck_bw<0x4b, "kunpck">;
Elena Demikhovskyc5f67262013-12-17 08:33:15 +0000[diff] [blame]1684def : Pat<(v16i1 (concat_vectors (v8i1 VK8:$src1), (v8i1 VK8:$src2))),
1685 (KUNPCKBWrr (COPY_TO_REGCLASS VK8:$src2, VK16),
1686 (COPY_TO_REGCLASS VK8:$src1, VK16))>;
1687
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1688
1689multiclass avx512_mask_unpck_int<string IntName, string InstName> {
1690 let Predicates = [HasAVX512] in
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1691 def : Pat<(!cast<Intrinsic>("int_x86_avx512_"##IntName##"_bw")
1692 (i16 GR16:$src1), (i16 GR16:$src2)),
1693 (COPY_TO_REGCLASS (!cast<Instruction>(InstName##"BWrr")
1694 (v16i1 (COPY_TO_REGCLASS GR16:$src1, VK16)),
1695 (v16i1 (COPY_TO_REGCLASS GR16:$src2, VK16))), GR16)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1696}
Elena Demikhovskye382c3f2013-12-10 13:53:10 +0000[diff] [blame]1697defm : avx512_mask_unpck_int<"kunpck", "KUNPCK">;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1698
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1699// Mask bit testing
1700multiclass avx512_mask_testop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1701 SDNode OpNode> {
1702 let Predicates = [HasAVX512], Defs = [EFLAGS] in
1703 def rr : I<opc, MRMSrcReg, (outs), (ins KRC:$src1, KRC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1704 !strconcat(OpcodeStr, " \t{$src2, $src1|$src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1705 [(set EFLAGS, (OpNode KRC:$src1, KRC:$src2))]>;
1706}
1707
1708multiclass avx512_mask_testop_w<bits<8> opc, string OpcodeStr, SDNode OpNode> {
1709 defm W : avx512_mask_testop<opc, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]1710 VEX, PS;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1711}
1712
1713defm KORTEST : avx512_mask_testop_w<0x98, "kortest", X86kortest>;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1714
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1715def : Pat<(X86cmp VK1:$src1, (i1 0)),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1716 (KORTESTWrr (COPY_TO_REGCLASS VK1:$src1, VK16),
Elena Demikhovsky64c95482013-12-24 14:24:07 +0000[diff] [blame]1717 (COPY_TO_REGCLASS VK1:$src1, VK16))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1718
1719// Mask shift
1720multiclass avx512_mask_shiftop<bits<8> opc, string OpcodeStr, RegisterClass KRC,
1721 SDNode OpNode> {
1722 let Predicates = [HasAVX512] in
1723 def ri : Ii8<opc, MRMSrcReg, (outs KRC:$dst), (ins KRC:$src, i8imm:$imm),
1724 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]1725 " \t{$imm, $src, $dst|$dst, $src, $imm}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1726 [(set KRC:$dst, (OpNode KRC:$src, (i8 imm:$imm)))]>;
1727}
1728
1729multiclass avx512_mask_shiftop_w<bits<8> opc1, bits<8> opc2, string OpcodeStr,
1730 SDNode OpNode> {
1731 defm W : avx512_mask_shiftop<opc1, !strconcat(OpcodeStr, "w"), VK16, OpNode>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]1732 VEX, TAPD, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1733}
1734
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1735defm KSHIFTL : avx512_mask_shiftop_w<0x32, 0x33, "kshiftl", X86vshli>;
1736defm KSHIFTR : avx512_mask_shiftop_w<0x30, 0x31, "kshiftr", X86vsrli>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1737
1738// Mask setting all 0s or 1s
1739multiclass avx512_mask_setop<RegisterClass KRC, ValueType VT, PatFrag Val> {
1740 let Predicates = [HasAVX512] in
1741 let isReMaterializable = 1, isAsCheapAsAMove = 1, isPseudo = 1 in
1742 def #NAME# : I<0, Pseudo, (outs KRC:$dst), (ins), "",
1743 [(set KRC:$dst, (VT Val))]>;
1744}
1745
1746multiclass avx512_mask_setop_w<PatFrag Val> {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]1747 defm B : avx512_mask_setop<VK8, v8i1, Val>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1748 defm W : avx512_mask_setop<VK16, v16i1, Val>;
1749}
1750
1751defm KSET0 : avx512_mask_setop_w<immAllZerosV>;
1752defm KSET1 : avx512_mask_setop_w<immAllOnesV>;
1753
1754// With AVX-512 only, 8-bit mask is promoted to 16-bit mask.
1755let Predicates = [HasAVX512] in {
1756 def : Pat<(v8i1 immAllZerosV), (COPY_TO_REGCLASS (KSET0W), VK8)>;
1757 def : Pat<(v8i1 immAllOnesV), (COPY_TO_REGCLASS (KSET1W), VK8)>;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]1758 def : Pat<(i1 0), (COPY_TO_REGCLASS (KSET0W), VK1)>;
1759 def : Pat<(i1 1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
1760 def : Pat<(i1 -1), (COPY_TO_REGCLASS (KSET1W), VK1)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1761}
1762def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 0))),
1763 (v8i1 (COPY_TO_REGCLASS VK16:$src, VK8))>;
1764
1765def : Pat<(v16i1 (insert_subvector undef, (v8i1 VK8:$src), (iPTR 0))),
1766 (v16i1 (COPY_TO_REGCLASS VK8:$src, VK16))>;
1767
1768def : Pat<(v8i1 (extract_subvector (v16i1 VK16:$src), (iPTR 8))),
1769 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri VK16:$src, (i8 8)), VK8))>;
1770
Elena Demikhovsky9737e382014-03-02 09:19:44 +0000[diff] [blame]1771def : Pat<(v8i1 (X86vshli VK8:$src, (i8 imm:$imm))),
1772 (v8i1 (COPY_TO_REGCLASS (KSHIFTLWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
1773
1774def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
1775 (v8i1 (COPY_TO_REGCLASS (KSHIFTRWri (COPY_TO_REGCLASS VK8:$src, VK16), (I8Imm $imm)), VK8))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1776//===----------------------------------------------------------------------===//
1777// AVX-512 - Aligned and unaligned load and store
1778//
1779
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1780multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
1781 RegisterClass KRC, RegisterClass RC,
1782 ValueType vt, ValueType zvt, X86MemOperand memop,
1783 Domain d, bit IsReMaterializable = 1> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1784let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1785 def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1786 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
1787 d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1788 def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1789 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1790 "${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1791 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1792 let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
1793 SchedRW = [WriteLoad] in
1794 def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
1795 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1796 [(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
1797 d>, EVEX;
1798
1799 let AddedComplexity = 20 in {
1800 let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
1801 let hasSideEffects = 0 in
1802 def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
1803 (ins RC:$src0, KRC:$mask, RC:$src1),
1804 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1805 "${dst} {${mask}}, $src1}"),
1806 [(set RC:$dst, (vt (vselect KRC:$mask,
1807 (vt RC:$src1),
1808 (vt RC:$src0))))],
1809 d>, EVEX, EVEX_K;
1810 let mayLoad = 1, SchedRW = [WriteLoad] in
1811 def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1812 (ins RC:$src0, KRC:$mask, memop:$src1),
1813 !strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
1814 "${dst} {${mask}}, $src1}"),
1815 [(set RC:$dst, (vt
1816 (vselect KRC:$mask,
1817 (vt (bitconvert (ld_frag addr:$src1))),
1818 (vt RC:$src0))))],
1819 d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1820 }
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1821 let mayLoad = 1, SchedRW = [WriteLoad] in
1822 def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
1823 (ins KRC:$mask, memop:$src),
1824 !strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
1825 "${dst} {${mask}} {z}, $src}"),
1826 [(set RC:$dst, (vt
1827 (vselect KRC:$mask,
1828 (vt (bitconvert (ld_frag addr:$src))),
1829 (vt (bitconvert (zvt immAllZerosV))))))],
1830 d>, EVEX, EVEX_KZ;
1831 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1832}
1833
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1834multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
1835 string elty, string elsz, string vsz512,
1836 string vsz256, string vsz128, Domain d,
1837 Predicate prd, bit IsReMaterializable = 1> {
1838 let Predicates = [prd] in
1839 defm Z : avx512_load<opc, OpcodeStr,
1840 !cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
1841 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1842 !cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
1843 !cast<X86MemOperand>(elty##"512mem"), d,
1844 IsReMaterializable>, EVEX_V512;
1845
1846 let Predicates = [prd, HasVLX] in {
1847 defm Z256 : avx512_load<opc, OpcodeStr,
1848 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1849 "v"##vsz256##elty##elsz, "v4i64")),
1850 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1851 !cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
1852 !cast<X86MemOperand>(elty##"256mem"), d,
1853 IsReMaterializable>, EVEX_V256;
1854
1855 defm Z128 : avx512_load<opc, OpcodeStr,
1856 !cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
1857 "v"##vsz128##elty##elsz, "v2i64")),
1858 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1859 !cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
1860 !cast<X86MemOperand>(elty##"128mem"), d,
1861 IsReMaterializable>, EVEX_V128;
1862 }
1863}
1864
1865
1866multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
1867 ValueType OpVT, RegisterClass KRC, RegisterClass RC,
1868 X86MemOperand memop, Domain d> {
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1869 let isAsmParserOnly = 1, hasSideEffects = 0 in {
1870 def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1871 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1872 EVEX;
1873 let Constraints = "$src1 = $dst" in
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1874 def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
1875 (ins RC:$src1, KRC:$mask, RC:$src2),
1876 !strconcat(OpcodeStr,
1877 "\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1878 EVEX, EVEX_K;
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1879 def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1880 (ins KRC:$mask, RC:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1881 !strconcat(OpcodeStr,
1882 "\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1883 [], d>, EVEX, EVEX_KZ;
1884 }
1885 let mayStore = 1 in {
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1886 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
1887 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
1888 [(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1889 def mrk : AVX512PI<opc, MRMDestMem, (outs),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1890 (ins memop:$dst, KRC:$mask, RC:$src),
1891 !strconcat(OpcodeStr,
1892 "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1893 [], d>, EVEX, EVEX_K;
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1894 }
1895}
1896
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1897
1898multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
1899 string st_suff_512, string st_suff_256,
1900 string st_suff_128, string elty, string elsz,
1901 string vsz512, string vsz256, string vsz128,
1902 Domain d, Predicate prd> {
1903 let Predicates = [prd] in
1904 defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
1905 !cast<ValueType>("v"##vsz512##elty##elsz),
1906 !cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
1907 !cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
1908
1909 let Predicates = [prd, HasVLX] in {
1910 defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
1911 !cast<ValueType>("v"##vsz256##elty##elsz),
1912 !cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
1913 !cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
1914
1915 defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
1916 !cast<ValueType>("v"##vsz128##elty##elsz),
1917 !cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
1918 !cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
1919 }
1920}
1921
1922defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
1923 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1924 avx512_store_vl<0x29, "vmovaps", "alignedstore",
1925 "512", "256", "", "f", "32", "16", "8", "4",
1926 SSEPackedSingle, HasAVX512>,
1927 PS, EVEX_CD8<32, CD8VF>;
1928
1929defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
1930 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1931 avx512_store_vl<0x29, "vmovapd", "alignedstore",
1932 "512", "256", "", "f", "64", "8", "4", "2",
1933 SSEPackedDouble, HasAVX512>,
1934 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1935
1936defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
1937 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1938 avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
1939 "16", "8", "4", SSEPackedSingle, HasAVX512>,
1940 PS, EVEX_CD8<32, CD8VF>;
1941
1942defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
1943 "8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
1944 avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
1945 "8", "4", "2", SSEPackedDouble, HasAVX512>,
1946 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1947
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1948def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1949 (bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1950 (VMOVUPDZrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1951
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1952def: Pat<(v16f32 (int_x86_avx512_mask_loadu_ps_512 addr:$ptr,
1953 (bc_v16f32 (v16i32 immAllZerosV)), GR16:$mask)),
1954 (VMOVUPSZrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]1955
Elena Demikhovskyfd056672014-03-13 12:05:52 +0000[diff] [blame]1956def: Pat<(int_x86_avx512_mask_storeu_ps_512 addr:$ptr, (v16f32 VR512:$src),
1957 GR16:$mask),
1958 (VMOVUPSZmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
1959 VR512:$src)>;
1960def: Pat<(int_x86_avx512_mask_storeu_pd_512 addr:$ptr, (v8f64 VR512:$src),
1961 GR8:$mask),
1962 (VMOVUPDZmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
1963 VR512:$src)>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]1964
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]1965defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
1966 "16", "8", "4", SSEPackedInt, HasAVX512>,
1967 avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
1968 "512", "256", "", "i", "32", "16", "8", "4",
1969 SSEPackedInt, HasAVX512>,
1970 PD, EVEX_CD8<32, CD8VF>;
1971
1972defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
1973 "8", "4", "2", SSEPackedInt, HasAVX512>,
1974 avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
1975 "512", "256", "", "i", "64", "8", "4", "2",
1976 SSEPackedInt, HasAVX512>,
1977 PD, VEX_W, EVEX_CD8<64, CD8VF>;
1978
1979defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
1980 "64", "32", "16", SSEPackedInt, HasBWI>,
1981 avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
1982 "i", "8", "64", "32", "16", SSEPackedInt,
1983 HasBWI>, XD, EVEX_CD8<8, CD8VF>;
1984
1985defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
1986 "32", "16", "8", SSEPackedInt, HasBWI>,
1987 avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
1988 "i", "16", "32", "16", "8", SSEPackedInt,
1989 HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
1990
1991defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
1992 "16", "8", "4", SSEPackedInt, HasAVX512>,
1993 avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
1994 "i", "32", "16", "8", "4", SSEPackedInt,
1995 HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
1996
1997defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
1998 "8", "4", "2", SSEPackedInt, HasAVX512>,
1999 avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
2000 "i", "64", "8", "4", "2", SSEPackedInt,
2001 HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky1f3ed412013-10-22 09:19:28 +0000[diff] [blame]2002
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2003def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
2004 (v16i32 immAllZerosV), GR16:$mask)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2005 (VMOVDQU32Zrmkz (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2006
2007def: Pat<(v8i64 (int_x86_avx512_mask_loadu_q_512 addr:$ptr,
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2008 (bc_v8i64 (v16i32 immAllZerosV)), GR8:$mask)),
2009 (VMOVDQU64Zrmkz (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), addr:$ptr)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]2010
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2011def: Pat<(int_x86_avx512_mask_storeu_d_512 addr:$ptr, (v16i32 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2012 GR16:$mask),
2013 (VMOVDQU32Zmrk addr:$ptr, (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2014 VR512:$src)>;
2015def: Pat<(int_x86_avx512_mask_storeu_q_512 addr:$ptr, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2016 GR8:$mask),
2017 (VMOVDQU64Zmrk addr:$ptr, (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]2018 VR512:$src)>;
2019
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2020let AddedComplexity = 20 in {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2021def : Pat<(v8i64 (vselect VK8WM:$mask, (v8i64 VR512:$src),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2022 (bc_v8i64 (v16i32 immAllZerosV)))),
2023 (VMOVDQU64Zrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2024
2025def : Pat<(v8i64 (vselect VK8WM:$mask, (bc_v8i64 (v16i32 immAllZerosV)),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2026 (v8i64 VR512:$src))),
2027 (VMOVDQU64Zrrkz (COPY_TO_REGCLASS (KNOTWrr (COPY_TO_REGCLASS VK8:$mask, VK16)),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2028 VK8), VR512:$src)>;
2029
2030def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 VR512:$src),
2031 (v16i32 immAllZerosV))),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2032 (VMOVDQU32Zrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]2033
2034def : Pat<(v16i32 (vselect VK16WM:$mask, (v16i32 immAllZerosV),
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2035 (v16i32 VR512:$src))),
2036 (VMOVDQU32Zrrkz (KNOTWrr VK16WM:$mask), VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2037}
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]2038
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2039// Move Int Doubleword to Packed Double Int
2040//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2041def VMOVDI2PDIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2042 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2043 [(set VR128X:$dst,
2044 (v4i32 (scalar_to_vector GR32:$src)))], IIC_SSE_MOVDQ>,
2045 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2046def VMOVDI2PDIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2047 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2048 [(set VR128X:$dst,
2049 (v4i32 (scalar_to_vector (loadi32 addr:$src))))],
2050 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2051def VMOV64toPQIZrr : AVX512BI<0x6E, MRMSrcReg, (outs VR128X:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2052 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2053 [(set VR128X:$dst,
2054 (v2i64 (scalar_to_vector GR64:$src)))],
2055 IIC_SSE_MOVDQ>, EVEX, VEX_W, VEX_LIG;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2056let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2057def VMOV64toSDZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR64:$dst), (ins GR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2058 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2059 [(set FR64:$dst, (bitconvert GR64:$src))],
2060 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2061def VMOVSDto64Zrr : AVX512BI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2062 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2063 [(set GR64:$dst, (bitconvert FR64:$src))],
2064 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteMove]>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2065}
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2066def VMOVSDto64Zmr : AVX512BI<0x7E, MRMDestMem, (outs), (ins i64mem:$dst, FR64:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2067 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2068 [(store (i64 (bitconvert FR64:$src)), addr:$dst)],
2069 IIC_SSE_MOVDQ>, EVEX, VEX_W, Sched<[WriteStore]>,
2070 EVEX_CD8<64, CD8VT1>;
2071
2072// Move Int Doubleword to Single Scalar
2073//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2074let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2075def VMOVDI2SSZrr : AVX512BI<0x6E, MRMSrcReg, (outs FR32X:$dst), (ins GR32:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2076 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2077 [(set FR32X:$dst, (bitconvert GR32:$src))],
2078 IIC_SSE_MOVDQ>, EVEX, VEX_LIG;
2079
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2080def VMOVDI2SSZrm : AVX512BI<0x6E, MRMSrcMem, (outs FR32X:$dst), (ins i32mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2081 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2082 [(set FR32X:$dst, (bitconvert (loadi32 addr:$src)))],
2083 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2084}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2085
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2086// Move doubleword from xmm register to r/m32
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2087//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2088def VMOVPDI2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2089 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2090 [(set GR32:$dst, (vector_extract (v4i32 VR128X:$src),
2091 (iPTR 0)))], IIC_SSE_MOVD_ToGP>,
2092 EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2093def VMOVPDI2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2094 (ins i32mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2095 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2096 [(store (i32 (vector_extract (v4i32 VR128X:$src),
2097 (iPTR 0))), addr:$dst)], IIC_SSE_MOVDQ>,
2098 EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
2099
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2100// Move quadword from xmm1 register to r/m64
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2101//
2102def VMOVPQIto64Zrr : I<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2103 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2104 [(set GR64:$dst, (extractelt (v2i64 VR128X:$src),
2105 (iPTR 0)))],
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2106 IIC_SSE_MOVD_ToGP>, PD, EVEX, VEX_LIG, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2107 Requires<[HasAVX512, In64BitMode]>;
2108
Elena Demikhovsky85aeffa2013-10-03 12:03:26 +0000[diff] [blame]2109def VMOVPQIto64Zmr : I<0xD6, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2110 (ins i64mem:$dst, VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2111 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2112 [(store (extractelt (v2i64 VR128X:$src), (iPTR 0)),
2113 addr:$dst)], IIC_SSE_MOVDQ>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2114 EVEX, PD, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2115 Sched<[WriteStore]>, Requires<[HasAVX512, In64BitMode]>;
2116
2117// Move Scalar Single to Double Int
2118//
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2119let isCodeGenOnly = 1 in {
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2120def VMOVSS2DIZrr : AVX512BI<0x7E, MRMDestReg, (outs GR32:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2121 (ins FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2122 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2123 [(set GR32:$dst, (bitconvert FR32X:$src))],
2124 IIC_SSE_MOVD_ToGP>, EVEX, VEX_LIG;
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2125def VMOVSS2DIZmr : AVX512BI<0x7E, MRMDestMem, (outs),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2126 (ins i32mem:$dst, FR32X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2127 "vmovd\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2128 [(store (i32 (bitconvert FR32X:$src)), addr:$dst)],
2129 IIC_SSE_MOVDQ>, EVEX, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Craig Topper88adf2a2013-10-12 05:41:08 +0000[diff] [blame]2130}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2131
2132// Move Quadword Int to Packed Quadword Int
2133//
Elena Demikhovsky767fc962014-01-14 15:10:08 +0000[diff] [blame]2134def VMOVQI2PQIZrm : AVX512BI<0x6E, MRMSrcMem, (outs VR128X:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2135 (ins i64mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2136 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2137 [(set VR128X:$dst,
2138 (v2i64 (scalar_to_vector (loadi64 addr:$src))))]>,
2139 EVEX, VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
2140
2141//===----------------------------------------------------------------------===//
2142// AVX-512 MOVSS, MOVSD
2143//===----------------------------------------------------------------------===//
2144
2145multiclass avx512_move_scalar <string asm, RegisterClass RC,
2146 SDNode OpNode, ValueType vt,
2147 X86MemOperand x86memop, PatFrag mem_pat> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2148 let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2149 def rr : SI<0x10, MRMSrcReg, (outs VR128X:$dst), (ins VR128X:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2150 !strconcat(asm, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2151 [(set VR128X:$dst, (vt (OpNode VR128X:$src1,
2152 (scalar_to_vector RC:$src2))))],
2153 IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2154 let Constraints = "$src1 = $dst" in
2155 def rrk : SI<0x10, MRMSrcReg, (outs VR128X:$dst),
2156 (ins VR128X:$src1, VK1WM:$mask, RC:$src2, RC:$src3),
2157 !strconcat(asm,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2158 " \t{$src3, $src2, $dst {${mask}}|$dst {${mask}}, $src2, $src3}"),
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2159 [], IIC_SSE_MOV_S_RR>, EVEX_4V, VEX_LIG, EVEX_K;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2160 def rm : SI<0x10, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2161 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2162 [(set RC:$dst, (mem_pat addr:$src))], IIC_SSE_MOV_S_RM>,
2163 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2164 let mayStore = 1 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2165 def mr: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2166 !strconcat(asm, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2167 [(store RC:$src, addr:$dst)], IIC_SSE_MOV_S_MR>,
2168 EVEX, VEX_LIG;
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2169 def mrk: SI<0x11, MRMDestMem, (outs), (ins x86memop:$dst, VK1WM:$mask, RC:$src),
2170 !strconcat(asm, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
2171 [], IIC_SSE_MOV_S_MR>,
2172 EVEX, VEX_LIG, EVEX_K;
2173 } // mayStore
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]2174 } //hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2175}
2176
2177let ExeDomain = SSEPackedSingle in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2178defm VMOVSSZ : avx512_move_scalar<"movss", FR32X, X86Movss, v4f32, f32mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2179 loadf32>, XS, EVEX_CD8<32, CD8VT1>;
2180
2181let ExeDomain = SSEPackedDouble in
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2182defm VMOVSDZ : avx512_move_scalar<"movsd", FR64X, X86Movsd, v2f64, f64mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2183 loadf64>, XD, VEX_W, EVEX_CD8<64, CD8VT1>;
2184
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]2185def : Pat<(f32 (X86select VK1WM:$mask, (f32 FR32X:$src1), (f32 FR32X:$src2))),
2186 (COPY_TO_REGCLASS (VMOVSSZrrk (COPY_TO_REGCLASS FR32X:$src2, VR128X),
2187 VK1WM:$mask, (f32 (IMPLICIT_DEF)), FR32X:$src1), FR32X)>;
2188
2189def : Pat<(f64 (X86select VK1WM:$mask, (f64 FR64X:$src1), (f64 FR64X:$src2))),
2190 (COPY_TO_REGCLASS (VMOVSDZrrk (COPY_TO_REGCLASS FR64X:$src2, VR128X),
2191 VK1WM:$mask, (f64 (IMPLICIT_DEF)), FR64X:$src1), FR64X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2192
Elena Demikhovskyff620ed2014-08-27 07:38:43 +0000[diff] [blame]2193def : Pat<(int_x86_avx512_mask_store_ss addr:$dst, VR128X:$src, GR8:$mask),
2194 (VMOVSSZmrk addr:$dst, (i1 (COPY_TO_REGCLASS GR8:$mask, VK1WM)),
2195 (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2196
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2197// For the disassembler
Craig Topper3484fc22014-01-05 04:17:28 +0000[diff] [blame]2198let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2199 def VMOVSSZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2200 (ins VR128X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2201 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2202 IIC_SSE_MOV_S_RR>,
2203 XS, EVEX_4V, VEX_LIG;
2204 def VMOVSDZrr_REV : SI<0x11, MRMDestReg, (outs VR128X:$dst),
2205 (ins VR128X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2206 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}", [],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2207 IIC_SSE_MOV_S_RR>,
2208 XD, EVEX_4V, VEX_LIG, VEX_W;
2209}
2210
2211let Predicates = [HasAVX512] in {
2212 let AddedComplexity = 15 in {
2213 // Move scalar to XMM zero-extended, zeroing a VR128X then do a
2214 // MOVS{S,D} to the lower bits.
2215 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector FR32X:$src)))),
2216 (VMOVSSZrr (v4f32 (V_SET0)), FR32X:$src)>;
2217 def : Pat<(v4f32 (X86vzmovl (v4f32 VR128X:$src))),
2218 (VMOVSSZrr (v4f32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2219 def : Pat<(v4i32 (X86vzmovl (v4i32 VR128X:$src))),
2220 (VMOVSSZrr (v4i32 (V_SET0)), (COPY_TO_REGCLASS VR128X:$src, FR32X))>;
2221 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector FR64X:$src)))),
2222 (VMOVSDZrr (v2f64 (V_SET0)), FR64X:$src)>;
2223
2224 // Move low f32 and clear high bits.
2225 def : Pat<(v8f32 (X86vzmovl (v8f32 VR256X:$src))),
2226 (SUBREG_TO_REG (i32 0),
2227 (VMOVSSZrr (v4f32 (V_SET0)),
2228 (EXTRACT_SUBREG (v8f32 VR256X:$src), sub_xmm)), sub_xmm)>;
2229 def : Pat<(v8i32 (X86vzmovl (v8i32 VR256X:$src))),
2230 (SUBREG_TO_REG (i32 0),
2231 (VMOVSSZrr (v4i32 (V_SET0)),
2232 (EXTRACT_SUBREG (v8i32 VR256X:$src), sub_xmm)), sub_xmm)>;
2233 }
2234
2235 let AddedComplexity = 20 in {
2236 // MOVSSrm zeros the high parts of the register; represent this
2237 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2238 def : Pat<(v4f32 (X86vzmovl (v4f32 (scalar_to_vector (loadf32 addr:$src))))),
2239 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2240 def : Pat<(v4f32 (scalar_to_vector (loadf32 addr:$src))),
2241 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2242 def : Pat<(v4f32 (X86vzmovl (loadv4f32 addr:$src))),
2243 (COPY_TO_REGCLASS (VMOVSSZrm addr:$src), VR128X)>;
2244
2245 // MOVSDrm zeros the high parts of the register; represent this
2246 // with SUBREG_TO_REG. The AVX versions also write: DST[255:128] <- 0
2247 def : Pat<(v2f64 (X86vzmovl (v2f64 (scalar_to_vector (loadf64 addr:$src))))),
2248 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2249 def : Pat<(v2f64 (scalar_to_vector (loadf64 addr:$src))),
2250 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2251 def : Pat<(v2f64 (X86vzmovl (loadv2f64 addr:$src))),
2252 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2253 def : Pat<(v2f64 (X86vzmovl (bc_v2f64 (loadv4f32 addr:$src)))),
2254 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2255 def : Pat<(v2f64 (X86vzload addr:$src)),
2256 (COPY_TO_REGCLASS (VMOVSDZrm addr:$src), VR128X)>;
2257
2258 // Represent the same patterns above but in the form they appear for
2259 // 256-bit types
2260 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2261 (v4i32 (scalar_to_vector (loadi32 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2262 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2263 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2264 (v4f32 (scalar_to_vector (loadf32 addr:$src))), (iPTR 0)))),
2265 (SUBREG_TO_REG (i32 0), (VMOVSSZrm addr:$src), sub_xmm)>;
2266 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2267 (v2f64 (scalar_to_vector (loadf64 addr:$src))), (iPTR 0)))),
2268 (SUBREG_TO_REG (i32 0), (VMOVSDZrm addr:$src), sub_xmm)>;
2269 }
2270 def : Pat<(v8f32 (X86vzmovl (insert_subvector undef,
2271 (v4f32 (scalar_to_vector FR32X:$src)), (iPTR 0)))),
2272 (SUBREG_TO_REG (i32 0), (v4f32 (VMOVSSZrr (v4f32 (V_SET0)),
2273 FR32X:$src)), sub_xmm)>;
2274 def : Pat<(v4f64 (X86vzmovl (insert_subvector undef,
2275 (v2f64 (scalar_to_vector FR64X:$src)), (iPTR 0)))),
2276 (SUBREG_TO_REG (i64 0), (v2f64 (VMOVSDZrr (v2f64 (V_SET0)),
2277 FR64X:$src)), sub_xmm)>;
2278 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2279 (v2i64 (scalar_to_vector (loadi64 addr:$src))), (iPTR 0)))),
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]2280 (SUBREG_TO_REG (i64 0), (VMOVQI2PQIZrm addr:$src), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2281
2282 // Move low f64 and clear high bits.
2283 def : Pat<(v4f64 (X86vzmovl (v4f64 VR256X:$src))),
2284 (SUBREG_TO_REG (i32 0),
2285 (VMOVSDZrr (v2f64 (V_SET0)),
2286 (EXTRACT_SUBREG (v4f64 VR256X:$src), sub_xmm)), sub_xmm)>;
2287
2288 def : Pat<(v4i64 (X86vzmovl (v4i64 VR256X:$src))),
2289 (SUBREG_TO_REG (i32 0), (VMOVSDZrr (v2i64 (V_SET0)),
2290 (EXTRACT_SUBREG (v4i64 VR256X:$src), sub_xmm)), sub_xmm)>;
2291
2292 // Extract and store.
2293 def : Pat<(store (f32 (vector_extract (v4f32 VR128X:$src), (iPTR 0))),
2294 addr:$dst),
2295 (VMOVSSZmr addr:$dst, (COPY_TO_REGCLASS (v4f32 VR128X:$src), FR32X))>;
2296 def : Pat<(store (f64 (vector_extract (v2f64 VR128X:$src), (iPTR 0))),
2297 addr:$dst),
2298 (VMOVSDZmr addr:$dst, (COPY_TO_REGCLASS (v2f64 VR128X:$src), FR64X))>;
2299
2300 // Shuffle with VMOVSS
2301 def : Pat<(v4i32 (X86Movss VR128X:$src1, VR128X:$src2)),
2302 (VMOVSSZrr (v4i32 VR128X:$src1),
2303 (COPY_TO_REGCLASS (v4i32 VR128X:$src2), FR32X))>;
2304 def : Pat<(v4f32 (X86Movss VR128X:$src1, VR128X:$src2)),
2305 (VMOVSSZrr (v4f32 VR128X:$src1),
2306 (COPY_TO_REGCLASS (v4f32 VR128X:$src2), FR32X))>;
2307
2308 // 256-bit variants
2309 def : Pat<(v8i32 (X86Movss VR256X:$src1, VR256X:$src2)),
2310 (SUBREG_TO_REG (i32 0),
2311 (VMOVSSZrr (EXTRACT_SUBREG (v8i32 VR256X:$src1), sub_xmm),
2312 (EXTRACT_SUBREG (v8i32 VR256X:$src2), sub_xmm)),
2313 sub_xmm)>;
2314 def : Pat<(v8f32 (X86Movss VR256X:$src1, VR256X:$src2)),
2315 (SUBREG_TO_REG (i32 0),
2316 (VMOVSSZrr (EXTRACT_SUBREG (v8f32 VR256X:$src1), sub_xmm),
2317 (EXTRACT_SUBREG (v8f32 VR256X:$src2), sub_xmm)),
2318 sub_xmm)>;
2319
2320 // Shuffle with VMOVSD
2321 def : Pat<(v2i64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2322 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2323 def : Pat<(v2f64 (X86Movsd VR128X:$src1, VR128X:$src2)),
2324 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2325 def : Pat<(v4f32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2326 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2327 def : Pat<(v4i32 (X86Movsd VR128X:$src1, VR128X:$src2)),
2328 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2329
2330 // 256-bit variants
2331 def : Pat<(v4i64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2332 (SUBREG_TO_REG (i32 0),
2333 (VMOVSDZrr (EXTRACT_SUBREG (v4i64 VR256X:$src1), sub_xmm),
2334 (EXTRACT_SUBREG (v4i64 VR256X:$src2), sub_xmm)),
2335 sub_xmm)>;
2336 def : Pat<(v4f64 (X86Movsd VR256X:$src1, VR256X:$src2)),
2337 (SUBREG_TO_REG (i32 0),
2338 (VMOVSDZrr (EXTRACT_SUBREG (v4f64 VR256X:$src1), sub_xmm),
2339 (EXTRACT_SUBREG (v4f64 VR256X:$src2), sub_xmm)),
2340 sub_xmm)>;
2341
2342 def : Pat<(v2f64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2343 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2344 def : Pat<(v2i64 (X86Movlpd VR128X:$src1, VR128X:$src2)),
2345 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2346 def : Pat<(v4f32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2347 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2348 def : Pat<(v4i32 (X86Movlps VR128X:$src1, VR128X:$src2)),
2349 (VMOVSDZrr VR128X:$src1, (COPY_TO_REGCLASS VR128X:$src2, FR64X))>;
2350}
2351
2352let AddedComplexity = 15 in
2353def VMOVZPQILo2PQIZrr : AVX512XSI<0x7E, MRMSrcReg, (outs VR128X:$dst),
2354 (ins VR128X:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2355 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2356 [(set VR128X:$dst, (v2i64 (X86vzmovl
2357 (v2i64 VR128X:$src))))],
2358 IIC_SSE_MOVQ_RR>, EVEX, VEX_W;
2359
2360let AddedComplexity = 20 in
2361def VMOVZPQILo2PQIZrm : AVX512XSI<0x7E, MRMSrcMem, (outs VR128X:$dst),
2362 (ins i128mem:$src),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2363 "vmovq\t{$src, $dst|$dst, $src}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2364 [(set VR128X:$dst, (v2i64 (X86vzmovl
2365 (loadv2i64 addr:$src))))],
2366 IIC_SSE_MOVDQ>, EVEX, VEX_W,
2367 EVEX_CD8<8, CD8VT8>;
2368
2369let Predicates = [HasAVX512] in {
2370 // AVX 128-bit movd/movq instruction write zeros in the high 128-bit part.
2371 let AddedComplexity = 20 in {
2372 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector (loadi32 addr:$src))))),
2373 (VMOVDI2PDIZrm addr:$src)>;
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2374 def : Pat<(v2i64 (X86vzmovl (v2i64 (scalar_to_vector GR64:$src)))),
2375 (VMOV64toPQIZrr GR64:$src)>;
2376 def : Pat<(v4i32 (X86vzmovl (v4i32 (scalar_to_vector GR32:$src)))),
2377 (VMOVDI2PDIZrr GR32:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2378
2379 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv4f32 addr:$src)))),
2380 (VMOVDI2PDIZrm addr:$src)>;
2381 def : Pat<(v4i32 (X86vzmovl (bc_v4i32 (loadv2i64 addr:$src)))),
2382 (VMOVDI2PDIZrm addr:$src)>;
2383 def : Pat<(v2i64 (X86vzmovl (loadv2i64 addr:$src))),
2384 (VMOVZPQILo2PQIZrm addr:$src)>;
2385 def : Pat<(v2f64 (X86vzmovl (v2f64 VR128X:$src))),
2386 (VMOVZPQILo2PQIZrr VR128X:$src)>;
Cameron McInally30bbb212013-12-05 00:11:25 +0000[diff] [blame]2387 def : Pat<(v2i64 (X86vzload addr:$src)),
2388 (VMOVZPQILo2PQIZrm addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2389 }
Elena Demikhovsky3b75f5d2013-10-01 08:38:02 +0000[diff] [blame]2390
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2391 // Use regular 128-bit instructions to match 256-bit scalar_to_vec+zext.
2392 def : Pat<(v8i32 (X86vzmovl (insert_subvector undef,
2393 (v4i32 (scalar_to_vector GR32:$src)),(iPTR 0)))),
2394 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src), sub_xmm)>;
2395 def : Pat<(v4i64 (X86vzmovl (insert_subvector undef,
2396 (v2i64 (scalar_to_vector GR64:$src)),(iPTR 0)))),
2397 (SUBREG_TO_REG (i64 0), (VMOV64toPQIZrr GR64:$src), sub_xmm)>;
2398}
2399
2400def : Pat<(v16i32 (X86Vinsert (v16i32 immAllZerosV), GR32:$src2, (iPTR 0))),
2401 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2402
2403def : Pat<(v8i64 (X86Vinsert (bc_v8i64 (v16i32 immAllZerosV)), GR64:$src2, (iPTR 0))),
2404 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2405
2406def : Pat<(v16i32 (X86Vinsert undef, GR32:$src2, (iPTR 0))),
2407 (SUBREG_TO_REG (i32 0), (VMOVDI2PDIZrr GR32:$src2), sub_xmm)>;
2408
2409def : Pat<(v8i64 (X86Vinsert undef, GR64:$src2, (iPTR 0))),
2410 (SUBREG_TO_REG (i32 0), (VMOV64toPQIZrr GR64:$src2), sub_xmm)>;
2411
2412//===----------------------------------------------------------------------===//
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2413// AVX-512 - Non-temporals
2414//===----------------------------------------------------------------------===//
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2415let SchedRW = [WriteLoad] in {
2416 def VMOVNTDQAZrm : AVX512PI<0x2A, MRMSrcMem, (outs VR512:$dst),
2417 (ins i512mem:$src), "vmovntdqa\t{$src, $dst|$dst, $src}",
2418 [(set VR512:$dst, (int_x86_avx512_movntdqa addr:$src))],
2419 SSEPackedInt>, EVEX, T8PD, EVEX_V512,
2420 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2421
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2422 let Predicates = [HasAVX512, HasVLX] in {
2423 def VMOVNTDQAZ256rm : AVX512PI<0x2A, MRMSrcMem, (outs VR256X:$dst),
2424 (ins i256mem:$src),
2425 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2426 SSEPackedInt>, EVEX, T8PD, EVEX_V256,
2427 EVEX_CD8<64, CD8VF>;
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2428
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2429 def VMOVNTDQAZ128rm : AVX512PI<0x2A, MRMSrcMem, (outs VR128X:$dst),
2430 (ins i128mem:$src),
2431 "vmovntdqa\t{$src, $dst|$dst, $src}", [],
2432 SSEPackedInt>, EVEX, T8PD, EVEX_V128,
2433 EVEX_CD8<64, CD8VF>;
2434 }
Adam Nemetefd07852014-06-18 16:51:10 +0000[diff] [blame]2435}
2436
Robert Khasanoved882972014-08-13 10:46:00 +0000[diff] [blame]2437multiclass avx512_movnt<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2438 ValueType OpVT, RegisterClass RC, X86MemOperand memop,
2439 Domain d, InstrItinClass itin = IIC_SSE_MOVNT> {
2440 let SchedRW = [WriteStore], mayStore = 1,
2441 AddedComplexity = 400 in
2442 def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
2443 !strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
2444 [(st_frag (OpVT RC:$src), addr:$dst)], d, itin>, EVEX;
2445}
2446
2447multiclass avx512_movnt_vl<bits<8> opc, string OpcodeStr, PatFrag st_frag,
2448 string elty, string elsz, string vsz512,
2449 string vsz256, string vsz128, Domain d,
2450 Predicate prd, InstrItinClass itin = IIC_SSE_MOVNT> {
2451 let Predicates = [prd] in
2452 defm Z : avx512_movnt<opc, OpcodeStr, st_frag,
2453 !cast<ValueType>("v"##vsz512##elty##elsz), VR512,
2454 !cast<X86MemOperand>(elty##"512mem"), d, itin>,
2455 EVEX_V512;
2456
2457 let Predicates = [prd, HasVLX] in {
2458 defm Z256 : avx512_movnt<opc, OpcodeStr, st_frag,
2459 !cast<ValueType>("v"##vsz256##elty##elsz), VR256X,
2460 !cast<X86MemOperand>(elty##"256mem"), d, itin>,
2461 EVEX_V256;
2462
2463 defm Z128 : avx512_movnt<opc, OpcodeStr, st_frag,
2464 !cast<ValueType>("v"##vsz128##elty##elsz), VR128X,
2465 !cast<X86MemOperand>(elty##"128mem"), d, itin>,
2466 EVEX_V128;
2467 }
2468}
2469
2470defm VMOVNTDQ : avx512_movnt_vl<0xE7, "vmovntdq", alignednontemporalstore,
2471 "i", "64", "8", "4", "2", SSEPackedInt,
2472 HasAVX512>, PD, EVEX_CD8<64, CD8VF>;
2473
2474defm VMOVNTPD : avx512_movnt_vl<0x2B, "vmovntpd", alignednontemporalstore,
2475 "f", "64", "8", "4", "2", SSEPackedDouble,
2476 HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
2477
2478defm VMOVNTPS : avx512_movnt_vl<0x2B, "vmovntps", alignednontemporalstore,
2479 "f", "32", "16", "8", "4", SSEPackedSingle,
2480 HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
2481
Adam Nemet7f62b232014-06-10 16:39:53 +0000[diff] [blame]2482//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2483// AVX-512 - Integer arithmetic
2484//
2485multiclass avx512_binop_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2486 ValueType OpVT, RegisterClass KRC,
2487 RegisterClass RC, PatFrag memop_frag,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2488 X86MemOperand x86memop, PatFrag scalar_mfrag,
2489 X86MemOperand x86scalar_mop, string BrdcstStr,
2490 OpndItins itins, bit IsCommutable = 0> {
2491 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2492 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2493 (ins RC:$src1, RC:$src2),
2494 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2495 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2496 itins.rr>, EVEX_4V;
2497 let AddedComplexity = 30 in {
2498 let Constraints = "$src0 = $dst" in
2499 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2500 (ins RC:$src0, KRC:$mask, RC:$src1, RC:$src2),
2501 !strconcat(OpcodeStr,
2502 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2503 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2504 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2505 RC:$src0)))],
2506 itins.rr>, EVEX_4V, EVEX_K;
2507 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2508 (ins KRC:$mask, RC:$src1, RC:$src2),
2509 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2510 "|$dst {${mask}} {z}, $src1, $src2}"),
2511 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2512 (OpNode (OpVT RC:$src1), (OpVT RC:$src2)),
2513 (OpVT immAllZerosV))))],
2514 itins.rr>, EVEX_4V, EVEX_KZ;
2515 }
2516
2517 let mayLoad = 1 in {
2518 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2519 (ins RC:$src1, x86memop:$src2),
2520 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2521 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (memop_frag addr:$src2))))],
2522 itins.rm>, EVEX_4V;
2523 let AddedComplexity = 30 in {
2524 let Constraints = "$src0 = $dst" in
2525 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2526 (ins RC:$src0, KRC:$mask, RC:$src1, x86memop:$src2),
2527 !strconcat(OpcodeStr,
2528 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2529 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2530 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2531 RC:$src0)))],
2532 itins.rm>, EVEX_4V, EVEX_K;
2533 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2534 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2535 !strconcat(OpcodeStr,
2536 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2537 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2538 (OpNode (OpVT RC:$src1), (memop_frag addr:$src2)),
2539 (OpVT immAllZerosV))))],
2540 itins.rm>, EVEX_4V, EVEX_KZ;
2541 }
2542 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2543 (ins RC:$src1, x86scalar_mop:$src2),
2544 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2545 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2546 [(set RC:$dst, (OpNode RC:$src1,
2547 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))))],
2548 itins.rm>, EVEX_4V, EVEX_B;
2549 let AddedComplexity = 30 in {
2550 let Constraints = "$src0 = $dst" in
2551 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2552 (ins RC:$src0, KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2553 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2554 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2555 BrdcstStr, "}"),
2556 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2557 (OpNode (OpVT RC:$src1),
2558 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2559 RC:$src0)))],
2560 itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2561 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2562 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2563 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2564 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2565 BrdcstStr, "}"),
2566 [(set RC:$dst, (OpVT (vselect KRC:$mask,
2567 (OpNode (OpVT RC:$src1),
2568 (OpVT (X86VBroadcast (scalar_mfrag addr:$src2)))),
2569 (OpVT immAllZerosV))))],
2570 itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2571 }
2572 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2573}
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2574
2575multiclass avx512_binop_rm2<bits<8> opc, string OpcodeStr, ValueType DstVT,
2576 ValueType SrcVT, RegisterClass KRC, RegisterClass RC,
2577 PatFrag memop_frag, X86MemOperand x86memop,
2578 PatFrag scalar_mfrag, X86MemOperand x86scalar_mop,
2579 string BrdcstStr, OpndItins itins, bit IsCommutable = 0> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2580 let isCommutable = IsCommutable in
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2581 {
2582 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2583 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2584 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2585 []>, EVEX_4V;
2586 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2587 (ins KRC:$mask, RC:$src1, RC:$src2),
2588 !strconcat(OpcodeStr,
2589 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2590 [], itins.rr>, EVEX_4V, EVEX_K;
2591 def rrkz : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2592 (ins KRC:$mask, RC:$src1, RC:$src2),
2593 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst {${mask}} {z}" ,
2594 "|$dst {${mask}} {z}, $src1, $src2}"),
2595 [], itins.rr>, EVEX_4V, EVEX_KZ;
2596 }
2597 let mayLoad = 1 in {
2598 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2599 (ins RC:$src1, x86memop:$src2),
2600 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
2601 []>, EVEX_4V;
2602 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2603 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2604 !strconcat(OpcodeStr,
2605 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2606 [], itins.rm>, EVEX_4V, EVEX_K;
2607 def rmkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2608 (ins KRC:$mask, RC:$src1, x86memop:$src2),
2609 !strconcat(OpcodeStr,
2610 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2611 [], itins.rm>, EVEX_4V, EVEX_KZ;
2612 def rmb : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2613 (ins RC:$src1, x86scalar_mop:$src2),
2614 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2615 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
2616 [], itins.rm>, EVEX_4V, EVEX_B;
2617 def rmbk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2618 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2619 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2620 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}",
2621 BrdcstStr, "}"),
2622 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_K;
2623 def rmbkz : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2624 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2),
2625 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
2626 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2627 BrdcstStr, "}"),
2628 [], itins.rm>, EVEX_4V, EVEX_B, EVEX_KZ;
2629 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2630}
2631
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2632defm VPADDDZ : avx512_binop_rm<0xFE, "vpaddd", add, v16i32, VK16WM, VR512,
2633 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2634 SSE_INTALU_ITINS_P, 1>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2635
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2636defm VPSUBDZ : avx512_binop_rm<0xFA, "vpsubd", sub, v16i32, VK16WM, VR512,
2637 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2638 SSE_INTALU_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2639
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2640defm VPMULLDZ : avx512_binop_rm<0x40, "vpmulld", mul, v16i32, VK16WM, VR512,
2641 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2642 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2643
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2644defm VPADDQZ : avx512_binop_rm<0xD4, "vpaddq", add, v8i64, VK8WM, VR512,
2645 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2646 SSE_INTALU_ITINS_P, 1>, EVEX_CD8<64, CD8VF>, EVEX_V512, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2647
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2648defm VPSUBQZ : avx512_binop_rm<0xFB, "vpsubq", sub, v8i64, VK8WM, VR512,
2649 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2650 SSE_INTALU_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2651
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2652defm VPMULDQZ : avx512_binop_rm2<0x28, "vpmuldq", v8i64, v16i32, VK8WM, VR512,
2653 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2654 SSE_INTALU_ITINS_P, 1>, T8PD, EVEX_V512,
2655 EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2656
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2657defm VPMULUDQZ : avx512_binop_rm2<0xF4, "vpmuludq", v8i64, v16i32, VK8WM, VR512,
2658 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2659 SSE_INTMUL_ITINS_P, 1>, EVEX_V512, EVEX_CD8<64, CD8VF>, VEX_W;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2660
2661def : Pat<(v8i64 (X86pmuludq (v16i32 VR512:$src1), (v16i32 VR512:$src2))),
2662 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2663
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2664def : Pat<(v8i64 (int_x86_avx512_mask_pmulu_dq_512 (v16i32 VR512:$src1),
2665 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2666 (VPMULUDQZrr VR512:$src1, VR512:$src2)>;
2667def : Pat<(v8i64 (int_x86_avx512_mask_pmul_dq_512 (v16i32 VR512:$src1),
2668 (v16i32 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2669 (VPMULDQZrr VR512:$src1, VR512:$src2)>;
2670
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2671defm VPMAXUDZ : avx512_binop_rm<0x3F, "vpmaxud", X86umax, v16i32, VK16WM, VR512,
2672 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2673 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2674 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2675defm VPMAXUQZ : avx512_binop_rm<0x3F, "vpmaxuq", X86umax, v8i64, VK8WM, VR512,
2676 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2677 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2678 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2679
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2680defm VPMAXSDZ : avx512_binop_rm<0x3D, "vpmaxsd", X86smax, v16i32, VK16WM, VR512,
2681 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2682 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2683 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2684defm VPMAXSQZ : avx512_binop_rm<0x3D, "vpmaxsq", X86smax, v8i64, VK8WM, VR512,
2685 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2686 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2687 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2688
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2689defm VPMINUDZ : avx512_binop_rm<0x3B, "vpminud", X86umin, v16i32, VK16WM, VR512,
2690 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2691 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2692 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2693defm VPMINUQZ : avx512_binop_rm<0x3B, "vpminuq", X86umin, v8i64, VK8WM, VR512,
2694 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2695 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2696 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2697
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2698defm VPMINSDZ : avx512_binop_rm<0x39, "vpminsd", X86smin, v16i32, VK16WM, VR512,
2699 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2700 SSE_INTALU_ITINS_P, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2701 T8PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2702defm VPMINSQZ : avx512_binop_rm<0x39, "vpminsq", X86smin, v8i64, VK8WM, VR512,
2703 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2704 SSE_INTALU_ITINS_P, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2705 T8PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky199c8232013-10-27 08:18:37 +0000[diff] [blame]2706
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]2707def : Pat <(v16i32 (int_x86_avx512_mask_pmaxs_d_512 (v16i32 VR512:$src1),
2708 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2709 (VPMAXSDZrr VR512:$src1, VR512:$src2)>;
2710def : Pat <(v16i32 (int_x86_avx512_mask_pmaxu_d_512 (v16i32 VR512:$src1),
2711 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2712 (VPMAXUDZrr VR512:$src1, VR512:$src2)>;
2713def : Pat <(v8i64 (int_x86_avx512_mask_pmaxs_q_512 (v8i64 VR512:$src1),
2714 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2715 (VPMAXSQZrr VR512:$src1, VR512:$src2)>;
2716def : Pat <(v8i64 (int_x86_avx512_mask_pmaxu_q_512 (v8i64 VR512:$src1),
2717 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2718 (VPMAXUQZrr VR512:$src1, VR512:$src2)>;
2719def : Pat <(v16i32 (int_x86_avx512_mask_pmins_d_512 (v16i32 VR512:$src1),
2720 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2721 (VPMINSDZrr VR512:$src1, VR512:$src2)>;
2722def : Pat <(v16i32 (int_x86_avx512_mask_pminu_d_512 (v16i32 VR512:$src1),
2723 (v16i32 VR512:$src2), (v16i32 immAllZerosV), (i16 -1))),
2724 (VPMINUDZrr VR512:$src1, VR512:$src2)>;
2725def : Pat <(v8i64 (int_x86_avx512_mask_pmins_q_512 (v8i64 VR512:$src1),
2726 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2727 (VPMINSQZrr VR512:$src1, VR512:$src2)>;
2728def : Pat <(v8i64 (int_x86_avx512_mask_pminu_q_512 (v8i64 VR512:$src1),
2729 (v8i64 VR512:$src2), (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
2730 (VPMINUQZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2731//===----------------------------------------------------------------------===//
2732// AVX-512 - Unpack Instructions
2733//===----------------------------------------------------------------------===//
2734
2735multiclass avx512_unpack_fp<bits<8> opc, SDNode OpNode, ValueType vt,
2736 PatFrag mem_frag, RegisterClass RC,
2737 X86MemOperand x86memop, string asm,
2738 Domain d> {
2739 def rr : AVX512PI<opc, MRMSrcReg,
2740 (outs RC:$dst), (ins RC:$src1, RC:$src2),
2741 asm, [(set RC:$dst,
2742 (vt (OpNode RC:$src1, RC:$src2)))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2743 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2744 def rm : AVX512PI<opc, MRMSrcMem,
2745 (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
2746 asm, [(set RC:$dst,
2747 (vt (OpNode RC:$src1,
2748 (bitconvert (mem_frag addr:$src2)))))],
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]2749 d>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2750}
2751
2752defm VUNPCKHPSZ: avx512_unpack_fp<0x15, X86Unpckh, v16f32, memopv8f64,
2753 VR512, f512mem, "vunpckhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2754 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2755defm VUNPCKHPDZ: avx512_unpack_fp<0x15, X86Unpckh, v8f64, memopv8f64,
2756 VR512, f512mem, "vunpckhpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2757 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2758defm VUNPCKLPSZ: avx512_unpack_fp<0x14, X86Unpckl, v16f32, memopv8f64,
2759 VR512, f512mem, "vunpcklps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2760 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2761defm VUNPCKLPDZ: avx512_unpack_fp<0x14, X86Unpckl, v8f64, memopv8f64,
2762 VR512, f512mem, "vunpcklpd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2763 SSEPackedDouble>, PD, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2764
2765multiclass avx512_unpack_int<bits<8> opc, string OpcodeStr, SDNode OpNode,
2766 ValueType OpVT, RegisterClass RC, PatFrag memop_frag,
2767 X86MemOperand x86memop> {
2768 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
2769 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2770 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2771 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1), (OpVT RC:$src2))))],
2772 IIC_SSE_UNPCK>, EVEX_4V;
2773 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
2774 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2775 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2776 [(set RC:$dst, (OpVT (OpNode (OpVT RC:$src1),
2777 (bitconvert (memop_frag addr:$src2)))))],
2778 IIC_SSE_UNPCK>, EVEX_4V;
2779}
2780defm VPUNPCKLDQZ : avx512_unpack_int<0x62, "vpunpckldq", X86Unpckl, v16i32,
2781 VR512, memopv16i32, i512mem>, EVEX_V512,
2782 EVEX_CD8<32, CD8VF>;
2783defm VPUNPCKLQDQZ : avx512_unpack_int<0x6C, "vpunpcklqdq", X86Unpckl, v8i64,
2784 VR512, memopv8i64, i512mem>, EVEX_V512,
2785 VEX_W, EVEX_CD8<64, CD8VF>;
2786defm VPUNPCKHDQZ : avx512_unpack_int<0x6A, "vpunpckhdq", X86Unpckh, v16i32,
2787 VR512, memopv16i32, i512mem>, EVEX_V512,
2788 EVEX_CD8<32, CD8VF>;
2789defm VPUNPCKHQDQZ : avx512_unpack_int<0x6D, "vpunpckhqdq", X86Unpckh, v8i64,
2790 VR512, memopv8i64, i512mem>, EVEX_V512,
2791 VEX_W, EVEX_CD8<64, CD8VF>;
2792//===----------------------------------------------------------------------===//
2793// AVX-512 - PSHUFD
2794//
2795
2796multiclass avx512_pshuf_imm<bits<8> opc, string OpcodeStr, RegisterClass RC,
2797 SDNode OpNode, PatFrag mem_frag,
2798 X86MemOperand x86memop, ValueType OpVT> {
2799 def ri : AVX512Ii8<opc, MRMSrcReg, (outs RC:$dst),
2800 (ins RC:$src1, i8imm:$src2),
2801 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2802 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2803 [(set RC:$dst,
2804 (OpVT (OpNode RC:$src1, (i8 imm:$src2))))]>,
2805 EVEX;
2806 def mi : AVX512Ii8<opc, MRMSrcMem, (outs RC:$dst),
2807 (ins x86memop:$src1, i8imm:$src2),
2808 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2809 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2810 [(set RC:$dst,
2811 (OpVT (OpNode (mem_frag addr:$src1),
2812 (i8 imm:$src2))))]>, EVEX;
2813}
2814
2815defm VPSHUFDZ : avx512_pshuf_imm<0x70, "vpshufd", VR512, X86PShufd, memopv16i32,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2816 i512mem, v16i32>, PD, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2817
2818let ExeDomain = SSEPackedSingle in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2819defm VPERMILPSZ : avx512_pshuf_imm<0x04, "vpermilps", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2820 memopv16f32, i512mem, v16f32>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2821 EVEX_CD8<32, CD8VF>;
2822let ExeDomain = SSEPackedDouble in
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2823defm VPERMILPDZ : avx512_pshuf_imm<0x05, "vpermilpd", VR512, X86VPermilpi,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2824 memopv8f64, i512mem, v8f64>, TAPD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2825 VEX_W, EVEX_CD8<32, CD8VF>;
2826
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2827def : Pat<(v16i32 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2828 (VPERMILPSZri VR512:$src1, imm:$imm)>;
Chandler Carruthed5dfff2014-09-22 22:29:42 +0000[diff] [blame]2829def : Pat<(v8i64 (X86VPermilpi VR512:$src1, (i8 imm:$imm))),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2830 (VPERMILPDZri VR512:$src1, imm:$imm)>;
2831
2832//===----------------------------------------------------------------------===//
2833// AVX-512 Logical Instructions
2834//===----------------------------------------------------------------------===//
2835
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2836defm VPANDDZ : avx512_binop_rm<0xDB, "vpandd", and, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2837 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2838 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2839defm VPANDQZ : avx512_binop_rm<0xDB, "vpandq", and, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2840 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2841 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2842defm VPORDZ : avx512_binop_rm<0xEB, "vpord", or, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2843 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2844 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2845defm VPORQZ : avx512_binop_rm<0xEB, "vporq", or, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2846 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2847 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2848defm VPXORDZ : avx512_binop_rm<0xEF, "vpxord", xor, v16i32, VK16WM, VR512, memopv16i32,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2849 i512mem, loadi32, i32mem, "{1to16}", SSE_BIT_ITINS_P, 1>,
2850 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2851defm VPXORQZ : avx512_binop_rm<0xEF, "vpxorq", xor, v8i64, VK8WM, VR512, memopv8i64,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2852 i512mem, loadi64, i64mem, "{1to8}", SSE_BIT_ITINS_P, 1>,
2853 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2854defm VPANDNDZ : avx512_binop_rm<0xDF, "vpandnd", X86andnp, v16i32, VK16WM, VR512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2855 memopv16i32, i512mem, loadi32, i32mem, "{1to16}",
2856 SSE_BIT_ITINS_P, 0>, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]2857defm VPANDNQZ : avx512_binop_rm<0xDF, "vpandnq", X86andnp, v8i64, VK8WM, VR512,
2858 memopv8i64, i512mem, loadi64, i64mem, "{1to8}",
2859 SSE_BIT_ITINS_P, 0>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2860
2861//===----------------------------------------------------------------------===//
2862// AVX-512 FP arithmetic
2863//===----------------------------------------------------------------------===//
2864
2865multiclass avx512_binop_s<bits<8> opc, string OpcodeStr, SDNode OpNode,
2866 SizeItins itins> {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2867 defm SSZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "ss"), OpNode, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2868 f32mem, itins.s, 0>, XS, EVEX_4V, VEX_LIG,
2869 EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]2870 defm SDZ : sse12_fp_scalar<opc, !strconcat(OpcodeStr, "sd"), OpNode, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2871 f64mem, itins.d, 0>, XD, VEX_W, EVEX_4V, VEX_LIG,
2872 EVEX_CD8<64, CD8VT1>;
2873}
2874
2875let isCommutable = 1 in {
2876defm VADD : avx512_binop_s<0x58, "add", fadd, SSE_ALU_ITINS_S>;
2877defm VMUL : avx512_binop_s<0x59, "mul", fmul, SSE_ALU_ITINS_S>;
2878defm VMIN : avx512_binop_s<0x5D, "min", X86fmin, SSE_ALU_ITINS_S>;
2879defm VMAX : avx512_binop_s<0x5F, "max", X86fmax, SSE_ALU_ITINS_S>;
2880}
2881let isCommutable = 0 in {
2882defm VSUB : avx512_binop_s<0x5C, "sub", fsub, SSE_ALU_ITINS_S>;
2883defm VDIV : avx512_binop_s<0x5E, "div", fdiv, SSE_ALU_ITINS_S>;
2884}
2885
2886multiclass avx512_fp_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2887 RegisterClass KRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2888 RegisterClass RC, ValueType vt,
2889 X86MemOperand x86memop, PatFrag mem_frag,
2890 X86MemOperand x86scalar_mop, PatFrag scalar_mfrag,
2891 string BrdcstStr,
2892 Domain d, OpndItins itins, bit commutable> {
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2893 let isCommutable = commutable in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2894 def rr : PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2895 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2896 [(set RC:$dst, (vt (OpNode RC:$src1, RC:$src2)))], itins.rr, d>,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2897 EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2898
2899 def rrk: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2900 !strconcat(OpcodeStr,
2901 " \t{$src2, $src1, $dst {${mask}} |$dst {${mask}}, $src1, $src2}"),
2902 [], itins.rr, d>, EVEX_4V, EVEX_K;
2903
2904 def rrkz: PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src1, RC:$src2),
2905 !strconcat(OpcodeStr,
2906 " \t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2907 [], itins.rr, d>, EVEX_4V, EVEX_KZ;
2908 }
2909
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2910 let mayLoad = 1 in {
2911 def rm : PI<opc, MRMSrcMem, (outs RC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2912 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2913 [(set RC:$dst, (OpNode RC:$src1, (mem_frag addr:$src2)))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2914 itins.rm, d>, EVEX_4V;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2915
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2916 def rmb : PI<opc, MRMSrcMem, (outs RC:$dst),
2917 (ins RC:$src1, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2918 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2919 ", $src1, $dst|$dst, $src1, ${src2}", BrdcstStr, "}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2920 [(set RC:$dst, (OpNode RC:$src1,
2921 (vt (X86VBroadcast (scalar_mfrag addr:$src2)))))],
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]2922 itins.rm, d>, EVEX_4V, EVEX_B;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2923
2924 def rmk : PI<opc, MRMSrcMem, (outs RC:$dst),
2925 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2926 "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
2927 [], itins.rm, d>, EVEX_4V, EVEX_K;
2928
2929 def rmkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2930 (ins KRC:$mask, RC:$src1, x86memop:$src2), !strconcat(OpcodeStr,
2931 "\t{$src2, $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, $src2}"),
2932 [], itins.rm, d>, EVEX_4V, EVEX_KZ;
2933
2934 def rmbk : PI<opc, MRMSrcMem, (outs RC:$dst),
2935 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2936 " \t{${src2}", BrdcstStr,
2937 ", $src1, $dst {${mask}}|$dst {${mask}}, $src1, ${src2}", BrdcstStr, "}"),
2938 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_K;
2939
2940 def rmbkz : PI<opc, MRMSrcMem, (outs RC:$dst),
2941 (ins KRC:$mask, RC:$src1, x86scalar_mop:$src2), !strconcat(OpcodeStr,
2942 " \t{${src2}", BrdcstStr,
2943 ", $src1, $dst {${mask}} {z}|$dst {${mask}} {z}, $src1, ${src2}",
2944 BrdcstStr, "}"),
2945 [], itins.rm, d>, EVEX_4V, EVEX_B, EVEX_KZ;
2946 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2947}
2948
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2949defm VADDPSZ : avx512_fp_packed<0x58, "addps", fadd, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2950 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2951 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2952
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2953defm VADDPDZ : avx512_fp_packed<0x58, "addpd", fadd, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2954 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2955 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2956 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2957
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2958defm VMULPSZ : avx512_fp_packed<0x59, "mulps", fmul, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2959 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2960 SSE_ALU_ITINS_P.s, 1>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2961defm VMULPDZ : avx512_fp_packed<0x59, "mulpd", fmul, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2962 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2963 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2964 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2965
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2966defm VMINPSZ : avx512_fp_packed<0x5D, "minps", X86fmin, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2967 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2968 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2969 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2970defm VMAXPSZ : avx512_fp_packed<0x5F, "maxps", X86fmax, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2971 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
2972 SSE_ALU_ITINS_P.s, 1>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2973 EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2974
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2975defm VMINPDZ : avx512_fp_packed<0x5D, "minpd", X86fmin, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2976 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2977 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2978 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2979defm VMAXPDZ : avx512_fp_packed<0x5F, "maxpd", X86fmax, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2980 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2981 SSE_ALU_ITINS_P.d, 1>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2982 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2983
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2984defm VSUBPSZ : avx512_fp_packed<0x5C, "subps", fsub, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2985 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2986 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2987defm VDIVPSZ : avx512_fp_packed<0x5E, "divps", fdiv, VK16WM, VR512, v16f32, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2988 memopv16f32, f32mem, loadf32, "{1to16}", SSEPackedSingle,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]2989 SSE_ALU_ITINS_P.s, 0>, EVEX_V512, PS, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2990
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2991defm VSUBPDZ : avx512_fp_packed<0x5C, "subpd", fsub, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2992 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2993 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2994 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyf7c1b162014-03-06 08:45:30 +0000[diff] [blame]2995defm VDIVPDZ : avx512_fp_packed<0x5E, "divpd", fdiv, VK8WM, VR512, v8f64, f512mem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2996 memopv8f64, f64mem, loadf64, "{1to8}", SSEPackedDouble,
2997 SSE_ALU_ITINS_P.d, 0>,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]2998 EVEX_V512, PD, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]2999
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3000def : Pat<(v16f32 (int_x86_avx512_mask_max_ps_512 (v16f32 VR512:$src1),
3001 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3002 (i16 -1), FROUND_CURRENT)),
3003 (VMAXPSZrr VR512:$src1, VR512:$src2)>;
3004
3005def : Pat<(v8f64 (int_x86_avx512_mask_max_pd_512 (v8f64 VR512:$src1),
3006 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3007 (i8 -1), FROUND_CURRENT)),
3008 (VMAXPDZrr VR512:$src1, VR512:$src2)>;
3009
3010def : Pat<(v16f32 (int_x86_avx512_mask_min_ps_512 (v16f32 VR512:$src1),
3011 (v16f32 VR512:$src2), (bc_v16f32 (v16i32 immAllZerosV)),
3012 (i16 -1), FROUND_CURRENT)),
3013 (VMINPSZrr VR512:$src1, VR512:$src2)>;
3014
3015def : Pat<(v8f64 (int_x86_avx512_mask_min_pd_512 (v8f64 VR512:$src1),
3016 (v8f64 VR512:$src2), (bc_v8f64 (v16i32 immAllZerosV)),
3017 (i8 -1), FROUND_CURRENT)),
3018 (VMINPDZrr VR512:$src1, VR512:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3019//===----------------------------------------------------------------------===//
3020// AVX-512 VPTESTM instructions
3021//===----------------------------------------------------------------------===//
3022
3023multiclass avx512_vptest<bits<8> opc, string OpcodeStr, RegisterClass KRC,
3024 RegisterClass RC, X86MemOperand x86memop, PatFrag memop_frag,
3025 SDNode OpNode, ValueType vt> {
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3026 def rr : AVX512PI<opc, MRMSrcReg,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3027 (outs KRC:$dst), (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3028 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3029 [(set KRC:$dst, (OpNode (vt RC:$src1), (vt RC:$src2)))],
3030 SSEPackedInt>, EVEX_4V;
3031 def rm : AVX512PI<opc, MRMSrcMem,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3032 (outs KRC:$dst), (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3033 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3034 [(set KRC:$dst, (OpNode (vt RC:$src1),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3035 (bitconvert (memop_frag addr:$src2))))], SSEPackedInt>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3036}
3037
3038defm VPTESTMDZ : avx512_vptest<0x27, "vptestmd", VK16, VR512, f512mem,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3039 memopv16i32, X86testm, v16i32>, T8PD, EVEX_V512,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3040 EVEX_CD8<32, CD8VF>;
3041defm VPTESTMQZ : avx512_vptest<0x27, "vptestmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3042 memopv8i64, X86testm, v8i64>, T8PD, EVEX_V512, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3043 EVEX_CD8<64, CD8VF>;
3044
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3045let Predicates = [HasCDI] in {
3046defm VPTESTNMDZ : avx512_vptest<0x27, "vptestnmd", VK16, VR512, f512mem,
3047 memopv16i32, X86testnm, v16i32>, T8XS, EVEX_V512,
3048 EVEX_CD8<32, CD8VF>;
3049defm VPTESTNMQZ : avx512_vptest<0x27, "vptestnmq", VK8, VR512, f512mem,
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3050 memopv8i64, X86testnm, v8i64>, T8XS, EVEX_V512, VEX_W,
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3051 EVEX_CD8<64, CD8VF>;
3052}
3053
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3054def : Pat <(i16 (int_x86_avx512_mask_ptestm_d_512 (v16i32 VR512:$src1),
3055 (v16i32 VR512:$src2), (i16 -1))),
3056 (COPY_TO_REGCLASS (VPTESTMDZrr VR512:$src1, VR512:$src2), GR16)>;
3057
3058def : Pat <(i8 (int_x86_avx512_mask_ptestm_q_512 (v8i64 VR512:$src1),
3059 (v8i64 VR512:$src2), (i8 -1))),
Elena Demikhovsky3ebfe112014-02-23 14:28:35 +0000[diff] [blame]3060 (COPY_TO_REGCLASS (VPTESTMQZrr VR512:$src1, VR512:$src2), GR8)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3061//===----------------------------------------------------------------------===//
3062// AVX-512 Shift instructions
3063//===----------------------------------------------------------------------===//
3064multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM,
3065 string OpcodeStr, SDNode OpNode, RegisterClass RC,
3066 ValueType vt, X86MemOperand x86memop, PatFrag mem_frag,
3067 RegisterClass KRC> {
3068 def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3069 (ins RC:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3070 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3071 [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))],
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3072 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3073 def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3074 (ins KRC:$mask, RC:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3075 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3076 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3077 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3078 def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3079 (ins x86memop:$src1, i8imm:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3080 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3081 [(set RC:$dst, (OpNode (mem_frag addr:$src1),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3082 (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3083 def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst),
Lang Hames27839932013-10-21 17:51:24 +0000[diff] [blame]3084 (ins KRC:$mask, x86memop:$src1, i8imm:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3085 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3086 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3087 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3088}
3089
3090multiclass avx512_shift_rrm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3091 RegisterClass RC, ValueType vt, ValueType SrcVT,
3092 PatFrag bc_frag, RegisterClass KRC> {
3093 // src2 is always 128-bit
3094 def rr : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3095 (ins RC:$src1, VR128X:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3096 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3097 [(set RC:$dst, (vt (OpNode RC:$src1, (SrcVT VR128X:$src2))))],
3098 SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V;
3099 def rrk : AVX512BI<opc, MRMSrcReg, (outs RC:$dst),
3100 (ins KRC:$mask, RC:$src1, VR128X:$src2),
3101 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3102 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3103 [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K;
3104 def rm : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3105 (ins RC:$src1, i128mem:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3106 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3107 [(set RC:$dst, (vt (OpNode RC:$src1,
3108 (bc_frag (memopv2i64 addr:$src2)))))],
3109 SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V;
3110 def rmk : AVX512BI<opc, MRMSrcMem, (outs RC:$dst),
3111 (ins KRC:$mask, RC:$src1, i128mem:$src2),
3112 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3113 " \t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3114 [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K;
3115}
3116
3117defm VPSRLDZ : avx512_shift_rmi<0x72, MRM2r, MRM2m, "vpsrld", X86vsrli,
3118 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3119 EVEX_V512, EVEX_CD8<32, CD8VF>;
3120defm VPSRLDZ : avx512_shift_rrm<0xD2, "vpsrld", X86vsrl,
3121 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3122 EVEX_CD8<32, CD8VQ>;
3123
3124defm VPSRLQZ : avx512_shift_rmi<0x73, MRM2r, MRM2m, "vpsrlq", X86vsrli,
3125 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3126 EVEX_CD8<64, CD8VF>, VEX_W;
3127defm VPSRLQZ : avx512_shift_rrm<0xD3, "vpsrlq", X86vsrl,
3128 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3129 EVEX_CD8<64, CD8VQ>, VEX_W;
3130
3131defm VPSLLDZ : avx512_shift_rmi<0x72, MRM6r, MRM6m, "vpslld", X86vshli,
3132 VR512, v16i32, i512mem, memopv16i32, VK16WM>, EVEX_V512,
3133 EVEX_CD8<32, CD8VF>;
3134defm VPSLLDZ : avx512_shift_rrm<0xF2, "vpslld", X86vshl,
3135 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3136 EVEX_CD8<32, CD8VQ>;
3137
3138defm VPSLLQZ : avx512_shift_rmi<0x73, MRM6r, MRM6m, "vpsllq", X86vshli,
3139 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3140 EVEX_CD8<64, CD8VF>, VEX_W;
3141defm VPSLLQZ : avx512_shift_rrm<0xF3, "vpsllq", X86vshl,
3142 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3143 EVEX_CD8<64, CD8VQ>, VEX_W;
3144
3145defm VPSRADZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsrad", X86vsrai,
3146 VR512, v16i32, i512mem, memopv16i32, VK16WM>,
3147 EVEX_V512, EVEX_CD8<32, CD8VF>;
3148defm VPSRADZ : avx512_shift_rrm<0xE2, "vpsrad", X86vsra,
3149 VR512, v16i32, v4i32, bc_v4i32, VK16WM>, EVEX_V512,
3150 EVEX_CD8<32, CD8VQ>;
3151
3152defm VPSRAQZ : avx512_shift_rmi<0x72, MRM4r, MRM4m, "vpsraq", X86vsrai,
3153 VR512, v8i64, i512mem, memopv8i64, VK8WM>, EVEX_V512,
3154 EVEX_CD8<64, CD8VF>, VEX_W;
3155defm VPSRAQZ : avx512_shift_rrm<0xE2, "vpsraq", X86vsra,
3156 VR512, v8i64, v2i64, bc_v2i64, VK8WM>, EVEX_V512,
3157 EVEX_CD8<64, CD8VQ>, VEX_W;
3158
3159//===-------------------------------------------------------------------===//
3160// Variable Bit Shifts
3161//===-------------------------------------------------------------------===//
3162multiclass avx512_var_shift<bits<8> opc, string OpcodeStr, SDNode OpNode,
3163 RegisterClass RC, ValueType vt,
3164 X86MemOperand x86memop, PatFrag mem_frag> {
3165 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3166 (ins RC:$src1, RC:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3167 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3168 [(set RC:$dst,
3169 (vt (OpNode RC:$src1, (vt RC:$src2))))]>,
3170 EVEX_4V;
3171 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3172 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3173 !strconcat(OpcodeStr, " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3174 [(set RC:$dst,
3175 (vt (OpNode RC:$src1, (mem_frag addr:$src2))))]>,
3176 EVEX_4V;
3177}
3178
3179defm VPSLLVDZ : avx512_var_shift<0x47, "vpsllvd", shl, VR512, v16i32,
3180 i512mem, memopv16i32>, EVEX_V512,
3181 EVEX_CD8<32, CD8VF>;
3182defm VPSLLVQZ : avx512_var_shift<0x47, "vpsllvq", shl, VR512, v8i64,
3183 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3184 EVEX_CD8<64, CD8VF>;
3185defm VPSRLVDZ : avx512_var_shift<0x45, "vpsrlvd", srl, VR512, v16i32,
3186 i512mem, memopv16i32>, EVEX_V512,
3187 EVEX_CD8<32, CD8VF>;
3188defm VPSRLVQZ : avx512_var_shift<0x45, "vpsrlvq", srl, VR512, v8i64,
3189 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3190 EVEX_CD8<64, CD8VF>;
3191defm VPSRAVDZ : avx512_var_shift<0x46, "vpsravd", sra, VR512, v16i32,
3192 i512mem, memopv16i32>, EVEX_V512,
3193 EVEX_CD8<32, CD8VF>;
3194defm VPSRAVQZ : avx512_var_shift<0x46, "vpsravq", sra, VR512, v8i64,
3195 i512mem, memopv8i64>, EVEX_V512, VEX_W,
3196 EVEX_CD8<64, CD8VF>;
3197
3198//===----------------------------------------------------------------------===//
3199// AVX-512 - MOVDDUP
3200//===----------------------------------------------------------------------===//
3201
3202multiclass avx512_movddup<string OpcodeStr, RegisterClass RC, ValueType VT,
3203 X86MemOperand x86memop, PatFrag memop_frag> {
3204def rr : AVX512PDI<0x12, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3205 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3206 [(set RC:$dst, (VT (X86Movddup RC:$src)))]>, EVEX;
3207def rm : AVX512PDI<0x12, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3208 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3209 [(set RC:$dst,
3210 (VT (X86Movddup (memop_frag addr:$src))))]>, EVEX;
3211}
3212
3213defm VMOVDDUPZ : avx512_movddup<"vmovddup", VR512, v8f64, f512mem, memopv8f64>,
3214 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
3215def : Pat<(X86Movddup (v8f64 (scalar_to_vector (loadf64 addr:$src)))),
3216 (VMOVDDUPZrm addr:$src)>;
3217
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3218//===---------------------------------------------------------------------===//
3219// Replicate Single FP - MOVSHDUP and MOVSLDUP
3220//===---------------------------------------------------------------------===//
3221multiclass avx512_replicate_sfp<bits<8> op, SDNode OpNode, string OpcodeStr,
3222 ValueType vt, RegisterClass RC, PatFrag mem_frag,
3223 X86MemOperand x86memop> {
3224 def rr : AVX512XSI<op, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3225 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3226 [(set RC:$dst, (vt (OpNode RC:$src)))]>, EVEX;
3227 let mayLoad = 1 in
3228 def rm : AVX512XSI<op, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3229 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]3230 [(set RC:$dst, (OpNode (mem_frag addr:$src)))]>, EVEX;
3231}
3232
3233defm VMOVSHDUPZ : avx512_replicate_sfp<0x16, X86Movshdup, "vmovshdup",
3234 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3235 EVEX_CD8<32, CD8VF>;
3236defm VMOVSLDUPZ : avx512_replicate_sfp<0x12, X86Movsldup, "vmovsldup",
3237 v16f32, VR512, memopv16f32, f512mem>, EVEX_V512,
3238 EVEX_CD8<32, CD8VF>;
3239
3240def : Pat<(v16i32 (X86Movshdup VR512:$src)), (VMOVSHDUPZrr VR512:$src)>;
3241def : Pat<(v16i32 (X86Movshdup (memopv16i32 addr:$src))),
3242 (VMOVSHDUPZrm addr:$src)>;
3243def : Pat<(v16i32 (X86Movsldup VR512:$src)), (VMOVSLDUPZrr VR512:$src)>;
3244def : Pat<(v16i32 (X86Movsldup (memopv16i32 addr:$src))),
3245 (VMOVSLDUPZrm addr:$src)>;
3246
3247//===----------------------------------------------------------------------===//
3248// Move Low to High and High to Low packed FP Instructions
3249//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3250def VMOVLHPSZrr : AVX512PSI<0x16, MRMSrcReg, (outs VR128X:$dst),
3251 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3252 "vmovlhps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3253 [(set VR128X:$dst, (v4f32 (X86Movlhps VR128X:$src1, VR128X:$src2)))],
3254 IIC_SSE_MOV_LH>, EVEX_4V;
3255def VMOVHLPSZrr : AVX512PSI<0x12, MRMSrcReg, (outs VR128X:$dst),
3256 (ins VR128X:$src1, VR128X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3257 "vmovhlps\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3258 [(set VR128X:$dst, (v4f32 (X86Movhlps VR128X:$src1, VR128X:$src2)))],
3259 IIC_SSE_MOV_LH>, EVEX_4V;
3260
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3261let Predicates = [HasAVX512] in {
3262 // MOVLHPS patterns
3263 def : Pat<(v4i32 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3264 (VMOVLHPSZrr VR128X:$src1, VR128X:$src2)>;
3265 def : Pat<(v2i64 (X86Movlhps VR128X:$src1, VR128X:$src2)),
3266 (VMOVLHPSZrr (v2i64 VR128X:$src1), VR128X:$src2)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3267
Craig Topperdbe8b7d2013-09-27 07:20:47 +0000[diff] [blame]3268 // MOVHLPS patterns
3269 def : Pat<(v4i32 (X86Movhlps VR128X:$src1, VR128X:$src2)),
3270 (VMOVHLPSZrr VR128X:$src1, VR128X:$src2)>;
3271}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3272
3273//===----------------------------------------------------------------------===//
3274// FMA - Fused Multiply Operations
3275//
3276let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3277multiclass avx512_fma3p_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3278 X86VectorVTInfo _> {
3279 defm r: AVX512_masking_3src<opc, MRMSrcReg, _, (outs _.RC:$dst),
3280 (ins _.RC:$src2, _.RC:$src3),
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3281 OpcodeStr, "$src3, $src2", "$src2, $src3",
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3282 (_.VT (OpNode _.RC:$src1, _.RC:$src2, _.RC:$src3))>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3283 AVX512FMA3Base;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3284
3285 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3286 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3287 (ins _.RC:$src1, _.RC:$src2, _.MemOp:$src3),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3288 !strconcat(OpcodeStr, " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3289 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, _.RC:$src2,
3290 (_.MemOpFrag addr:$src3))))]>;
3291 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3292 (ins _.RC:$src1, _.RC:$src2, _.ScalarMemOp:$src3),
3293 !strconcat(OpcodeStr, " \t{${src3}", _.BroadcastStr,
3294 ", $src2, $dst|$dst, $src2, ${src3}", _.BroadcastStr, "}"),
3295 [(set _.RC:$dst, (OpNode _.RC:$src1, _.RC:$src2,
3296 (_.VT (X86VBroadcast (_.ScalarLdFrag addr:$src3)))))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3297}
3298} // Constraints = "$src1 = $dst"
3299
3300let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3301 defm VFMADD213PSZ : avx512_fma3p_rm<0xA8, "vfmadd213ps", X86Fmadd,
3302 v16f32_info>,
3303 EVEX_V512, EVEX_CD8<32, CD8VF>;
3304 defm VFMSUB213PSZ : avx512_fma3p_rm<0xAA, "vfmsub213ps", X86Fmsub,
3305 v16f32_info>,
3306 EVEX_V512, EVEX_CD8<32, CD8VF>;
3307 defm VFMADDSUB213PSZ : avx512_fma3p_rm<0xA6, "vfmaddsub213ps", X86Fmaddsub,
3308 v16f32_info>,
3309 EVEX_V512, EVEX_CD8<32, CD8VF>;
3310 defm VFMSUBADD213PSZ : avx512_fma3p_rm<0xA7, "vfmsubadd213ps", X86Fmsubadd,
3311 v16f32_info>,
3312 EVEX_V512, EVEX_CD8<32, CD8VF>;
3313 defm VFNMADD213PSZ : avx512_fma3p_rm<0xAC, "vfnmadd213ps", X86Fnmadd,
3314 v16f32_info>,
3315 EVEX_V512, EVEX_CD8<32, CD8VF>;
3316 defm VFNMSUB213PSZ : avx512_fma3p_rm<0xAE, "vfnmsub213ps", X86Fnmsub,
3317 v16f32_info>,
3318 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3319}
3320let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3321 defm VFMADD213PDZ : avx512_fma3p_rm<0xA8, "vfmadd213pd", X86Fmadd,
3322 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3323 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3324 defm VFMSUB213PDZ : avx512_fma3p_rm<0xAA, "vfmsub213pd", X86Fmsub,
3325 v8f64_info>,
Adam Nemet2e91ee52014-08-14 17:13:19 +0000[diff] [blame]3326 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3327 defm VFMADDSUB213PDZ : avx512_fma3p_rm<0xA6, "vfmaddsub213pd", X86Fmaddsub,
3328 v8f64_info>,
3329 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3330 defm VFMSUBADD213PDZ : avx512_fma3p_rm<0xA7, "vfmsubadd213pd", X86Fmsubadd,
3331 v8f64_info>,
3332 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3333 defm VFNMADD213PDZ : avx512_fma3p_rm<0xAC, "vfnmadd213pd", X86Fnmadd,
3334 v8f64_info>,
3335 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3336 defm VFNMSUB213PDZ : avx512_fma3p_rm<0xAE, "vfnmsub213pd", X86Fnmsub,
3337 v8f64_info>,
3338 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3339}
3340
3341let Constraints = "$src1 = $dst" in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3342multiclass avx512_fma3p_m132<bits<8> opc, string OpcodeStr, SDNode OpNode,
3343 X86VectorVTInfo _> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3344 let mayLoad = 1 in
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3345 def m: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3346 (ins _.RC:$src1, _.RC:$src3, _.MemOp:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3347 !strconcat(OpcodeStr, " \t{$src2, $src3, $dst|$dst, $src3, $src2}"),
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3348 [(set _.RC:$dst, (_.VT (OpNode _.RC:$src1, (_.MemOpFrag addr:$src2),
3349 _.RC:$src3)))]>;
3350 def mb: AVX512FMA3<opc, MRMSrcMem, (outs _.RC:$dst),
3351 (ins _.RC:$src1, _.RC:$src3, _.ScalarMemOp:$src2),
3352 !strconcat(OpcodeStr, " \t{${src2}", _.BroadcastStr,
3353 ", $src3, $dst|$dst, $src3, ${src2}", _.BroadcastStr, "}"),
3354 [(set _.RC:$dst,
3355 (OpNode _.RC:$src1, (_.VT (X86VBroadcast
3356 (_.ScalarLdFrag addr:$src2))),
3357 _.RC:$src3))]>, EVEX_B;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3358}
3359} // Constraints = "$src1 = $dst"
3360
3361
3362let ExeDomain = SSEPackedSingle in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3363 defm VFMADD132PSZ : avx512_fma3p_m132<0x98, "vfmadd132ps", X86Fmadd,
3364 v16f32_info>,
3365 EVEX_V512, EVEX_CD8<32, CD8VF>;
3366 defm VFMSUB132PSZ : avx512_fma3p_m132<0x9A, "vfmsub132ps", X86Fmsub,
3367 v16f32_info>,
3368 EVEX_V512, EVEX_CD8<32, CD8VF>;
3369 defm VFMADDSUB132PSZ : avx512_fma3p_m132<0x96, "vfmaddsub132ps", X86Fmaddsub,
3370 v16f32_info>,
3371 EVEX_V512, EVEX_CD8<32, CD8VF>;
3372 defm VFMSUBADD132PSZ : avx512_fma3p_m132<0x97, "vfmsubadd132ps", X86Fmsubadd,
3373 v16f32_info>,
3374 EVEX_V512, EVEX_CD8<32, CD8VF>;
3375 defm VFNMADD132PSZ : avx512_fma3p_m132<0x9C, "vfnmadd132ps", X86Fnmadd,
3376 v16f32_info>,
3377 EVEX_V512, EVEX_CD8<32, CD8VF>;
3378 defm VFNMSUB132PSZ : avx512_fma3p_m132<0x9E, "vfnmsub132ps", X86Fnmsub,
3379 v16f32_info>,
3380 EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3381}
3382let ExeDomain = SSEPackedDouble in {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]3383 defm VFMADD132PDZ : avx512_fma3p_m132<0x98, "vfmadd132pd", X86Fmadd,
3384 v8f64_info>,
3385 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3386 defm VFMSUB132PDZ : avx512_fma3p_m132<0x9A, "vfmsub132pd", X86Fmsub,
3387 v8f64_info>,
3388 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3389 defm VFMADDSUB132PDZ : avx512_fma3p_m132<0x96, "vfmaddsub132pd", X86Fmaddsub,
3390 v8f64_info>,
3391 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3392 defm VFMSUBADD132PDZ : avx512_fma3p_m132<0x97, "vfmsubadd132pd", X86Fmsubadd,
3393 v8f64_info>,
3394 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3395 defm VFNMADD132PDZ : avx512_fma3p_m132<0x9C, "vfnmadd132pd", X86Fnmadd,
3396 v8f64_info>,
3397 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
3398 defm VFNMSUB132PDZ : avx512_fma3p_m132<0x9E, "vfnmsub132pd", X86Fnmsub,
3399 v8f64_info>,
3400 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3401}
3402
3403// Scalar FMA
3404let Constraints = "$src1 = $dst" in {
3405multiclass avx512_fma3s_rm<bits<8> opc, string OpcodeStr, SDNode OpNode,
3406 RegisterClass RC, ValueType OpVT,
3407 X86MemOperand x86memop, Operand memop,
3408 PatFrag mem_frag> {
3409 let isCommutable = 1 in
3410 def r : AVX512FMA3<opc, MRMSrcReg, (outs RC:$dst),
3411 (ins RC:$src1, RC:$src2, RC:$src3),
3412 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3413 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3414 [(set RC:$dst,
3415 (OpVT (OpNode RC:$src2, RC:$src1, RC:$src3)))]>;
3416 let mayLoad = 1 in
3417 def m : AVX512FMA3<opc, MRMSrcMem, (outs RC:$dst),
3418 (ins RC:$src1, RC:$src2, f128mem:$src3),
3419 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3420 " \t{$src3, $src2, $dst|$dst, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3421 [(set RC:$dst,
3422 (OpVT (OpNode RC:$src2, RC:$src1,
3423 (mem_frag addr:$src3))))]>;
3424}
3425
3426} // Constraints = "$src1 = $dst"
3427
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3428defm VFMADDSSZ : avx512_fma3s_rm<0xA9, "vfmadd213ss", X86Fmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3429 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3430defm VFMADDSDZ : avx512_fma3s_rm<0xA9, "vfmadd213sd", X86Fmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3431 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3432defm VFMSUBSSZ : avx512_fma3s_rm<0xAB, "vfmsub213ss", X86Fmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3433 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3434defm VFMSUBSDZ : avx512_fma3s_rm<0xAB, "vfmsub213sd", X86Fmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3435 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3436defm VFNMADDSSZ : avx512_fma3s_rm<0xAD, "vfnmadd213ss", X86Fnmadd, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3437 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3438defm VFNMADDSDZ : avx512_fma3s_rm<0xAD, "vfnmadd213sd", X86Fnmadd, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3439 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3440defm VFNMSUBSSZ : avx512_fma3s_rm<0xAF, "vfnmsub213ss", X86Fnmsub, FR32X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3441 f32, f32mem, ssmem, loadf32>, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3442defm VFNMSUBSDZ : avx512_fma3s_rm<0xAF, "vfnmsub213sd", X86Fnmsub, FR64X,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3443 f64, f64mem, sdmem, loadf64>, VEX_W, EVEX_CD8<64, CD8VT1>;
3444
3445//===----------------------------------------------------------------------===//
3446// AVX-512 Scalar convert from sign integer to float/double
3447//===----------------------------------------------------------------------===//
3448
3449multiclass avx512_vcvtsi<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3450 X86MemOperand x86memop, string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3451let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3452 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3453 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3454 EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3455 let mayLoad = 1 in
3456 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst),
3457 (ins DstRC:$src1, x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3458 !strconcat(asm," \t{$src, $src1, $dst|$dst, $src1, $src}"), []>,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3459 EVEX_4V;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3460} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3461}
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3462let Predicates = [HasAVX512] in {
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3463defm VCVTSI2SSZ : avx512_vcvtsi<0x2A, GR32, FR32X, i32mem, "cvtsi2ss{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3464 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3465defm VCVTSI642SSZ : avx512_vcvtsi<0x2A, GR64, FR32X, i64mem, "cvtsi2ss{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3466 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3467defm VCVTSI2SDZ : avx512_vcvtsi<0x2A, GR32, FR64X, i32mem, "cvtsi2sd{l}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3468 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3469defm VCVTSI642SDZ : avx512_vcvtsi<0x2A, GR64, FR64X, i64mem, "cvtsi2sd{q}">,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3470 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3471
3472def : Pat<(f32 (sint_to_fp (loadi32 addr:$src))),
3473 (VCVTSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3474def : Pat<(f32 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3475 (VCVTSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3476def : Pat<(f64 (sint_to_fp (loadi32 addr:$src))),
3477 (VCVTSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3478def : Pat<(f64 (sint_to_fp (loadi64 addr:$src))),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3479 (VCVTSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3480
3481def : Pat<(f32 (sint_to_fp GR32:$src)),
3482 (VCVTSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3483def : Pat<(f32 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3484 (VCVTSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3485def : Pat<(f64 (sint_to_fp GR32:$src)),
3486 (VCVTSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3487def : Pat<(f64 (sint_to_fp GR64:$src)),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3488 (VCVTSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
3489
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3490defm VCVTUSI2SSZ : avx512_vcvtsi<0x7B, GR32, FR32X, i32mem, "cvtusi2ss{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3491 XS, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3492defm VCVTUSI642SSZ : avx512_vcvtsi<0x7B, GR64, FR32X, i64mem, "cvtusi2ss{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3493 XS, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3494defm VCVTUSI2SDZ : avx512_vcvtsi<0x7B, GR32, FR64X, i32mem, "cvtusi2sd{l}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3495 XD, VEX_LIG, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3496defm VCVTUSI642SDZ : avx512_vcvtsi<0x7B, GR64, FR64X, i64mem, "cvtusi2sd{q}">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3497 XD, VEX_W, VEX_LIG, EVEX_CD8<64, CD8VT1>;
3498
3499def : Pat<(f32 (uint_to_fp (loadi32 addr:$src))),
3500 (VCVTUSI2SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3501def : Pat<(f32 (uint_to_fp (loadi64 addr:$src))),
3502 (VCVTUSI642SSZrm (f32 (IMPLICIT_DEF)), addr:$src)>;
3503def : Pat<(f64 (uint_to_fp (loadi32 addr:$src))),
3504 (VCVTUSI2SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3505def : Pat<(f64 (uint_to_fp (loadi64 addr:$src))),
3506 (VCVTUSI642SDZrm (f64 (IMPLICIT_DEF)), addr:$src)>;
3507
3508def : Pat<(f32 (uint_to_fp GR32:$src)),
3509 (VCVTUSI2SSZrr (f32 (IMPLICIT_DEF)), GR32:$src)>;
3510def : Pat<(f32 (uint_to_fp GR64:$src)),
3511 (VCVTUSI642SSZrr (f32 (IMPLICIT_DEF)), GR64:$src)>;
3512def : Pat<(f64 (uint_to_fp GR32:$src)),
3513 (VCVTUSI2SDZrr (f64 (IMPLICIT_DEF)), GR32:$src)>;
3514def : Pat<(f64 (uint_to_fp GR64:$src)),
3515 (VCVTUSI642SDZrr (f64 (IMPLICIT_DEF)), GR64:$src)>;
Andrew Trick15a47742013-10-09 05:11:10 +0000[diff] [blame]3516}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3517
3518//===----------------------------------------------------------------------===//
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3519// AVX-512 Scalar convert from float/double to integer
3520//===----------------------------------------------------------------------===//
3521multiclass avx512_cvt_s_int<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3522 Intrinsic Int, Operand memop, ComplexPattern mem_cpat,
3523 string asm> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3524let hasSideEffects = 0 in {
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3525 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3526 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3527 [(set DstRC:$dst, (Int SrcRC:$src))]>, EVEX, VEX_LIG,
3528 Requires<[HasAVX512]>;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3529 let mayLoad = 1 in
3530 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3531 !strconcat(asm," \t{$src, $dst|$dst, $src}"), []>, EVEX, VEX_LIG,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3532 Requires<[HasAVX512]>;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3533} // hasSideEffects = 0
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3534}
3535let Predicates = [HasAVX512] in {
3536// Convert float/double to signed/unsigned int 32/64
3537defm VCVTSS2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse_cvtss2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3538 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3539 XS, EVEX_CD8<32, CD8VT1>;
3540defm VCVTSS2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse_cvtss2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3541 ssmem, sse_load_f32, "cvtss2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3542 XS, VEX_W, EVEX_CD8<32, CD8VT1>;
3543defm VCVTSS2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtss2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3544 ssmem, sse_load_f32, "cvtss2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3545 XS, EVEX_CD8<32, CD8VT1>;
3546defm VCVTSS2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3547 int_x86_avx512_cvtss2usi64, ssmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3548 sse_load_f32, "cvtss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3549 EVEX_CD8<32, CD8VT1>;
3550defm VCVTSD2SIZ: avx512_cvt_s_int<0x2D, VR128X, GR32, int_x86_sse2_cvtsd2si,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3551 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3552 XD, EVEX_CD8<64, CD8VT1>;
3553defm VCVTSD2SI64Z: avx512_cvt_s_int<0x2D, VR128X, GR64, int_x86_sse2_cvtsd2si64,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3554 sdmem, sse_load_f64, "cvtsd2si">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3555 XD, VEX_W, EVEX_CD8<64, CD8VT1>;
3556defm VCVTSD2USIZ: avx512_cvt_s_int<0x79, VR128X, GR32, int_x86_avx512_cvtsd2usi,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3557 sdmem, sse_load_f64, "cvtsd2usi">,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3558 XD, EVEX_CD8<64, CD8VT1>;
3559defm VCVTSD2USI64Z: avx512_cvt_s_int<0x79, VR128X, GR64,
3560 int_x86_avx512_cvtsd2usi64, sdmem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3561 sse_load_f64, "cvtsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3562 EVEX_CD8<64, CD8VT1>;
3563
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3564let isCodeGenOnly = 1 in {
3565 defm Int_VCVTSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3566 int_x86_sse_cvtsi2ss, i32mem, loadi32, "cvtsi2ss{l}",
3567 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3568 defm Int_VCVTSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3569 int_x86_sse_cvtsi642ss, i64mem, loadi64, "cvtsi2ss{q}",
3570 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3571 defm Int_VCVTSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3572 int_x86_sse2_cvtsi2sd, i32mem, loadi32, "cvtsi2sd{l}",
3573 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3574 defm Int_VCVTSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3575 int_x86_sse2_cvtsi642sd, i64mem, loadi64, "cvtsi2sd{q}",
3576 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3577
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3578 defm Int_VCVTUSI2SSZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3579 int_x86_avx512_cvtusi2ss, i32mem, loadi32, "cvtusi2ss{l}",
3580 SSE_CVT_Scalar, 0>, XS, EVEX_4V;
3581 defm Int_VCVTUSI2SS64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3582 int_x86_avx512_cvtusi642ss, i64mem, loadi64, "cvtusi2ss{q}",
3583 SSE_CVT_Scalar, 0>, XS, EVEX_4V, VEX_W;
3584 defm Int_VCVTUSI2SDZ : sse12_cvt_sint_3addr<0x2A, GR32, VR128X,
3585 int_x86_avx512_cvtusi2sd, i32mem, loadi32, "cvtusi2sd{l}",
3586 SSE_CVT_Scalar, 0>, XD, EVEX_4V;
3587 defm Int_VCVTUSI2SD64Z : sse12_cvt_sint_3addr<0x2A, GR64, VR128X,
3588 int_x86_avx512_cvtusi642sd, i64mem, loadi64, "cvtusi2sd{q}",
3589 SSE_CVT_Scalar, 0>, XD, EVEX_4V, VEX_W;
3590} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3591
3592// Convert float/double to signed/unsigned int 32/64 with truncation
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3593let isCodeGenOnly = 1 in {
3594 defm Int_VCVTTSS2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse_cvttss2si,
3595 ssmem, sse_load_f32, "cvttss2si">,
3596 XS, EVEX_CD8<32, CD8VT1>;
3597 defm Int_VCVTTSS2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3598 int_x86_sse_cvttss2si64, ssmem, sse_load_f32,
3599 "cvttss2si">, XS, VEX_W,
3600 EVEX_CD8<32, CD8VT1>;
3601 defm Int_VCVTTSD2SIZ : avx512_cvt_s_int<0x2C, VR128X, GR32, int_x86_sse2_cvttsd2si,
3602 sdmem, sse_load_f64, "cvttsd2si">, XD,
3603 EVEX_CD8<64, CD8VT1>;
3604 defm Int_VCVTTSD2SI64Z : avx512_cvt_s_int<0x2C, VR128X, GR64,
3605 int_x86_sse2_cvttsd2si64, sdmem, sse_load_f64,
3606 "cvttsd2si">, XD, VEX_W,
3607 EVEX_CD8<64, CD8VT1>;
3608 defm Int_VCVTTSS2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3609 int_x86_avx512_cvttss2usi, ssmem, sse_load_f32,
3610 "cvttss2usi">, XS, EVEX_CD8<32, CD8VT1>;
3611 defm Int_VCVTTSS2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3612 int_x86_avx512_cvttss2usi64, ssmem,
3613 sse_load_f32, "cvttss2usi">, XS, VEX_W,
3614 EVEX_CD8<32, CD8VT1>;
3615 defm Int_VCVTTSD2USIZ : avx512_cvt_s_int<0x78, VR128X, GR32,
3616 int_x86_avx512_cvttsd2usi,
3617 sdmem, sse_load_f64, "cvttsd2usi">, XD,
3618 EVEX_CD8<64, CD8VT1>;
3619 defm Int_VCVTTSD2USI64Z : avx512_cvt_s_int<0x78, VR128X, GR64,
3620 int_x86_avx512_cvttsd2usi64, sdmem,
3621 sse_load_f64, "cvttsd2usi">, XD, VEX_W,
3622 EVEX_CD8<64, CD8VT1>;
3623} // isCodeGenOnly = 1
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3624
3625multiclass avx512_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
3626 SDNode OpNode, X86MemOperand x86memop, PatFrag ld_frag,
3627 string asm> {
3628 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3629 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3630 [(set DstRC:$dst, (OpNode SrcRC:$src))]>, EVEX;
3631 def rm : SI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3632 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3633 [(set DstRC:$dst, (OpNode (ld_frag addr:$src)))]>, EVEX;
3634}
3635
3636defm VCVTTSS2SIZ : avx512_cvt_s<0x2C, FR32X, GR32, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3637 loadf32, "cvttss2si">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3638 EVEX_CD8<32, CD8VT1>;
3639defm VCVTTSS2USIZ : avx512_cvt_s<0x78, FR32X, GR32, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3640 loadf32, "cvttss2usi">, XS,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3641 EVEX_CD8<32, CD8VT1>;
3642defm VCVTTSS2SI64Z : avx512_cvt_s<0x2C, FR32X, GR64, fp_to_sint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3643 loadf32, "cvttss2si">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3644 EVEX_CD8<32, CD8VT1>;
3645defm VCVTTSS2USI64Z : avx512_cvt_s<0x78, FR32X, GR64, fp_to_uint, f32mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3646 loadf32, "cvttss2usi">, XS, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3647 EVEX_CD8<32, CD8VT1>;
3648defm VCVTTSD2SIZ : avx512_cvt_s<0x2C, FR64X, GR32, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3649 loadf64, "cvttsd2si">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3650 EVEX_CD8<64, CD8VT1>;
3651defm VCVTTSD2USIZ : avx512_cvt_s<0x78, FR64X, GR32, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3652 loadf64, "cvttsd2usi">, XD,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3653 EVEX_CD8<64, CD8VT1>;
3654defm VCVTTSD2SI64Z : avx512_cvt_s<0x2C, FR64X, GR64, fp_to_sint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3655 loadf64, "cvttsd2si">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3656 EVEX_CD8<64, CD8VT1>;
3657defm VCVTTSD2USI64Z : avx512_cvt_s<0x78, FR64X, GR64, fp_to_uint, f64mem,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3658 loadf64, "cvttsd2usi">, XD, VEX_W,
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3659 EVEX_CD8<64, CD8VT1>;
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3660} // HasAVX512
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]3661//===----------------------------------------------------------------------===//
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3662// AVX-512 Convert form float to double and back
3663//===----------------------------------------------------------------------===//
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3664let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3665def VCVTSS2SDZrr : AVX512XSI<0x5A, MRMSrcReg, (outs FR64X:$dst),
3666 (ins FR32X:$src1, FR32X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3667 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3668 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2F]>;
3669let mayLoad = 1 in
3670def VCVTSS2SDZrm : AVX512XSI<0x5A, MRMSrcMem, (outs FR64X:$dst),
3671 (ins FR32X:$src1, f32mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3672 "vcvtss2sd\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3673 []>, EVEX_4V, VEX_LIG, Sched<[WriteCvtF2FLd, ReadAfterLd]>,
3674 EVEX_CD8<32, CD8VT1>;
3675
3676// Convert scalar double to scalar single
3677def VCVTSD2SSZrr : AVX512XDI<0x5A, MRMSrcReg, (outs FR32X:$dst),
3678 (ins FR64X:$src1, FR64X:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3679 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3680 []>, EVEX_4V, VEX_LIG, VEX_W, Sched<[WriteCvtF2F]>;
3681let mayLoad = 1 in
3682def VCVTSD2SSZrm : AVX512XDI<0x5A, MRMSrcMem, (outs FR32X:$dst),
3683 (ins FR64X:$src1, f64mem:$src2),
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]3684 "vcvtsd2ss\t{$src2, $src1, $dst|$dst, $src1, $src2}",
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3685 []>, EVEX_4V, VEX_LIG, VEX_W,
3686 Sched<[WriteCvtF2FLd, ReadAfterLd]>, EVEX_CD8<64, CD8VT1>;
3687}
3688
3689def : Pat<(f64 (fextend FR32X:$src)), (VCVTSS2SDZrr FR32X:$src, FR32X:$src)>,
3690 Requires<[HasAVX512]>;
3691def : Pat<(fextend (loadf32 addr:$src)),
3692 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>, Requires<[HasAVX512]>;
3693
3694def : Pat<(extloadf32 addr:$src),
3695 (VCVTSS2SDZrm (f32 (IMPLICIT_DEF)), addr:$src)>,
3696 Requires<[HasAVX512, OptForSize]>;
3697
3698def : Pat<(extloadf32 addr:$src),
3699 (VCVTSS2SDZrr (f32 (IMPLICIT_DEF)), (VMOVSSZrm addr:$src))>,
3700 Requires<[HasAVX512, OptForSpeed]>;
3701
3702def : Pat<(f32 (fround FR64X:$src)), (VCVTSD2SSZrr FR64X:$src, FR64X:$src)>,
3703 Requires<[HasAVX512]>;
3704
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3705multiclass avx512_vcvt_fp_with_rc<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3706 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3707 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3708 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3709let hasSideEffects = 0 in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3710 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3711 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3712 [(set DstRC:$dst,
3713 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3714 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3715 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3716 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3717 let mayLoad = 1 in
3718 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3719 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3720 [(set DstRC:$dst,
3721 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3722} // hasSideEffects = 0
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3723}
3724
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3725multiclass avx512_vcvt_fp<bits<8> opc, string asm, RegisterClass SrcRC,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3726 RegisterClass DstRC, SDNode OpNode, PatFrag mem_frag,
3727 X86MemOperand x86memop, ValueType OpVT, ValueType InVT,
3728 Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3729let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3730 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3731 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3732 [(set DstRC:$dst,
3733 (OpVT (OpNode (InVT SrcRC:$src))))], d>, EVEX;
3734 let mayLoad = 1 in
3735 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3736 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3737 [(set DstRC:$dst,
3738 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3739} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3740}
3741
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3742defm VCVTPD2PSZ : avx512_vcvt_fp_with_rc<0x5A, "vcvtpd2ps", VR512, VR256X, fround,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3743 memopv8f64, f512mem, v8f32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3744 SSEPackedSingle>, EVEX_V512, VEX_W, PD,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3745 EVEX_CD8<64, CD8VF>;
3746
3747defm VCVTPS2PDZ : avx512_vcvt_fp<0x5A, "vcvtps2pd", VR256X, VR512, fextend,
3748 memopv4f64, f256mem, v8f64, v8f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3749 SSEPackedDouble>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3750 EVEX_CD8<32, CD8VH>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3751def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3752 (VCVTPS2PDZrm addr:$src)>;
Elena Demikhovsky3629b4a2014-01-06 08:45:54 +0000[diff] [blame]3753
3754def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3755 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), (i32 FROUND_CURRENT))),
3756 (VCVTPD2PSZrr VR512:$src)>;
3757
3758def : Pat<(v8f32 (int_x86_avx512_mask_cvtpd2ps_512 (v8f64 VR512:$src),
3759 (bc_v8f32(v8i32 immAllZerosV)), (i8 -1), imm:$rc)),
3760 (VCVTPD2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3761
3762//===----------------------------------------------------------------------===//
3763// AVX-512 Vector convert from sign integer to float/double
3764//===----------------------------------------------------------------------===//
3765
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3766defm VCVTDQ2PSZ : avx512_vcvt_fp_with_rc<0x5B, "vcvtdq2ps", VR512, VR512, sint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3767 memopv8i64, i512mem, v16f32, v16i32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3768 SSEPackedSingle>, EVEX_V512, PS,
Craig Topperda7160d2014-02-01 08:17:56 +0000[diff] [blame]3769 EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3770
3771defm VCVTDQ2PDZ : avx512_vcvt_fp<0xE6, "vcvtdq2pd", VR256X, VR512, sint_to_fp,
3772 memopv4i64, i256mem, v8f64, v8i32,
3773 SSEPackedDouble>, EVEX_V512, XS,
3774 EVEX_CD8<32, CD8VH>;
3775
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3776defm VCVTTPS2DQZ : avx512_vcvt_fp<0x5B, "vcvttps2dq", VR512, VR512, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3777 memopv16f32, f512mem, v16i32, v16f32,
3778 SSEPackedSingle>, EVEX_V512, XS,
3779 EVEX_CD8<32, CD8VF>;
3780
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3781defm VCVTTPD2DQZ : avx512_vcvt_fp<0xE6, "vcvttpd2dq", VR512, VR256X, fp_to_sint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3782 memopv8f64, f512mem, v8i32, v8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3783 SSEPackedDouble>, EVEX_V512, PD, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3784 EVEX_CD8<64, CD8VF>;
3785
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3786defm VCVTTPS2UDQZ : avx512_vcvt_fp<0x78, "vcvttps2udq", VR512, VR512, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3787 memopv16f32, f512mem, v16i32, v16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3788 SSEPackedSingle>, EVEX_V512, PS,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3789 EVEX_CD8<32, CD8VF>;
3790
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3791// cvttps2udq (src, 0, mask-all-ones, sae-current)
3792def : Pat<(v16i32 (int_x86_avx512_mask_cvttps2udq_512 (v16f32 VR512:$src),
3793 (v16i32 immAllZerosV), (i16 -1), FROUND_CURRENT)),
3794 (VCVTTPS2UDQZrr VR512:$src)>;
3795
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3796defm VCVTTPD2UDQZ : avx512_vcvt_fp<0x78, "vcvttpd2udq", VR512, VR256X, fp_to_uint,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3797 memopv8f64, f512mem, v8i32, v8f64,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3798 SSEPackedDouble>, EVEX_V512, PS, VEX_W,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3799 EVEX_CD8<64, CD8VF>;
3800
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3801// cvttpd2udq (src, 0, mask-all-ones, sae-current)
3802def : Pat<(v8i32 (int_x86_avx512_mask_cvttpd2udq_512 (v8f64 VR512:$src),
3803 (v8i32 immAllZerosV), (i8 -1), FROUND_CURRENT)),
3804 (VCVTTPD2UDQZrr VR512:$src)>;
3805
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3806defm VCVTUDQ2PDZ : avx512_vcvt_fp<0x7A, "vcvtudq2pd", VR256X, VR512, uint_to_fp,
3807 memopv4i64, f256mem, v8f64, v8i32,
3808 SSEPackedDouble>, EVEX_V512, XS,
3809 EVEX_CD8<32, CD8VH>;
3810
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3811defm VCVTUDQ2PSZ : avx512_vcvt_fp_with_rc<0x7A, "vcvtudq2ps", VR512, VR512, uint_to_fp,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3812 memopv16i32, f512mem, v16f32, v16i32,
3813 SSEPackedSingle>, EVEX_V512, XD,
3814 EVEX_CD8<32, CD8VF>;
3815
3816def : Pat<(v8i32 (fp_to_uint (v8f32 VR256X:$src1))),
3817 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3818 (v16f32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3819
Elena Demikhovsky3dcfbdf2014-04-08 07:24:02 +0000[diff] [blame]3820def : Pat<(v4i32 (fp_to_uint (v4f32 VR128X:$src1))),
3821 (EXTRACT_SUBREG (v16i32 (VCVTTPS2UDQZrr
3822 (v16f32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
3823
3824def : Pat<(v8f32 (uint_to_fp (v8i32 VR256X:$src1))),
3825 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3826 (v16i32 (SUBREG_TO_REG (i32 0), VR256X:$src1, sub_ymm)))), sub_ymm)>;
3827
3828def : Pat<(v4f32 (uint_to_fp (v4i32 VR128X:$src1))),
3829 (EXTRACT_SUBREG (v16f32 (VCVTUDQ2PSZrr
3830 (v16i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_xmm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3831
Cameron McInallyf10a7c92014-06-18 14:04:37 +0000[diff] [blame]3832def : Pat<(v4f64 (uint_to_fp (v4i32 VR128X:$src1))),
3833 (EXTRACT_SUBREG (v8f64 (VCVTUDQ2PDZrr
3834 (v8i32 (SUBREG_TO_REG (i32 0), VR128X:$src1, sub_xmm)))), sub_ymm)>;
3835
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3836def : Pat<(v16f32 (int_x86_avx512_mask_cvtdq2ps_512 (v16i32 VR512:$src),
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3837 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3838 (VCVTDQ2PSZrrb VR512:$src, imm:$rc)>;
Elena Demikhovsky52e4a0e2014-01-05 10:46:09 +0000[diff] [blame]3839def : Pat<(v8f64 (int_x86_avx512_mask_cvtdq2pd_512 (v8i32 VR256X:$src),
3840 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3841 (VCVTDQ2PDZrr VR256X:$src)>;
3842def : Pat<(v16f32 (int_x86_avx512_mask_cvtudq2ps_512 (v16i32 VR512:$src),
3843 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), imm:$rc)),
3844 (VCVTUDQ2PSZrrb VR512:$src, imm:$rc)>;
3845def : Pat<(v8f64 (int_x86_avx512_mask_cvtudq2pd_512 (v8i32 VR256X:$src),
3846 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
3847 (VCVTUDQ2PDZrr VR256X:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3848
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3849multiclass avx512_vcvt_fp2int<bits<8> opc, string asm, RegisterClass SrcRC,
3850 RegisterClass DstRC, PatFrag mem_frag,
3851 X86MemOperand x86memop, Domain d> {
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3852let hasSideEffects = 0 in {
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3853 def rr : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3854 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3855 [], d>, EVEX;
3856 def rrb : AVX512PI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src, AVX512RC:$rc),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3857 !strconcat(asm," \t{$rc, $src, $dst|$dst, $src, $rc}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3858 [], d>, EVEX, EVEX_B, EVEX_RC;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3859 let mayLoad = 1 in
3860 def rm : AVX512PI<opc, MRMSrcMem, (outs DstRC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3861 !strconcat(asm," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3862 [], d>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3863} // hasSideEffects = 0
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3864}
3865
3866defm VCVTPS2DQZ : avx512_vcvt_fp2int<0x5B, "vcvtps2dq", VR512, VR512,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3867 memopv16f32, f512mem, SSEPackedSingle>, PD,
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3868 EVEX_V512, EVEX_CD8<32, CD8VF>;
3869defm VCVTPD2DQZ : avx512_vcvt_fp2int<0xE6, "vcvtpd2dq", VR512, VR256X,
3870 memopv8f64, f512mem, SSEPackedDouble>, XD, VEX_W,
3871 EVEX_V512, EVEX_CD8<64, CD8VF>;
3872
3873def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2dq_512 (v16f32 VR512:$src),
3874 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3875 (VCVTPS2DQZrrb VR512:$src, imm:$rc)>;
3876
3877def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2dq_512 (v8f64 VR512:$src),
3878 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3879 (VCVTPD2DQZrrb VR512:$src, imm:$rc)>;
3880
3881defm VCVTPS2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtps2udq", VR512, VR512,
3882 memopv16f32, f512mem, SSEPackedSingle>,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3883 PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3884defm VCVTPD2UDQZ : avx512_vcvt_fp2int<0x79, "vcvtpd2udq", VR512, VR256X,
3885 memopv8f64, f512mem, SSEPackedDouble>, VEX_W,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3886 PS, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]3887
3888def : Pat <(v16i32 (int_x86_avx512_mask_cvtps2udq_512 (v16f32 VR512:$src),
3889 (v16i32 immAllZerosV), (i16 -1), imm:$rc)),
3890 (VCVTPS2UDQZrrb VR512:$src, imm:$rc)>;
3891
3892def : Pat <(v8i32 (int_x86_avx512_mask_cvtpd2udq_512 (v8f64 VR512:$src),
3893 (v8i32 immAllZerosV), (i8 -1), imm:$rc)),
3894 (VCVTPD2UDQZrrb VR512:$src, imm:$rc)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3895
3896let Predicates = [HasAVX512] in {
3897 def : Pat<(v8f32 (fround (loadv8f64 addr:$src))),
3898 (VCVTPD2PSZrm addr:$src)>;
3899 def : Pat<(v8f64 (extloadv8f32 addr:$src)),
3900 (VCVTPS2PDZrm addr:$src)>;
3901}
3902
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3903//===----------------------------------------------------------------------===//
3904// Half precision conversion instructions
3905//===----------------------------------------------------------------------===//
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3906multiclass avx512_cvtph2ps<RegisterClass destRC, RegisterClass srcRC,
3907 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3908 def rr : AVX5128I<0x13, MRMSrcReg, (outs destRC:$dst), (ins srcRC:$src),
3909 "vcvtph2ps\t{$src, $dst|$dst, $src}",
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3910 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3911 let hasSideEffects = 0, mayLoad = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3912 def rm : AVX5128I<0x13, MRMSrcMem, (outs destRC:$dst), (ins x86memop:$src),
3913 "vcvtph2ps\t{$src, $dst|$dst, $src}", []>, EVEX;
3914}
3915
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3916multiclass avx512_cvtps2ph<RegisterClass destRC, RegisterClass srcRC,
3917 X86MemOperand x86memop> {
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3918 def rr : AVX512AIi8<0x1D, MRMDestReg, (outs destRC:$dst),
3919 (ins srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3920 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}",
3921 []>, EVEX;
Elena Demikhovskyf404e052014-01-05 14:21:07 +0000[diff] [blame]3922 let hasSideEffects = 0, mayStore = 1 in
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3923 def mr : AVX512AIi8<0x1D, MRMDestMem, (outs),
3924 (ins x86memop:$dst, srcRC:$src1, i32i8imm:$src2),
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3925 "vcvtps2ph \t{$src2, $src1, $dst|$dst, $src1, $src2}", []>, EVEX;
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3926}
3927
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3928defm VCVTPH2PSZ : avx512_cvtph2ps<VR512, VR256X, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3929 EVEX_CD8<32, CD8VH>;
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3930defm VCVTPS2PHZ : avx512_cvtps2ph<VR256X, VR512, f256mem>, EVEX_V512,
Elena Demikhovskydd0794e2013-10-24 07:16:35 +0000[diff] [blame]3931 EVEX_CD8<32, CD8VH>;
3932
Elena Demikhovskya30e4372014-02-05 07:05:03 +0000[diff] [blame]3933def : Pat<(v16i16 (int_x86_avx512_mask_vcvtps2ph_512 (v16f32 VR512:$src),
3934 imm:$rc, (bc_v16i16(v8i32 immAllZerosV)), (i16 -1))),
3935 (VCVTPS2PHZrr VR512:$src, imm:$rc)>;
3936
3937def : Pat<(v16f32 (int_x86_avx512_mask_vcvtph2ps_512 (v16i16 VR256X:$src),
3938 (bc_v16f32(v16i32 immAllZerosV)), (i16 -1), (i32 FROUND_CURRENT))),
3939 (VCVTPH2PSZrr VR256X:$src)>;
3940
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3941let Defs = [EFLAGS], Predicates = [HasAVX512] in {
3942 defm VUCOMISSZ : sse12_ord_cmp<0x2E, FR32X, X86cmp, f32, f32mem, loadf32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3943 "ucomiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3944 EVEX_CD8<32, CD8VT1>;
3945 defm VUCOMISDZ : sse12_ord_cmp<0x2E, FR64X, X86cmp, f64, f64mem, loadf64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3946 "ucomisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3947 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3948 let Pattern = []<dag> in {
3949 defm VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, undef, v4f32, f128mem, load,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3950 "comiss">, PS, EVEX, VEX_LIG,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3951 EVEX_CD8<32, CD8VT1>;
3952 defm VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, undef, v2f64, f128mem, load,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3953 "comisd">, PD, EVEX,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3954 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3955 }
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3956 let isCodeGenOnly = 1 in {
3957 defm Int_VUCOMISSZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3958 load, "ucomiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3959 EVEX_CD8<32, CD8VT1>;
3960 defm Int_VUCOMISDZ : sse12_ord_cmp<0x2E, VR128X, X86ucomi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3961 load, "ucomisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3962 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3963
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3964 defm Int_VCOMISSZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v4f32, f128mem,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]3965 load, "comiss">, PS, EVEX, VEX_LIG,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3966 EVEX_CD8<32, CD8VT1>;
3967 defm Int_VCOMISDZ : sse12_ord_cmp<0x2F, VR128X, X86comi, v2f64, f128mem,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]3968 load, "comisd">, PD, EVEX,
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]3969 VEX_LIG, VEX_W, EVEX_CD8<64, CD8VT1>;
3970 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3971}
3972
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3973/// avx512_fp14_s rcp14ss, rcp14sd, rsqrt14ss, rsqrt14sd
3974multiclass avx512_fp14_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
3975 X86MemOperand x86memop> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3976 let hasSideEffects = 0 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3977 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
3978 (ins RC:$src1, RC:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3979 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3980 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3981 let mayLoad = 1 in {
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3982 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
3983 (ins RC:$src1, x86memop:$src2),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3984 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]3985 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3986 }
3987}
3988}
3989
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3990defm VRCP14SS : avx512_fp14_s<0x4D, "vrcp14ss", FR32X, f32mem>,
3991 EVEX_CD8<32, CD8VT1>;
3992defm VRCP14SD : avx512_fp14_s<0x4D, "vrcp14sd", FR64X, f64mem>,
3993 VEX_W, EVEX_CD8<64, CD8VT1>;
3994defm VRSQRT14SS : avx512_fp14_s<0x4F, "vrsqrt14ss", FR32X, f32mem>,
3995 EVEX_CD8<32, CD8VT1>;
3996defm VRSQRT14SD : avx512_fp14_s<0x4F, "vrsqrt14sd", FR64X, f64mem>,
3997 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]3998
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]3999def : Pat <(v4f32 (int_x86_avx512_rcp14_ss (v4f32 VR128X:$src1),
4000 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4001 (COPY_TO_REGCLASS (VRCP14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4002 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4003
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4004def : Pat <(v2f64 (int_x86_avx512_rcp14_sd (v2f64 VR128X:$src1),
4005 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4006 (COPY_TO_REGCLASS (VRCP14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4007 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4008
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4009def : Pat <(v4f32 (int_x86_avx512_rsqrt14_ss (v4f32 VR128X:$src1),
4010 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1))),
4011 (COPY_TO_REGCLASS (VRSQRT14SSrr (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4012 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4013
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4014def : Pat <(v2f64 (int_x86_avx512_rsqrt14_sd (v2f64 VR128X:$src1),
4015 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1))),
4016 (COPY_TO_REGCLASS (VRSQRT14SDrr (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4017 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4018
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4019/// avx512_fp14_p rcp14ps, rcp14pd, rsqrt14ps, rsqrt14pd
4020multiclass avx512_fp14_p<bits<8> opc, string OpcodeStr, SDNode OpNode,
4021 RegisterClass RC, X86MemOperand x86memop,
4022 PatFrag mem_frag, ValueType OpVt> {
4023 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4024 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4025 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4026 [(set RC:$dst, (OpVt (OpNode RC:$src)))]>,
4027 EVEX;
4028 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4029 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4030 [(set RC:$dst, (OpVt (OpNode (mem_frag addr:$src))))]>,
4031 EVEX;
4032}
4033defm VRSQRT14PSZ : avx512_fp14_p<0x4E, "vrsqrt14ps", X86frsqrt, VR512, f512mem,
4034 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4035defm VRSQRT14PDZ : avx512_fp14_p<0x4E, "vrsqrt14pd", X86frsqrt, VR512, f512mem,
4036 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4037defm VRCP14PSZ : avx512_fp14_p<0x4C, "vrcp14ps", X86frcp, VR512, f512mem,
4038 memopv16f32, v16f32>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4039defm VRCP14PDZ : avx512_fp14_p<0x4C, "vrcp14pd", X86frcp, VR512, f512mem,
4040 memopv8f64, v8f64>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4041
4042def : Pat <(v16f32 (int_x86_avx512_rsqrt14_ps_512 (v16f32 VR512:$src),
4043 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4044 (VRSQRT14PSZr VR512:$src)>;
4045def : Pat <(v8f64 (int_x86_avx512_rsqrt14_pd_512 (v8f64 VR512:$src),
4046 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4047 (VRSQRT14PDZr VR512:$src)>;
4048
4049def : Pat <(v16f32 (int_x86_avx512_rcp14_ps_512 (v16f32 VR512:$src),
4050 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1))),
4051 (VRCP14PSZr VR512:$src)>;
4052def : Pat <(v8f64 (int_x86_avx512_rcp14_pd_512 (v8f64 VR512:$src),
4053 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1))),
4054 (VRCP14PDZr VR512:$src)>;
4055
4056/// avx512_fp28_s rcp28ss, rcp28sd, rsqrt28ss, rsqrt28sd
4057multiclass avx512_fp28_s<bits<8> opc, string OpcodeStr, RegisterClass RC,
4058 X86MemOperand x86memop> {
4059 let hasSideEffects = 0, Predicates = [HasERI] in {
4060 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4061 (ins RC:$src1, RC:$src2),
4062 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4063 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4064 def rrb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4065 (ins RC:$src1, RC:$src2),
4066 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4067 " \t{{sae}, $src2, $src1, $dst|$dst, $src1, $src2, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4068 []>, EVEX_4V, EVEX_B;
4069 let mayLoad = 1 in {
4070 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4071 (ins RC:$src1, x86memop:$src2),
4072 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4073 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>, EVEX_4V;
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4074 }
4075}
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4076}
4077
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4078defm VRCP28SS : avx512_fp28_s<0xCB, "vrcp28ss", FR32X, f32mem>,
4079 EVEX_CD8<32, CD8VT1>;
4080defm VRCP28SD : avx512_fp28_s<0xCB, "vrcp28sd", FR64X, f64mem>,
4081 VEX_W, EVEX_CD8<64, CD8VT1>;
4082defm VRSQRT28SS : avx512_fp28_s<0xCD, "vrsqrt28ss", FR32X, f32mem>,
4083 EVEX_CD8<32, CD8VT1>;
4084defm VRSQRT28SD : avx512_fp28_s<0xCD, "vrsqrt28sd", FR64X, f64mem>,
4085 VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4086
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4087def : Pat <(v4f32 (int_x86_avx512_rcp28_ss (v4f32 VR128X:$src1),
4088 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4089 FROUND_NO_EXC)),
4090 (COPY_TO_REGCLASS (VRCP28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4091 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4092
4093def : Pat <(v2f64 (int_x86_avx512_rcp28_sd (v2f64 VR128X:$src1),
4094 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4095 FROUND_NO_EXC)),
4096 (COPY_TO_REGCLASS (VRCP28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4097 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4098
4099def : Pat <(v4f32 (int_x86_avx512_rsqrt28_ss (v4f32 VR128X:$src1),
4100 (v4f32 VR128X:$src2), (bc_v4f32 (v4i32 immAllZerosV)), (i8 -1),
4101 FROUND_NO_EXC)),
4102 (COPY_TO_REGCLASS (VRSQRT28SSrrb (COPY_TO_REGCLASS VR128X:$src1, FR32X),
4103 (COPY_TO_REGCLASS VR128X:$src2, FR32X)), VR128X)>;
4104
4105def : Pat <(v2f64 (int_x86_avx512_rsqrt28_sd (v2f64 VR128X:$src1),
4106 (v2f64 VR128X:$src2), (bc_v2f64 (v4i32 immAllZerosV)), (i8 -1),
4107 FROUND_NO_EXC)),
4108 (COPY_TO_REGCLASS (VRSQRT28SDrrb (COPY_TO_REGCLASS VR128X:$src1, FR64X),
4109 (COPY_TO_REGCLASS VR128X:$src2, FR64X)), VR128X)>;
4110
4111/// avx512_fp28_p rcp28ps, rcp28pd, rsqrt28ps, rsqrt28pd
4112multiclass avx512_fp28_p<bits<8> opc, string OpcodeStr,
4113 RegisterClass RC, X86MemOperand x86memop> {
4114 let hasSideEffects = 0, Predicates = [HasERI] in {
4115 def r : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4116 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4117 " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4118 []>, EVEX;
4119 def rb : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4120 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4121 " \t{{sae}, $src, $dst|$dst, $src, {sae}}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4122 []>, EVEX, EVEX_B;
4123 def m : AVX5128I<opc, MRMSrcMem, (outs RC:$dst), (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4124 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4125 []>, EVEX;
4126 }
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4127}
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4128defm VRSQRT28PSZ : avx512_fp28_p<0xCC, "vrsqrt28ps", VR512, f512mem>,
4129 EVEX_V512, EVEX_CD8<32, CD8VF>;
4130defm VRSQRT28PDZ : avx512_fp28_p<0xCC, "vrsqrt28pd", VR512, f512mem>,
4131 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4132defm VRCP28PSZ : avx512_fp28_p<0xCA, "vrcp28ps", VR512, f512mem>,
4133 EVEX_V512, EVEX_CD8<32, CD8VF>;
4134defm VRCP28PDZ : avx512_fp28_p<0xCA, "vrcp28pd", VR512, f512mem>,
4135 VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
4136
4137def : Pat <(v16f32 (int_x86_avx512_rsqrt28_ps (v16f32 VR512:$src),
4138 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4139 (VRSQRT28PSZrb VR512:$src)>;
4140def : Pat <(v8f64 (int_x86_avx512_rsqrt28_pd (v8f64 VR512:$src),
4141 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4142 (VRSQRT28PDZrb VR512:$src)>;
4143
4144def : Pat <(v16f32 (int_x86_avx512_rcp28_ps (v16f32 VR512:$src),
4145 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_NO_EXC)),
4146 (VRCP28PSZrb VR512:$src)>;
4147def : Pat <(v8f64 (int_x86_avx512_rcp28_pd (v8f64 VR512:$src),
4148 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_NO_EXC)),
4149 (VRCP28PDZrb VR512:$src)>;
4150
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4151multiclass avx512_sqrt_packed<bits<8> opc, string OpcodeStr, SDNode OpNode,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4152 OpndItins itins_s, OpndItins itins_d> {
4153 def PSZrr :AVX512PSI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4154 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4155 [(set VR512:$dst, (v16f32 (OpNode VR512:$src)))], itins_s.rr>,
4156 EVEX, EVEX_V512;
4157
4158 let mayLoad = 1 in
4159 def PSZrm : AVX512PSI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4160 !strconcat(OpcodeStr, "ps\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4161 [(set VR512:$dst,
4162 (OpNode (v16f32 (bitconvert (memopv16f32 addr:$src)))))],
4163 itins_s.rm>, EVEX, EVEX_V512, EVEX_CD8<32, CD8VF>;
4164
4165 def PDZrr : AVX512PDI<opc, MRMSrcReg, (outs VR512:$dst), (ins VR512:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4166 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4167 [(set VR512:$dst, (v8f64 (OpNode VR512:$src)))], itins_d.rr>,
4168 EVEX, EVEX_V512;
4169
4170 let mayLoad = 1 in
4171 def PDZrm : AVX512PDI<opc, MRMSrcMem, (outs VR512:$dst), (ins f512mem:$src),
Cameron McInally7b544f02014-02-19 15:16:09 +0000[diff] [blame]4172 !strconcat(OpcodeStr, "pd\t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4173 [(set VR512:$dst, (OpNode
4174 (v8f64 (bitconvert (memopv16f32 addr:$src)))))],
4175 itins_d.rm>, EVEX, EVEX_V512, EVEX_CD8<64, CD8VF>;
4176
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4177}
4178
4179multiclass avx512_sqrt_scalar<bits<8> opc, string OpcodeStr,
4180 Intrinsic F32Int, Intrinsic F64Int,
4181 OpndItins itins_s, OpndItins itins_d> {
4182 def SSZr : SI<opc, MRMSrcReg, (outs FR32X:$dst),
4183 (ins FR32X:$src1, FR32X:$src2),
4184 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4185 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4186 [], itins_s.rr>, XS, EVEX_4V;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4187 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4188 def SSZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4189 (ins VR128X:$src1, VR128X:$src2),
4190 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4191 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4192 [(set VR128X:$dst,
4193 (F32Int VR128X:$src1, VR128X:$src2))],
4194 itins_s.rr>, XS, EVEX_4V;
4195 let mayLoad = 1 in {
4196 def SSZm : SI<opc, MRMSrcMem, (outs FR32X:$dst),
4197 (ins FR32X:$src1, f32mem:$src2),
4198 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4199 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4200 [], itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4201 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4202 def SSZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4203 (ins VR128X:$src1, ssmem:$src2),
4204 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4205 "ss\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4206 [(set VR128X:$dst,
4207 (F32Int VR128X:$src1, sse_load_f32:$src2))],
4208 itins_s.rm>, XS, EVEX_4V, EVEX_CD8<32, CD8VT1>;
4209 }
4210 def SDZr : SI<opc, MRMSrcReg, (outs FR64X:$dst),
4211 (ins FR64X:$src1, FR64X:$src2),
4212 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4213 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4214 XD, EVEX_4V, VEX_W;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4215 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4216 def SDZr_Int : SIi8<opc, MRMSrcReg, (outs VR128X:$dst),
4217 (ins VR128X:$src1, VR128X:$src2),
4218 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4219 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4220 [(set VR128X:$dst,
4221 (F64Int VR128X:$src1, VR128X:$src2))],
4222 itins_s.rr>, XD, EVEX_4V, VEX_W;
4223 let mayLoad = 1 in {
4224 def SDZm : SI<opc, MRMSrcMem, (outs FR64X:$dst),
4225 (ins FR64X:$src1, f64mem:$src2),
4226 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4227 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"), []>,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4228 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4229 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4230 def SDZm_Int : SIi8<opc, MRMSrcMem, (outs VR128X:$dst),
4231 (ins VR128X:$src1, sdmem:$src2),
4232 !strconcat(OpcodeStr,
Elena Demikhovskycf088092013-12-11 14:31:04 +0000[diff] [blame]4233 "sd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4234 [(set VR128X:$dst,
4235 (F64Int VR128X:$src1, sse_load_f64:$src2))]>,
4236 XD, EVEX_4V, VEX_W, EVEX_CD8<64, CD8VT1>;
4237 }
4238}
4239
4240
4241defm VSQRT : avx512_sqrt_scalar<0x51, "sqrt",
4242 int_x86_avx512_sqrt_ss, int_x86_avx512_sqrt_sd,
4243 SSE_SQRTSS, SSE_SQRTSD>,
4244 avx512_sqrt_packed<0x51, "vsqrt", fsqrt,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4245 SSE_SQRTPS, SSE_SQRTPD>;
4246
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4247let Predicates = [HasAVX512] in {
Elena Demikhovskyf1648592014-07-22 11:07:31 +0000[diff] [blame]4248 def : Pat<(v16f32 (int_x86_avx512_sqrt_ps_512 (v16f32 VR512:$src1),
4249 (bc_v16f32 (v16i32 immAllZerosV)), (i16 -1), FROUND_CURRENT)),
4250 (VSQRTPSZrr VR512:$src1)>;
4251 def : Pat<(v8f64 (int_x86_avx512_sqrt_pd_512 (v8f64 VR512:$src1),
4252 (bc_v8f64 (v16i32 immAllZerosV)), (i8 -1), FROUND_CURRENT)),
4253 (VSQRTPDZrr VR512:$src1)>;
4254
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4255 def : Pat<(f32 (fsqrt FR32X:$src)),
4256 (VSQRTSSZr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
4257 def : Pat<(f32 (fsqrt (load addr:$src))),
4258 (VSQRTSSZm (f32 (IMPLICIT_DEF)), addr:$src)>,
4259 Requires<[OptForSize]>;
4260 def : Pat<(f64 (fsqrt FR64X:$src)),
4261 (VSQRTSDZr (f64 (IMPLICIT_DEF)), FR64X:$src)>;
4262 def : Pat<(f64 (fsqrt (load addr:$src))),
4263 (VSQRTSDZm (f64 (IMPLICIT_DEF)), addr:$src)>,
4264 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4265
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4266 def : Pat<(f32 (X86frsqrt FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4267 (VRSQRT14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4268 def : Pat<(f32 (X86frsqrt (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4269 (VRSQRT14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4270 Requires<[OptForSize]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4271
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4272 def : Pat<(f32 (X86frcp FR32X:$src)),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4273 (VRCP14SSrr (f32 (IMPLICIT_DEF)), FR32X:$src)>;
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4274 def : Pat<(f32 (X86frcp (load addr:$src))),
Elena Demikhovskyb19c9dc2014-01-13 12:55:03 +0000[diff] [blame]4275 (VRCP14SSrm (f32 (IMPLICIT_DEF)), addr:$src)>,
Elena Demikhovskya3a71402013-10-09 08:16:14 +0000[diff] [blame]4276 Requires<[OptForSize]>;
4277
4278 def : Pat<(int_x86_sse_sqrt_ss VR128X:$src),
4279 (COPY_TO_REGCLASS (VSQRTSSZr (f32 (IMPLICIT_DEF)),
4280 (COPY_TO_REGCLASS VR128X:$src, FR32)),
4281 VR128X)>;
4282 def : Pat<(int_x86_sse_sqrt_ss sse_load_f32:$src),
4283 (VSQRTSSZm_Int (v4f32 (IMPLICIT_DEF)), sse_load_f32:$src)>;
4284
4285 def : Pat<(int_x86_sse2_sqrt_sd VR128X:$src),
4286 (COPY_TO_REGCLASS (VSQRTSDZr (f64 (IMPLICIT_DEF)),
4287 (COPY_TO_REGCLASS VR128X:$src, FR64)),
4288 VR128X)>;
4289 def : Pat<(int_x86_sse2_sqrt_sd sse_load_f64:$src),
4290 (VSQRTSDZm_Int (v2f64 (IMPLICIT_DEF)), sse_load_f64:$src)>;
4291}
4292
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4293
4294multiclass avx512_fp_unop_rm<bits<8> opcps, bits<8> opcpd, string OpcodeStr,
4295 X86MemOperand x86memop, RegisterClass RC,
4296 PatFrag mem_frag32, PatFrag mem_frag64,
4297 Intrinsic V4F32Int, Intrinsic V2F64Int,
4298 CD8VForm VForm> {
4299let ExeDomain = SSEPackedSingle in {
4300 // Intrinsic operation, reg.
4301 // Vector intrinsic operation, reg
4302 def PSr : AVX512AIi8<opcps, MRMSrcReg,
4303 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4304 !strconcat(OpcodeStr,
4305 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4306 [(set RC:$dst, (V4F32Int RC:$src1, imm:$src2))]>;
4307
4308 // Vector intrinsic operation, mem
4309 def PSm : AVX512AIi8<opcps, MRMSrcMem,
4310 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4311 !strconcat(OpcodeStr,
4312 "ps\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4313 [(set RC:$dst,
4314 (V4F32Int (mem_frag32 addr:$src1),imm:$src2))]>,
4315 EVEX_CD8<32, VForm>;
4316} // ExeDomain = SSEPackedSingle
4317
4318let ExeDomain = SSEPackedDouble in {
4319 // Vector intrinsic operation, reg
4320 def PDr : AVX512AIi8<opcpd, MRMSrcReg,
4321 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4322 !strconcat(OpcodeStr,
4323 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4324 [(set RC:$dst, (V2F64Int RC:$src1, imm:$src2))]>;
4325
4326 // Vector intrinsic operation, mem
4327 def PDm : AVX512AIi8<opcpd, MRMSrcMem,
4328 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4329 !strconcat(OpcodeStr,
4330 "pd\t{$src2, $src1, $dst|$dst, $src1, $src2}"),
4331 [(set RC:$dst,
4332 (V2F64Int (mem_frag64 addr:$src1),imm:$src2))]>,
4333 EVEX_CD8<64, VForm>;
4334} // ExeDomain = SSEPackedDouble
4335}
4336
4337multiclass avx512_fp_binop_rm<bits<8> opcss, bits<8> opcsd,
4338 string OpcodeStr,
4339 Intrinsic F32Int,
4340 Intrinsic F64Int> {
4341let ExeDomain = GenericDomain in {
4342 // Operation, reg.
4343 let hasSideEffects = 0 in
4344 def SSr : AVX512AIi8<opcss, MRMSrcReg,
4345 (outs FR32X:$dst), (ins FR32X:$src1, FR32X:$src2, i32i8imm:$src3),
4346 !strconcat(OpcodeStr,
4347 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4348 []>;
4349
4350 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4351 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4352 def SSr_Int : AVX512AIi8<opcss, MRMSrcReg,
4353 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4354 !strconcat(OpcodeStr,
4355 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4356 [(set VR128X:$dst, (F32Int VR128X:$src1, VR128X:$src2, imm:$src3))]>;
4357
4358 // Intrinsic operation, mem.
4359 def SSm : AVX512AIi8<opcss, MRMSrcMem, (outs VR128X:$dst),
4360 (ins VR128X:$src1, ssmem:$src2, i32i8imm:$src3),
4361 !strconcat(OpcodeStr,
4362 "ss\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4363 [(set VR128X:$dst, (F32Int VR128X:$src1,
4364 sse_load_f32:$src2, imm:$src3))]>,
4365 EVEX_CD8<32, CD8VT1>;
4366
4367 // Operation, reg.
4368 let hasSideEffects = 0 in
4369 def SDr : AVX512AIi8<opcsd, MRMSrcReg,
4370 (outs FR64X:$dst), (ins FR64X:$src1, FR64X:$src2, i32i8imm:$src3),
4371 !strconcat(OpcodeStr,
4372 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4373 []>, VEX_W;
4374
4375 // Intrinsic operation, reg.
Craig Topper9dd48c82014-01-02 17:28:14 +0000[diff] [blame]4376 let isCodeGenOnly = 1 in
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4377 def SDr_Int : AVX512AIi8<opcsd, MRMSrcReg,
4378 (outs VR128X:$dst), (ins VR128X:$src1, VR128X:$src2, i32i8imm:$src3),
4379 !strconcat(OpcodeStr,
4380 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4381 [(set VR128X:$dst, (F64Int VR128X:$src1, VR128X:$src2, imm:$src3))]>,
4382 VEX_W;
4383
4384 // Intrinsic operation, mem.
4385 def SDm : AVX512AIi8<opcsd, MRMSrcMem,
4386 (outs VR128X:$dst), (ins VR128X:$src1, sdmem:$src2, i32i8imm:$src3),
4387 !strconcat(OpcodeStr,
4388 "sd\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
4389 [(set VR128X:$dst,
4390 (F64Int VR128X:$src1, sse_load_f64:$src2, imm:$src3))]>,
4391 VEX_W, EVEX_CD8<64, CD8VT1>;
4392} // ExeDomain = GenericDomain
4393}
4394
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4395multiclass avx512_rndscale<bits<8> opc, string OpcodeStr,
4396 X86MemOperand x86memop, RegisterClass RC,
4397 PatFrag mem_frag, Domain d> {
4398let ExeDomain = d in {
4399 // Intrinsic operation, reg.
4400 // Vector intrinsic operation, reg
4401 def r : AVX512AIi8<opc, MRMSrcReg,
4402 (outs RC:$dst), (ins RC:$src1, i32i8imm:$src2),
4403 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4404 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4405 []>, EVEX;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4406
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4407 // Vector intrinsic operation, mem
4408 def m : AVX512AIi8<opc, MRMSrcMem,
4409 (outs RC:$dst), (ins x86memop:$src1, i32i8imm:$src2),
4410 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4411 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4412 []>, EVEX;
4413} // ExeDomain
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4414}
4415
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4416
4417defm VRNDSCALEPSZ : avx512_rndscale<0x08, "vrndscaleps", f512mem, VR512,
4418 memopv16f32, SSEPackedSingle>, EVEX_V512,
4419 EVEX_CD8<32, CD8VF>;
4420
4421def : Pat<(v16f32 (int_x86_avx512_mask_rndscale_ps_512 (v16f32 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4422 imm:$src2, (v16f32 VR512:$src1), (i16 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4423 FROUND_CURRENT)),
4424 (VRNDSCALEPSZr VR512:$src1, imm:$src2)>;
4425
4426
4427defm VRNDSCALEPDZ : avx512_rndscale<0x09, "vrndscalepd", f512mem, VR512,
4428 memopv8f64, SSEPackedDouble>, EVEX_V512,
4429 VEX_W, EVEX_CD8<64, CD8VF>;
4430
4431def : Pat<(v8f64 (int_x86_avx512_mask_rndscale_pd_512 (v8f64 VR512:$src1),
Elena Demikhovskye73333a2014-05-04 13:35:37 +0000[diff] [blame]4432 imm:$src2, (v8f64 VR512:$src1), (i8 -1),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4433 FROUND_CURRENT)),
4434 (VRNDSCALEPDZr VR512:$src1, imm:$src2)>;
4435
4436multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
4437 Operand x86memop, RegisterClass RC, Domain d> {
4438let ExeDomain = d in {
4439 def r : AVX512AIi8<opc, MRMSrcReg,
4440 (outs RC:$dst), (ins RC:$src1, RC:$src2, i32i8imm:$src3),
4441 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4442 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4443 []>, EVEX_4V;
4444
4445 def m : AVX512AIi8<opc, MRMSrcMem,
4446 (outs RC:$dst), (ins RC:$src1, x86memop:$src2, i32i8imm:$src3),
4447 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4448 " \t{$src2, $src1, $dst|$dst, $src1, $src2}"),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4449 []>, EVEX_4V;
4450} // ExeDomain
4451}
4452
4453defm VRNDSCALESS : avx512_rndscale_scalar<0x0A, "vrndscaless", ssmem, FR32X,
4454 SSEPackedSingle>, EVEX_CD8<32, CD8VT1>;
4455
4456defm VRNDSCALESD : avx512_rndscale_scalar<0x0B, "vrndscalesd", sdmem, FR64X,
4457 SSEPackedDouble>, EVEX_CD8<64, CD8VT1>;
4458
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4459def : Pat<(ffloor FR32X:$src),
4460 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x1))>;
4461def : Pat<(f64 (ffloor FR64X:$src)),
4462 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x1))>;
4463def : Pat<(f32 (fnearbyint FR32X:$src)),
4464 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0xC))>;
4465def : Pat<(f64 (fnearbyint FR64X:$src)),
4466 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0xC))>;
4467def : Pat<(f32 (fceil FR32X:$src)),
4468 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x2))>;
4469def : Pat<(f64 (fceil FR64X:$src)),
4470 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x2))>;
4471def : Pat<(f32 (frint FR32X:$src)),
4472 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x4))>;
4473def : Pat<(f64 (frint FR64X:$src)),
4474 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x4))>;
4475def : Pat<(f32 (ftrunc FR32X:$src)),
4476 (VRNDSCALESSr (f32 (IMPLICIT_DEF)), FR32X:$src, (i32 0x3))>;
4477def : Pat<(f64 (ftrunc FR64X:$src)),
4478 (VRNDSCALESDr (f64 (IMPLICIT_DEF)), FR64X:$src, (i32 0x3))>;
4479
4480def : Pat<(v16f32 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4481 (VRNDSCALEPSZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4482def : Pat<(v16f32 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4483 (VRNDSCALEPSZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4484def : Pat<(v16f32 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4485 (VRNDSCALEPSZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4486def : Pat<(v16f32 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4487 (VRNDSCALEPSZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4488def : Pat<(v16f32 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4489 (VRNDSCALEPSZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4490
4491def : Pat<(v8f64 (ffloor VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4492 (VRNDSCALEPDZr VR512:$src, (i32 0x1))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4493def : Pat<(v8f64 (fnearbyint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4494 (VRNDSCALEPDZr VR512:$src, (i32 0xC))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4495def : Pat<(v8f64 (fceil VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4496 (VRNDSCALEPDZr VR512:$src, (i32 0x2))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4497def : Pat<(v8f64 (frint VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4498 (VRNDSCALEPDZr VR512:$src, (i32 0x4))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4499def : Pat<(v8f64 (ftrunc VR512:$src)),
Elena Demikhovskyde3f7512014-01-01 15:12:34 +0000[diff] [blame]4500 (VRNDSCALEPDZr VR512:$src, (i32 0x3))>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4501
4502//-------------------------------------------------
4503// Integer truncate and extend operations
4504//-------------------------------------------------
4505
4506multiclass avx512_trunc_sat<bits<8> opc, string OpcodeStr,
4507 RegisterClass dstRC, RegisterClass srcRC,
4508 RegisterClass KRC, X86MemOperand x86memop> {
4509 def rr : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4510 (ins srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4511 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4512 []>, EVEX;
4513
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4514 def rrk : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
4515 (ins KRC:$mask, srcRC:$src),
4516 !strconcat(OpcodeStr,
4517 " \t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
4518 []>, EVEX, EVEX_K;
4519
4520 def rrkz : AVX512XS8I<opc, MRMDestReg, (outs dstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4521 (ins KRC:$mask, srcRC:$src),
4522 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4523 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4524 []>, EVEX, EVEX_KZ;
4525
4526 def mr : AVX512XS8I<opc, MRMDestMem, (outs), (ins x86memop:$dst, srcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4527 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4528 []>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4529
4530 def mrk : AVX512XS8I<opc, MRMDestMem, (outs),
4531 (ins x86memop:$dst, KRC:$mask, srcRC:$src),
4532 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|${dst} {${mask}}, $src}"),
4533 []>, EVEX, EVEX_K;
4534
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4535}
4536defm VPMOVQB : avx512_trunc_sat<0x32, "vpmovqb", VR128X, VR512, VK8WM,
4537 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4538defm VPMOVSQB : avx512_trunc_sat<0x22, "vpmovsqb", VR128X, VR512, VK8WM,
4539 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4540defm VPMOVUSQB : avx512_trunc_sat<0x12, "vpmovusqb", VR128X, VR512, VK8WM,
4541 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VO>;
4542defm VPMOVQW : avx512_trunc_sat<0x34, "vpmovqw", VR128X, VR512, VK8WM,
4543 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4544defm VPMOVSQW : avx512_trunc_sat<0x24, "vpmovsqw", VR128X, VR512, VK8WM,
4545 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4546defm VPMOVUSQW : avx512_trunc_sat<0x14, "vpmovusqw", VR128X, VR512, VK8WM,
4547 i128mem>, EVEX_V512, EVEX_CD8<16, CD8VQ>;
4548defm VPMOVQD : avx512_trunc_sat<0x35, "vpmovqd", VR256X, VR512, VK8WM,
4549 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4550defm VPMOVSQD : avx512_trunc_sat<0x25, "vpmovsqd", VR256X, VR512, VK8WM,
4551 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4552defm VPMOVUSQD : avx512_trunc_sat<0x15, "vpmovusqd", VR256X, VR512, VK8WM,
4553 i256mem>, EVEX_V512, EVEX_CD8<32, CD8VH>;
4554defm VPMOVDW : avx512_trunc_sat<0x33, "vpmovdw", VR256X, VR512, VK16WM,
4555 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4556defm VPMOVSDW : avx512_trunc_sat<0x23, "vpmovsdw", VR256X, VR512, VK16WM,
4557 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4558defm VPMOVUSDW : avx512_trunc_sat<0x13, "vpmovusdw", VR256X, VR512, VK16WM,
4559 i256mem>, EVEX_V512, EVEX_CD8<16, CD8VH>;
4560defm VPMOVDB : avx512_trunc_sat<0x31, "vpmovdb", VR128X, VR512, VK16WM,
4561 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4562defm VPMOVSDB : avx512_trunc_sat<0x21, "vpmovsdb", VR128X, VR512, VK16WM,
4563 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4564defm VPMOVUSDB : avx512_trunc_sat<0x11, "vpmovusdb", VR128X, VR512, VK16WM,
4565 i128mem>, EVEX_V512, EVEX_CD8<8, CD8VQ>;
4566
4567def : Pat<(v16i8 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQBrr VR512:$src)>;
4568def : Pat<(v8i16 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQWrr VR512:$src)>;
4569def : Pat<(v16i16 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDWrr VR512:$src)>;
4570def : Pat<(v16i8 (X86vtrunc (v16i32 VR512:$src))), (VPMOVDBrr VR512:$src)>;
4571def : Pat<(v8i32 (X86vtrunc (v8i64 VR512:$src))), (VPMOVQDrr VR512:$src)>;
4572
4573def : Pat<(v16i8 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4574 (VPMOVDBrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4575def : Pat<(v16i16 (X86vtruncm VK16WM:$mask, (v16i32 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4576 (VPMOVDWrrkz VK16WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4577def : Pat<(v8i16 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4578 (VPMOVQWrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4579def : Pat<(v8i32 (X86vtruncm VK8WM:$mask, (v8i64 VR512:$src))),
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4580 (VPMOVQDrrkz VK8WM:$mask, VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4581
4582
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4583multiclass avx512_extend<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4584 RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode,
4585 PatFrag mem_frag, X86MemOperand x86memop,
4586 ValueType OpVT, ValueType InVT> {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4587
4588 def rr : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4589 (ins SrcRC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4590 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4591 [(set DstRC:$dst, (OpVT (OpNode (InVT SrcRC:$src))))]>, EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4592
4593 def rrk : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4594 (ins KRC:$mask, SrcRC:$src),
4595 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4596 []>, EVEX, EVEX_K;
4597
4598 def rrkz : AVX5128I<opc, MRMSrcReg, (outs DstRC:$dst),
4599 (ins KRC:$mask, SrcRC:$src),
4600 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4601 []>, EVEX, EVEX_KZ;
4602
4603 let mayLoad = 1 in {
4604 def rm : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4605 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4606 !strconcat(OpcodeStr," \t{$src, $dst|$dst, $src}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4607 [(set DstRC:$dst,
4608 (OpVT (OpNode (InVT (bitconvert (mem_frag addr:$src))))))]>,
4609 EVEX;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4610
4611 def rmk : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4612 (ins KRC:$mask, x86memop:$src),
4613 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} |$dst {${mask}}, $src}"),
4614 []>,
4615 EVEX, EVEX_K;
4616
4617 def rmkz : AVX5128I<opc, MRMSrcMem, (outs DstRC:$dst),
4618 (ins KRC:$mask, x86memop:$src),
4619 !strconcat(OpcodeStr," \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4620 []>,
4621 EVEX, EVEX_KZ;
4622 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4623}
4624
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4625defm VPMOVZXBDZ: avx512_extend<0x31, "vpmovzxbd", VK16WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4626 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4627 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4628defm VPMOVZXBQZ: avx512_extend<0x32, "vpmovzxbq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4629 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4630 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4631defm VPMOVZXWDZ: avx512_extend<0x33, "vpmovzxwd", VK16WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4632 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4633 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4634defm VPMOVZXWQZ: avx512_extend<0x34, "vpmovzxwq", VK8WM, VR512, VR128X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4635 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4636 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4637defm VPMOVZXDQZ: avx512_extend<0x35, "vpmovzxdq", VK8WM, VR512, VR256X, X86vzext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4638 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4639 EVEX_CD8<32, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4640
4641defm VPMOVSXBDZ: avx512_extend<0x21, "vpmovsxbd", VK16WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4642 memopv2i64, i128mem, v16i32, v16i8>, EVEX_V512,
4643 EVEX_CD8<8, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4644defm VPMOVSXBQZ: avx512_extend<0x22, "vpmovsxbq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4645 memopv2i64, i128mem, v8i64, v16i8>, EVEX_V512,
4646 EVEX_CD8<8, CD8VO>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4647defm VPMOVSXWDZ: avx512_extend<0x23, "vpmovsxwd", VK16WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4648 memopv4i64, i256mem, v16i32, v16i16>, EVEX_V512,
4649 EVEX_CD8<16, CD8VH>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4650defm VPMOVSXWQZ: avx512_extend<0x24, "vpmovsxwq", VK8WM, VR512, VR128X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4651 memopv2i64, i128mem, v8i64, v8i16>, EVEX_V512,
4652 EVEX_CD8<16, CD8VQ>;
Robert Khasanov189e7fd2014-04-22 11:36:19 +0000[diff] [blame]4653defm VPMOVSXDQZ: avx512_extend<0x25, "vpmovsxdq", VK8WM, VR512, VR256X, X86vsext,
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4654 memopv4i64, i256mem, v8i64, v8i32>, EVEX_V512,
4655 EVEX_CD8<32, CD8VH>;
4656
4657//===----------------------------------------------------------------------===//
4658// GATHER - SCATTER Operations
4659
4660multiclass avx512_gather<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4661 RegisterClass RC, X86MemOperand memop> {
4662let mayLoad = 1,
4663 Constraints = "@earlyclobber $dst, $src1 = $dst, $mask = $mask_wb" in
4664 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst, KRC:$mask_wb),
4665 (ins RC:$src1, KRC:$mask, memop:$src2),
4666 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4667 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4668 []>, EVEX, EVEX_K;
4669}
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4670
4671let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4672defm VGATHERDPDZ : avx512_gather<0x92, "vgatherdpd", VK8WM, VR512, vy64xmem>,
4673 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4674defm VGATHERQPDZ : avx512_gather<0x93, "vgatherqpd", VK8WM, VR512, vz64mem>,
4675 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4676}
4677
4678let ExeDomain = SSEPackedSingle in {
4679defm VGATHERDPSZ : avx512_gather<0x92, "vgatherdps", VK16WM, VR512, vz32mem>,
4680 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4681defm VGATHERQPSZ : avx512_gather<0x93, "vgatherqps", VK8WM, VR256X, vz64mem>,
4682 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4683}
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4684
4685defm VPGATHERDQZ : avx512_gather<0x90, "vpgatherdq", VK8WM, VR512, vy64xmem>,
4686 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4687defm VPGATHERDDZ : avx512_gather<0x90, "vpgatherdd", VK16WM, VR512, vz32mem>,
4688 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4689
4690defm VPGATHERQQZ : avx512_gather<0x91, "vpgatherqq", VK8WM, VR512, vz64mem>,
4691 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4692defm VPGATHERQDZ : avx512_gather<0x91, "vpgatherqd", VK8WM, VR256X, vz64mem>,
4693 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4694
4695multiclass avx512_scatter<bits<8> opc, string OpcodeStr, RegisterClass KRC,
4696 RegisterClass RC, X86MemOperand memop> {
4697let mayStore = 1, Constraints = "$mask = $mask_wb" in
4698 def mr : AVX5128I<opc, MRMDestMem, (outs KRC:$mask_wb),
4699 (ins memop:$dst, KRC:$mask, RC:$src2),
4700 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4701 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4702 []>, EVEX, EVEX_K;
4703}
4704
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4705let ExeDomain = SSEPackedDouble in {
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4706defm VSCATTERDPDZ : avx512_scatter<0xA2, "vscatterdpd", VK8WM, VR512, vy64xmem>,
4707 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4708defm VSCATTERQPDZ : avx512_scatter<0xA3, "vscatterqpd", VK8WM, VR512, vz64mem>,
4709 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4710}
4711
4712let ExeDomain = SSEPackedSingle in {
4713defm VSCATTERDPSZ : avx512_scatter<0xA2, "vscatterdps", VK16WM, VR512, vz32mem>,
4714 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4715defm VSCATTERQPSZ : avx512_scatter<0xA3, "vscatterqps", VK8WM, VR256X, vz64mem>,
4716 EVEX_V512, EVEX_CD8<32, CD8VT1>;
Cameron McInally45325962014-03-26 13:50:50 +0000[diff] [blame]4717}
4718
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4719defm VPSCATTERDQZ : avx512_scatter<0xA0, "vpscatterdq", VK8WM, VR512, vy64xmem>,
4720 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4721defm VPSCATTERDDZ : avx512_scatter<0xA0, "vpscatterdd", VK16WM, VR512, vz32mem>,
4722 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4723
4724defm VPSCATTERQQZ : avx512_scatter<0xA1, "vpscatterqq", VK8WM, VR512, vz64mem>,
4725 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4726defm VPSCATTERQDZ : avx512_scatter<0xA1, "vpscatterqd", VK8WM, VR256X, vz64mem>,
4727 EVEX_V512, EVEX_CD8<32, CD8VT1>;
4728
Elena Demikhovsky8e8fde82014-05-12 07:18:51 +0000[diff] [blame]4729// prefetch
4730multiclass avx512_gather_scatter_prefetch<bits<8> opc, Format F, string OpcodeStr,
4731 RegisterClass KRC, X86MemOperand memop> {
4732 let Predicates = [HasPFI], hasSideEffects = 1 in
4733 def m : AVX5128I<opc, F, (outs), (ins KRC:$mask, memop:$src),
4734 !strconcat(OpcodeStr, " \t{$src {${mask}}|{${mask}}, $src}"),
4735 []>, EVEX, EVEX_K;
4736}
4737
4738defm VGATHERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dps",
4739 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4740
4741defm VGATHERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qps",
4742 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4743
4744defm VGATHERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM1m, "vgatherpf0dpd",
4745 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4746
4747defm VGATHERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM1m, "vgatherpf0qpd",
4748 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4749
4750defm VGATHERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dps",
4751 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4752
4753defm VGATHERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qps",
4754 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4755
4756defm VGATHERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM2m, "vgatherpf1dpd",
4757 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4758
4759defm VGATHERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM2m, "vgatherpf1qpd",
4760 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4761
4762defm VSCATTERPF0DPS: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dps",
4763 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4764
4765defm VSCATTERPF0QPS: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qps",
4766 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4767
4768defm VSCATTERPF0DPD: avx512_gather_scatter_prefetch<0xC6, MRM5m, "vscatterpf0dpd",
4769 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4770
4771defm VSCATTERPF0QPD: avx512_gather_scatter_prefetch<0xC7, MRM5m, "vscatterpf0qpd",
4772 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
4773
4774defm VSCATTERPF1DPS: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dps",
4775 VK16WM, vz32mem>, EVEX_V512, EVEX_CD8<32, CD8VT1>;
4776
4777defm VSCATTERPF1QPS: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qps",
4778 VK8WM, vz64mem>, EVEX_V512, EVEX_CD8<64, CD8VT1>;
4779
4780defm VSCATTERPF1DPD: avx512_gather_scatter_prefetch<0xC6, MRM6m, "vscatterpf1dpd",
4781 VK8WM, vy32mem>, EVEX_V512, VEX_W, EVEX_CD8<32, CD8VT1>;
4782
4783defm VSCATTERPF1QPD: avx512_gather_scatter_prefetch<0xC7, MRM6m, "vscatterpf1qpd",
4784 VK8WM, vz64mem>, EVEX_V512, VEX_W, EVEX_CD8<64, CD8VT1>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4785//===----------------------------------------------------------------------===//
4786// VSHUFPS - VSHUFPD Operations
4787
4788multiclass avx512_shufp<RegisterClass RC, X86MemOperand x86memop,
4789 ValueType vt, string OpcodeStr, PatFrag mem_frag,
4790 Domain d> {
4791 def rmi : AVX512PIi8<0xC6, MRMSrcMem, (outs RC:$dst),
4792 (ins RC:$src1, x86memop:$src2, i8imm:$src3),
4793 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4794 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4795 [(set RC:$dst, (vt (X86Shufp RC:$src1, (mem_frag addr:$src2),
4796 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4797 EVEX_4V, Sched<[WriteShuffleLd, ReadAfterLd]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4798 def rri : AVX512PIi8<0xC6, MRMSrcReg, (outs RC:$dst),
4799 (ins RC:$src1, RC:$src2, i8imm:$src3),
4800 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4801 " \t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4802 [(set RC:$dst, (vt (X86Shufp RC:$src1, RC:$src2,
4803 (i8 imm:$src3))))], d, IIC_SSE_SHUFP>,
Elena Demikhovskyb30371c2013-10-02 06:39:07 +0000[diff] [blame]4804 EVEX_4V, Sched<[WriteShuffle]>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4805}
4806
4807defm VSHUFPSZ : avx512_shufp<VR512, f512mem, v16f32, "vshufps", memopv16f32,
Craig Topper5ccb6172014-02-18 00:21:49 +0000[diff] [blame]4808 SSEPackedSingle>, PS, EVEX_V512, EVEX_CD8<32, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4809defm VSHUFPDZ : avx512_shufp<VR512, f512mem, v8f64, "vshufpd", memopv8f64,
Craig Topperae11aed2014-01-14 07:41:20 +0000[diff] [blame]4810 SSEPackedDouble>, PD, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4811
Elena Demikhovsky462a2d22013-10-06 06:11:18 +0000[diff] [blame]4812def : Pat<(v16i32 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4813 (VSHUFPSZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4814def : Pat<(v16i32 (X86Shufp VR512:$src1,
4815 (memopv16i32 addr:$src2), (i8 imm:$imm))),
4816 (VSHUFPSZrmi VR512:$src1, addr:$src2, imm:$imm)>;
4817
4818def : Pat<(v8i64 (X86Shufp VR512:$src1, VR512:$src2, (i8 imm:$imm))),
4819 (VSHUFPDZrri VR512:$src1, VR512:$src2, imm:$imm)>;
4820def : Pat<(v8i64 (X86Shufp VR512:$src1,
4821 (memopv8i64 addr:$src2), (i8 imm:$imm))),
4822 (VSHUFPDZrmi VR512:$src1, addr:$src2, imm:$imm)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4823
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4824multiclass avx512_valign<X86VectorVTInfo _> {
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]4825 defm rri : AVX512_masking<0x03, MRMSrcReg, _, (outs _.RC:$dst),
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4826 (ins _.RC:$src1, _.RC:$src2, i8imm:$src3),
4827 "valign"##_.Suffix,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4828 "$src3, $src2, $src1", "$src1, $src2, $src3",
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4829 (_.VT (X86VAlign _.RC:$src2, _.RC:$src1,
Adam Nemet6bddb8c2014-09-29 22:54:41 +0000[diff] [blame^]4830 (i8 imm:$src3)))>,
Adam Nemet2e2537f2014-08-07 17:53:55 +0000[diff] [blame]4831 AVX512AIi8Base, EVEX_4V;
Adam Nemetfd2161b2014-08-05 17:23:04 +0000[diff] [blame]4832
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4833 // Also match valign of packed floats.
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4834 def : Pat<(_.FloatVT (X86VAlign _.RC:$src1, _.RC:$src2, (i8 imm:$imm))),
4835 (!cast<Instruction>(NAME##rri) _.RC:$src2, _.RC:$src1, imm:$imm)>;
Adam Nemetf92139d2014-08-05 17:22:50 +0000[diff] [blame]4836
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4837 let mayLoad = 1 in
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4838 def rmi : AVX512AIi8<0x03, MRMSrcMem, (outs _.RC:$dst),
4839 (ins _.RC:$src1, _.MemOp:$src2, i8imm:$src3),
4840 !strconcat("valign"##_.Suffix,
Adam Nemet1c752d82014-08-05 17:22:47 +0000[diff] [blame]4841 " \t{$src3, $src2, $src1, $dst|"
4842 "$dst, $src1, $src2, $src3}"),
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4843 []>, EVEX_4V;
4844}
Adam Nemet5ed17da2014-08-21 19:50:07 +0000[diff] [blame]4845defm VALIGND : avx512_valign<v16i32_info>, EVEX_V512, EVEX_CD8<32, CD8VF>;
4846defm VALIGNQ : avx512_valign<v8i64_info>, VEX_W, EVEX_V512, EVEX_CD8<64, CD8VF>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4847
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4848// Helper fragments to match sext vXi1 to vXiY.
4849def v16i1sextv16i32 : PatLeaf<(v16i32 (X86vsrai VR512:$src, (i8 31)))>;
4850def v8i1sextv8i64 : PatLeaf<(v8i64 (X86vsrai VR512:$src, (i8 63)))>;
4851
4852multiclass avx512_vpabs<bits<8> opc, string OpcodeStr, ValueType OpVT,
4853 RegisterClass KRC, RegisterClass RC,
4854 X86MemOperand x86memop, X86MemOperand x86scalar_mop,
4855 string BrdcstStr> {
4856 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
4857 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4858 []>, EVEX;
4859 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4860 !strconcat(OpcodeStr, " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4861 []>, EVEX, EVEX_K;
4862 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
4863 !strconcat(OpcodeStr,
4864 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4865 []>, EVEX, EVEX_KZ;
4866 let mayLoad = 1 in {
4867 def rm : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4868 (ins x86memop:$src),
4869 !strconcat(OpcodeStr, " \t{$src, $dst|$dst, $src}"),
4870 []>, EVEX;
4871 def rmk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4872 (ins KRC:$mask, x86memop:$src),
4873 !strconcat(OpcodeStr,
4874 " \t{$src, $dst {${mask}}|$dst {${mask}}, $src}"),
4875 []>, EVEX, EVEX_K;
4876 def rmkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4877 (ins KRC:$mask, x86memop:$src),
4878 !strconcat(OpcodeStr,
4879 " \t{$src, $dst {${mask}} {z}|$dst {${mask}} {z}, $src}"),
4880 []>, EVEX, EVEX_KZ;
4881 def rmb : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4882 (ins x86scalar_mop:$src),
4883 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4884 ", $dst|$dst, ${src}", BrdcstStr, "}"),
4885 []>, EVEX, EVEX_B;
4886 def rmbk : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4887 (ins KRC:$mask, x86scalar_mop:$src),
4888 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4889 ", $dst {${mask}}|$dst {${mask}}, ${src}", BrdcstStr, "}"),
4890 []>, EVEX, EVEX_B, EVEX_K;
4891 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs VR512:$dst),
4892 (ins KRC:$mask, x86scalar_mop:$src),
4893 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
4894 ", $dst {${mask}} {z}|$dst {${mask}} {z}, ${src}",
4895 BrdcstStr, "}"),
4896 []>, EVEX, EVEX_B, EVEX_KZ;
4897 }
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4898}
4899
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4900defm VPABSDZ : avx512_vpabs<0x1E, "vpabsd", v16i32, VK16WM, VR512,
4901 i512mem, i32mem, "{1to16}">, EVEX_V512,
4902 EVEX_CD8<32, CD8VF>;
4903defm VPABSQZ : avx512_vpabs<0x1F, "vpabsq", v8i64, VK8WM, VR512,
4904 i512mem, i64mem, "{1to8}">, EVEX_V512, VEX_W,
4905 EVEX_CD8<64, CD8VF>;
4906
4907def : Pat<(xor
4908 (bc_v16i32 (v16i1sextv16i32)),
4909 (bc_v16i32 (add (v16i32 VR512:$src), (v16i1sextv16i32)))),
4910 (VPABSDZrr VR512:$src)>;
4911def : Pat<(xor
4912 (bc_v8i64 (v8i1sextv8i64)),
4913 (bc_v8i64 (add (v8i64 VR512:$src), (v8i1sextv8i64)))),
4914 (VPABSQZrr VR512:$src)>;
Elena Demikhovskyac3e8eb2013-09-17 07:34:34 +0000[diff] [blame]4915
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4916def : Pat<(v16i32 (int_x86_avx512_mask_pabs_d_512 (v16i32 VR512:$src),
4917 (v16i32 immAllZerosV), (i16 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4918 (VPABSDZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4919def : Pat<(v8i64 (int_x86_avx512_mask_pabs_q_512 (v8i64 VR512:$src),
4920 (bc_v8i64 (v16i32 immAllZerosV)), (i8 -1))),
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]4921 (VPABSQZrr VR512:$src)>;
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]4922
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4923multiclass avx512_conflict<bits<8> opc, string OpcodeStr,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4924 RegisterClass RC, RegisterClass KRC,
4925 X86MemOperand x86memop,
4926 X86MemOperand x86scalar_mop, string BrdcstStr> {
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4927 def rr : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4928 (ins RC:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4929 !strconcat(OpcodeStr, " \t{$src, ${dst} |${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4930 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4931 def rm : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4932 (ins x86memop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4933 !strconcat(OpcodeStr, " \t{$src, ${dst}|${dst}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4934 []>, EVEX;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4935 def rmb : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4936 (ins x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4937 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4938 ", ${dst}|${dst}, ${src}", BrdcstStr, "}"),
4939 []>, EVEX, EVEX_B;
4940 def rrkz : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4941 (ins KRC:$mask, RC:$src),
4942 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4943 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4944 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4945 def rmkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4946 (ins KRC:$mask, x86memop:$src),
4947 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4948 " \t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4949 []>, EVEX, EVEX_KZ;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4950 def rmbkz : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4951 (ins KRC:$mask, x86scalar_mop:$src),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4952 !strconcat(OpcodeStr, " \t{${src}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4953 ", ${dst} {${mask}} {z}|${dst} {${mask}} {z}, ${src}",
4954 BrdcstStr, "}"),
4955 []>, EVEX, EVEX_KZ, EVEX_B;
4956
4957 let Constraints = "$src1 = $dst" in {
4958 def rrk : AVX5128I<opc, MRMSrcReg, (outs RC:$dst),
4959 (ins RC:$src1, KRC:$mask, RC:$src2),
4960 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4961 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4962 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4963 def rmk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4964 (ins RC:$src1, KRC:$mask, x86memop:$src2),
4965 !strconcat(OpcodeStr,
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4966 " \t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"),
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4967 []>, EVEX, EVEX_K;
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4968 def rmbk : AVX5128I<opc, MRMSrcMem, (outs RC:$dst),
4969 (ins RC:$src1, KRC:$mask, x86scalar_mop:$src2),
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]4970 !strconcat(OpcodeStr, " \t{${src2}", BrdcstStr,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4971 ", ${dst} {${mask}}|${dst} {${mask}}, ${src2}", BrdcstStr, "}"),
4972 []>, EVEX, EVEX_K, EVEX_B;
4973 }
4974}
4975
4976let Predicates = [HasCDI] in {
4977defm VPCONFLICTD : avx512_conflict<0xC4, "vpconflictd", VR512, VK16WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4978 i512mem, i32mem, "{1to16}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4979 EVEX_V512, EVEX_CD8<32, CD8VF>;
4980
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4981
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4982defm VPCONFLICTQ : avx512_conflict<0xC4, "vpconflictq", VR512, VK8WM,
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4983 i512mem, i64mem, "{1to8}">,
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4984 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4985
Elena Demikhovskydacddb02013-11-03 13:46:31 +0000[diff] [blame]4986}
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4987
4988def : Pat<(int_x86_avx512_mask_conflict_d_512 VR512:$src2, VR512:$src1,
4989 GR16:$mask),
4990 (VPCONFLICTDrrk VR512:$src1,
4991 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
4992
4993def : Pat<(int_x86_avx512_mask_conflict_q_512 VR512:$src2, VR512:$src1,
4994 GR8:$mask),
4995 (VPCONFLICTQrrk VR512:$src1,
4996 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]4997
Cameron McInally5d1b7b92014-06-11 12:54:45 +0000[diff] [blame]4998let Predicates = [HasCDI] in {
4999defm VPLZCNTD : avx512_conflict<0x44, "vplzcntd", VR512, VK16WM,
5000 i512mem, i32mem, "{1to16}">,
5001 EVEX_V512, EVEX_CD8<32, CD8VF>;
5002
5003
5004defm VPLZCNTQ : avx512_conflict<0x44, "vplzcntq", VR512, VK8WM,
5005 i512mem, i64mem, "{1to8}">,
5006 EVEX_V512, VEX_W, EVEX_CD8<64, CD8VF>;
5007
5008}
5009
5010def : Pat<(int_x86_avx512_mask_lzcnt_d_512 VR512:$src2, VR512:$src1,
5011 GR16:$mask),
5012 (VPLZCNTDrrk VR512:$src1,
5013 (v16i1 (COPY_TO_REGCLASS GR16:$mask, VK16WM)), VR512:$src2)>;
5014
5015def : Pat<(int_x86_avx512_mask_lzcnt_q_512 VR512:$src2, VR512:$src1,
5016 GR8:$mask),
5017 (VPLZCNTQrrk VR512:$src1,
5018 (v8i1 (COPY_TO_REGCLASS GR8:$mask, VK8WM)), VR512:$src2)>;
5019
Cameron McInally0d0489c2014-06-16 14:12:28 +0000[diff] [blame]5020def : Pat<(v16i32 (ctlz (memopv16i32 addr:$src))),
5021 (VPLZCNTDrm addr:$src)>;
5022def : Pat<(v16i32 (ctlz (v16i32 VR512:$src))),
5023 (VPLZCNTDrr VR512:$src)>;
5024def : Pat<(v8i64 (ctlz (memopv8i64 addr:$src))),
5025 (VPLZCNTQrm addr:$src)>;
5026def : Pat<(v8i64 (ctlz (v8i64 VR512:$src))),
5027 (VPLZCNTQrr VR512:$src)>;
5028
Elena Demikhovskycf0b9ba2014-04-09 12:37:50 +0000[diff] [blame]5029def : Pat<(store (i1 -1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5030def : Pat<(store (i1 1), addr:$dst), (MOV8mi addr:$dst, (i8 1))>;
5031def : Pat<(store (i1 0), addr:$dst), (MOV8mi addr:$dst, (i8 0))>;
Elena Demikhovskyacc5c9e2014-04-22 14:13:10 +0000[diff] [blame]5032
5033def : Pat<(store VK1:$src, addr:$dst),
5034 (KMOVWmk addr:$dst, (COPY_TO_REGCLASS VK1:$src, VK16))>;
5035
5036def truncstorei1 : PatFrag<(ops node:$val, node:$ptr),
5037 (truncstore node:$val, node:$ptr), [{
5038 return cast<StoreSDNode>(N)->getMemoryVT() == MVT::i1;
5039}]>;
5040
5041def : Pat<(truncstorei1 GR8:$src, addr:$dst),
5042 (MOV8mr addr:$dst, GR8:$src)>;
5043