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gerrit-public.fairphone.software / toolchain / llvm-project / 6ce20bd184e6684fb96d643bd4b113d0eb9f0d21 / . / llvm / lib / Target / X86 / InstPrinter / X86InstComments.cpp
blob: df2fc33486b3795f44769823f8fcff046362a5de [file] [log] [blame]
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1//===-- X86InstComments.cpp - Generate verbose-asm comments for instrs ----===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This defines functionality used to emit comments about X86 instructions to
11// an output stream for -fverbose-asm.
12//
13//===----------------------------------------------------------------------===//
14
15#include "X86InstComments.h"
16#include "MCTargetDesc/X86MCTargetDesc.h"
17#include "Utils/X86ShuffleDecode.h"
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]18#include "llvm/CodeGen/MachineValueType.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +0000[diff] [blame]19#include "llvm/MC/MCInst.h"
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]20#include "llvm/Support/raw_ostream.h"
21
22using namespace llvm;
23
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]24#define CASE_SSE_INS_COMMON(Inst, src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]25 case X86::Inst##src:
26
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]27#define CASE_AVX_INS_COMMON(Inst, Suffix, src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]28 case X86::V##Inst##Suffix##src:
29
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]30#define CASE_MASK_INS_COMMON(Inst, Suffix, src) \
31 case X86::V##Inst##Suffix##src##k:
32
33#define CASE_MASKZ_INS_COMMON(Inst, Suffix, src) \
34 case X86::V##Inst##Suffix##src##kz:
35
36#define CASE_AVX512_INS_COMMON(Inst, Suffix, src) \
37 CASE_AVX_INS_COMMON(Inst, Suffix, src) \
38 CASE_MASK_INS_COMMON(Inst, Suffix, src) \
39 CASE_MASKZ_INS_COMMON(Inst, Suffix, src)
40
41#define CASE_MOVDUP(Inst, src) \
42 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
43 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
44 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
45 CASE_AVX_INS_COMMON(Inst, , r##src) \
46 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]47 CASE_SSE_INS_COMMON(Inst, r##src)
48
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]49#define CASE_MASK_MOVDUP(Inst, src) \
50 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
51 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
52 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
53
54#define CASE_MASKZ_MOVDUP(Inst, src) \
55 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
56 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
57 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
58
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]59#define CASE_PMOVZX(Inst, src) \
60 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
61 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
62 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
63 CASE_AVX_INS_COMMON(Inst, , r##src) \
64 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]65 CASE_SSE_INS_COMMON(Inst, r##src)
66
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]67#define CASE_MASK_PMOVZX(Inst, src) \
68 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
69 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
70 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
71
72#define CASE_MASKZ_PMOVZX(Inst, src) \
73 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
74 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
75 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
76
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]77#define CASE_UNPCK(Inst, src) \
78 CASE_AVX512_INS_COMMON(Inst, Z, r##src) \
79 CASE_AVX512_INS_COMMON(Inst, Z256, r##src) \
80 CASE_AVX512_INS_COMMON(Inst, Z128, r##src) \
81 CASE_AVX_INS_COMMON(Inst, , r##src) \
82 CASE_AVX_INS_COMMON(Inst, Y, r##src) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]83 CASE_SSE_INS_COMMON(Inst, r##src)
84
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]85#define CASE_MASK_UNPCK(Inst, src) \
86 CASE_MASK_INS_COMMON(Inst, Z, r##src) \
87 CASE_MASK_INS_COMMON(Inst, Z256, r##src) \
88 CASE_MASK_INS_COMMON(Inst, Z128, r##src)
89
90#define CASE_MASKZ_UNPCK(Inst, src) \
91 CASE_MASKZ_INS_COMMON(Inst, Z, r##src) \
92 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src) \
93 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src)
94
95#define CASE_SHUF(Inst, suf) \
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]96 CASE_AVX512_INS_COMMON(Inst, Z, suf) \
97 CASE_AVX512_INS_COMMON(Inst, Z256, suf) \
98 CASE_AVX512_INS_COMMON(Inst, Z128, suf) \
99 CASE_AVX_INS_COMMON(Inst, , suf) \
100 CASE_AVX_INS_COMMON(Inst, Y, suf) \
101 CASE_SSE_INS_COMMON(Inst, suf)
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]102
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]103#define CASE_MASK_SHUF(Inst, src) \
104 CASE_MASK_INS_COMMON(Inst, Z, r##src##i) \
105 CASE_MASK_INS_COMMON(Inst, Z256, r##src##i) \
106 CASE_MASK_INS_COMMON(Inst, Z128, r##src##i)
107
108#define CASE_MASKZ_SHUF(Inst, src) \
109 CASE_MASKZ_INS_COMMON(Inst, Z, r##src##i) \
110 CASE_MASKZ_INS_COMMON(Inst, Z256, r##src##i) \
111 CASE_MASKZ_INS_COMMON(Inst, Z128, r##src##i)
112
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]113#define CASE_VPERMILPI(Inst, src) \
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]114 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
115 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
116 CASE_AVX512_INS_COMMON(Inst, Z128, src##i) \
117 CASE_AVX_INS_COMMON(Inst, , src##i) \
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]118 CASE_AVX_INS_COMMON(Inst, Y, src##i)
119
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]120#define CASE_MASK_VPERMILPI(Inst, src) \
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]121 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
122 CASE_MASK_INS_COMMON(Inst, Z256, src##i) \
123 CASE_MASK_INS_COMMON(Inst, Z128, src##i)
124
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]125#define CASE_MASKZ_VPERMILPI(Inst, src) \
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]126 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
127 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i) \
128 CASE_MASKZ_INS_COMMON(Inst, Z128, src##i)
129
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]130#define CASE_VPERM(Inst, src) \
131 CASE_AVX512_INS_COMMON(Inst, Z, src##i) \
132 CASE_AVX512_INS_COMMON(Inst, Z256, src##i) \
133 CASE_AVX_INS_COMMON(Inst, Y, src##i)
134
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]135#define CASE_MASK_VPERM(Inst, src) \
136 CASE_MASK_INS_COMMON(Inst, Z, src##i) \
137 CASE_MASK_INS_COMMON(Inst, Z256, src##i)
138
139#define CASE_MASKZ_VPERM(Inst, src) \
140 CASE_MASKZ_INS_COMMON(Inst, Z, src##i) \
141 CASE_MASKZ_INS_COMMON(Inst, Z256, src##i)
142
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]143#define CASE_VSHUF(Inst, src) \
Simon Pilgrim41c05c02016-05-11 11:55:12 +0000[diff] [blame]144 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
145 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
146 CASE_AVX512_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
147 CASE_AVX512_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
Simon Pilgrimbfa5f232016-02-06 17:02:15 +0000[diff] [blame]148
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]149#define CASE_MASK_VSHUF(Inst, src) \
150 CASE_MASK_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
151 CASE_MASK_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
152 CASE_MASK_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
153 CASE_MASK_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
154
155#define CASE_MASKZ_VSHUF(Inst, src) \
156 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z, r##src##i) \
157 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z, r##src##i) \
158 CASE_MASKZ_INS_COMMON(SHUFF##Inst, Z256, r##src##i) \
159 CASE_MASKZ_INS_COMMON(SHUFI##Inst, Z256, r##src##i)
160
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]161static unsigned getVectorRegSize(unsigned RegNo) {
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]162 if (X86::ZMM0 <= RegNo && RegNo <= X86::ZMM31)
163 return 512;
164 if (X86::YMM0 <= RegNo && RegNo <= X86::YMM31)
165 return 256;
166 if (X86::XMM0 <= RegNo && RegNo <= X86::XMM31)
167 return 128;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]168 if (X86::MM0 <= RegNo && RegNo <= X86::MM7)
169 return 64;
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]170
171 llvm_unreachable("Unknown vector reg!");
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]172}
173
174static MVT getRegOperandVectorVT(const MCInst *MI, const MVT &ScalarVT,
175 unsigned OperandIndex) {
176 unsigned OpReg = MI->getOperand(OperandIndex).getReg();
177 return MVT::getVectorVT(ScalarVT,
178 getVectorRegSize(OpReg)/ScalarVT.getSizeInBits());
179}
180
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]181/// \brief Extracts the dst type for a given zero extension instruction.
182static MVT getZeroExtensionResultType(const MCInst *MI) {
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]183 switch (MI->getOpcode()) {
184 default:
185 llvm_unreachable("Unknown zero extension instruction");
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]186 // zero extension to i16
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]187 CASE_PMOVZX(PMOVZXBW, m)
188 CASE_PMOVZX(PMOVZXBW, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]189 return getRegOperandVectorVT(MI, MVT::i16, 0);
190 // zero extension to i32
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]191 CASE_PMOVZX(PMOVZXBD, m)
192 CASE_PMOVZX(PMOVZXBD, r)
193 CASE_PMOVZX(PMOVZXWD, m)
194 CASE_PMOVZX(PMOVZXWD, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]195 return getRegOperandVectorVT(MI, MVT::i32, 0);
196 // zero extension to i64
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]197 CASE_PMOVZX(PMOVZXBQ, m)
198 CASE_PMOVZX(PMOVZXBQ, r)
199 CASE_PMOVZX(PMOVZXWQ, m)
200 CASE_PMOVZX(PMOVZXWQ, r)
201 CASE_PMOVZX(PMOVZXDQ, m)
202 CASE_PMOVZX(PMOVZXDQ, r)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]203 return getRegOperandVectorVT(MI, MVT::i64, 0);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]204 }
205}
206
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]207/// Wraps the destination register name with AVX512 mask/maskz filtering.
208static std::string getMaskName(const MCInst *MI, const char *DestName,
209 const char *(*getRegName)(unsigned)) {
210 std::string OpMaskName(DestName);
211
212 bool MaskWithZero = false;
213 const char *MaskRegName = nullptr;
214
215 switch (MI->getOpcode()) {
216 default:
217 return OpMaskName;
218 CASE_MASKZ_MOVDUP(MOVDDUP, m)
219 CASE_MASKZ_MOVDUP(MOVDDUP, r)
220 CASE_MASKZ_MOVDUP(MOVSHDUP, m)
221 CASE_MASKZ_MOVDUP(MOVSHDUP, r)
222 CASE_MASKZ_MOVDUP(MOVSLDUP, m)
223 CASE_MASKZ_MOVDUP(MOVSLDUP, r)
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]224 CASE_MASKZ_PMOVZX(PMOVZXBD, m)
225 CASE_MASKZ_PMOVZX(PMOVZXBD, r)
226 CASE_MASKZ_PMOVZX(PMOVZXBQ, m)
227 CASE_MASKZ_PMOVZX(PMOVZXBQ, r)
228 CASE_MASKZ_PMOVZX(PMOVZXBW, m)
229 CASE_MASKZ_PMOVZX(PMOVZXBW, r)
230 CASE_MASKZ_PMOVZX(PMOVZXDQ, m)
231 CASE_MASKZ_PMOVZX(PMOVZXDQ, r)
232 CASE_MASKZ_PMOVZX(PMOVZXWD, m)
233 CASE_MASKZ_PMOVZX(PMOVZXWD, r)
234 CASE_MASKZ_PMOVZX(PMOVZXWQ, m)
235 CASE_MASKZ_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]236 CASE_MASKZ_UNPCK(PUNPCKHBW, m)
237 CASE_MASKZ_UNPCK(PUNPCKHBW, r)
238 CASE_MASKZ_UNPCK(PUNPCKHWD, m)
239 CASE_MASKZ_UNPCK(PUNPCKHWD, r)
240 CASE_MASKZ_UNPCK(PUNPCKHDQ, m)
241 CASE_MASKZ_UNPCK(PUNPCKHDQ, r)
242 CASE_MASKZ_UNPCK(PUNPCKLBW, m)
243 CASE_MASKZ_UNPCK(PUNPCKLBW, r)
244 CASE_MASKZ_UNPCK(PUNPCKLWD, m)
245 CASE_MASKZ_UNPCK(PUNPCKLWD, r)
246 CASE_MASKZ_UNPCK(PUNPCKLDQ, m)
247 CASE_MASKZ_UNPCK(PUNPCKLDQ, r)
248 CASE_MASKZ_UNPCK(UNPCKHPD, m)
249 CASE_MASKZ_UNPCK(UNPCKHPD, r)
250 CASE_MASKZ_UNPCK(UNPCKHPS, m)
251 CASE_MASKZ_UNPCK(UNPCKHPS, r)
252 CASE_MASKZ_UNPCK(UNPCKLPD, m)
253 CASE_MASKZ_UNPCK(UNPCKLPD, r)
254 CASE_MASKZ_UNPCK(UNPCKLPS, m)
255 CASE_MASKZ_UNPCK(UNPCKLPS, r)
Simon Pilgrimdbd6db02016-07-03 15:00:51 +0000[diff] [blame]256 CASE_MASKZ_SHUF(PALIGNR, r)
257 CASE_MASKZ_SHUF(PALIGNR, m)
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]258 CASE_MASKZ_SHUF(ALIGNQ, r)
259 CASE_MASKZ_SHUF(ALIGNQ, m)
260 CASE_MASKZ_SHUF(ALIGND, r)
261 CASE_MASKZ_SHUF(ALIGND, m)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]262 CASE_MASKZ_SHUF(SHUFPD, m)
263 CASE_MASKZ_SHUF(SHUFPD, r)
264 CASE_MASKZ_SHUF(SHUFPS, m)
265 CASE_MASKZ_SHUF(SHUFPS, r)
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]266 CASE_MASKZ_VPERMILPI(PERMILPD, m)
267 CASE_MASKZ_VPERMILPI(PERMILPD, r)
268 CASE_MASKZ_VPERMILPI(PERMILPS, m)
269 CASE_MASKZ_VPERMILPI(PERMILPS, r)
270 CASE_MASKZ_VPERMILPI(PSHUFD, m)
271 CASE_MASKZ_VPERMILPI(PSHUFD, r)
272 CASE_MASKZ_VPERMILPI(PSHUFHW, m)
273 CASE_MASKZ_VPERMILPI(PSHUFHW, r)
274 CASE_MASKZ_VPERMILPI(PSHUFLW, m)
275 CASE_MASKZ_VPERMILPI(PSHUFLW, r)
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]276 CASE_MASKZ_VPERM(PERMPD, m)
277 CASE_MASKZ_VPERM(PERMPD, r)
278 CASE_MASKZ_VPERM(PERMQ, m)
279 CASE_MASKZ_VPERM(PERMQ, r)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]280 CASE_MASKZ_VSHUF(64X2, m)
281 CASE_MASKZ_VSHUF(64X2, r)
282 CASE_MASKZ_VSHUF(32X4, m)
283 CASE_MASKZ_VSHUF(32X4, r)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]284 CASE_MASKZ_INS_COMMON(BROADCASTF64X2, Z128, rm)
285 CASE_MASKZ_INS_COMMON(BROADCASTI64X2, Z128, rm)
286 CASE_MASKZ_INS_COMMON(BROADCASTF64X2, , rm)
287 CASE_MASKZ_INS_COMMON(BROADCASTI64X2, , rm)
288 CASE_MASKZ_INS_COMMON(BROADCASTF64X4, , rm)
289 CASE_MASKZ_INS_COMMON(BROADCASTI64X4, , rm)
290 CASE_MASKZ_INS_COMMON(BROADCASTF32X4, Z256, rm)
291 CASE_MASKZ_INS_COMMON(BROADCASTI32X4, Z256, rm)
292 CASE_MASKZ_INS_COMMON(BROADCASTF32X4, , rm)
293 CASE_MASKZ_INS_COMMON(BROADCASTI32X4, , rm)
294 CASE_MASKZ_INS_COMMON(BROADCASTF32X8, , rm)
295 CASE_MASKZ_INS_COMMON(BROADCASTI32X8, , rm)
Craig Topper6ce20bd2017-10-11 00:11:53 +0000[diff] [blame^]296 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z128, r)
297 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z128, m)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]298 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, r)
299 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, r)
300 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z256, m)
301 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z256, m)
302 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, r)
303 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, r)
304 CASE_MASKZ_INS_COMMON(BROADCASTF32X2, Z, m)
305 CASE_MASKZ_INS_COMMON(BROADCASTI32X2, Z, m)
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]306 MaskWithZero = true;
307 MaskRegName = getRegName(MI->getOperand(1).getReg());
308 break;
309 CASE_MASK_MOVDUP(MOVDDUP, m)
310 CASE_MASK_MOVDUP(MOVDDUP, r)
311 CASE_MASK_MOVDUP(MOVSHDUP, m)
312 CASE_MASK_MOVDUP(MOVSHDUP, r)
313 CASE_MASK_MOVDUP(MOVSLDUP, m)
314 CASE_MASK_MOVDUP(MOVSLDUP, r)
Simon Pilgrim68f438a2016-07-03 13:33:28 +0000[diff] [blame]315 CASE_MASK_PMOVZX(PMOVZXBD, m)
316 CASE_MASK_PMOVZX(PMOVZXBD, r)
317 CASE_MASK_PMOVZX(PMOVZXBQ, m)
318 CASE_MASK_PMOVZX(PMOVZXBQ, r)
319 CASE_MASK_PMOVZX(PMOVZXBW, m)
320 CASE_MASK_PMOVZX(PMOVZXBW, r)
321 CASE_MASK_PMOVZX(PMOVZXDQ, m)
322 CASE_MASK_PMOVZX(PMOVZXDQ, r)
323 CASE_MASK_PMOVZX(PMOVZXWD, m)
324 CASE_MASK_PMOVZX(PMOVZXWD, r)
325 CASE_MASK_PMOVZX(PMOVZXWQ, m)
326 CASE_MASK_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim598bdb62016-07-03 14:26:21 +0000[diff] [blame]327 CASE_MASK_UNPCK(PUNPCKHBW, m)
328 CASE_MASK_UNPCK(PUNPCKHBW, r)
329 CASE_MASK_UNPCK(PUNPCKHWD, m)
330 CASE_MASK_UNPCK(PUNPCKHWD, r)
331 CASE_MASK_UNPCK(PUNPCKHDQ, m)
332 CASE_MASK_UNPCK(PUNPCKHDQ, r)
333 CASE_MASK_UNPCK(PUNPCKLBW, m)
334 CASE_MASK_UNPCK(PUNPCKLBW, r)
335 CASE_MASK_UNPCK(PUNPCKLWD, m)
336 CASE_MASK_UNPCK(PUNPCKLWD, r)
337 CASE_MASK_UNPCK(PUNPCKLDQ, m)
338 CASE_MASK_UNPCK(PUNPCKLDQ, r)
339 CASE_MASK_UNPCK(UNPCKHPD, m)
340 CASE_MASK_UNPCK(UNPCKHPD, r)
341 CASE_MASK_UNPCK(UNPCKHPS, m)
342 CASE_MASK_UNPCK(UNPCKHPS, r)
343 CASE_MASK_UNPCK(UNPCKLPD, m)
344 CASE_MASK_UNPCK(UNPCKLPD, r)
345 CASE_MASK_UNPCK(UNPCKLPS, m)
346 CASE_MASK_UNPCK(UNPCKLPS, r)
Simon Pilgrimdbd6db02016-07-03 15:00:51 +0000[diff] [blame]347 CASE_MASK_SHUF(PALIGNR, r)
348 CASE_MASK_SHUF(PALIGNR, m)
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]349 CASE_MASK_SHUF(ALIGNQ, r)
350 CASE_MASK_SHUF(ALIGNQ, m)
351 CASE_MASK_SHUF(ALIGND, r)
352 CASE_MASK_SHUF(ALIGND, m)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]353 CASE_MASK_SHUF(SHUFPD, m)
354 CASE_MASK_SHUF(SHUFPD, r)
355 CASE_MASK_SHUF(SHUFPS, m)
356 CASE_MASK_SHUF(SHUFPS, r)
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]357 CASE_MASK_VPERMILPI(PERMILPD, m)
358 CASE_MASK_VPERMILPI(PERMILPD, r)
359 CASE_MASK_VPERMILPI(PERMILPS, m)
360 CASE_MASK_VPERMILPI(PERMILPS, r)
361 CASE_MASK_VPERMILPI(PSHUFD, m)
362 CASE_MASK_VPERMILPI(PSHUFD, r)
363 CASE_MASK_VPERMILPI(PSHUFHW, m)
364 CASE_MASK_VPERMILPI(PSHUFHW, r)
365 CASE_MASK_VPERMILPI(PSHUFLW, m)
366 CASE_MASK_VPERMILPI(PSHUFLW, r)
Simon Pilgrim68ea8062016-07-03 18:40:24 +0000[diff] [blame]367 CASE_MASK_VPERM(PERMPD, m)
368 CASE_MASK_VPERM(PERMPD, r)
369 CASE_MASK_VPERM(PERMQ, m)
370 CASE_MASK_VPERM(PERMQ, r)
Simon Pilgrim1f590762016-07-03 13:55:41 +0000[diff] [blame]371 CASE_MASK_VSHUF(64X2, m)
372 CASE_MASK_VSHUF(64X2, r)
373 CASE_MASK_VSHUF(32X4, m)
374 CASE_MASK_VSHUF(32X4, r)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]375 CASE_MASK_INS_COMMON(BROADCASTF64X2, Z128, rm)
376 CASE_MASK_INS_COMMON(BROADCASTI64X2, Z128, rm)
377 CASE_MASK_INS_COMMON(BROADCASTF64X2, , rm)
378 CASE_MASK_INS_COMMON(BROADCASTI64X2, , rm)
379 CASE_MASK_INS_COMMON(BROADCASTF64X4, , rm)
380 CASE_MASK_INS_COMMON(BROADCASTI64X4, , rm)
381 CASE_MASK_INS_COMMON(BROADCASTF32X4, Z256, rm)
382 CASE_MASK_INS_COMMON(BROADCASTI32X4, Z256, rm)
383 CASE_MASK_INS_COMMON(BROADCASTF32X4, , rm)
384 CASE_MASK_INS_COMMON(BROADCASTI32X4, , rm)
385 CASE_MASK_INS_COMMON(BROADCASTF32X8, , rm)
386 CASE_MASK_INS_COMMON(BROADCASTI32X8, , rm)
Craig Topper6ce20bd2017-10-11 00:11:53 +0000[diff] [blame^]387 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z128, r)
388 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z128, m)
Simon Pilgrim32b06232016-10-21 12:14:24 +0000[diff] [blame]389 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, r)
390 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, r)
391 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z256, m)
392 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z256, m)
393 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, r)
394 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, r)
395 CASE_MASK_INS_COMMON(BROADCASTF32X2, Z, m)
396 CASE_MASK_INS_COMMON(BROADCASTI32X2, Z, m)
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]397 MaskRegName = getRegName(MI->getOperand(2).getReg());
398 break;
399 }
400
401 // MASK: zmmX {%kY}
402 OpMaskName += " {%";
403 OpMaskName += MaskRegName;
404 OpMaskName += "}";
405
406 // MASKZ: zmmX {%kY} {z}
407 if (MaskWithZero)
408 OpMaskName += " {z}";
409
410 return OpMaskName;
411}
412
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]413//===----------------------------------------------------------------------===//
414// Top Level Entrypoint
415//===----------------------------------------------------------------------===//
416
417/// EmitAnyX86InstComments - This function decodes x86 instructions and prints
418/// newline terminated strings to the specified string if desired. This
419/// information is shown in disassembly dumps when verbose assembly is enabled.
420bool llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS,
421 const char *(*getRegName)(unsigned)) {
422 // If this is a shuffle operation, the switch should fill in this state.
423 SmallVector<int, 8> ShuffleMask;
424 const char *DestName = nullptr, *Src1Name = nullptr, *Src2Name = nullptr;
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]425 unsigned NumOperands = MI->getNumOperands();
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]426 bool RegForm = false;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]427
428 switch (MI->getOpcode()) {
429 default:
430 // Not an instruction for which we can decode comments.
431 return false;
432
433 case X86::BLENDPDrri:
434 case X86::VBLENDPDrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]435 case X86::VBLENDPDYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]436 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]437 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]438 case X86::BLENDPDrmi:
439 case X86::VBLENDPDrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]440 case X86::VBLENDPDYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]441 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]442 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]443 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]444 ShuffleMask);
445 Src1Name = getRegName(MI->getOperand(1).getReg());
446 DestName = getRegName(MI->getOperand(0).getReg());
447 break;
448
449 case X86::BLENDPSrri:
450 case X86::VBLENDPSrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]451 case X86::VBLENDPSYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]452 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]453 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]454 case X86::BLENDPSrmi:
455 case X86::VBLENDPSrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]456 case X86::VBLENDPSYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]457 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]458 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]459 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]460 ShuffleMask);
461 Src1Name = getRegName(MI->getOperand(1).getReg());
462 DestName = getRegName(MI->getOperand(0).getReg());
463 break;
464
465 case X86::PBLENDWrri:
466 case X86::VPBLENDWrri:
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]467 case X86::VPBLENDWYrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]468 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]469 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]470 case X86::PBLENDWrmi:
471 case X86::VPBLENDWrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]472 case X86::VPBLENDWYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]473 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]474 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]475 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]476 ShuffleMask);
477 Src1Name = getRegName(MI->getOperand(1).getReg());
478 DestName = getRegName(MI->getOperand(0).getReg());
479 break;
480
481 case X86::VPBLENDDrri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]482 case X86::VPBLENDDYrri:
483 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]484 LLVM_FALLTHROUGH;
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]485 case X86::VPBLENDDrmi:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]486 case X86::VPBLENDDYrmi:
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]487 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim13d3a202015-11-16 23:03:18 +0000[diff] [blame]488 DecodeBLENDMask(getRegOperandVectorVT(MI, MVT::i32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]489 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]490 ShuffleMask);
491 Src1Name = getRegName(MI->getOperand(1).getReg());
492 DestName = getRegName(MI->getOperand(0).getReg());
493 break;
494
495 case X86::INSERTPSrr:
496 case X86::VINSERTPSrr:
Craig Topper6189d3e2016-07-19 01:26:19 +0000[diff] [blame]497 case X86::VINSERTPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]498 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]499 LLVM_FALLTHROUGH;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]500 case X86::INSERTPSrm:
501 case X86::VINSERTPSrm:
Craig Topper6189d3e2016-07-19 01:26:19 +0000[diff] [blame]502 case X86::VINSERTPSZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]503 DestName = getRegName(MI->getOperand(0).getReg());
504 Src1Name = getRegName(MI->getOperand(1).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]505 if (MI->getOperand(NumOperands - 1).isImm())
506 DecodeINSERTPSMask(MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]507 ShuffleMask);
508 break;
509
510 case X86::MOVLHPSrr:
511 case X86::VMOVLHPSrr:
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]512 case X86::VMOVLHPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]513 Src2Name = getRegName(MI->getOperand(2).getReg());
514 Src1Name = getRegName(MI->getOperand(1).getReg());
515 DestName = getRegName(MI->getOperand(0).getReg());
516 DecodeMOVLHPSMask(2, ShuffleMask);
517 break;
518
519 case X86::MOVHLPSrr:
520 case X86::VMOVHLPSrr:
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]521 case X86::VMOVHLPSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]522 Src2Name = getRegName(MI->getOperand(2).getReg());
523 Src1Name = getRegName(MI->getOperand(1).getReg());
524 DestName = getRegName(MI->getOperand(0).getReg());
525 DecodeMOVHLPSMask(2, ShuffleMask);
526 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]527
Simon Pilgrima3d67442016-02-07 15:39:22 +0000[diff] [blame]528 case X86::MOVHPDrm:
529 case X86::VMOVHPDrm:
530 case X86::VMOVHPDZ128rm:
531 Src1Name = getRegName(MI->getOperand(1).getReg());
532 DestName = getRegName(MI->getOperand(0).getReg());
533 DecodeInsertElementMask(MVT::v2f64, 1, 1, ShuffleMask);
534 break;
535
536 case X86::MOVHPSrm:
537 case X86::VMOVHPSrm:
538 case X86::VMOVHPSZ128rm:
539 Src1Name = getRegName(MI->getOperand(1).getReg());
540 DestName = getRegName(MI->getOperand(0).getReg());
541 DecodeInsertElementMask(MVT::v4f32, 2, 2, ShuffleMask);
542 break;
543
544 case X86::MOVLPDrm:
545 case X86::VMOVLPDrm:
546 case X86::VMOVLPDZ128rm:
547 Src1Name = getRegName(MI->getOperand(1).getReg());
548 DestName = getRegName(MI->getOperand(0).getReg());
549 DecodeInsertElementMask(MVT::v2f64, 0, 1, ShuffleMask);
550 break;
551
552 case X86::MOVLPSrm:
553 case X86::VMOVLPSrm:
554 case X86::VMOVLPSZ128rm:
555 Src1Name = getRegName(MI->getOperand(1).getReg());
556 DestName = getRegName(MI->getOperand(0).getReg());
557 DecodeInsertElementMask(MVT::v4f32, 0, 2, ShuffleMask);
558 break;
559
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]560 CASE_MOVDUP(MOVSLDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]561 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]562 LLVM_FALLTHROUGH;
563
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]564 CASE_MOVDUP(MOVSLDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]565 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]566 DecodeMOVSLDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]567 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]568
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]569 CASE_MOVDUP(MOVSHDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]570 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]571 LLVM_FALLTHROUGH;
572
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]573 CASE_MOVDUP(MOVSHDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]574 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]575 DecodeMOVSHDUPMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]576 break;
577
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]578 CASE_MOVDUP(MOVDDUP, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]579 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]580 LLVM_FALLTHROUGH;
581
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]582 CASE_MOVDUP(MOVDDUP, m)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]583 DestName = getRegName(MI->getOperand(0).getReg());
Igor Breger1f782962015-11-19 08:26:56 +0000[diff] [blame]584 DecodeMOVDDUPMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]585 break;
586
587 case X86::PSLLDQri:
588 case X86::VPSLLDQri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]589 case X86::VPSLLDQYri:
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]590 case X86::VPSLLDQZ128rr:
591 case X86::VPSLLDQZ256rr:
592 case X86::VPSLLDQZ512rr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]593 Src1Name = getRegName(MI->getOperand(1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]594 LLVM_FALLTHROUGH;
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]595 case X86::VPSLLDQZ128rm:
596 case X86::VPSLLDQZ256rm:
597 case X86::VPSLLDQZ512rm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]598 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]599 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]600 DecodePSLLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]601 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]602 ShuffleMask);
603 break;
604
605 case X86::PSRLDQri:
606 case X86::VPSRLDQri:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]607 case X86::VPSRLDQYri:
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]608 case X86::VPSRLDQZ128rr:
609 case X86::VPSRLDQZ256rr:
610 case X86::VPSRLDQZ512rr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]611 Src1Name = getRegName(MI->getOperand(1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]612 LLVM_FALLTHROUGH;
Simon Pilgrim643734c2016-06-09 22:03:15 +0000[diff] [blame]613 case X86::VPSRLDQZ128rm:
614 case X86::VPSRLDQZ256rm:
615 case X86::VPSRLDQZ512rm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]616 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]617 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]618 DecodePSRLDQMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]619 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]620 ShuffleMask);
621 break;
622
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]623 CASE_SHUF(PALIGNR, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]624 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
625 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]626 LLVM_FALLTHROUGH;
627
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]628 CASE_SHUF(PALIGNR, rmi)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]629 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]630 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]631 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimb9ada272015-11-16 22:54:41 +0000[diff] [blame]632 DecodePALIGNRMask(getRegOperandVectorVT(MI, MVT::i8, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]633 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]634 ShuffleMask);
635 break;
636
Craig Topperb084c902016-10-22 06:51:56 +0000[diff] [blame]637 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rri)
638 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rri)
639 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rri)
640 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
641 RegForm = true;
642 LLVM_FALLTHROUGH;
643
644 CASE_AVX512_INS_COMMON(ALIGNQ, Z, rmi)
645 CASE_AVX512_INS_COMMON(ALIGNQ, Z256, rmi)
646 CASE_AVX512_INS_COMMON(ALIGNQ, Z128, rmi)
647 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
648 DestName = getRegName(MI->getOperand(0).getReg());
649 if (MI->getOperand(NumOperands - 1).isImm())
650 DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i64, 0),
651 MI->getOperand(NumOperands - 1).getImm(),
652 ShuffleMask);
653 break;
654
655 CASE_AVX512_INS_COMMON(ALIGND, Z, rri)
656 CASE_AVX512_INS_COMMON(ALIGND, Z256, rri)
657 CASE_AVX512_INS_COMMON(ALIGND, Z128, rri)
658 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
659 RegForm = true;
660 LLVM_FALLTHROUGH;
661
662 CASE_AVX512_INS_COMMON(ALIGND, Z, rmi)
663 CASE_AVX512_INS_COMMON(ALIGND, Z256, rmi)
664 CASE_AVX512_INS_COMMON(ALIGND, Z128, rmi)
665 Src2Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
666 DestName = getRegName(MI->getOperand(0).getReg());
667 if (MI->getOperand(NumOperands - 1).isImm())
668 DecodeVALIGNMask(getRegOperandVectorVT(MI, MVT::i32, 0),
669 MI->getOperand(NumOperands - 1).getImm(),
670 ShuffleMask);
671 break;
672
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]673 CASE_SHUF(PSHUFD, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]674 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]675 LLVM_FALLTHROUGH;
676
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]677 CASE_SHUF(PSHUFD, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]678 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]679 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]680 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::i32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]681 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]682 ShuffleMask);
683 break;
684
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]685 CASE_SHUF(PSHUFHW, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]686 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]687 LLVM_FALLTHROUGH;
688
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]689 CASE_SHUF(PSHUFHW, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]690 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]691 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]692 DecodePSHUFHWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]693 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]694 ShuffleMask);
695 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]696
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]697 CASE_SHUF(PSHUFLW, ri)
Craig Topper6f7288d2016-06-09 07:49:08 +0000[diff] [blame]698 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]699 LLVM_FALLTHROUGH;
700
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]701 CASE_SHUF(PSHUFLW, mi)
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]702 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]703 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]704 DecodePSHUFLWMask(getRegOperandVectorVT(MI, MVT::i16, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]705 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]706 ShuffleMask);
707 break;
708
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]709 case X86::MMX_PSHUFWri:
710 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]711 LLVM_FALLTHROUGH;
712
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]713 case X86::MMX_PSHUFWmi:
714 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]715 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]716 DecodePSHUFMask(MVT::v4i16,
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]717 MI->getOperand(NumOperands - 1).getImm(),
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]718 ShuffleMask);
719 break;
720
721 case X86::PSWAPDrr:
722 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]723 LLVM_FALLTHROUGH;
724
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]725 case X86::PSWAPDrm:
726 DestName = getRegName(MI->getOperand(0).getReg());
727 DecodePSWAPMask(MVT::v2i32, ShuffleMask);
728 break;
729
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]730 CASE_UNPCK(PUNPCKHBW, r)
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]731 case X86::MMX_PUNPCKHBWirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]732 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
733 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]734 LLVM_FALLTHROUGH;
735
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]736 CASE_UNPCK(PUNPCKHBW, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]737 case X86::MMX_PUNPCKHBWirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]738 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]739 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]740 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]741 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]742
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]743 CASE_UNPCK(PUNPCKHWD, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]744 case X86::MMX_PUNPCKHWDirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]745 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
746 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]747 LLVM_FALLTHROUGH;
748
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]749 CASE_UNPCK(PUNPCKHWD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]750 case X86::MMX_PUNPCKHWDirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]751 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]752 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]753 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]754 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]755
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]756 CASE_UNPCK(PUNPCKHDQ, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]757 case X86::MMX_PUNPCKHDQirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]758 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
759 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]760 LLVM_FALLTHROUGH;
761
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]762 CASE_UNPCK(PUNPCKHDQ, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]763 case X86::MMX_PUNPCKHDQirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]764 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]765 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]766 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]767 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]768
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]769 CASE_UNPCK(PUNPCKHQDQ, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]770 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
771 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]772 LLVM_FALLTHROUGH;
773
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]774 CASE_UNPCK(PUNPCKHQDQ, m)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]775 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]776 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]777 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]778 break;
779
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]780 CASE_UNPCK(PUNPCKLBW, r)
Simon Pilgrimf8f86ab2015-09-13 11:28:45 +0000[diff] [blame]781 case X86::MMX_PUNPCKLBWirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]782 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
783 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]784 LLVM_FALLTHROUGH;
785
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]786 CASE_UNPCK(PUNPCKLBW, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]787 case X86::MMX_PUNPCKLBWirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]788 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]789 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]790 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i8, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]791 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]792
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]793 CASE_UNPCK(PUNPCKLWD, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]794 case X86::MMX_PUNPCKLWDirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]795 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
796 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]797 LLVM_FALLTHROUGH;
798
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]799 CASE_UNPCK(PUNPCKLWD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]800 case X86::MMX_PUNPCKLWDirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]801 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]802 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]803 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i16, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]804 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]805
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]806 CASE_UNPCK(PUNPCKLDQ, r)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]807 case X86::MMX_PUNPCKLDQirr:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]808 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
809 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]810 LLVM_FALLTHROUGH;
811
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]812 CASE_UNPCK(PUNPCKLDQ, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]813 case X86::MMX_PUNPCKLDQirm:
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]814 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]815 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]816 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i32, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]817 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]818
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]819 CASE_UNPCK(PUNPCKLQDQ, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]820 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
821 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]822 LLVM_FALLTHROUGH;
823
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]824 CASE_UNPCK(PUNPCKLQDQ, m)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]825 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]826 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]827 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::i64, 0), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]828 break;
829
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]830 CASE_SHUF(SHUFPD, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]831 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
832 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]833 LLVM_FALLTHROUGH;
834
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]835 CASE_SHUF(SHUFPD, rmi)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]836 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]837 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]838 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]839 ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]840 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]841 DestName = getRegName(MI->getOperand(0).getReg());
842 break;
843
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]844 CASE_SHUF(SHUFPS, rri)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]845 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
846 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]847 LLVM_FALLTHROUGH;
848
Craig Topper01f53b12016-06-03 05:31:00 +0000[diff] [blame]849 CASE_SHUF(SHUFPS, rmi)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]850 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]851 DecodeSHUFPMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]852 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]853 ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]854 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]855 DestName = getRegName(MI->getOperand(0).getReg());
856 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]857
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]858 CASE_VSHUF(64X2, r)
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]859 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
860 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]861 LLVM_FALLTHROUGH;
862
Igor Breger24cab0f2015-11-16 07:22:00 +0000[diff] [blame]863 CASE_VSHUF(64X2, m)
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]864 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i64, 0),
865 MI->getOperand(NumOperands - 1).getImm(),
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]866 ShuffleMask);
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]867 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]868 DestName = getRegName(MI->getOperand(0).getReg());
Igor Bregerd7bae452015-10-15 13:29:07 +0000[diff] [blame]869 break;
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]870
871 CASE_VSHUF(32X4, r)
872 Src2Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
873 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]874 LLVM_FALLTHROUGH;
875
Simon Pilgrimd3869412016-06-11 11:18:38 +0000[diff] [blame]876 CASE_VSHUF(32X4, m)
877 decodeVSHUF64x2FamilyMask(getRegOperandVectorVT(MI, MVT::i32, 0),
878 MI->getOperand(NumOperands - 1).getImm(),
879 ShuffleMask);
880 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?3:7)).getReg());
881 DestName = getRegName(MI->getOperand(0).getReg());
882 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]883
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]884 CASE_UNPCK(UNPCKLPD, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]885 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
886 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]887 LLVM_FALLTHROUGH;
888
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]889 CASE_UNPCK(UNPCKLPD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]890 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]891 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]892 DestName = getRegName(MI->getOperand(0).getReg());
893 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]894
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]895 CASE_UNPCK(UNPCKLPS, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]896 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
897 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]898 LLVM_FALLTHROUGH;
899
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]900 CASE_UNPCK(UNPCKLPS, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]901 DecodeUNPCKLMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]902 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]903 DestName = getRegName(MI->getOperand(0).getReg());
904 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]905
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]906 CASE_UNPCK(UNPCKHPD, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]907 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
908 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]909 LLVM_FALLTHROUGH;
910
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]911 CASE_UNPCK(UNPCKHPD, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]912 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f64, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]913 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]914 DestName = getRegName(MI->getOperand(0).getReg());
915 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]916
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]917 CASE_UNPCK(UNPCKHPS, r)
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]918 Src2Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
919 RegForm = true;
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]920 LLVM_FALLTHROUGH;
921
Simon Pilgrim8483df62015-11-17 22:35:45 +0000[diff] [blame]922 CASE_UNPCK(UNPCKHPS, m)
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]923 DecodeUNPCKHMask(getRegOperandVectorVT(MI, MVT::f32, 0), ShuffleMask);
Craig Topper89c17612016-06-10 04:48:05 +0000[diff] [blame]924 Src1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg());
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]925 DestName = getRegName(MI->getOperand(0).getReg());
926 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]927
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]928 CASE_VPERMILPI(PERMILPS, r)
Simon Pilgrim6ce35dd2016-05-11 18:53:44 +0000[diff] [blame]929 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]930 LLVM_FALLTHROUGH;
931
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]932 CASE_VPERMILPI(PERMILPS, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]933 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]934 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f32, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]935 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]936 ShuffleMask);
937 DestName = getRegName(MI->getOperand(0).getReg());
938 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]939
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]940 CASE_VPERMILPI(PERMILPD, r)
Simon Pilgrim6ce35dd2016-05-11 18:53:44 +0000[diff] [blame]941 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]942 LLVM_FALLTHROUGH;
943
Simon Pilgrim5080e7f2016-07-03 18:02:43 +0000[diff] [blame]944 CASE_VPERMILPI(PERMILPD, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]945 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrim5883a732015-11-16 22:39:27 +0000[diff] [blame]946 DecodePSHUFMask(getRegOperandVectorVT(MI, MVT::f64, 0),
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]947 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]948 ShuffleMask);
949 DestName = getRegName(MI->getOperand(0).getReg());
950 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]951
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]952 case X86::VPERM2F128rr:
953 case X86::VPERM2I128rr:
954 Src2Name = getRegName(MI->getOperand(2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]955 LLVM_FALLTHROUGH;
956
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]957 case X86::VPERM2F128rm:
958 case X86::VPERM2I128rm:
959 // For instruction comments purpose, assume the 256-bit vector is v4i64.
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]960 if (MI->getOperand(NumOperands - 1).isImm())
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]961 DecodeVPERM2X128Mask(MVT::v4i64,
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]962 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]963 ShuffleMask);
964 Src1Name = getRegName(MI->getOperand(1).getReg());
965 DestName = getRegName(MI->getOperand(0).getReg());
966 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]967
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]968 CASE_VPERM(PERMPD, r)
Craig Topper200d2372016-06-10 05:12:40 +0000[diff] [blame]969 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]970 LLVM_FALLTHROUGH;
971
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]972 CASE_VPERM(PERMPD, m)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]973 if (MI->getOperand(NumOperands - 1).isImm())
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]974 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::f64, 0),
975 MI->getOperand(NumOperands - 1).getImm(),
976 ShuffleMask);
977 DestName = getRegName(MI->getOperand(0).getReg());
978 break;
979
980 CASE_VPERM(PERMQ, r)
981 Src1Name = getRegName(MI->getOperand(NumOperands - 2).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]982 LLVM_FALLTHROUGH;
983
Simon Pilgrima0d73832016-07-03 18:27:37 +0000[diff] [blame]984 CASE_VPERM(PERMQ, m)
985 if (MI->getOperand(NumOperands - 1).isImm())
986 DecodeVPERMMask(getRegOperandVectorVT(MI, MVT::i64, 0),
987 MI->getOperand(NumOperands - 1).getImm(),
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]988 ShuffleMask);
989 DestName = getRegName(MI->getOperand(0).getReg());
990 break;
991
992 case X86::MOVSDrr:
993 case X86::VMOVSDrr:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]994 case X86::VMOVSDZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]995 Src2Name = getRegName(MI->getOperand(2).getReg());
996 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]997 LLVM_FALLTHROUGH;
998
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]999 case X86::MOVSDrm:
1000 case X86::VMOVSDrm:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]1001 case X86::VMOVSDZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1002 DecodeScalarMoveMask(MVT::v2f64, nullptr == Src2Name, ShuffleMask);
1003 DestName = getRegName(MI->getOperand(0).getReg());
1004 break;
Simon Pilgrimd5a15442015-11-21 13:04:42 +0000[diff] [blame]1005
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1006 case X86::MOVSSrr:
1007 case X86::VMOVSSrr:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]1008 case X86::VMOVSSZrr:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1009 Src2Name = getRegName(MI->getOperand(2).getReg());
1010 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1011 LLVM_FALLTHROUGH;
1012
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1013 case X86::MOVSSrm:
1014 case X86::VMOVSSrm:
Simon Pilgrimf5c23ad2016-02-01 22:26:28 +0000[diff] [blame]1015 case X86::VMOVSSZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1016 DecodeScalarMoveMask(MVT::v4f32, nullptr == Src2Name, ShuffleMask);
1017 DestName = getRegName(MI->getOperand(0).getReg());
1018 break;
1019
1020 case X86::MOVPQI2QIrr:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1021 case X86::MOVZPQILo2PQIrr:
1022 case X86::VMOVPQI2QIrr:
1023 case X86::VMOVZPQILo2PQIrr:
1024 case X86::VMOVZPQILo2PQIZrr:
1025 Src1Name = getRegName(MI->getOperand(1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1026 LLVM_FALLTHROUGH;
1027
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1028 case X86::MOVQI2PQIrm:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1029 case X86::VMOVQI2PQIrm:
Simon Pilgrim96fe4ef2016-02-02 13:32:56 +0000[diff] [blame]1030 case X86::VMOVQI2PQIZrm:
Simon Pilgrim3e0c0222015-12-13 12:49:48 +0000[diff] [blame]1031 DecodeZeroMoveLowMask(MVT::v2i64, ShuffleMask);
1032 DestName = getRegName(MI->getOperand(0).getReg());
1033 break;
Simon Pilgrim66e43ee2015-11-16 22:21:10 +0000[diff] [blame]1034
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1035 case X86::MOVDI2PDIrm:
1036 case X86::VMOVDI2PDIrm:
Simon Pilgrim5be17b62016-02-01 23:04:05 +0000[diff] [blame]1037 case X86::VMOVDI2PDIZrm:
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1038 DecodeZeroMoveLowMask(MVT::v4i32, ShuffleMask);
1039 DestName = getRegName(MI->getOperand(0).getReg());
1040 break;
1041
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1042 case X86::EXTRQI:
1043 if (MI->getOperand(2).isImm() &&
1044 MI->getOperand(3).isImm())
Simon Pilgrim9f0a0bd2017-07-04 16:53:12 +0000[diff] [blame]1045 DecodeEXTRQIMask(MVT::v16i8, MI->getOperand(2).getImm(),
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1046 MI->getOperand(3).getImm(),
1047 ShuffleMask);
1048
1049 DestName = getRegName(MI->getOperand(0).getReg());
1050 Src1Name = getRegName(MI->getOperand(1).getReg());
1051 break;
1052
1053 case X86::INSERTQI:
1054 if (MI->getOperand(3).isImm() &&
1055 MI->getOperand(4).isImm())
Simon Pilgrim9f0a0bd2017-07-04 16:53:12 +0000[diff] [blame]1056 DecodeINSERTQIMask(MVT::v16i8, MI->getOperand(3).getImm(),
Simon Pilgrimd85cae32015-07-06 20:46:41 +0000[diff] [blame]1057 MI->getOperand(4).getImm(),
1058 ShuffleMask);
1059
1060 DestName = getRegName(MI->getOperand(0).getReg());
1061 Src1Name = getRegName(MI->getOperand(1).getReg());
1062 Src2Name = getRegName(MI->getOperand(2).getReg());
1063 break;
1064
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1065 case X86::VBROADCASTF128:
1066 case X86::VBROADCASTI128:
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1067 CASE_AVX512_INS_COMMON(BROADCASTF64X2, Z128, rm)
1068 CASE_AVX512_INS_COMMON(BROADCASTI64X2, Z128, rm)
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1069 DecodeSubVectorBroadcast(MVT::v4f64, MVT::v2f64, ShuffleMask);
1070 DestName = getRegName(MI->getOperand(0).getReg());
1071 break;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1072 CASE_AVX512_INS_COMMON(BROADCASTF64X2, , rm)
1073 CASE_AVX512_INS_COMMON(BROADCASTI64X2, , rm)
1074 DecodeSubVectorBroadcast(MVT::v8f64, MVT::v2f64, ShuffleMask);
1075 DestName = getRegName(MI->getOperand(0).getReg());
1076 break;
1077 CASE_AVX512_INS_COMMON(BROADCASTF64X4, , rm)
1078 CASE_AVX512_INS_COMMON(BROADCASTI64X4, , rm)
1079 DecodeSubVectorBroadcast(MVT::v8f64, MVT::v4f64, ShuffleMask);
1080 DestName = getRegName(MI->getOperand(0).getReg());
1081 break;
1082 CASE_AVX512_INS_COMMON(BROADCASTF32X4, Z256, rm)
1083 CASE_AVX512_INS_COMMON(BROADCASTI32X4, Z256, rm)
1084 DecodeSubVectorBroadcast(MVT::v8f32, MVT::v4f32, ShuffleMask);
1085 DestName = getRegName(MI->getOperand(0).getReg());
1086 break;
1087 CASE_AVX512_INS_COMMON(BROADCASTF32X4, , rm)
1088 CASE_AVX512_INS_COMMON(BROADCASTI32X4, , rm)
1089 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v4f32, ShuffleMask);
1090 DestName = getRegName(MI->getOperand(0).getReg());
1091 break;
1092 CASE_AVX512_INS_COMMON(BROADCASTF32X8, , rm)
1093 CASE_AVX512_INS_COMMON(BROADCASTI32X8, , rm)
1094 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v8f32, ShuffleMask);
1095 DestName = getRegName(MI->getOperand(0).getReg());
1096 break;
Craig Topper6ce20bd2017-10-11 00:11:53 +0000[diff] [blame^]1097 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, r)
1098 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
1099 LLVM_FALLTHROUGH;
1100 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z128, m)
1101 DecodeSubVectorBroadcast(MVT::v4f32, MVT::v2f32, ShuffleMask);
1102 DestName = getRegName(MI->getOperand(0).getReg());
1103 break;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1104 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, r)
1105 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, r)
1106 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]1107 LLVM_FALLTHROUGH;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1108 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z256, m)
1109 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z256, m)
1110 DecodeSubVectorBroadcast(MVT::v8f32, MVT::v2f32, ShuffleMask);
1111 DestName = getRegName(MI->getOperand(0).getReg());
1112 break;
1113 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, r)
1114 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, r)
1115 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Galina Kistanovab2c01162017-05-31 19:41:33 +0000[diff] [blame]1116 LLVM_FALLTHROUGH;
Craig Topperdde865a2016-10-15 16:26:07 +0000[diff] [blame]1117 CASE_AVX512_INS_COMMON(BROADCASTF32X2, Z, m)
1118 CASE_AVX512_INS_COMMON(BROADCASTI32X2, Z, m)
1119 DecodeSubVectorBroadcast(MVT::v16f32, MVT::v2f32, ShuffleMask);
1120 DestName = getRegName(MI->getOperand(0).getReg());
1121 break;
Simon Pilgrima76a8e52016-07-14 12:07:43 +0000[diff] [blame]1122
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1123 CASE_PMOVZX(PMOVZXBW, r)
1124 CASE_PMOVZX(PMOVZXBD, r)
1125 CASE_PMOVZX(PMOVZXBQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1126 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1127 LLVM_FALLTHROUGH;
1128
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1129 CASE_PMOVZX(PMOVZXBW, m)
1130 CASE_PMOVZX(PMOVZXBD, m)
1131 CASE_PMOVZX(PMOVZXBQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1132 DecodeZeroExtendMask(MVT::i8, getZeroExtensionResultType(MI), ShuffleMask);
1133 DestName = getRegName(MI->getOperand(0).getReg());
1134 break;
1135
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1136 CASE_PMOVZX(PMOVZXWD, r)
1137 CASE_PMOVZX(PMOVZXWQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1138 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1139 LLVM_FALLTHROUGH;
1140
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1141 CASE_PMOVZX(PMOVZXWD, m)
1142 CASE_PMOVZX(PMOVZXWQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1143 DecodeZeroExtendMask(MVT::i16, getZeroExtensionResultType(MI), ShuffleMask);
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1144 DestName = getRegName(MI->getOperand(0).getReg());
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1145 break;
1146
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1147 CASE_PMOVZX(PMOVZXDQ, r)
Simon Pilgrim3016d9e2016-05-11 17:36:32 +0000[diff] [blame]1148 Src1Name = getRegName(MI->getOperand(NumOperands - 1).getReg());
Justin Bognercd1d5aa2016-08-17 20:30:52 +0000[diff] [blame]1149 LLVM_FALLTHROUGH;
1150
Simon Pilgrim0acc32a2016-02-06 19:51:21 +0000[diff] [blame]1151 CASE_PMOVZX(PMOVZXDQ, m)
Simon Pilgrime1b6db92016-02-06 16:33:42 +0000[diff] [blame]1152 DecodeZeroExtendMask(MVT::i32, getZeroExtensionResultType(MI), ShuffleMask);
1153 DestName = getRegName(MI->getOperand(0).getReg());
1154 break;
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1155 }
1156
1157 // The only comments we decode are shuffles, so give up if we were unable to
1158 // decode a shuffle mask.
1159 if (ShuffleMask.empty())
1160 return false;
1161
1162 if (!DestName) DestName = Src1Name;
Simon Pilgrim7c2fbdc2016-07-03 13:08:29 +0000[diff] [blame]1163 OS << (DestName ? getMaskName(MI, DestName, getRegName) : "mem") << " = ";
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1164
1165 // If the two sources are the same, canonicalize the input elements to be
1166 // from the first src so that we get larger element spans.
1167 if (Src1Name == Src2Name) {
1168 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1169 if ((int)ShuffleMask[i] >= 0 && // Not sentinel.
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1170 ShuffleMask[i] >= (int)e) // From second mask.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1171 ShuffleMask[i] -= e;
1172 }
1173 }
1174
1175 // The shuffle mask specifies which elements of the src1/src2 fill in the
1176 // destination, with a few sentinel values. Loop through and print them
1177 // out.
1178 for (unsigned i = 0, e = ShuffleMask.size(); i != e; ++i) {
1179 if (i != 0)
1180 OS << ',';
1181 if (ShuffleMask[i] == SM_SentinelZero) {
1182 OS << "zero";
1183 continue;
1184 }
1185
1186 // Otherwise, it must come from src1 or src2. Print the span of elements
1187 // that comes from this src.
1188 bool isSrc1 = ShuffleMask[i] < (int)ShuffleMask.size();
1189 const char *SrcName = isSrc1 ? Src1Name : Src2Name;
1190 OS << (SrcName ? SrcName : "mem") << '[';
1191 bool IsFirst = true;
1192 while (i != e && (int)ShuffleMask[i] != SM_SentinelZero &&
1193 (ShuffleMask[i] < (int)ShuffleMask.size()) == isSrc1) {
1194 if (!IsFirst)
1195 OS << ',';
1196 else
1197 IsFirst = false;
1198 if (ShuffleMask[i] == SM_SentinelUndef)
1199 OS << "u";
1200 else
1201 OS << ShuffleMask[i] % ShuffleMask.size();
1202 ++i;
1203 }
1204 OS << ']';
NAKAMURA Takumi5582a6a2015-05-25 01:43:34 +0000[diff] [blame]1205 --i; // For loop increments element #.
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1206 }
NAKAMURA Takumifb3bd712015-05-25 01:43:23 +0000[diff] [blame]1207
1208 // We successfully added a comment to this instruction.
1209 return true;
1210}