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Akira Hatanaka44ebe002013-03-14 19:09:52 +00001//===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===//
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// Subclass of MipsTargetLowering specialized for mips32/64.
11//
12//===----------------------------------------------------------------------===//
13#include "MipsSEISelLowering.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +000014#include "MipsMachineFunction.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +000015#include "MipsRegisterInfo.h"
16#include "MipsTargetMachine.h"
17#include "llvm/CodeGen/MachineInstrBuilder.h"
18#include "llvm/CodeGen/MachineRegisterInfo.h"
Akira Hatanakaa6bbde52013-04-13 02:13:30 +000019#include "llvm/IR/Intrinsics.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +000020#include "llvm/Support/CommandLine.h"
Daniel Sanders62aeab82013-10-30 13:31:27 +000021#include "llvm/Support/Debug.h"
Hans Wennborg3e9b1c12013-10-30 16:10:10 +000022#include "llvm/Support/raw_ostream.h"
Akira Hatanaka96ca1822013-03-13 00:54:29 +000023#include "llvm/Target/TargetInstrInfo.h"
24
25using namespace llvm;
26
Chandler Carruth84e68b22014-04-22 02:41:26 +000027#define DEBUG_TYPE "mips-isel"
28
Akira Hatanaka96ca1822013-03-13 00:54:29 +000029static cl::opt<bool>
30EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden,
31 cl::desc("MIPS: Enable tail calls."), cl::init(false));
32
Akira Hatanaka63791212013-09-07 00:52:30 +000033static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false),
34 cl::desc("Expand double precision loads and "
35 "stores to their single precision "
36 "counterparts"));
37
Eric Christopherb1526602014-09-19 23:30:42 +000038MipsSETargetLowering::MipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +000039 const MipsSubtarget &STI)
40 : MipsTargetLowering(TM, STI) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +000041 // Set up the register classes
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +000042 addRegisterClass(MVT::i32, &Mips::GPR32RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +000043
Eric Christopher1c29a652014-07-18 22:55:25 +000044 if (Subtarget.isGP64bit())
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +000045 addRegisterClass(MVT::i64, &Mips::GPR64RegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +000046
Eric Christopher1c29a652014-07-18 22:55:25 +000047 if (Subtarget.hasDSP() || Subtarget.hasMSA()) {
Daniel Sanders36c671e2013-09-27 09:44:59 +000048 // Expand all truncating stores and extending loads.
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +000049 for (MVT VT0 : MVT::vector_valuetypes()) {
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +000050 for (MVT VT1 : MVT::vector_valuetypes()) {
Ahmed Bougacha67dd2d22015-01-07 21:27:10 +000051 setTruncStoreAction(VT0, VT1, Expand);
Ahmed Bougacha2b6917b2015-01-08 00:51:32 +000052 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand);
53 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand);
54 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand);
55 }
Daniel Sanders36c671e2013-09-27 09:44:59 +000056 }
57 }
58
Eric Christopher1c29a652014-07-18 22:55:25 +000059 if (Subtarget.hasDSP()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +000060 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8};
61
62 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) {
Akira Hatanaka654655f2013-08-14 00:53:38 +000063 addRegisterClass(VecTys[i], &Mips::DSPRRegClass);
Akira Hatanaka96ca1822013-03-13 00:54:29 +000064
65 // Expand all builtin opcodes.
66 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
67 setOperationAction(Opc, VecTys[i], Expand);
68
Akira Hatanaka2f088222013-04-13 00:55:41 +000069 setOperationAction(ISD::ADD, VecTys[i], Legal);
70 setOperationAction(ISD::SUB, VecTys[i], Legal);
Akira Hatanaka96ca1822013-03-13 00:54:29 +000071 setOperationAction(ISD::LOAD, VecTys[i], Legal);
72 setOperationAction(ISD::STORE, VecTys[i], Legal);
73 setOperationAction(ISD::BITCAST, VecTys[i], Legal);
74 }
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +000075
76 setTargetDAGCombine(ISD::SHL);
77 setTargetDAGCombine(ISD::SRA);
78 setTargetDAGCombine(ISD::SRL);
Akira Hatanaka68741cc2013-04-30 22:37:26 +000079 setTargetDAGCombine(ISD::SETCC);
80 setTargetDAGCombine(ISD::VSELECT);
Akira Hatanaka96ca1822013-03-13 00:54:29 +000081 }
82
Eric Christopher1c29a652014-07-18 22:55:25 +000083 if (Subtarget.hasDSPR2())
Akira Hatanaka2f088222013-04-13 00:55:41 +000084 setOperationAction(ISD::MUL, MVT::v2i16, Legal);
85
Eric Christopher1c29a652014-07-18 22:55:25 +000086 if (Subtarget.hasMSA()) {
Daniel Sandersc65f58a2013-09-11 10:15:48 +000087 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass);
88 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass);
89 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass);
90 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass);
91 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass);
92 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass);
93 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass);
Daniel Sandersf7456c72013-09-23 13:22:24 +000094
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +000095 setTargetDAGCombine(ISD::AND);
Daniel Sanders53fe6c42013-10-30 13:51:01 +000096 setTargetDAGCombine(ISD::OR);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +000097 setTargetDAGCombine(ISD::SRA);
Daniel Sanderse1d24352013-09-24 12:04:44 +000098 setTargetDAGCombine(ISD::VSELECT);
Daniel Sandersf7456c72013-09-23 13:22:24 +000099 setTargetDAGCombine(ISD::XOR);
Jack Carter3a2c2d42013-08-13 20:54:07 +0000100 }
101
Eric Christophere8ae3e32015-05-07 23:10:21 +0000102 if (!Subtarget.useSoftFloat()) {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000103 addRegisterClass(MVT::f32, &Mips::FGR32RegClass);
104
105 // When dealing with single precision only, use libcalls
Eric Christopher1c29a652014-07-18 22:55:25 +0000106 if (!Subtarget.isSingleFloat()) {
107 if (Subtarget.isFP64bit())
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000108 addRegisterClass(MVT::f64, &Mips::FGR64RegClass);
109 else
110 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass);
111 }
112 }
113
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000114 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom);
115 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom);
116 setOperationAction(ISD::MULHS, MVT::i32, Custom);
117 setOperationAction(ISD::MULHU, MVT::i32, Custom);
118
Eric Christopher1c29a652014-07-18 22:55:25 +0000119 if (Subtarget.hasCnMips())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000120 setOperationAction(ISD::MUL, MVT::i64, Legal);
Eric Christopher1c29a652014-07-18 22:55:25 +0000121 else if (Subtarget.isGP64bit())
Kai Nacke93fe5e82014-03-20 11:51:58 +0000122 setOperationAction(ISD::MUL, MVT::i64, Custom);
123
Eric Christopher1c29a652014-07-18 22:55:25 +0000124 if (Subtarget.isGP64bit()) {
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000125 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Custom);
126 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000127 setOperationAction(ISD::MULHS, MVT::i64, Custom);
128 setOperationAction(ISD::MULHU, MVT::i64, Custom);
Jan Vesely54468a5a2014-10-17 14:45:28 +0000129 setOperationAction(ISD::SDIVREM, MVT::i64, Custom);
130 setOperationAction(ISD::UDIVREM, MVT::i64, Custom);
Akira Hatanaka4f1130e2013-04-11 19:29:26 +0000131 }
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000132
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom);
134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom);
135
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000136 setOperationAction(ISD::SDIVREM, MVT::i32, Custom);
137 setOperationAction(ISD::UDIVREM, MVT::i32, Custom);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000138 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom);
139 setOperationAction(ISD::LOAD, MVT::i32, Custom);
140 setOperationAction(ISD::STORE, MVT::i32, Custom);
141
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000142 setTargetDAGCombine(ISD::ADDE);
143 setTargetDAGCombine(ISD::SUBE);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000144 setTargetDAGCombine(ISD::MUL);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000145
Daniel Sandersce09d072013-08-28 12:14:50 +0000146 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000147 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
148 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom);
149
Akira Hatanaka63791212013-09-07 00:52:30 +0000150 if (NoDPLoadStore) {
151 setOperationAction(ISD::LOAD, MVT::f64, Custom);
152 setOperationAction(ISD::STORE, MVT::f64, Custom);
153 }
154
Eric Christopher1c29a652014-07-18 22:55:25 +0000155 if (Subtarget.hasMips32r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000156 // MIPS32r6 replaces the accumulator-based multiplies with a three register
157 // instruction
Daniel Sanders826f8b32014-06-12 10:54:16 +0000158 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Expand);
159 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000160 setOperationAction(ISD::MUL, MVT::i32, Legal);
161 setOperationAction(ISD::MULHS, MVT::i32, Legal);
162 setOperationAction(ISD::MULHU, MVT::i32, Legal);
163
164 // MIPS32r6 replaces the accumulator-based division/remainder with separate
165 // three register division and remainder instructions.
166 setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
167 setOperationAction(ISD::UDIVREM, MVT::i32, Expand);
168 setOperationAction(ISD::SDIV, MVT::i32, Legal);
169 setOperationAction(ISD::UDIV, MVT::i32, Legal);
170 setOperationAction(ISD::SREM, MVT::i32, Legal);
171 setOperationAction(ISD::UREM, MVT::i32, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000172
173 // MIPS32r6 replaces conditional moves with an equivalent that removes the
174 // need for three GPR read ports.
175 setOperationAction(ISD::SETCC, MVT::i32, Legal);
176 setOperationAction(ISD::SELECT, MVT::i32, Legal);
177 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
178
179 setOperationAction(ISD::SETCC, MVT::f32, Legal);
180 setOperationAction(ISD::SELECT, MVT::f32, Legal);
181 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
182
Eric Christopher1c29a652014-07-18 22:55:25 +0000183 assert(Subtarget.isFP64bit() && "FR=1 is required for MIPS32r6");
Daniel Sanders0fa60412014-06-12 13:39:06 +0000184 setOperationAction(ISD::SETCC, MVT::f64, Legal);
185 setOperationAction(ISD::SELECT, MVT::f64, Legal);
186 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
187
Daniel Sanders3d3ea532014-06-12 15:00:17 +0000188 setOperationAction(ISD::BRCOND, MVT::Other, Legal);
189
Daniel Sanders0fa60412014-06-12 13:39:06 +0000190 // Floating point > and >= are supported via < and <=
191 setCondCodeAction(ISD::SETOGE, MVT::f32, Expand);
192 setCondCodeAction(ISD::SETOGT, MVT::f32, Expand);
193 setCondCodeAction(ISD::SETUGE, MVT::f32, Expand);
194 setCondCodeAction(ISD::SETUGT, MVT::f32, Expand);
195
196 setCondCodeAction(ISD::SETOGE, MVT::f64, Expand);
197 setCondCodeAction(ISD::SETOGT, MVT::f64, Expand);
198 setCondCodeAction(ISD::SETUGE, MVT::f64, Expand);
199 setCondCodeAction(ISD::SETUGT, MVT::f64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000200 }
201
Eric Christopher1c29a652014-07-18 22:55:25 +0000202 if (Subtarget.hasMips64r6()) {
Daniel Sanders308181e2014-06-12 10:44:10 +0000203 // MIPS64r6 replaces the accumulator-based multiplies with a three register
204 // instruction
Vasileios Kalintirisef96a8e2015-01-26 12:33:22 +0000205 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
206 setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000207 setOperationAction(ISD::MUL, MVT::i64, Legal);
208 setOperationAction(ISD::MULHS, MVT::i64, Legal);
209 setOperationAction(ISD::MULHU, MVT::i64, Legal);
210
211 // MIPS32r6 replaces the accumulator-based division/remainder with separate
212 // three register division and remainder instructions.
213 setOperationAction(ISD::SDIVREM, MVT::i64, Expand);
214 setOperationAction(ISD::UDIVREM, MVT::i64, Expand);
215 setOperationAction(ISD::SDIV, MVT::i64, Legal);
216 setOperationAction(ISD::UDIV, MVT::i64, Legal);
217 setOperationAction(ISD::SREM, MVT::i64, Legal);
218 setOperationAction(ISD::UREM, MVT::i64, Legal);
Daniel Sanders0fa60412014-06-12 13:39:06 +0000219
220 // MIPS64r6 replaces conditional moves with an equivalent that removes the
221 // need for three GPR read ports.
222 setOperationAction(ISD::SETCC, MVT::i64, Legal);
223 setOperationAction(ISD::SELECT, MVT::i64, Legal);
224 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
Daniel Sanders308181e2014-06-12 10:44:10 +0000225 }
226
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000227 computeRegisterProperties(Subtarget.getRegisterInfo());
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000228}
229
230const MipsTargetLowering *
Eric Christopherb1526602014-09-19 23:30:42 +0000231llvm::createMipsSETargetLowering(const MipsTargetMachine &TM,
Eric Christopher8924d272014-07-18 23:25:04 +0000232 const MipsSubtarget &STI) {
233 return new MipsSETargetLowering(TM, STI);
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000234}
235
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000236const TargetRegisterClass *
237MipsSETargetLowering::getRepRegClassFor(MVT VT) const {
238 if (VT == MVT::Untyped)
Eric Christopher1c29a652014-07-18 22:55:25 +0000239 return Subtarget.hasDSP() ? &Mips::ACC64DSPRegClass : &Mips::ACC64RegClass;
Eric Christopherbf33a3c2014-07-02 23:18:40 +0000240
241 return TargetLowering::getRepRegClassFor(VT);
242}
243
Daniel Sanders7a289d02013-09-23 12:02:46 +0000244// Enable MSA support for the given integer type and Register class.
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000245void MipsSETargetLowering::
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000246addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
247 addRegisterClass(Ty, RC);
248
249 // Expand all builtin opcodes.
250 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
251 setOperationAction(Opc, Ty, Expand);
252
253 setOperationAction(ISD::BITCAST, Ty, Legal);
254 setOperationAction(ISD::LOAD, Ty, Legal);
255 setOperationAction(ISD::STORE, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000256 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom);
257 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000258 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000259
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +0000260 setOperationAction(ISD::ADD, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000261 setOperationAction(ISD::AND, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000262 setOperationAction(ISD::CTLZ, Ty, Legal);
Daniel Sanders766cb692013-09-23 13:40:21 +0000263 setOperationAction(ISD::CTPOP, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000264 setOperationAction(ISD::MUL, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000265 setOperationAction(ISD::OR, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000266 setOperationAction(ISD::SDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000267 setOperationAction(ISD::SREM, Ty, Legal);
Daniel Sandersfbcb5822013-09-11 11:58:30 +0000268 setOperationAction(ISD::SHL, Ty, Legal);
269 setOperationAction(ISD::SRA, Ty, Legal);
270 setOperationAction(ISD::SRL, Ty, Legal);
271 setOperationAction(ISD::SUB, Ty, Legal);
Daniel Sanders607952b2013-09-11 10:38:58 +0000272 setOperationAction(ISD::UDIV, Ty, Legal);
Daniel Sanders0210dd42013-10-01 10:22:35 +0000273 setOperationAction(ISD::UREM, Ty, Legal);
Daniel Sanderse5087042013-09-24 14:02:15 +0000274 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000275 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sanders8ca81e42013-09-23 12:57:42 +0000276 setOperationAction(ISD::XOR, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000277
Daniel Sanders015972b2013-10-11 10:00:06 +0000278 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) {
279 setOperationAction(ISD::FP_TO_SINT, Ty, Legal);
280 setOperationAction(ISD::FP_TO_UINT, Ty, Legal);
281 setOperationAction(ISD::SINT_TO_FP, Ty, Legal);
282 setOperationAction(ISD::UINT_TO_FP, Ty, Legal);
283 }
284
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000285 setOperationAction(ISD::SETCC, Ty, Legal);
286 setCondCodeAction(ISD::SETNE, Ty, Expand);
287 setCondCodeAction(ISD::SETGE, Ty, Expand);
288 setCondCodeAction(ISD::SETGT, Ty, Expand);
289 setCondCodeAction(ISD::SETUGE, Ty, Expand);
290 setCondCodeAction(ISD::SETUGT, Ty, Expand);
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000291}
292
Daniel Sanders7a289d02013-09-23 12:02:46 +0000293// Enable MSA support for the given floating-point type and Register class.
Daniel Sandersc65f58a2013-09-11 10:15:48 +0000294void MipsSETargetLowering::
295addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) {
Daniel Sanders3c9a0ad2013-08-23 10:10:13 +0000296 addRegisterClass(Ty, RC);
Jack Carterbabdcc82013-08-15 12:24:57 +0000297
298 // Expand all builtin opcodes.
299 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc)
300 setOperationAction(Opc, Ty, Expand);
301
302 setOperationAction(ISD::LOAD, Ty, Legal);
303 setOperationAction(ISD::STORE, Ty, Legal);
304 setOperationAction(ISD::BITCAST, Ty, Legal);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000305 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal);
Daniel Sandersa5150702013-09-27 12:31:32 +0000306 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal);
Daniel Sanders1dfddc72013-10-15 13:14:41 +0000307 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000308
309 if (Ty != MVT::v8f16) {
Daniel Sanders4f3ff1b2013-09-24 13:02:08 +0000310 setOperationAction(ISD::FABS, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000311 setOperationAction(ISD::FADD, Ty, Legal);
312 setOperationAction(ISD::FDIV, Ty, Legal);
Daniel Sandersa9521602013-10-23 10:36:52 +0000313 setOperationAction(ISD::FEXP2, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000314 setOperationAction(ISD::FLOG2, Ty, Legal);
Daniel Sandersd7103f32013-10-11 10:14:25 +0000315 setOperationAction(ISD::FMA, Ty, Legal);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000316 setOperationAction(ISD::FMUL, Ty, Legal);
317 setOperationAction(ISD::FRINT, Ty, Legal);
318 setOperationAction(ISD::FSQRT, Ty, Legal);
319 setOperationAction(ISD::FSUB, Ty, Legal);
Daniel Sanderse1d24352013-09-24 12:04:44 +0000320 setOperationAction(ISD::VSELECT, Ty, Legal);
Daniel Sandersfd538dc2013-09-24 10:46:19 +0000321
322 setOperationAction(ISD::SETCC, Ty, Legal);
323 setCondCodeAction(ISD::SETOGE, Ty, Expand);
324 setCondCodeAction(ISD::SETOGT, Ty, Expand);
325 setCondCodeAction(ISD::SETUGE, Ty, Expand);
326 setCondCodeAction(ISD::SETUGT, Ty, Expand);
327 setCondCodeAction(ISD::SETGE, Ty, Expand);
328 setCondCodeAction(ISD::SETGT, Ty, Expand);
Daniel Sandersf5bd9372013-09-11 10:51:30 +0000329 }
Jack Carterbabdcc82013-08-15 12:24:57 +0000330}
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000331
332bool
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000333MipsSETargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
334 unsigned,
335 unsigned,
336 bool *Fast) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000337 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy;
338
Eric Christopher1c29a652014-07-18 22:55:25 +0000339 if (Subtarget.systemSupportsUnalignedAccess()) {
Daniel Sandersac272632014-05-23 13:18:02 +0000340 // MIPS32r6/MIPS64r6 is required to support unaligned access. It's
341 // implementation defined whether this is handled by hardware, software, or
342 // a hybrid of the two but it's expected that most implementations will
343 // handle the majority of cases in hardware.
344 if (Fast)
345 *Fast = true;
346 return true;
347 }
348
Akira Hatanaka96ca1822013-03-13 00:54:29 +0000349 switch (SVT) {
350 case MVT::i64:
351 case MVT::i32:
352 if (Fast)
353 *Fast = true;
354 return true;
355 default:
356 return false;
357 }
358}
359
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000360SDValue MipsSETargetLowering::LowerOperation(SDValue Op,
361 SelectionDAG &DAG) const {
362 switch(Op.getOpcode()) {
Akira Hatanaka63791212013-09-07 00:52:30 +0000363 case ISD::LOAD: return lowerLOAD(Op, DAG);
364 case ISD::STORE: return lowerSTORE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000365 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG);
366 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG);
367 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG);
368 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG);
369 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG);
370 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG);
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000371 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true,
372 DAG);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +0000373 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG);
374 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +0000375 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000376 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG);
Daniel Sanders7a289d02013-09-23 12:02:46 +0000377 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG);
Daniel Sanderse5087042013-09-24 14:02:15 +0000378 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG);
Akira Hatanakabe8612f2013-03-30 01:36:35 +0000379 }
380
381 return MipsTargetLowering::LowerOperation(Op, DAG);
382}
383
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000384// selectMADD -
385// Transforms a subgraph in CurDAG if the following pattern is found:
386// (addc multLo, Lo0), (adde multHi, Hi0),
387// where,
388// multHi/Lo: product of multiplication
389// Lo0: initial value of Lo register
390// Hi0: initial value of Hi register
391// Return true if pattern matching was successful.
392static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) {
393 // ADDENode's second operand must be a flag output of an ADDC node in order
394 // for the matching to be successful.
395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode();
396
397 if (ADDCNode->getOpcode() != ISD::ADDC)
398 return false;
399
400 SDValue MultHi = ADDENode->getOperand(0);
401 SDValue MultLo = ADDCNode->getOperand(0);
402 SDNode *MultNode = MultHi.getNode();
403 unsigned MultOpc = MultHi.getOpcode();
404
405 // MultHi and MultLo must be generated by the same node,
406 if (MultLo.getNode() != MultNode)
407 return false;
408
409 // and it must be a multiplication.
410 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
411 return false;
412
413 // MultLo amd MultHi must be the first and second output of MultNode
414 // respectively.
415 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
416 return false;
417
418 // Transform this to a MADD only if ADDENode and ADDCNode are the only users
419 // of the values of MultNode, in which case MultNode will be removed in later
420 // phases.
421 // If there exist users other than ADDENode or ADDCNode, this function returns
422 // here, which will result in MultNode being mapped to a single MULT
423 // instruction node rather than a pair of MULT and MADD instructions being
424 // produced.
425 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
426 return false;
427
Andrew Trickef9de2a2013-05-25 02:42:55 +0000428 SDLoc DL(ADDENode);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000429
430 // Initialize accumulator.
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000431 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000432 ADDCNode->getOperand(1),
433 ADDENode->getOperand(1));
434
435 // create MipsMAdd(u) node
436 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
437
438 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped,
439 MultNode->getOperand(0),// Factor 0
440 MultNode->getOperand(1),// Factor 1
441 ACCIn);
442
443 // replace uses of adde and addc here
444 if (!SDValue(ADDCNode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000445 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000446 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut);
447 }
448 if (!SDValue(ADDENode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000449 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000450 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut);
451 }
452
453 return true;
454}
455
456// selectMSUB -
457// Transforms a subgraph in CurDAG if the following pattern is found:
458// (addc Lo0, multLo), (sube Hi0, multHi),
459// where,
460// multHi/Lo: product of multiplication
461// Lo0: initial value of Lo register
462// Hi0: initial value of Hi register
463// Return true if pattern matching was successful.
464static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) {
465 // SUBENode's second operand must be a flag output of an SUBC node in order
466 // for the matching to be successful.
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode();
468
469 if (SUBCNode->getOpcode() != ISD::SUBC)
470 return false;
471
472 SDValue MultHi = SUBENode->getOperand(1);
473 SDValue MultLo = SUBCNode->getOperand(1);
474 SDNode *MultNode = MultHi.getNode();
475 unsigned MultOpc = MultHi.getOpcode();
476
477 // MultHi and MultLo must be generated by the same node,
478 if (MultLo.getNode() != MultNode)
479 return false;
480
481 // and it must be a multiplication.
482 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
483 return false;
484
485 // MultLo amd MultHi must be the first and second output of MultNode
486 // respectively.
487 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
488 return false;
489
490 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users
491 // of the values of MultNode, in which case MultNode will be removed in later
492 // phases.
493 // If there exist users other than SUBENode or SUBCNode, this function returns
494 // here, which will result in MultNode being mapped to a single MULT
495 // instruction node rather than a pair of MULT and MSUB instructions being
496 // produced.
497 if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
498 return false;
499
Andrew Trickef9de2a2013-05-25 02:42:55 +0000500 SDLoc DL(SUBENode);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000501
502 // Initialize accumulator.
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000503 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped,
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000504 SUBCNode->getOperand(0),
505 SUBENode->getOperand(0));
506
507 // create MipsSub(u) node
508 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
509
510 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue,
511 MultNode->getOperand(0),// Factor 0
512 MultNode->getOperand(1),// Factor 1
513 ACCIn);
514
515 // replace uses of sube and subc here
516 if (!SDValue(SUBCNode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000517 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000518 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut);
519 }
520 if (!SDValue(SUBENode, 0).use_empty()) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +0000521 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub);
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000522 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut);
523 }
524
525 return true;
526}
527
528static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG,
529 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000530 const MipsSubtarget &Subtarget) {
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000531 if (DCI.isBeforeLegalize())
532 return SDValue();
533
Eric Christopher1c29a652014-07-18 22:55:25 +0000534 if (Subtarget.hasMips32() && !Subtarget.hasMips32r6() &&
Daniel Sanders826f8b32014-06-12 10:54:16 +0000535 N->getValueType(0) == MVT::i32 && selectMADD(N, &DAG))
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000536 return SDValue(N, 0);
537
538 return SDValue();
539}
540
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000541// Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT
542//
543// Performs the following transformations:
544// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its
545// sign/zero-extension is completely overwritten by the new one performed by
546// the ISD::AND.
547// - Removes redundant zero extensions performed by an ISD::AND.
548static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG,
549 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000550 const MipsSubtarget &Subtarget) {
551 if (!Subtarget.hasMSA())
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000552 return SDValue();
553
554 SDValue Op0 = N->getOperand(0);
555 SDValue Op1 = N->getOperand(1);
556 unsigned Op0Opcode = Op0->getOpcode();
557
558 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d)
559 // where $d + 1 == 2^n and n == 32
560 // or $d + 1 == 2^n and n <= 32 and ZExt
561 // -> (MipsVExtractZExt $a, $b, $c)
562 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT ||
563 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) {
564 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1);
565
566 if (!Mask)
567 return SDValue();
568
569 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2();
570
571 if (Log2IfPositive <= 0)
572 return SDValue(); // Mask+1 is not a power of 2
573
574 SDValue Op0Op2 = Op0->getOperand(2);
575 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT();
576 unsigned ExtendTySize = ExtendTy.getSizeInBits();
577 unsigned Log2 = Log2IfPositive;
578
579 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) ||
580 Log2 == ExtendTySize) {
581 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
Chandler Carruth356665a2014-08-01 22:09:43 +0000582 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
583 Op0->getVTList(),
584 makeArrayRef(Ops, Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000585 }
586 }
587
588 return SDValue();
589}
590
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000591// Determine if the specified node is a constant vector splat.
592//
593// Returns true and sets Imm if:
594// * N is a ISD::BUILD_VECTOR representing a constant splat
595//
596// This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The
597// differences are that it assumes the MSA has already been checked and the
598// arbitrary requirement for a maximum of 32-bit integers isn't applied (and
599// must not be in order for binsri.d to be selectable).
600static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) {
601 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode());
602
Craig Topper062a2ba2014-04-25 05:30:21 +0000603 if (!Node)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000604 return false;
605
606 APInt SplatValue, SplatUndef;
607 unsigned SplatBitSize;
608 bool HasAnyUndefs;
609
610 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
611 8, !IsLittleEndian))
612 return false;
613
614 Imm = SplatValue;
615
616 return true;
617}
618
Daniel Sandersab94b532013-10-30 15:20:38 +0000619// Test whether the given node is an all-ones build_vector.
620static bool isVectorAllOnes(SDValue N) {
621 // Look through bitcasts. Endianness doesn't matter because we are looking
622 // for an all-ones value.
623 if (N->getOpcode() == ISD::BITCAST)
624 N = N->getOperand(0);
625
626 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N);
627
628 if (!BVN)
629 return false;
630
631 APInt SplatValue, SplatUndef;
632 unsigned SplatBitSize;
633 bool HasAnyUndefs;
634
635 // Endianness doesn't matter in this context because we are looking for
636 // an all-ones value.
637 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs))
638 return SplatValue.isAllOnesValue();
639
640 return false;
641}
642
643// Test whether N is the bitwise inverse of OfNode.
644static bool isBitwiseInverse(SDValue N, SDValue OfNode) {
645 if (N->getOpcode() != ISD::XOR)
646 return false;
647
648 if (isVectorAllOnes(N->getOperand(0)))
649 return N->getOperand(1) == OfNode;
650
651 if (isVectorAllOnes(N->getOperand(1)))
652 return N->getOperand(0) == OfNode;
653
654 return false;
655}
656
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000657// Perform combines where ISD::OR is the root node.
658//
659// Performs the following transformations:
660// - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b)
661// where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit
662// vector type.
663static SDValue performORCombine(SDNode *N, SelectionDAG &DAG,
664 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000665 const MipsSubtarget &Subtarget) {
666 if (!Subtarget.hasMSA())
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000667 return SDValue();
668
669 EVT Ty = N->getValueType(0);
670
671 if (!Ty.is128BitVector())
672 return SDValue();
673
674 SDValue Op0 = N->getOperand(0);
675 SDValue Op1 = N->getOperand(1);
676
677 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) {
678 SDValue Op0Op0 = Op0->getOperand(0);
679 SDValue Op0Op1 = Op0->getOperand(1);
680 SDValue Op1Op0 = Op1->getOperand(0);
681 SDValue Op1Op1 = Op1->getOperand(1);
Eric Christopher1c29a652014-07-18 22:55:25 +0000682 bool IsLittleEndian = !Subtarget.isLittle();
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000683
684 SDValue IfSet, IfClr, Cond;
Daniel Sandersab94b532013-10-30 15:20:38 +0000685 bool IsConstantMask = false;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000686 APInt Mask, InvMask;
687
688 // If Op0Op0 is an appropriate mask, try to find it's inverse in either
689 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while
690 // looking.
691 // IfClr will be set if we find a valid match.
692 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) {
693 Cond = Op0Op0;
694 IfSet = Op0Op1;
695
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000696 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
697 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000698 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000699 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
700 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000701 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000702
703 IsConstantMask = true;
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000704 }
705
706 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same
707 // thing again using this mask.
708 // IfClr will be set if we find a valid match.
709 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) {
710 Cond = Op0Op1;
711 IfSet = Op0Op0;
712
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000713 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) &&
714 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000715 IfClr = Op1Op1;
Daniel Sandersc8c50fb2013-11-21 16:11:31 +0000716 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) &&
717 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask)
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000718 IfClr = Op1Op0;
Daniel Sandersab94b532013-10-30 15:20:38 +0000719
720 IsConstantMask = true;
721 }
722
723 // If IfClr is not yet set, try looking for a non-constant match.
724 // IfClr will be set if we find a valid match amongst the eight
725 // possibilities.
726 if (!IfClr.getNode()) {
727 if (isBitwiseInverse(Op0Op0, Op1Op0)) {
728 Cond = Op1Op0;
729 IfSet = Op1Op1;
730 IfClr = Op0Op1;
731 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) {
732 Cond = Op1Op0;
733 IfSet = Op1Op1;
734 IfClr = Op0Op0;
735 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) {
736 Cond = Op1Op1;
737 IfSet = Op1Op0;
738 IfClr = Op0Op1;
739 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) {
740 Cond = Op1Op1;
741 IfSet = Op1Op0;
742 IfClr = Op0Op0;
743 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) {
744 Cond = Op0Op0;
745 IfSet = Op0Op1;
746 IfClr = Op1Op1;
747 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) {
748 Cond = Op0Op0;
749 IfSet = Op0Op1;
750 IfClr = Op1Op0;
751 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) {
752 Cond = Op0Op1;
753 IfSet = Op0Op0;
754 IfClr = Op1Op1;
755 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) {
756 Cond = Op0Op1;
757 IfSet = Op0Op0;
758 IfClr = Op1Op0;
759 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000760 }
761
762 // At this point, IfClr will be set if we have a valid match.
763 if (!IfClr.getNode())
764 return SDValue();
765
766 assert(Cond.getNode() && IfSet.getNode());
767
768 // Fold degenerate cases.
Daniel Sandersab94b532013-10-30 15:20:38 +0000769 if (IsConstantMask) {
770 if (Mask.isAllOnesValue())
771 return IfSet;
772 else if (Mask == 0)
773 return IfClr;
774 }
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000775
776 // Transform the DAG into an equivalent VSELECT.
Daniel Sandersdf2215452014-03-12 11:54:00 +0000777 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfSet, IfClr);
Daniel Sanders53fe6c42013-10-30 13:51:01 +0000778 }
779
780 return SDValue();
781}
782
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000783static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG,
784 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000785 const MipsSubtarget &Subtarget) {
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000786 if (DCI.isBeforeLegalize())
787 return SDValue();
788
Eric Christopher1c29a652014-07-18 22:55:25 +0000789 if (Subtarget.hasMips32() && N->getValueType(0) == MVT::i32 &&
Akira Hatanaka9efcd762013-03-30 01:42:24 +0000790 selectMSUB(N, &DAG))
791 return SDValue(N, 0);
792
793 return SDValue();
794}
795
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000796static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT,
797 EVT ShiftTy, SelectionDAG &DAG) {
798 // Clear the upper (64 - VT.sizeInBits) bits.
799 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits());
800
801 // Return 0.
802 if (C == 0)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000803 return DAG.getConstant(0, DL, VT);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000804
805 // Return x.
806 if (C == 1)
807 return X;
808
809 // If c is power of 2, return (shl x, log2(c)).
810 if (isPowerOf2_64(C))
811 return DAG.getNode(ISD::SHL, DL, VT, X,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000812 DAG.getConstant(Log2_64(C), DL, ShiftTy));
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000813
814 unsigned Log2Ceil = Log2_64_Ceil(C);
815 uint64_t Floor = 1LL << Log2_64(C);
816 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil;
817
818 // If |c - floor_c| <= |c - ceil_c|,
819 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))),
820 // return (add constMult(x, floor_c), constMult(x, c - floor_c)).
821 if (C - Floor <= Ceil - C) {
822 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG);
823 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG);
824 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1);
825 }
826
827 // If |c - floor_c| > |c - ceil_c|,
828 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)).
829 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG);
830 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG);
831 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1);
832}
833
834static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG,
835 const TargetLowering::DAGCombinerInfo &DCI,
836 const MipsSETargetLowering *TL) {
837 EVT VT = N->getValueType(0);
838
839 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1)))
840 if (!VT.isVector())
Mehdi Amini9639d652015-07-09 02:09:20 +0000841 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), VT,
Mehdi Aminieaabc512015-07-09 15:12:23 +0000842 TL->getScalarShiftAmountTy(DAG.getDataLayout(), VT),
843 DAG);
Akira Hatanaka5832fc62013-06-26 18:48:17 +0000844
845 return SDValue(N, 0);
846}
847
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000848static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty,
849 SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +0000850 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000851 // See if this is a vector splat immediate node.
852 APInt SplatValue, SplatUndef;
853 unsigned SplatBitSize;
854 bool HasAnyUndefs;
855 unsigned EltSize = Ty.getVectorElementType().getSizeInBits();
856 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1));
857
Eric Christopher1c29a652014-07-18 22:55:25 +0000858 if (!Subtarget.hasDSP())
Daniel Sanders6e664bc2013-11-21 11:40:14 +0000859 return SDValue();
860
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000861 if (!BV ||
Akira Hatanakad8fb0322013-04-22 20:13:37 +0000862 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
Eric Christopher1c29a652014-07-18 22:55:25 +0000863 EltSize, !Subtarget.isLittle()) ||
Akira Hatanaka0d6964c2013-04-22 19:58:23 +0000864 (SplatBitSize != EltSize) ||
Akira Hatanakae9d0b312013-04-23 18:09:42 +0000865 (SplatValue.getZExtValue() >= EltSize))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000866 return SDValue();
867
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000868 SDLoc DL(N);
869 return DAG.getNode(Opc, DL, Ty, N->getOperand(0),
870 DAG.getConstant(SplatValue.getZExtValue(), DL, MVT::i32));
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000871}
872
873static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG,
874 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000875 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000876 EVT Ty = N->getValueType(0);
877
878 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
879 return SDValue();
880
881 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget);
882}
883
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000884// Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold
885// constant splats into MipsISD::SHRA_DSP for DSPr2.
886//
887// Performs the following transformations:
888// - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its
889// sign/zero-extension is completely overwritten by the new one performed by
890// the ISD::SRA and ISD::SHL nodes.
891// - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL
892// sequence.
893//
894// See performDSPShiftCombine for more information about the transformation
895// used for DSPr2.
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000896static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG,
897 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000898 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000899 EVT Ty = N->getValueType(0);
900
Eric Christopher1c29a652014-07-18 22:55:25 +0000901 if (Subtarget.hasMSA()) {
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000902 SDValue Op0 = N->getOperand(0);
903 SDValue Op1 = N->getOperand(1);
904
905 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d)
906 // where $d + sizeof($c) == 32
907 // or $d + sizeof($c) <= 32 and SExt
908 // -> (MipsVExtractSExt $a, $b, $c)
909 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) {
910 SDValue Op0Op0 = Op0->getOperand(0);
911 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1);
912
913 if (!ShAmount)
914 return SDValue();
915
Daniel Sandersf4f1a872013-09-27 09:25:29 +0000916 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT &&
917 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT)
918 return SDValue();
919
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000920 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT();
921 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits();
922
923 if (TotalBits == 32 ||
924 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT &&
925 TotalBits <= 32)) {
926 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1),
927 Op0Op0->getOperand(2) };
Chandler Carruth356665a2014-08-01 22:09:43 +0000928 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, SDLoc(Op0Op0),
929 Op0Op0->getVTList(),
930 makeArrayRef(Ops, Op0Op0->getNumOperands()));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +0000931 }
932 }
933 }
934
Eric Christopher1c29a652014-07-18 22:55:25 +0000935 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget.hasDSPR2()))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000936 return SDValue();
937
938 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget);
939}
940
941
942static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG,
943 TargetLowering::DAGCombinerInfo &DCI,
Eric Christopher1c29a652014-07-18 22:55:25 +0000944 const MipsSubtarget &Subtarget) {
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000945 EVT Ty = N->getValueType(0);
946
Eric Christopher1c29a652014-07-18 22:55:25 +0000947 if (((Ty != MVT::v2i16) || !Subtarget.hasDSPR2()) && (Ty != MVT::v4i8))
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +0000948 return SDValue();
949
950 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget);
951}
952
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000953static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) {
954 bool IsV216 = (Ty == MVT::v2i16);
955
956 switch (CC) {
957 case ISD::SETEQ:
958 case ISD::SETNE: return true;
959 case ISD::SETLT:
960 case ISD::SETLE:
961 case ISD::SETGT:
962 case ISD::SETGE: return IsV216;
963 case ISD::SETULT:
964 case ISD::SETULE:
965 case ISD::SETUGT:
966 case ISD::SETUGE: return !IsV216;
967 default: return false;
968 }
969}
970
971static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) {
972 EVT Ty = N->getValueType(0);
973
974 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8))
975 return SDValue();
976
977 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get()))
978 return SDValue();
979
Andrew Trickef9de2a2013-05-25 02:42:55 +0000980 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0),
Akira Hatanaka68741cc2013-04-30 22:37:26 +0000981 N->getOperand(1), N->getOperand(2));
982}
983
984static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) {
985 EVT Ty = N->getValueType(0);
986
Daniel Sanders3ce56622013-09-24 12:18:31 +0000987 if (Ty.is128BitVector() && Ty.isInteger()) {
988 // Try the following combines:
989 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b)
990 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b)
991 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b)
992 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b)
993 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b)
994 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b)
995 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b)
996 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b)
997 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but
998 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the
999 // legalizer.
1000 SDValue Op0 = N->getOperand(0);
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001001
Daniel Sanders3ce56622013-09-24 12:18:31 +00001002 if (Op0->getOpcode() != ISD::SETCC)
1003 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001004
Daniel Sanders3ce56622013-09-24 12:18:31 +00001005 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get();
1006 bool Signed;
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001007
Daniel Sanders3ce56622013-09-24 12:18:31 +00001008 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE)
1009 Signed = true;
1010 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE)
1011 Signed = false;
1012 else
1013 return SDValue();
1014
1015 SDValue Op1 = N->getOperand(1);
1016 SDValue Op2 = N->getOperand(2);
1017 SDValue Op0Op0 = Op0->getOperand(0);
1018 SDValue Op0Op1 = Op0->getOperand(1);
1019
1020 if (Op1 == Op0Op0 && Op2 == Op0Op1)
1021 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N),
1022 Ty, Op1, Op2);
1023 else if (Op1 == Op0Op1 && Op2 == Op0Op0)
1024 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N),
1025 Ty, Op1, Op2);
1026 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) {
1027 SDValue SetCC = N->getOperand(0);
1028
1029 if (SetCC.getOpcode() != MipsISD::SETCC_DSP)
1030 return SDValue();
1031
1032 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty,
1033 SetCC.getOperand(0), SetCC.getOperand(1),
1034 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2));
1035 }
1036
1037 return SDValue();
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001038}
1039
Daniel Sandersf7456c72013-09-23 13:22:24 +00001040static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG,
Eric Christopher1c29a652014-07-18 22:55:25 +00001041 const MipsSubtarget &Subtarget) {
Daniel Sandersf7456c72013-09-23 13:22:24 +00001042 EVT Ty = N->getValueType(0);
1043
Eric Christopher1c29a652014-07-18 22:55:25 +00001044 if (Subtarget.hasMSA() && Ty.is128BitVector() && Ty.isInteger()) {
Daniel Sandersf7456c72013-09-23 13:22:24 +00001045 // Try the following combines:
1046 // (xor (or $a, $b), (build_vector allones))
1047 // (xor (or $a, $b), (bitcast (build_vector allones)))
1048 SDValue Op0 = N->getOperand(0);
1049 SDValue Op1 = N->getOperand(1);
1050 SDValue NotOp;
Daniel Sandersf7456c72013-09-23 13:22:24 +00001051
1052 if (ISD::isBuildVectorAllOnes(Op0.getNode()))
1053 NotOp = Op1;
1054 else if (ISD::isBuildVectorAllOnes(Op1.getNode()))
1055 NotOp = Op0;
Daniel Sandersf7456c72013-09-23 13:22:24 +00001056 else
1057 return SDValue();
1058
1059 if (NotOp->getOpcode() == ISD::OR)
1060 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0),
1061 NotOp->getOperand(1));
1062 }
1063
1064 return SDValue();
1065}
1066
Akira Hatanaka9efcd762013-03-30 01:42:24 +00001067SDValue
1068MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const {
1069 SelectionDAG &DAG = DCI.DAG;
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001070 SDValue Val;
Akira Hatanaka9efcd762013-03-30 01:42:24 +00001071
1072 switch (N->getOpcode()) {
1073 case ISD::ADDE:
1074 return performADDECombine(N, DAG, DCI, Subtarget);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00001075 case ISD::AND:
1076 Val = performANDCombine(N, DAG, DCI, Subtarget);
1077 break;
Daniel Sanders53fe6c42013-10-30 13:51:01 +00001078 case ISD::OR:
1079 Val = performORCombine(N, DAG, DCI, Subtarget);
1080 break;
Akira Hatanaka9efcd762013-03-30 01:42:24 +00001081 case ISD::SUBE:
1082 return performSUBECombine(N, DAG, DCI, Subtarget);
Akira Hatanaka5832fc62013-06-26 18:48:17 +00001083 case ISD::MUL:
1084 return performMULCombine(N, DAG, DCI, this);
Akira Hatanaka1ebb2a12013-04-19 23:21:32 +00001085 case ISD::SHL:
1086 return performSHLCombine(N, DAG, DCI, Subtarget);
1087 case ISD::SRA:
1088 return performSRACombine(N, DAG, DCI, Subtarget);
1089 case ISD::SRL:
1090 return performSRLCombine(N, DAG, DCI, Subtarget);
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001091 case ISD::VSELECT:
1092 return performVSELECTCombine(N, DAG);
Daniel Sandersf7456c72013-09-23 13:22:24 +00001093 case ISD::XOR:
1094 Val = performXORCombine(N, DAG, Subtarget);
1095 break;
1096 case ISD::SETCC:
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001097 Val = performSETCCCombine(N, DAG);
1098 break;
Akira Hatanaka9efcd762013-03-30 01:42:24 +00001099 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001100
Daniel Sanders62aeab82013-10-30 13:31:27 +00001101 if (Val.getNode()) {
1102 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n";
1103 N->printrWithDepth(dbgs(), &DAG);
1104 dbgs() << "\n=> \n";
1105 Val.getNode()->printrWithDepth(dbgs(), &DAG);
1106 dbgs() << "\n");
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001107 return Val;
Daniel Sanders62aeab82013-10-30 13:31:27 +00001108 }
Akira Hatanaka68741cc2013-04-30 22:37:26 +00001109
1110 return MipsTargetLowering::PerformDAGCombine(N, DCI);
Akira Hatanaka9efcd762013-03-30 01:42:24 +00001111}
1112
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001113MachineBasicBlock *
1114MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
1115 MachineBasicBlock *BB) const {
1116 switch (MI->getOpcode()) {
1117 default:
1118 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB);
1119 case Mips::BPOSGE32_PSEUDO:
1120 return emitBPOSGE32(MI, BB);
Daniel Sandersce09d072013-08-28 12:14:50 +00001121 case Mips::SNZ_B_PSEUDO:
1122 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B);
1123 case Mips::SNZ_H_PSEUDO:
1124 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H);
1125 case Mips::SNZ_W_PSEUDO:
1126 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W);
1127 case Mips::SNZ_D_PSEUDO:
1128 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D);
1129 case Mips::SNZ_V_PSEUDO:
1130 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V);
1131 case Mips::SZ_B_PSEUDO:
1132 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B);
1133 case Mips::SZ_H_PSEUDO:
1134 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H);
1135 case Mips::SZ_W_PSEUDO:
1136 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W);
1137 case Mips::SZ_D_PSEUDO:
1138 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D);
1139 case Mips::SZ_V_PSEUDO:
1140 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00001141 case Mips::COPY_FW_PSEUDO:
1142 return emitCOPY_FW(MI, BB);
1143 case Mips::COPY_FD_PSEUDO:
1144 return emitCOPY_FD(MI, BB);
Daniel Sandersa5150702013-09-27 12:31:32 +00001145 case Mips::INSERT_FW_PSEUDO:
1146 return emitINSERT_FW(MI, BB);
1147 case Mips::INSERT_FD_PSEUDO:
1148 return emitINSERT_FD(MI, BB);
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001149 case Mips::INSERT_B_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001150 case Mips::INSERT_B_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001151 return emitINSERT_DF_VIDX(MI, BB, 1, false);
1152 case Mips::INSERT_H_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001153 case Mips::INSERT_H_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001154 return emitINSERT_DF_VIDX(MI, BB, 2, false);
1155 case Mips::INSERT_W_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001156 case Mips::INSERT_W_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001157 return emitINSERT_DF_VIDX(MI, BB, 4, false);
1158 case Mips::INSERT_D_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001159 case Mips::INSERT_D_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001160 return emitINSERT_DF_VIDX(MI, BB, 8, false);
1161 case Mips::INSERT_FW_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001162 case Mips::INSERT_FW_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001163 return emitINSERT_DF_VIDX(MI, BB, 4, true);
1164 case Mips::INSERT_FD_VIDX_PSEUDO:
Daniel Sanderseda60d22015-05-05 10:32:24 +00001165 case Mips::INSERT_FD_VIDX64_PSEUDO:
Daniel Sanderse296a0f2014-04-30 12:09:32 +00001166 return emitINSERT_DF_VIDX(MI, BB, 8, true);
Daniel Sanders1dfddc72013-10-15 13:14:41 +00001167 case Mips::FILL_FW_PSEUDO:
1168 return emitFILL_FW(MI, BB);
1169 case Mips::FILL_FD_PSEUDO:
1170 return emitFILL_FD(MI, BB);
Daniel Sandersa9521602013-10-23 10:36:52 +00001171 case Mips::FEXP2_W_1_PSEUDO:
1172 return emitFEXP2_W_1(MI, BB);
1173 case Mips::FEXP2_D_1_PSEUDO:
1174 return emitFEXP2_D_1(MI, BB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001175 }
1176}
1177
Daniel Sanders23e98772014-11-02 16:09:29 +00001178bool MipsSETargetLowering::isEligibleForTailCallOptimization(
1179 const CCState &CCInfo, unsigned NextStackOffset,
1180 const MipsFunctionInfo &FI) const {
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001181 if (!EnableMipsTailCalls)
1182 return false;
1183
Vasileios Kalintiris43dff0c2015-10-26 12:38:43 +00001184 // Exception has to be cleared with eret.
1185 if (FI.isISR())
1186 return false;
1187
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001188 // Return false if either the callee or caller has a byval argument.
Daniel Sanders23e98772014-11-02 16:09:29 +00001189 if (CCInfo.getInRegsParamsCount() > 0 || FI.hasByvalArg())
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001190 return false;
1191
1192 // Return true if the callee's argument area is no larger than the
1193 // caller's.
1194 return NextStackOffset <= FI.getIncomingArgSize();
1195}
1196
1197void MipsSETargetLowering::
1198getOpndList(SmallVectorImpl<SDValue> &Ops,
1199 std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
1200 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
Sasa Stankovic7072a792014-10-01 08:22:21 +00001201 bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
1202 SDValue Chain) const {
Akira Hatanaka168d4e52013-11-27 23:38:42 +00001203 Ops.push_back(Callee);
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001204 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal,
Sasa Stankovic7072a792014-10-01 08:22:21 +00001205 InternalLinkage, IsCallReloc, CLI, Callee,
1206 Chain);
Akira Hatanaka96ca1822013-03-13 00:54:29 +00001207}
1208
Akira Hatanaka63791212013-09-07 00:52:30 +00001209SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1210 LoadSDNode &Nd = *cast<LoadSDNode>(Op);
1211
1212 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1213 return MipsTargetLowering::lowerLOAD(Op, DAG);
1214
1215 // Replace a double precision load with two i32 loads and a buildpair64.
1216 SDLoc DL(Op);
1217 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1218 EVT PtrVT = Ptr.getValueType();
1219
1220 // i32 load from lower address.
1221 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr,
1222 MachinePointerInfo(), Nd.isVolatile(),
1223 Nd.isNonTemporal(), Nd.isInvariant(),
1224 Nd.getAlignment());
1225
1226 // i32 load from higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001227 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Akira Hatanaka63791212013-09-07 00:52:30 +00001228 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr,
1229 MachinePointerInfo(), Nd.isVolatile(),
1230 Nd.isNonTemporal(), Nd.isInvariant(),
Akira Hatanaka9cf069f2013-09-09 17:59:32 +00001231 std::min(Nd.getAlignment(), 4U));
Akira Hatanaka63791212013-09-07 00:52:30 +00001232
Eric Christopher1c29a652014-07-18 22:55:25 +00001233 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +00001234 std::swap(Lo, Hi);
1235
1236 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
1237 SDValue Ops[2] = {BP, Hi.getValue(1)};
Craig Topper64941d92014-04-27 19:20:57 +00001238 return DAG.getMergeValues(Ops, DL);
Akira Hatanaka63791212013-09-07 00:52:30 +00001239}
1240
1241SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1242 StoreSDNode &Nd = *cast<StoreSDNode>(Op);
1243
1244 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore)
1245 return MipsTargetLowering::lowerSTORE(Op, DAG);
1246
1247 // Replace a double precision store with two extractelement64s and i32 stores.
1248 SDLoc DL(Op);
1249 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain();
1250 EVT PtrVT = Ptr.getValueType();
1251 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001252 Val, DAG.getConstant(0, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +00001253 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001254 Val, DAG.getConstant(1, DL, MVT::i32));
Akira Hatanaka63791212013-09-07 00:52:30 +00001255
Eric Christopher1c29a652014-07-18 22:55:25 +00001256 if (!Subtarget.isLittle())
Akira Hatanaka63791212013-09-07 00:52:30 +00001257 std::swap(Lo, Hi);
1258
1259 // i32 store to lower address.
1260 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(),
1261 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(),
Hal Finkelcc39b672014-07-24 12:16:19 +00001262 Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +00001263
1264 // i32 store to higher address.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001265 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, DL, PtrVT));
Akira Hatanaka63791212013-09-07 00:52:30 +00001266 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(),
Akira Hatanaka9cf069f2013-09-09 17:59:32 +00001267 Nd.isVolatile(), Nd.isNonTemporal(),
Hal Finkelcc39b672014-07-24 12:16:19 +00001268 std::min(Nd.getAlignment(), 4U), Nd.getAAInfo());
Akira Hatanaka63791212013-09-07 00:52:30 +00001269}
1270
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001271SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc,
1272 bool HasLo, bool HasHi,
1273 SelectionDAG &DAG) const {
Daniel Sanders308181e2014-06-12 10:44:10 +00001274 // MIPS32r6/MIPS64r6 removed accumulator based multiplies.
Eric Christopher1c29a652014-07-18 22:55:25 +00001275 assert(!Subtarget.hasMips32r6());
Daniel Sanders308181e2014-06-12 10:44:10 +00001276
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001277 EVT Ty = Op.getOperand(0).getValueType();
Andrew Trickef9de2a2013-05-25 02:42:55 +00001278 SDLoc DL(Op);
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001279 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped,
1280 Op.getOperand(0), Op.getOperand(1));
1281 SDValue Lo, Hi;
1282
1283 if (HasLo)
Akira Hatanakad98c99f2013-10-15 01:12:50 +00001284 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001285 if (HasHi)
Akira Hatanakad98c99f2013-10-15 01:12:50 +00001286 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult);
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001287
1288 if (!HasLo || !HasHi)
1289 return HasLo ? Lo : Hi;
1290
1291 SDValue Vals[] = { Lo, Hi };
Craig Topper64941d92014-04-27 19:20:57 +00001292 return DAG.getMergeValues(Vals, DL);
Akira Hatanakabe8612f2013-03-30 01:36:35 +00001293}
1294
Vasileios Kalintiris36901dd2016-03-01 20:25:43 +00001295
Andrew Trickef9de2a2013-05-25 02:42:55 +00001296static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001297 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001298 DAG.getConstant(0, DL, MVT::i32));
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001299 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001300 DAG.getConstant(1, DL, MVT::i32));
Akira Hatanakad98c99f2013-10-15 01:12:50 +00001301 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001302}
1303
Andrew Trickef9de2a2013-05-25 02:42:55 +00001304static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) {
Akira Hatanakad98c99f2013-10-15 01:12:50 +00001305 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op);
1306 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001307 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi);
1308}
1309
1310// This function expands mips intrinsic nodes which have 64-bit input operands
1311// or output values.
1312//
1313// out64 = intrinsic-node in64
1314// =>
1315// lo = copy (extract-element (in64, 0))
1316// hi = copy (extract-element (in64, 1))
1317// mips-specific-node
1318// v0 = copy lo
1319// v1 = copy hi
1320// out64 = merge-values (v0, v1)
1321//
1322static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
Andrew Trickef9de2a2013-05-25 02:42:55 +00001323 SDLoc DL(Op);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001324 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other;
1325 SmallVector<SDValue, 3> Ops;
1326 unsigned OpNo = 0;
1327
1328 // See if Op has a chain input.
1329 if (HasChainIn)
1330 Ops.push_back(Op->getOperand(OpNo++));
1331
1332 // The next operand is the intrinsic opcode.
1333 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant);
1334
1335 // See if the next operand has type i64.
1336 SDValue Opnd = Op->getOperand(++OpNo), In64;
1337
1338 if (Opnd.getValueType() == MVT::i64)
1339 In64 = initAccumulator(Opnd, DL, DAG);
1340 else
1341 Ops.push_back(Opnd);
1342
1343 // Push the remaining operands.
1344 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo)
1345 Ops.push_back(Op->getOperand(OpNo));
1346
1347 // Add In64 to the end of the list.
1348 if (In64.getNode())
1349 Ops.push_back(In64);
1350
1351 // Scan output.
1352 SmallVector<EVT, 2> ResTys;
1353
1354 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end();
1355 I != E; ++I)
1356 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I);
1357
1358 // Create node.
Craig Topper48d114b2014-04-26 18:35:24 +00001359 SDValue Val = DAG.getNode(Opc, DL, ResTys, Ops);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001360 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val;
1361
1362 if (!HasChainIn)
1363 return Out;
1364
1365 assert(Val->getValueType(1) == MVT::Other);
1366 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) };
Craig Topper64941d92014-04-27 19:20:57 +00001367 return DAG.getMergeValues(Vals, DL);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001368}
1369
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00001370// Lower an MSA copy intrinsic into the specified SelectionDAG node
1371static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
1372 SDLoc DL(Op);
1373 SDValue Vec = Op->getOperand(1);
1374 SDValue Idx = Op->getOperand(2);
1375 EVT ResTy = Op->getValueType(0);
1376 EVT EltTy = Vec->getValueType(0).getVectorElementType();
1377
1378 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx,
1379 DAG.getValueType(EltTy));
1380
1381 return Result;
1382}
1383
Daniel Sanders50b80412013-11-15 12:56:49 +00001384static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) {
1385 EVT ResVecTy = Op->getValueType(0);
1386 EVT ViaVecTy = ResVecTy;
1387 SDLoc DL(Op);
Daniel Sanders86d0c8d2013-09-23 14:29:55 +00001388
Daniel Sanders50b80412013-11-15 12:56:49 +00001389 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and
1390 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating
1391 // lanes.
1392 SDValue LaneA;
1393 SDValue LaneB = Op->getOperand(2);
1394
1395 if (ResVecTy == MVT::v2i64) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001396 LaneA = DAG.getConstant(0, DL, MVT::i32);
Daniel Sandersf49dd822013-09-24 13:33:07 +00001397 ViaVecTy = MVT::v4i32;
Daniel Sanders50b80412013-11-15 12:56:49 +00001398 } else
1399 LaneA = LaneB;
Daniel Sanders86d0c8d2013-09-23 14:29:55 +00001400
Daniel Sanders50b80412013-11-15 12:56:49 +00001401 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB,
1402 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB };
Daniel Sandersf49dd822013-09-24 13:33:07 +00001403
Ahmed Bougacha128f8732016-04-26 21:15:30 +00001404 SDValue Result = DAG.getBuildVector(
1405 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +00001406
1407 if (ViaVecTy != ResVecTy)
1408 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result);
Daniel Sandersf49dd822013-09-24 13:33:07 +00001409
1410 return Result;
1411}
1412
Daniel Sanders50b80412013-11-15 12:56:49 +00001413static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001414 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), SDLoc(Op),
1415 Op->getValueType(0));
Daniel Sanders50b80412013-11-15 12:56:49 +00001416}
1417
1418static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue,
1419 bool BigEndian, SelectionDAG &DAG) {
1420 EVT ViaVecTy = VecTy;
1421 SDValue SplatValueA = SplatValue;
1422 SDValue SplatValueB = SplatValue;
1423 SDLoc DL(SplatValue);
1424
1425 if (VecTy == MVT::v2i64) {
1426 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's.
1427 ViaVecTy = MVT::v4i32;
1428
1429 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue);
1430 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001431 DAG.getConstant(32, DL, MVT::i32));
Daniel Sanders50b80412013-11-15 12:56:49 +00001432 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB);
1433 }
1434
1435 // We currently hold the parts in little endian order. Swap them if
1436 // necessary.
1437 if (BigEndian)
1438 std::swap(SplatValueA, SplatValueB);
1439
1440 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1441 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1442 SplatValueA, SplatValueB, SplatValueA, SplatValueB,
1443 SplatValueA, SplatValueB, SplatValueA, SplatValueB };
1444
Ahmed Bougacha128f8732016-04-26 21:15:30 +00001445 SDValue Result = DAG.getBuildVector(
1446 ViaVecTy, DL, makeArrayRef(Ops, ViaVecTy.getVectorNumElements()));
Daniel Sanders50b80412013-11-15 12:56:49 +00001447
1448 if (VecTy != ViaVecTy)
1449 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result);
1450
1451 return Result;
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001452}
1453
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001454static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG,
1455 unsigned Opc, SDValue Imm,
1456 bool BigEndian) {
1457 EVT VecTy = Op->getValueType(0);
1458 SDValue Exp2Imm;
1459 SDLoc DL(Op);
1460
Daniel Sanders50b80412013-11-15 12:56:49 +00001461 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it
1462 // here for now.
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001463 if (VecTy == MVT::v2i64) {
1464 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1465 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue();
1466
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001467 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), DL,
1468 MVT::i32);
1469 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), DL, MVT::i32);
Daniel Sanders50b80412013-11-15 12:56:49 +00001470
1471 if (BigEndian)
1472 std::swap(BitImmLoOp, BitImmHiOp);
1473
Ahmed Bougacha128f8732016-04-26 21:15:30 +00001474 Exp2Imm = DAG.getNode(
1475 ISD::BITCAST, DL, MVT::v2i64,
1476 DAG.getBuildVector(MVT::v4i32, DL,
1477 {BitImmLoOp, BitImmHiOp, BitImmLoOp, BitImmHiOp}));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001478 }
1479 }
1480
Craig Topper062a2ba2014-04-25 05:30:21 +00001481 if (!Exp2Imm.getNode()) {
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001482 // We couldnt constant fold, do a vector shift instead
Daniel Sanders50b80412013-11-15 12:56:49 +00001483
1484 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since
1485 // only values 0-63 are valid.
1486 if (VecTy == MVT::v2i64)
1487 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1488
1489 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
1490
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001491 Exp2Imm = DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, DL, VecTy),
1492 Exp2Imm);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001493 }
1494
1495 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm);
1496}
1497
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001498static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) {
1499 EVT ResTy = Op->getValueType(0);
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001500 SDLoc DL(Op);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001501 SDValue One = DAG.getConstant(1, DL, ResTy);
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001502 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2));
1503
Daniel Sanders71ce0ca2013-11-15 16:02:04 +00001504 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1),
1505 DAG.getNOT(DL, Bit, ResTy));
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001506}
1507
1508static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) {
1509 SDLoc DL(Op);
1510 EVT ResTy = Op->getValueType(0);
Daniel Sanders50b80412013-11-15 12:56:49 +00001511 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1)
1512 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue();
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001513 SDValue BitMask = DAG.getConstant(~BitImm, DL, ResTy);
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001514
1515 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask);
1516}
1517
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001518SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
1519 SelectionDAG &DAG) const {
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001520 SDLoc DL(Op);
1521
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00001522 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) {
1523 default:
1524 return SDValue();
1525 case Intrinsic::mips_shilo:
1526 return lowerDSPIntr(Op, DAG, MipsISD::SHILO);
1527 case Intrinsic::mips_dpau_h_qbl:
1528 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL);
1529 case Intrinsic::mips_dpau_h_qbr:
1530 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR);
1531 case Intrinsic::mips_dpsu_h_qbl:
1532 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL);
1533 case Intrinsic::mips_dpsu_h_qbr:
1534 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR);
1535 case Intrinsic::mips_dpa_w_ph:
1536 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH);
1537 case Intrinsic::mips_dps_w_ph:
1538 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH);
1539 case Intrinsic::mips_dpax_w_ph:
1540 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH);
1541 case Intrinsic::mips_dpsx_w_ph:
1542 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH);
1543 case Intrinsic::mips_mulsa_w_ph:
1544 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH);
1545 case Intrinsic::mips_mult:
1546 return lowerDSPIntr(Op, DAG, MipsISD::Mult);
1547 case Intrinsic::mips_multu:
1548 return lowerDSPIntr(Op, DAG, MipsISD::Multu);
1549 case Intrinsic::mips_madd:
1550 return lowerDSPIntr(Op, DAG, MipsISD::MAdd);
1551 case Intrinsic::mips_maddu:
1552 return lowerDSPIntr(Op, DAG, MipsISD::MAddu);
1553 case Intrinsic::mips_msub:
1554 return lowerDSPIntr(Op, DAG, MipsISD::MSub);
1555 case Intrinsic::mips_msubu:
1556 return lowerDSPIntr(Op, DAG, MipsISD::MSubu);
Daniel Sandersfa5ab1c2013-09-11 10:28:16 +00001557 case Intrinsic::mips_addv_b:
1558 case Intrinsic::mips_addv_h:
1559 case Intrinsic::mips_addv_w:
1560 case Intrinsic::mips_addv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001561 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1562 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +00001563 case Intrinsic::mips_addvi_b:
1564 case Intrinsic::mips_addvi_h:
1565 case Intrinsic::mips_addvi_w:
1566 case Intrinsic::mips_addvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001567 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1),
1568 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders8ca81e42013-09-23 12:57:42 +00001569 case Intrinsic::mips_and_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001570 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1571 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +00001572 case Intrinsic::mips_andi_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001573 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1),
1574 lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3f6eb542013-11-12 10:45:18 +00001575 case Intrinsic::mips_bclr_b:
1576 case Intrinsic::mips_bclr_h:
1577 case Intrinsic::mips_bclr_w:
1578 case Intrinsic::mips_bclr_d:
1579 return lowerMSABitClear(Op, DAG);
1580 case Intrinsic::mips_bclri_b:
1581 case Intrinsic::mips_bclri_h:
1582 case Intrinsic::mips_bclri_w:
1583 case Intrinsic::mips_bclri_d:
1584 return lowerMSABitClearImm(Op, DAG);
Daniel Sandersd74b1302013-10-30 14:45:14 +00001585 case Intrinsic::mips_binsli_b:
1586 case Intrinsic::mips_binsli_h:
1587 case Intrinsic::mips_binsli_w:
1588 case Intrinsic::mips_binsli_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +00001589 // binsli_x(IfClear, IfSet, nbits) -> (vselect LBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +00001590 EVT VecTy = Op->getValueType(0);
1591 EVT EltTy = VecTy.getVectorElementType();
1592 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(),
1593 Op->getConstantOperandVal(3));
1594 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001595 DAG.getConstant(Mask, DL, VecTy, true),
1596 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +00001597 }
1598 case Intrinsic::mips_binsri_b:
1599 case Intrinsic::mips_binsri_h:
1600 case Intrinsic::mips_binsri_w:
1601 case Intrinsic::mips_binsri_d: {
Daniel Sandersdf2215452014-03-12 11:54:00 +00001602 // binsri_x(IfClear, IfSet, nbits) -> (vselect RBitsMask, IfSet, IfClear)
Daniel Sandersd74b1302013-10-30 14:45:14 +00001603 EVT VecTy = Op->getValueType(0);
1604 EVT EltTy = VecTy.getVectorElementType();
1605 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(),
1606 Op->getConstantOperandVal(3));
1607 return DAG.getNode(ISD::VSELECT, DL, VecTy,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001608 DAG.getConstant(Mask, DL, VecTy, true),
1609 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersd74b1302013-10-30 14:45:14 +00001610 }
Daniel Sandersab94b532013-10-30 15:20:38 +00001611 case Intrinsic::mips_bmnz_v:
1612 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1613 Op->getOperand(2), Op->getOperand(1));
1614 case Intrinsic::mips_bmnzi_b:
1615 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1616 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2),
1617 Op->getOperand(1));
1618 case Intrinsic::mips_bmz_v:
1619 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3),
1620 Op->getOperand(1), Op->getOperand(2));
1621 case Intrinsic::mips_bmzi_b:
1622 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
1623 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1),
1624 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001625 case Intrinsic::mips_bneg_b:
1626 case Intrinsic::mips_bneg_h:
1627 case Intrinsic::mips_bneg_w:
1628 case Intrinsic::mips_bneg_d: {
1629 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001630 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001631
1632 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1),
1633 DAG.getNode(ISD::SHL, DL, VecTy, One,
1634 Op->getOperand(2)));
1635 }
1636 case Intrinsic::mips_bnegi_b:
1637 case Intrinsic::mips_bnegi_h:
1638 case Intrinsic::mips_bnegi_w:
1639 case Intrinsic::mips_bnegi_d:
1640 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +00001641 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +00001642 case Intrinsic::mips_bnz_b:
1643 case Intrinsic::mips_bnz_h:
1644 case Intrinsic::mips_bnz_w:
1645 case Intrinsic::mips_bnz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001646 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0),
1647 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +00001648 case Intrinsic::mips_bnz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001649 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0),
1650 Op->getOperand(1));
Daniel Sanderse1d24352013-09-24 12:04:44 +00001651 case Intrinsic::mips_bsel_v:
Daniel Sandersdf2215452014-03-12 11:54:00 +00001652 // bsel_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001653 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +00001654 Op->getOperand(1), Op->getOperand(3),
1655 Op->getOperand(2));
Daniel Sanderse1d24352013-09-24 12:04:44 +00001656 case Intrinsic::mips_bseli_b:
Daniel Sandersdf2215452014-03-12 11:54:00 +00001657 // bseli_v(Mask, IfClear, IfSet) -> (vselect Mask, IfSet, IfClear)
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001658 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0),
Daniel Sandersdf2215452014-03-12 11:54:00 +00001659 Op->getOperand(1), lowerMSASplatImm(Op, 3, DAG),
1660 Op->getOperand(2));
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001661 case Intrinsic::mips_bset_b:
1662 case Intrinsic::mips_bset_h:
1663 case Intrinsic::mips_bset_w:
1664 case Intrinsic::mips_bset_d: {
1665 EVT VecTy = Op->getValueType(0);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001666 SDValue One = DAG.getConstant(1, DL, VecTy);
Daniel Sandersa5bc99f2013-11-12 10:31:49 +00001667
1668 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1),
1669 DAG.getNode(ISD::SHL, DL, VecTy, One,
1670 Op->getOperand(2)));
1671 }
1672 case Intrinsic::mips_bseti_b:
1673 case Intrinsic::mips_bseti_h:
1674 case Intrinsic::mips_bseti_w:
1675 case Intrinsic::mips_bseti_d:
1676 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2),
Eric Christopher1c29a652014-07-18 22:55:25 +00001677 !Subtarget.isLittle());
Daniel Sandersce09d072013-08-28 12:14:50 +00001678 case Intrinsic::mips_bz_b:
1679 case Intrinsic::mips_bz_h:
1680 case Intrinsic::mips_bz_w:
1681 case Intrinsic::mips_bz_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001682 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0),
1683 Op->getOperand(1));
Daniel Sandersce09d072013-08-28 12:14:50 +00001684 case Intrinsic::mips_bz_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001685 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0),
1686 Op->getOperand(1));
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001687 case Intrinsic::mips_ceq_b:
1688 case Intrinsic::mips_ceq_h:
1689 case Intrinsic::mips_ceq_w:
1690 case Intrinsic::mips_ceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001691 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001692 Op->getOperand(2), ISD::SETEQ);
1693 case Intrinsic::mips_ceqi_b:
1694 case Intrinsic::mips_ceqi_h:
1695 case Intrinsic::mips_ceqi_w:
1696 case Intrinsic::mips_ceqi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001697 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001698 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ);
1699 case Intrinsic::mips_cle_s_b:
1700 case Intrinsic::mips_cle_s_h:
1701 case Intrinsic::mips_cle_s_w:
1702 case Intrinsic::mips_cle_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001703 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001704 Op->getOperand(2), ISD::SETLE);
1705 case Intrinsic::mips_clei_s_b:
1706 case Intrinsic::mips_clei_s_h:
1707 case Intrinsic::mips_clei_s_w:
1708 case Intrinsic::mips_clei_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001709 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001710 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE);
1711 case Intrinsic::mips_cle_u_b:
1712 case Intrinsic::mips_cle_u_h:
1713 case Intrinsic::mips_cle_u_w:
1714 case Intrinsic::mips_cle_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001715 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001716 Op->getOperand(2), ISD::SETULE);
1717 case Intrinsic::mips_clei_u_b:
1718 case Intrinsic::mips_clei_u_h:
1719 case Intrinsic::mips_clei_u_w:
1720 case Intrinsic::mips_clei_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001721 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001722 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE);
1723 case Intrinsic::mips_clt_s_b:
1724 case Intrinsic::mips_clt_s_h:
1725 case Intrinsic::mips_clt_s_w:
1726 case Intrinsic::mips_clt_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001727 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001728 Op->getOperand(2), ISD::SETLT);
1729 case Intrinsic::mips_clti_s_b:
1730 case Intrinsic::mips_clti_s_h:
1731 case Intrinsic::mips_clti_s_w:
1732 case Intrinsic::mips_clti_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001733 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001734 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT);
1735 case Intrinsic::mips_clt_u_b:
1736 case Intrinsic::mips_clt_u_h:
1737 case Intrinsic::mips_clt_u_w:
1738 case Intrinsic::mips_clt_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001739 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001740 Op->getOperand(2), ISD::SETULT);
1741 case Intrinsic::mips_clti_u_b:
1742 case Intrinsic::mips_clti_u_h:
1743 case Intrinsic::mips_clti_u_w:
1744 case Intrinsic::mips_clti_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001745 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001746 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT);
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00001747 case Intrinsic::mips_copy_s_b:
1748 case Intrinsic::mips_copy_s_h:
1749 case Intrinsic::mips_copy_s_w:
1750 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +00001751 case Intrinsic::mips_copy_s_d:
Eric Christopher1c29a652014-07-18 22:55:25 +00001752 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +00001753 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64.
1754 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT);
1755 else {
1756 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1757 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1758 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1759 Op->getValueType(0), Op->getOperand(1),
1760 Op->getOperand(2));
1761 }
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00001762 case Intrinsic::mips_copy_u_b:
1763 case Intrinsic::mips_copy_u_h:
1764 case Intrinsic::mips_copy_u_w:
1765 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
Daniel Sanders7f3d9462013-09-27 13:04:21 +00001766 case Intrinsic::mips_copy_u_d:
Eric Christopher1c29a652014-07-18 22:55:25 +00001767 if (Subtarget.hasMips64())
Matheus Almeida74070322014-01-29 14:05:28 +00001768 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64.
1769 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT);
1770 else {
1771 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type
1772 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out.
1773 // Note: When i64 is illegal, this results in copy_s.w instructions
1774 // instead of copy_u.w instructions. This makes no difference to the
1775 // behaviour since i64 is only illegal when the register file is 32-bit.
1776 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op),
1777 Op->getValueType(0), Op->getOperand(1),
1778 Op->getOperand(2));
1779 }
Daniel Sanders607952b2013-09-11 10:38:58 +00001780 case Intrinsic::mips_div_s_b:
1781 case Intrinsic::mips_div_s_h:
1782 case Intrinsic::mips_div_s_w:
1783 case Intrinsic::mips_div_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001784 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1),
1785 Op->getOperand(2));
Daniel Sanders607952b2013-09-11 10:38:58 +00001786 case Intrinsic::mips_div_u_b:
1787 case Intrinsic::mips_div_u_h:
1788 case Intrinsic::mips_div_u_w:
1789 case Intrinsic::mips_div_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001790 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1),
1791 Op->getOperand(2));
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001792 case Intrinsic::mips_fadd_w:
Sanjay Patela2607012015-09-16 16:31:21 +00001793 case Intrinsic::mips_fadd_d: {
1794 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001795 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1),
1796 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +00001797 }
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001798 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away
1799 case Intrinsic::mips_fceq_w:
1800 case Intrinsic::mips_fceq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001801 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001802 Op->getOperand(2), ISD::SETOEQ);
1803 case Intrinsic::mips_fcle_w:
1804 case Intrinsic::mips_fcle_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001805 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001806 Op->getOperand(2), ISD::SETOLE);
1807 case Intrinsic::mips_fclt_w:
1808 case Intrinsic::mips_fclt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001809 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001810 Op->getOperand(2), ISD::SETOLT);
1811 case Intrinsic::mips_fcne_w:
1812 case Intrinsic::mips_fcne_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001813 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001814 Op->getOperand(2), ISD::SETONE);
1815 case Intrinsic::mips_fcor_w:
1816 case Intrinsic::mips_fcor_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001817 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001818 Op->getOperand(2), ISD::SETO);
1819 case Intrinsic::mips_fcueq_w:
1820 case Intrinsic::mips_fcueq_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001821 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001822 Op->getOperand(2), ISD::SETUEQ);
1823 case Intrinsic::mips_fcule_w:
1824 case Intrinsic::mips_fcule_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001825 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001826 Op->getOperand(2), ISD::SETULE);
1827 case Intrinsic::mips_fcult_w:
1828 case Intrinsic::mips_fcult_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001829 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001830 Op->getOperand(2), ISD::SETULT);
1831 case Intrinsic::mips_fcun_w:
1832 case Intrinsic::mips_fcun_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001833 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001834 Op->getOperand(2), ISD::SETUO);
1835 case Intrinsic::mips_fcune_w:
1836 case Intrinsic::mips_fcune_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001837 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1),
Daniel Sandersfd538dc2013-09-24 10:46:19 +00001838 Op->getOperand(2), ISD::SETUNE);
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001839 case Intrinsic::mips_fdiv_w:
Sanjay Patela2607012015-09-16 16:31:21 +00001840 case Intrinsic::mips_fdiv_d: {
1841 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001842 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1),
1843 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +00001844 }
Daniel Sanders015972b2013-10-11 10:00:06 +00001845 case Intrinsic::mips_ffint_u_w:
1846 case Intrinsic::mips_ffint_u_d:
1847 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0),
1848 Op->getOperand(1));
1849 case Intrinsic::mips_ffint_s_w:
1850 case Intrinsic::mips_ffint_s_d:
1851 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0),
1852 Op->getOperand(1));
Daniel Sanders7a289d02013-09-23 12:02:46 +00001853 case Intrinsic::mips_fill_b:
1854 case Intrinsic::mips_fill_h:
Daniel Sandersc72593e2013-09-27 13:20:41 +00001855 case Intrinsic::mips_fill_w:
1856 case Intrinsic::mips_fill_d: {
Daniel Sandersf49dd822013-09-24 13:33:07 +00001857 EVT ResTy = Op->getValueType(0);
Benjamin Kramer6cd780f2015-02-17 15:29:18 +00001858 SmallVector<SDValue, 16> Ops(ResTy.getVectorNumElements(),
1859 Op->getOperand(1));
Daniel Sandersf49dd822013-09-24 13:33:07 +00001860
Daniel Sandersc72593e2013-09-27 13:20:41 +00001861 // If ResTy is v2i64 then the type legalizer will break this node down into
1862 // an equivalent v4i32.
Ahmed Bougacha128f8732016-04-26 21:15:30 +00001863 return DAG.getBuildVector(ResTy, DL, Ops);
Daniel Sandersf49dd822013-09-24 13:33:07 +00001864 }
Daniel Sandersa9521602013-10-23 10:36:52 +00001865 case Intrinsic::mips_fexp2_w:
1866 case Intrinsic::mips_fexp2_d: {
Sanjay Patela2607012015-09-16 16:31:21 +00001867 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sandersa9521602013-10-23 10:36:52 +00001868 EVT ResTy = Op->getValueType(0);
1869 return DAG.getNode(
1870 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1),
1871 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2)));
1872 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001873 case Intrinsic::mips_flog2_w:
1874 case Intrinsic::mips_flog2_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001875 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersd7103f32013-10-11 10:14:25 +00001876 case Intrinsic::mips_fmadd_w:
1877 case Intrinsic::mips_fmadd_d:
1878 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0),
1879 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001880 case Intrinsic::mips_fmul_w:
Sanjay Patela2607012015-09-16 16:31:21 +00001881 case Intrinsic::mips_fmul_d: {
1882 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001883 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1),
1884 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +00001885 }
Daniel Sanderse67bd872013-10-11 10:27:32 +00001886 case Intrinsic::mips_fmsub_w:
1887 case Intrinsic::mips_fmsub_d: {
Sanjay Patela2607012015-09-16 16:31:21 +00001888 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanderse67bd872013-10-11 10:27:32 +00001889 EVT ResTy = Op->getValueType(0);
1890 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1),
1891 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy,
1892 Op->getOperand(2), Op->getOperand(3)));
1893 }
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001894 case Intrinsic::mips_frint_w:
1895 case Intrinsic::mips_frint_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001896 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001897 case Intrinsic::mips_fsqrt_w:
1898 case Intrinsic::mips_fsqrt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001899 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf5bd9372013-09-11 10:51:30 +00001900 case Intrinsic::mips_fsub_w:
Sanjay Patela2607012015-09-16 16:31:21 +00001901 case Intrinsic::mips_fsub_d: {
1902 // TODO: If intrinsics have fast-math-flags, propagate them.
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001903 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1),
1904 Op->getOperand(2));
Sanjay Patela2607012015-09-16 16:31:21 +00001905 }
Daniel Sanders015972b2013-10-11 10:00:06 +00001906 case Intrinsic::mips_ftrunc_u_w:
1907 case Intrinsic::mips_ftrunc_u_d:
1908 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0),
1909 Op->getOperand(1));
1910 case Intrinsic::mips_ftrunc_s_w:
1911 case Intrinsic::mips_ftrunc_s_d:
1912 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0),
1913 Op->getOperand(1));
Daniel Sanders2ed228b2013-09-24 14:36:12 +00001914 case Intrinsic::mips_ilvev_b:
1915 case Intrinsic::mips_ilvev_h:
1916 case Intrinsic::mips_ilvev_w:
1917 case Intrinsic::mips_ilvev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001918 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +00001919 Op->getOperand(1), Op->getOperand(2));
1920 case Intrinsic::mips_ilvl_b:
1921 case Intrinsic::mips_ilvl_h:
1922 case Intrinsic::mips_ilvl_w:
1923 case Intrinsic::mips_ilvl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001924 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +00001925 Op->getOperand(1), Op->getOperand(2));
1926 case Intrinsic::mips_ilvod_b:
1927 case Intrinsic::mips_ilvod_h:
1928 case Intrinsic::mips_ilvod_w:
1929 case Intrinsic::mips_ilvod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001930 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +00001931 Op->getOperand(1), Op->getOperand(2));
1932 case Intrinsic::mips_ilvr_b:
1933 case Intrinsic::mips_ilvr_h:
1934 case Intrinsic::mips_ilvr_w:
1935 case Intrinsic::mips_ilvr_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001936 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0),
Daniel Sanders2ed228b2013-09-24 14:36:12 +00001937 Op->getOperand(1), Op->getOperand(2));
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00001938 case Intrinsic::mips_insert_b:
1939 case Intrinsic::mips_insert_h:
1940 case Intrinsic::mips_insert_w:
Daniel Sanders6098b332013-09-27 13:36:54 +00001941 case Intrinsic::mips_insert_d:
1942 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0),
1943 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2));
Daniel Sandersb50ccf82014-04-01 10:35:28 +00001944 case Intrinsic::mips_insve_b:
1945 case Intrinsic::mips_insve_h:
1946 case Intrinsic::mips_insve_w:
1947 case Intrinsic::mips_insve_d:
1948 return DAG.getNode(MipsISD::INSVE, DL, Op->getValueType(0),
1949 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00001950 DAG.getConstant(0, DL, MVT::i32));
Daniel Sanders7a289d02013-09-23 12:02:46 +00001951 case Intrinsic::mips_ldi_b:
1952 case Intrinsic::mips_ldi_h:
1953 case Intrinsic::mips_ldi_w:
1954 case Intrinsic::mips_ldi_d:
Daniel Sandersf49dd822013-09-24 13:33:07 +00001955 return lowerMSASplatImm(Op, 1, DAG);
Matheus Almeida4b27eb52014-02-10 12:05:17 +00001956 case Intrinsic::mips_lsa:
1957 case Intrinsic::mips_dlsa: {
Daniel Sandersa4eaf592013-10-17 13:38:20 +00001958 EVT ResTy = Op->getValueType(0);
1959 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1960 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy,
1961 Op->getOperand(2), Op->getOperand(3)));
1962 }
Daniel Sanders50e5ed32013-10-11 10:50:42 +00001963 case Intrinsic::mips_maddv_b:
1964 case Intrinsic::mips_maddv_h:
1965 case Intrinsic::mips_maddv_w:
1966 case Intrinsic::mips_maddv_d: {
1967 EVT ResTy = Op->getValueType(0);
1968 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1),
1969 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
1970 Op->getOperand(2), Op->getOperand(3)));
1971 }
Daniel Sanders3ce56622013-09-24 12:18:31 +00001972 case Intrinsic::mips_max_s_b:
1973 case Intrinsic::mips_max_s_h:
1974 case Intrinsic::mips_max_s_w:
1975 case Intrinsic::mips_max_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001976 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1977 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +00001978 case Intrinsic::mips_max_u_b:
1979 case Intrinsic::mips_max_u_h:
1980 case Intrinsic::mips_max_u_w:
1981 case Intrinsic::mips_max_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001982 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1983 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +00001984 case Intrinsic::mips_maxi_s_b:
1985 case Intrinsic::mips_maxi_s_h:
1986 case Intrinsic::mips_maxi_s_w:
1987 case Intrinsic::mips_maxi_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001988 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0),
1989 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +00001990 case Intrinsic::mips_maxi_u_b:
1991 case Intrinsic::mips_maxi_u_h:
1992 case Intrinsic::mips_maxi_u_w:
1993 case Intrinsic::mips_maxi_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00001994 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0),
1995 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +00001996 case Intrinsic::mips_min_s_b:
1997 case Intrinsic::mips_min_s_h:
1998 case Intrinsic::mips_min_s_w:
1999 case Intrinsic::mips_min_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002000 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2001 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +00002002 case Intrinsic::mips_min_u_b:
2003 case Intrinsic::mips_min_u_h:
2004 case Intrinsic::mips_min_u_w:
2005 case Intrinsic::mips_min_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002006 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2007 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders3ce56622013-09-24 12:18:31 +00002008 case Intrinsic::mips_mini_s_b:
2009 case Intrinsic::mips_mini_s_h:
2010 case Intrinsic::mips_mini_s_w:
2011 case Intrinsic::mips_mini_s_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002012 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0),
2013 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders3ce56622013-09-24 12:18:31 +00002014 case Intrinsic::mips_mini_u_b:
2015 case Intrinsic::mips_mini_u_h:
2016 case Intrinsic::mips_mini_u_w:
2017 case Intrinsic::mips_mini_u_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002018 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0),
2019 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanders0210dd42013-10-01 10:22:35 +00002020 case Intrinsic::mips_mod_s_b:
2021 case Intrinsic::mips_mod_s_h:
2022 case Intrinsic::mips_mod_s_w:
2023 case Intrinsic::mips_mod_s_d:
2024 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1),
2025 Op->getOperand(2));
2026 case Intrinsic::mips_mod_u_b:
2027 case Intrinsic::mips_mod_u_h:
2028 case Intrinsic::mips_mod_u_w:
2029 case Intrinsic::mips_mod_u_d:
2030 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1),
2031 Op->getOperand(2));
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002032 case Intrinsic::mips_mulv_b:
2033 case Intrinsic::mips_mulv_h:
2034 case Intrinsic::mips_mulv_w:
2035 case Intrinsic::mips_mulv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002036 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1),
2037 Op->getOperand(2));
Daniel Sanders50e5ed32013-10-11 10:50:42 +00002038 case Intrinsic::mips_msubv_b:
2039 case Intrinsic::mips_msubv_h:
2040 case Intrinsic::mips_msubv_w:
2041 case Intrinsic::mips_msubv_d: {
2042 EVT ResTy = Op->getValueType(0);
2043 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1),
2044 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy,
2045 Op->getOperand(2), Op->getOperand(3)));
2046 }
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002047 case Intrinsic::mips_nlzc_b:
2048 case Intrinsic::mips_nlzc_h:
2049 case Intrinsic::mips_nlzc_w:
2050 case Intrinsic::mips_nlzc_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002051 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sandersf7456c72013-09-23 13:22:24 +00002052 case Intrinsic::mips_nor_v: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002053 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2054 Op->getOperand(1), Op->getOperand(2));
2055 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersf7456c72013-09-23 13:22:24 +00002056 }
Daniel Sandersbfc39ce2013-09-24 12:32:47 +00002057 case Intrinsic::mips_nori_b: {
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002058 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2059 Op->getOperand(1),
2060 lowerMSASplatImm(Op, 2, DAG));
2061 return DAG.getNOT(DL, Res, Res->getValueType(0));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +00002062 }
Daniel Sanders8ca81e42013-09-23 12:57:42 +00002063 case Intrinsic::mips_or_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002064 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1),
2065 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +00002066 case Intrinsic::mips_ori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002067 return DAG.getNode(ISD::OR, DL, Op->getValueType(0),
2068 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002069 case Intrinsic::mips_pckev_b:
2070 case Intrinsic::mips_pckev_h:
2071 case Intrinsic::mips_pckev_w:
2072 case Intrinsic::mips_pckev_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002073 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002074 Op->getOperand(1), Op->getOperand(2));
2075 case Intrinsic::mips_pckod_b:
2076 case Intrinsic::mips_pckod_h:
2077 case Intrinsic::mips_pckod_w:
2078 case Intrinsic::mips_pckod_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002079 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0),
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002080 Op->getOperand(1), Op->getOperand(2));
Daniel Sanders766cb692013-09-23 13:40:21 +00002081 case Intrinsic::mips_pcnt_b:
2082 case Intrinsic::mips_pcnt_h:
2083 case Intrinsic::mips_pcnt_w:
2084 case Intrinsic::mips_pcnt_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002085 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1));
Daniel Sanders26307182013-09-24 14:20:00 +00002086 case Intrinsic::mips_shf_b:
2087 case Intrinsic::mips_shf_h:
2088 case Intrinsic::mips_shf_w:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002089 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0),
Daniel Sanders26307182013-09-24 14:20:00 +00002090 Op->getOperand(2), Op->getOperand(1));
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002091 case Intrinsic::mips_sll_b:
2092 case Intrinsic::mips_sll_h:
2093 case Intrinsic::mips_sll_w:
2094 case Intrinsic::mips_sll_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002095 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1),
2096 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +00002097 case Intrinsic::mips_slli_b:
2098 case Intrinsic::mips_slli_h:
2099 case Intrinsic::mips_slli_w:
2100 case Intrinsic::mips_slli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002101 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0),
2102 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse7ef0c82013-10-30 13:07:44 +00002103 case Intrinsic::mips_splat_b:
2104 case Intrinsic::mips_splat_h:
2105 case Intrinsic::mips_splat_w:
2106 case Intrinsic::mips_splat_d:
2107 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle
2108 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because
2109 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32.
2110 // Instead we lower to MipsISD::VSHF and match from there.
2111 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanders50b80412013-11-15 12:56:49 +00002112 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1),
Daniel Sanderse7ef0c82013-10-30 13:07:44 +00002113 Op->getOperand(1));
Daniel Sanders7e51fe12013-09-27 11:48:57 +00002114 case Intrinsic::mips_splati_b:
2115 case Intrinsic::mips_splati_h:
2116 case Intrinsic::mips_splati_w:
2117 case Intrinsic::mips_splati_d:
2118 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
2119 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1),
2120 Op->getOperand(1));
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002121 case Intrinsic::mips_sra_b:
2122 case Intrinsic::mips_sra_h:
2123 case Intrinsic::mips_sra_w:
2124 case Intrinsic::mips_sra_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002125 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1),
2126 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +00002127 case Intrinsic::mips_srai_b:
2128 case Intrinsic::mips_srai_h:
2129 case Intrinsic::mips_srai_w:
2130 case Intrinsic::mips_srai_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002131 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0),
2132 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002133 case Intrinsic::mips_srl_b:
2134 case Intrinsic::mips_srl_h:
2135 case Intrinsic::mips_srl_w:
2136 case Intrinsic::mips_srl_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002137 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1),
2138 Op->getOperand(2));
Daniel Sanderscba19222013-09-24 10:28:18 +00002139 case Intrinsic::mips_srli_b:
2140 case Intrinsic::mips_srli_h:
2141 case Intrinsic::mips_srli_w:
2142 case Intrinsic::mips_srli_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002143 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0),
2144 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sandersfbcb5822013-09-11 11:58:30 +00002145 case Intrinsic::mips_subv_b:
2146 case Intrinsic::mips_subv_h:
2147 case Intrinsic::mips_subv_w:
2148 case Intrinsic::mips_subv_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002149 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1),
2150 Op->getOperand(2));
Daniel Sanders86d0c8d2013-09-23 14:29:55 +00002151 case Intrinsic::mips_subvi_b:
2152 case Intrinsic::mips_subvi_h:
2153 case Intrinsic::mips_subvi_w:
2154 case Intrinsic::mips_subvi_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002155 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0),
2156 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Daniel Sanderse5087042013-09-24 14:02:15 +00002157 case Intrinsic::mips_vshf_b:
2158 case Intrinsic::mips_vshf_h:
2159 case Intrinsic::mips_vshf_w:
2160 case Intrinsic::mips_vshf_d:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002161 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0),
Daniel Sanderse5087042013-09-24 14:02:15 +00002162 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3));
Daniel Sanders8ca81e42013-09-23 12:57:42 +00002163 case Intrinsic::mips_xor_v:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002164 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1),
2165 Op->getOperand(2));
Daniel Sandersbfc39ce2013-09-24 12:32:47 +00002166 case Intrinsic::mips_xori_b:
Daniel Sanders84e7caf2013-09-27 10:25:41 +00002167 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0),
2168 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG));
Marcin Koscielnicki7efdca52016-04-27 17:21:49 +00002169 case Intrinsic::thread_pointer: {
2170 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2171 return DAG.getNode(MipsISD::ThreadPointer, DL, PtrVT);
2172 }
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00002173 }
2174}
2175
Daniel Sanderse6ed5b72013-08-28 12:04:29 +00002176static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2177 SDLoc DL(Op);
2178 SDValue ChainIn = Op->getOperand(0);
2179 SDValue Address = Op->getOperand(2);
2180 SDValue Offset = Op->getOperand(3);
2181 EVT ResTy = Op->getValueType(0);
2182 EVT PtrTy = Address->getValueType(0);
2183
2184 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2185
2186 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false,
2187 false, false, 16);
2188}
2189
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00002190SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
2191 SelectionDAG &DAG) const {
Daniel Sanderse6ed5b72013-08-28 12:04:29 +00002192 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2193 switch (Intr) {
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00002194 default:
2195 return SDValue();
2196 case Intrinsic::mips_extp:
2197 return lowerDSPIntr(Op, DAG, MipsISD::EXTP);
2198 case Intrinsic::mips_extpdp:
2199 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP);
2200 case Intrinsic::mips_extr_w:
2201 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W);
2202 case Intrinsic::mips_extr_r_w:
2203 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W);
2204 case Intrinsic::mips_extr_rs_w:
2205 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W);
2206 case Intrinsic::mips_extr_s_h:
2207 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H);
2208 case Intrinsic::mips_mthlip:
2209 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP);
2210 case Intrinsic::mips_mulsaq_s_w_ph:
2211 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH);
2212 case Intrinsic::mips_maq_s_w_phl:
2213 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL);
2214 case Intrinsic::mips_maq_s_w_phr:
2215 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR);
2216 case Intrinsic::mips_maq_sa_w_phl:
2217 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL);
2218 case Intrinsic::mips_maq_sa_w_phr:
2219 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR);
2220 case Intrinsic::mips_dpaq_s_w_ph:
2221 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH);
2222 case Intrinsic::mips_dpsq_s_w_ph:
2223 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH);
2224 case Intrinsic::mips_dpaq_sa_l_w:
2225 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W);
2226 case Intrinsic::mips_dpsq_sa_l_w:
2227 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W);
2228 case Intrinsic::mips_dpaqx_s_w_ph:
2229 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH);
2230 case Intrinsic::mips_dpaqx_sa_w_ph:
2231 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH);
2232 case Intrinsic::mips_dpsqx_s_w_ph:
2233 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH);
2234 case Intrinsic::mips_dpsqx_sa_w_ph:
2235 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH);
Daniel Sanderse6ed5b72013-08-28 12:04:29 +00002236 case Intrinsic::mips_ld_b:
2237 case Intrinsic::mips_ld_h:
2238 case Intrinsic::mips_ld_w:
2239 case Intrinsic::mips_ld_d:
Daniel Sanderse6ed5b72013-08-28 12:04:29 +00002240 return lowerMSALoadIntr(Op, DAG, Intr);
2241 }
2242}
2243
2244static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) {
2245 SDLoc DL(Op);
2246 SDValue ChainIn = Op->getOperand(0);
2247 SDValue Value = Op->getOperand(2);
2248 SDValue Address = Op->getOperand(3);
2249 SDValue Offset = Op->getOperand(4);
2250 EVT PtrTy = Address->getValueType(0);
2251
2252 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset);
2253
2254 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false,
2255 false, 16);
2256}
2257
2258SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op,
2259 SelectionDAG &DAG) const {
2260 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue();
2261 switch (Intr) {
2262 default:
2263 return SDValue();
2264 case Intrinsic::mips_st_b:
2265 case Intrinsic::mips_st_h:
2266 case Intrinsic::mips_st_w:
2267 case Intrinsic::mips_st_d:
Daniel Sandersce09d072013-08-28 12:14:50 +00002268 return lowerMSAStoreIntr(Op, DAG, Intr);
Akira Hatanakaa6bbde52013-04-13 02:13:30 +00002269 }
2270}
2271
Daniel Sanders7a289d02013-09-23 12:02:46 +00002272/// \brief Check if the given BuildVectorSDNode is a splat.
2273/// This method currently relies on DAG nodes being reused when equivalent,
2274/// so it's possible for this to return false even when isConstantSplat returns
2275/// true.
2276static bool isSplatVector(const BuildVectorSDNode *N) {
Daniel Sanders7a289d02013-09-23 12:02:46 +00002277 unsigned int nOps = N->getNumOperands();
Daniel Sandersab94b532013-10-30 15:20:38 +00002278 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector");
Daniel Sanders7a289d02013-09-23 12:02:46 +00002279
2280 SDValue Operand0 = N->getOperand(0);
2281
2282 for (unsigned int i = 1; i < nOps; ++i) {
2283 if (N->getOperand(i) != Operand0)
2284 return false;
2285 }
2286
2287 return true;
2288}
2289
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00002290// Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT.
2291//
2292// The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We
2293// choose to sign-extend but we could have equally chosen zero-extend. The
2294// DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT
2295// result into this node later (possibly changing it to a zero-extend in the
2296// process).
2297SDValue MipsSETargetLowering::
2298lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
2299 SDLoc DL(Op);
2300 EVT ResTy = Op->getValueType(0);
2301 SDValue Op0 = Op->getOperand(0);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00002302 EVT VecTy = Op0->getValueType(0);
2303
2304 if (!VecTy.is128BitVector())
2305 return SDValue();
2306
2307 if (ResTy.isInteger()) {
2308 SDValue Op1 = Op->getOperand(1);
2309 EVT EltTy = VecTy.getVectorElementType();
2310 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1,
2311 DAG.getValueType(EltTy));
2312 }
2313
2314 return Op;
Daniel Sandersa4c8f3a2013-09-23 14:03:12 +00002315}
2316
Daniel Sandersf49dd822013-09-24 13:33:07 +00002317static bool isConstantOrUndef(const SDValue Op) {
Sanjay Patel57195842016-03-14 17:28:46 +00002318 if (Op->isUndef())
Daniel Sandersf49dd822013-09-24 13:33:07 +00002319 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +00002320 if (isa<ConstantSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +00002321 return true;
Vasileios Kalintiris46963f62015-02-13 19:12:16 +00002322 if (isa<ConstantFPSDNode>(Op))
Daniel Sandersf49dd822013-09-24 13:33:07 +00002323 return true;
2324 return false;
2325}
2326
2327static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) {
2328 for (unsigned i = 0; i < Op->getNumOperands(); ++i)
2329 if (isConstantOrUndef(Op->getOperand(i)))
2330 return true;
2331 return false;
2332}
2333
Daniel Sanders7a289d02013-09-23 12:02:46 +00002334// Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the
2335// backend.
2336//
2337// Lowers according to the following rules:
Daniel Sandersf49dd822013-09-24 13:33:07 +00002338// - Constant splats are legal as-is as long as the SplatBitSize is a power of
2339// 2 less than or equal to 64 and the value fits into a signed 10-bit
2340// immediate
2341// - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize
2342// is a power of 2 less than or equal to 64 and the value does not fit into a
2343// signed 10-bit immediate
2344// - Non-constant splats are legal as-is.
2345// - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT.
2346// - All others are illegal and must be expanded.
Daniel Sanders7a289d02013-09-23 12:02:46 +00002347SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op,
2348 SelectionDAG &DAG) const {
2349 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op);
2350 EVT ResTy = Op->getValueType(0);
2351 SDLoc DL(Op);
2352 APInt SplatValue, SplatUndef;
2353 unsigned SplatBitSize;
2354 bool HasAnyUndefs;
2355
Eric Christopher1c29a652014-07-18 22:55:25 +00002356 if (!Subtarget.hasMSA() || !ResTy.is128BitVector())
Daniel Sanders7a289d02013-09-23 12:02:46 +00002357 return SDValue();
2358
2359 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
2360 HasAnyUndefs, 8,
Eric Christopher1c29a652014-07-18 22:55:25 +00002361 !Subtarget.isLittle()) && SplatBitSize <= 64) {
Daniel Sandersf49dd822013-09-24 13:33:07 +00002362 // We can only cope with 8, 16, 32, or 64-bit elements
2363 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 &&
2364 SplatBitSize != 64)
2365 return SDValue();
2366
2367 // If the value fits into a simm10 then we can use ldi.[bhwd]
Daniel Sandersfd8e4162013-11-22 11:24:50 +00002368 // However, if it isn't an integer type we will have to bitcast from an
Daniel Sandersd40aea82013-11-22 13:22:52 +00002369 // integer type first. Also, if there are any undefs, we must lower them
Daniel Sanders630dbe02013-11-22 13:14:06 +00002370 // to defined values first.
2371 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10))
Daniel Sandersf49dd822013-09-24 13:33:07 +00002372 return Op;
2373
2374 EVT ViaVecTy;
Daniel Sanders7a289d02013-09-23 12:02:46 +00002375
2376 switch (SplatBitSize) {
2377 default:
2378 return SDValue();
Daniel Sandersf49dd822013-09-24 13:33:07 +00002379 case 8:
2380 ViaVecTy = MVT::v16i8;
Daniel Sanders7a289d02013-09-23 12:02:46 +00002381 break;
2382 case 16:
Daniel Sandersf49dd822013-09-24 13:33:07 +00002383 ViaVecTy = MVT::v8i16;
Daniel Sanders7a289d02013-09-23 12:02:46 +00002384 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +00002385 case 32:
2386 ViaVecTy = MVT::v4i32;
Daniel Sanders7a289d02013-09-23 12:02:46 +00002387 break;
Daniel Sandersf49dd822013-09-24 13:33:07 +00002388 case 64:
2389 // There's no fill.d to fall back on for 64-bit values
2390 return SDValue();
Daniel Sanders7a289d02013-09-23 12:02:46 +00002391 }
2392
Daniel Sanders50b80412013-11-15 12:56:49 +00002393 // SelectionDAG::getConstant will promote SplatValue appropriately.
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00002394 SDValue Result = DAG.getConstant(SplatValue, DL, ViaVecTy);
Daniel Sandersf49dd822013-09-24 13:33:07 +00002395
Daniel Sanders50b80412013-11-15 12:56:49 +00002396 // Bitcast to the type we originally wanted
Daniel Sandersf49dd822013-09-24 13:33:07 +00002397 if (ViaVecTy != ResTy)
2398 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result);
Daniel Sanders7a289d02013-09-23 12:02:46 +00002399
2400 return Result;
Daniel Sandersf49dd822013-09-24 13:33:07 +00002401 } else if (isSplatVector(Node))
2402 return Op;
2403 else if (!isConstantOrUndefBUILD_VECTOR(Node)) {
Daniel Sandersf86622b2013-09-24 13:16:15 +00002404 // Use INSERT_VECTOR_ELT operations rather than expand to stores.
2405 // The resulting code is the same length as the expansion, but it doesn't
2406 // use memory operations
2407 EVT ResTy = Node->getValueType(0);
2408
2409 assert(ResTy.isVector());
2410
2411 unsigned NumElts = ResTy.getVectorNumElements();
2412 SDValue Vector = DAG.getUNDEF(ResTy);
2413 for (unsigned i = 0; i < NumElts; ++i) {
2414 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector,
2415 Node->getOperand(i),
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00002416 DAG.getConstant(i, DL, MVT::i32));
Daniel Sandersf86622b2013-09-24 13:16:15 +00002417 }
2418 return Vector;
2419 }
Daniel Sanders7a289d02013-09-23 12:02:46 +00002420
2421 return SDValue();
2422}
2423
Daniel Sanders26307182013-09-24 14:20:00 +00002424// Lower VECTOR_SHUFFLE into SHF (if possible).
2425//
2426// SHF splits the vector into blocks of four elements, then shuffles these
2427// elements according to a <4 x i2> constant (encoded as an integer immediate).
2428//
2429// It is therefore possible to lower into SHF when the mask takes the form:
2430// <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...>
2431// When undef's appear they are treated as if they were whatever value is
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002432// necessary in order to fit the above forms.
Daniel Sanders26307182013-09-24 14:20:00 +00002433//
2434// For example:
2435// %2 = shufflevector <8 x i16> %0, <8 x i16> undef,
2436// <8 x i32> <i32 3, i32 2, i32 1, i32 0,
2437// i32 7, i32 6, i32 5, i32 4>
2438// is lowered to:
2439// (SHF_H $w0, $w1, 27)
2440// where the 27 comes from:
2441// 3 + (2 << 2) + (1 << 4) + (0 << 6)
2442static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy,
2443 SmallVector<int, 16> Indices,
2444 SelectionDAG &DAG) {
2445 int SHFIndices[4] = { -1, -1, -1, -1 };
2446
2447 if (Indices.size() < 4)
2448 return SDValue();
2449
2450 for (unsigned i = 0; i < 4; ++i) {
2451 for (unsigned j = i; j < Indices.size(); j += 4) {
2452 int Idx = Indices[j];
2453
2454 // Convert from vector index to 4-element subvector index
2455 // If an index refers to an element outside of the subvector then give up
2456 if (Idx != -1) {
2457 Idx -= 4 * (j / 4);
2458 if (Idx < 0 || Idx >= 4)
2459 return SDValue();
2460 }
2461
2462 // If the mask has an undef, replace it with the current index.
2463 // Note that it might still be undef if the current index is also undef
2464 if (SHFIndices[i] == -1)
2465 SHFIndices[i] = Idx;
2466
2467 // Check that non-undef values are the same as in the mask. If they
2468 // aren't then give up
2469 if (!(Idx == -1 || Idx == SHFIndices[i]))
2470 return SDValue();
2471 }
2472 }
2473
2474 // Calculate the immediate. Replace any remaining undefs with zero
2475 APInt Imm(32, 0);
2476 for (int i = 3; i >= 0; --i) {
2477 int Idx = SHFIndices[i];
2478
2479 if (Idx == -1)
2480 Idx = 0;
2481
2482 Imm <<= 2;
2483 Imm |= Idx & 0x3;
2484 }
2485
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00002486 SDLoc DL(Op);
2487 return DAG.getNode(MipsISD::SHF, DL, ResTy,
2488 DAG.getConstant(Imm, DL, MVT::i32), Op->getOperand(0));
Daniel Sanders26307182013-09-24 14:20:00 +00002489}
2490
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002491/// Determine whether a range fits a regular pattern of values.
2492/// This function accounts for the possibility of jumping over the End iterator.
2493template <typename ValType>
2494static bool
2495fitsRegularPattern(typename SmallVectorImpl<ValType>::const_iterator Begin,
2496 unsigned CheckStride,
2497 typename SmallVectorImpl<ValType>::const_iterator End,
2498 ValType ExpectedIndex, unsigned ExpectedIndexStride) {
2499 auto &I = Begin;
2500
2501 while (I != End) {
2502 if (*I != -1 && *I != ExpectedIndex)
2503 return false;
2504 ExpectedIndex += ExpectedIndexStride;
2505
2506 // Incrementing past End is undefined behaviour so we must increment one
2507 // step at a time and check for End at each step.
2508 for (unsigned n = 0; n < CheckStride && I != End; ++n, ++I)
2509 ; // Empty loop body.
2510 }
2511 return true;
2512}
2513
2514// Determine whether VECTOR_SHUFFLE is a SPLATI.
2515//
2516// It is a SPLATI when the mask is:
2517// <x, x, x, ...>
2518// where x is any valid index.
2519//
2520// When undef's appear in the mask they are treated as if they were whatever
2521// value is necessary in order to fit the above form.
2522static bool isVECTOR_SHUFFLE_SPLATI(SDValue Op, EVT ResTy,
2523 SmallVector<int, 16> Indices,
2524 SelectionDAG &DAG) {
2525 assert((Indices.size() % 2) == 0);
2526
2527 int SplatIndex = -1;
2528 for (const auto &V : Indices) {
2529 if (V != -1) {
2530 SplatIndex = V;
2531 break;
2532 }
2533 }
2534
2535 return fitsRegularPattern<int>(Indices.begin(), 1, Indices.end(), SplatIndex,
2536 0);
2537}
2538
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002539// Lower VECTOR_SHUFFLE into ILVEV (if possible).
2540//
2541// ILVEV interleaves the even elements from each vector.
2542//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002543// It is possible to lower into ILVEV when the mask consists of two of the
2544// following forms interleaved:
2545// <0, 2, 4, ...>
2546// <n, n+2, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002547// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002548// For example:
2549// <0, 0, 2, 2, 4, 4, ...>
2550// <0, n, 2, n+2, 4, n+4, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002551//
2552// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002553// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002554static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy,
2555 SmallVector<int, 16> Indices,
2556 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002557 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002558
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002559 SDValue Wt;
2560 SDValue Ws;
2561 const auto &Begin = Indices.begin();
2562 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002563
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002564 // Check even elements are taken from the even elements of one half or the
2565 // other and pick an operand accordingly.
2566 if (fitsRegularPattern<int>(Begin, 2, End, 0, 2))
2567 Wt = Op->getOperand(0);
2568 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 2))
2569 Wt = Op->getOperand(1);
2570 else
2571 return SDValue();
2572
2573 // Check odd elements are taken from the even elements of one half or the
2574 // other and pick an operand accordingly.
2575 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 2))
2576 Ws = Op->getOperand(0);
2577 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 2))
2578 Ws = Op->getOperand(1);
2579 else
2580 return SDValue();
2581
2582 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002583}
2584
2585// Lower VECTOR_SHUFFLE into ILVOD (if possible).
2586//
2587// ILVOD interleaves the odd elements from each vector.
2588//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002589// It is possible to lower into ILVOD when the mask consists of two of the
2590// following forms interleaved:
2591// <1, 3, 5, ...>
2592// <n+1, n+3, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002593// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002594// For example:
2595// <1, 1, 3, 3, 5, 5, ...>
2596// <1, n+1, 3, n+3, 5, n+5, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002597//
2598// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002599// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002600static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy,
2601 SmallVector<int, 16> Indices,
2602 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002603 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002604
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002605 SDValue Wt;
2606 SDValue Ws;
2607 const auto &Begin = Indices.begin();
2608 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002609
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002610 // Check even elements are taken from the odd elements of one half or the
2611 // other and pick an operand accordingly.
2612 if (fitsRegularPattern<int>(Begin, 2, End, 1, 2))
2613 Wt = Op->getOperand(0);
2614 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + 1, 2))
2615 Wt = Op->getOperand(1);
2616 else
2617 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002618
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002619 // Check odd elements are taken from the odd elements of one half or the
2620 // other and pick an operand accordingly.
2621 if (fitsRegularPattern<int>(Begin + 1, 2, End, 1, 2))
2622 Ws = Op->getOperand(0);
2623 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + 1, 2))
2624 Ws = Op->getOperand(1);
2625 else
2626 return SDValue();
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002627
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002628 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Wt, Ws);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002629}
2630
2631// Lower VECTOR_SHUFFLE into ILVR (if possible).
2632//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002633// ILVR interleaves consecutive elements from the right (lowest-indexed) half of
2634// each vector.
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002635//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002636// It is possible to lower into ILVR when the mask consists of two of the
2637// following forms interleaved:
2638// <0, 1, 2, ...>
2639// <n, n+1, n+2, ...>
2640// where n is the number of elements in the vector.
2641// For example:
2642// <0, 0, 1, 1, 2, 2, ...>
2643// <0, n, 1, n+1, 2, n+2, ...>
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002644//
2645// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002646// value is necessary in order to fit the above forms.
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002647static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy,
2648 SmallVector<int, 16> Indices,
2649 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002650 assert((Indices.size() % 2) == 0);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002651
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002652 SDValue Wt;
2653 SDValue Ws;
2654 const auto &Begin = Indices.begin();
2655 const auto &End = Indices.end();
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002656
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002657 // Check even elements are taken from the right (lowest-indexed) elements of
2658 // one half or the other and pick an operand accordingly.
2659 if (fitsRegularPattern<int>(Begin, 2, End, 0, 1))
2660 Wt = Op->getOperand(0);
2661 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size(), 1))
2662 Wt = Op->getOperand(1);
2663 else
2664 return SDValue();
2665
2666 // Check odd elements are taken from the right (lowest-indexed) elements of
2667 // one half or the other and pick an operand accordingly.
2668 if (fitsRegularPattern<int>(Begin + 1, 2, End, 0, 1))
2669 Ws = Op->getOperand(0);
2670 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size(), 1))
2671 Ws = Op->getOperand(1);
2672 else
2673 return SDValue();
2674
2675 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Ws, Wt);
2676}
2677
2678// Lower VECTOR_SHUFFLE into ILVL (if possible).
2679//
2680// ILVL interleaves consecutive elements from the left (highest-indexed) half
2681// of each vector.
2682//
2683// It is possible to lower into ILVL when the mask consists of two of the
2684// following forms interleaved:
2685// <x, x+1, x+2, ...>
2686// <n+x, n+x+1, n+x+2, ...>
2687// where n is the number of elements in the vector and x is half n.
2688// For example:
2689// <x, x, x+1, x+1, x+2, x+2, ...>
2690// <x, n+x, x+1, n+x+1, x+2, n+x+2, ...>
2691//
2692// When undef's appear in the mask they are treated as if they were whatever
2693// value is necessary in order to fit the above forms.
2694static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy,
2695 SmallVector<int, 16> Indices,
2696 SelectionDAG &DAG) {
2697 assert((Indices.size() % 2) == 0);
2698
2699 unsigned HalfSize = Indices.size() / 2;
2700 SDValue Wt;
2701 SDValue Ws;
2702 const auto &Begin = Indices.begin();
2703 const auto &End = Indices.end();
2704
2705 // Check even elements are taken from the left (highest-indexed) elements of
2706 // one half or the other and pick an operand accordingly.
2707 if (fitsRegularPattern<int>(Begin, 2, End, HalfSize, 1))
2708 Wt = Op->getOperand(0);
2709 else if (fitsRegularPattern<int>(Begin, 2, End, Indices.size() + HalfSize, 1))
2710 Wt = Op->getOperand(1);
2711 else
2712 return SDValue();
2713
2714 // Check odd elements are taken from the left (highest-indexed) elements of
2715 // one half or the other and pick an operand accordingly.
2716 if (fitsRegularPattern<int>(Begin + 1, 2, End, HalfSize, 1))
2717 Ws = Op->getOperand(0);
2718 else if (fitsRegularPattern<int>(Begin + 1, 2, End, Indices.size() + HalfSize,
2719 1))
2720 Ws = Op->getOperand(1);
2721 else
2722 return SDValue();
2723
2724 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002725}
2726
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002727// Lower VECTOR_SHUFFLE into PCKEV (if possible).
2728//
2729// PCKEV copies the even elements of each vector into the result vector.
2730//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002731// It is possible to lower into PCKEV when the mask consists of two of the
2732// following forms concatenated:
2733// <0, 2, 4, ...>
2734// <n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002735// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002736// For example:
2737// <0, 2, 4, ..., 0, 2, 4, ...>
2738// <0, 2, 4, ..., n, n+2, n+4, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002739//
2740// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002741// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002742static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy,
2743 SmallVector<int, 16> Indices,
2744 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002745 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002746
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002747 SDValue Wt;
2748 SDValue Ws;
2749 const auto &Begin = Indices.begin();
2750 const auto &Mid = Indices.begin() + Indices.size() / 2;
2751 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002752
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002753 if (fitsRegularPattern<int>(Begin, 1, Mid, 0, 2))
2754 Wt = Op->getOperand(0);
2755 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size(), 2))
2756 Wt = Op->getOperand(1);
2757 else
2758 return SDValue();
2759
2760 if (fitsRegularPattern<int>(Mid, 1, End, 0, 2))
2761 Ws = Op->getOperand(0);
2762 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size(), 2))
2763 Ws = Op->getOperand(1);
2764 else
2765 return SDValue();
2766
2767 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002768}
2769
2770// Lower VECTOR_SHUFFLE into PCKOD (if possible).
2771//
2772// PCKOD copies the odd elements of each vector into the result vector.
2773//
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002774// It is possible to lower into PCKOD when the mask consists of two of the
2775// following forms concatenated:
2776// <1, 3, 5, ...>
2777// <n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002778// where n is the number of elements in the vector.
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002779// For example:
2780// <1, 3, 5, ..., 1, 3, 5, ...>
2781// <1, 3, 5, ..., n+1, n+3, n+5, ...>
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002782//
2783// When undef's appear in the mask they are treated as if they were whatever
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002784// value is necessary in order to fit the above forms.
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002785static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy,
2786 SmallVector<int, 16> Indices,
2787 SelectionDAG &DAG) {
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002788 assert((Indices.size() % 2) == 0);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002789
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002790 SDValue Wt;
2791 SDValue Ws;
2792 const auto &Begin = Indices.begin();
2793 const auto &Mid = Indices.begin() + Indices.size() / 2;
2794 const auto &End = Indices.end();
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002795
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002796 if (fitsRegularPattern<int>(Begin, 1, Mid, 1, 2))
2797 Wt = Op->getOperand(0);
2798 else if (fitsRegularPattern<int>(Begin, 1, Mid, Indices.size() + 1, 2))
2799 Wt = Op->getOperand(1);
2800 else
2801 return SDValue();
2802
2803 if (fitsRegularPattern<int>(Mid, 1, End, 1, 2))
2804 Ws = Op->getOperand(0);
2805 else if (fitsRegularPattern<int>(Mid, 1, End, Indices.size() + 1, 2))
2806 Ws = Op->getOperand(1);
2807 else
2808 return SDValue();
2809
2810 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Ws, Wt);
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002811}
2812
Daniel Sanderse5087042013-09-24 14:02:15 +00002813// Lower VECTOR_SHUFFLE into VSHF.
2814//
2815// This mostly consists of converting the shuffle indices in Indices into a
2816// BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is
2817// also code to eliminate unused operands of the VECTOR_SHUFFLE. For example,
2818// if the type is v8i16 and all the indices are less than 8 then the second
2819// operand is unused and can be replaced with anything. We choose to replace it
2820// with the used operand since this reduces the number of instructions overall.
2821static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy,
2822 SmallVector<int, 16> Indices,
2823 SelectionDAG &DAG) {
2824 SmallVector<SDValue, 16> Ops;
2825 SDValue Op0;
2826 SDValue Op1;
2827 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger();
2828 EVT MaskEltTy = MaskVecTy.getVectorElementType();
2829 bool Using1stVec = false;
2830 bool Using2ndVec = false;
2831 SDLoc DL(Op);
2832 int ResTyNumElts = ResTy.getVectorNumElements();
2833
2834 for (int i = 0; i < ResTyNumElts; ++i) {
2835 // Idx == -1 means UNDEF
2836 int Idx = Indices[i];
2837
2838 if (0 <= Idx && Idx < ResTyNumElts)
2839 Using1stVec = true;
2840 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2)
2841 Using2ndVec = true;
2842 }
2843
2844 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end();
2845 ++I)
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00002846 Ops.push_back(DAG.getTargetConstant(*I, DL, MaskEltTy));
Daniel Sanderse5087042013-09-24 14:02:15 +00002847
Ahmed Bougacha128f8732016-04-26 21:15:30 +00002848 SDValue MaskVec = DAG.getBuildVector(MaskVecTy, DL, Ops);
Daniel Sanderse5087042013-09-24 14:02:15 +00002849
2850 if (Using1stVec && Using2ndVec) {
2851 Op0 = Op->getOperand(0);
2852 Op1 = Op->getOperand(1);
2853 } else if (Using1stVec)
2854 Op0 = Op1 = Op->getOperand(0);
2855 else if (Using2ndVec)
2856 Op0 = Op1 = Op->getOperand(1);
2857 else
2858 llvm_unreachable("shuffle vector mask references neither vector operand?");
2859
Daniel Sandersf88a29e2014-03-21 16:56:51 +00002860 // VECTOR_SHUFFLE concatenates the vectors in an vectorwise fashion.
2861 // <0b00, 0b01> + <0b10, 0b11> -> <0b00, 0b01, 0b10, 0b11>
2862 // VSHF concatenates the vectors in a bitwise fashion:
2863 // <0b00, 0b01> + <0b10, 0b11> ->
2864 // 0b0100 + 0b1110 -> 0b01001110
2865 // <0b10, 0b11, 0b00, 0b01>
2866 // We must therefore swap the operands to get the correct result.
2867 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0);
Daniel Sanderse5087042013-09-24 14:02:15 +00002868}
2869
2870// Lower VECTOR_SHUFFLE into one of a number of instructions depending on the
2871// indices in the shuffle.
2872SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
2873 SelectionDAG &DAG) const {
2874 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op);
2875 EVT ResTy = Op->getValueType(0);
2876
2877 if (!ResTy.is128BitVector())
2878 return SDValue();
2879
2880 int ResTyNumElts = ResTy.getVectorNumElements();
2881 SmallVector<int, 16> Indices;
2882
2883 for (int i = 0; i < ResTyNumElts; ++i)
2884 Indices.push_back(Node->getMaskElt(i));
2885
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002886 // splati.[bhwd] is preferable to the others but is matched from
2887 // MipsISD::VSHF.
2888 if (isVECTOR_SHUFFLE_SPLATI(Op, ResTy, Indices, DAG))
2889 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002890 SDValue Result;
2891 if ((Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002892 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002893 if ((Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002894 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002895 if ((Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002896 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002897 if ((Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG)))
Daniel Sanders2ed228b2013-09-24 14:36:12 +00002898 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002899 if ((Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002900 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002901 if ((Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG)))
Daniel Sandersfae5f2a2013-09-24 14:53:25 +00002902 return Result;
Ahmed Bougachaf8dfb472016-02-09 22:54:12 +00002903 if ((Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG)))
Daniel Sandersc8cd58f2015-05-19 12:24:52 +00002904 return Result;
Daniel Sanderse5087042013-09-24 14:02:15 +00002905 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG);
2906}
2907
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002908MachineBasicBlock * MipsSETargetLowering::
2909emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{
2910 // $bb:
2911 // bposge32_pseudo $vr0
2912 // =>
2913 // $bb:
2914 // bposge32 $tbb
2915 // $fbb:
2916 // li $vr2, 0
2917 // b $sink
2918 // $tbb:
2919 // li $vr1, 1
2920 // $sink:
2921 // $vr0 = phi($vr2, $fbb, $vr1, $tbb)
2922
2923 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +00002924 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Akira Hatanaka13e6ccf2013-08-06 23:08:38 +00002925 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002926 DebugLoc DL = MI->getDebugLoc();
2927 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00002928 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002929 MachineFunction *F = BB->getParent();
2930 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2931 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2932 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
2933 F->insert(It, FBB);
2934 F->insert(It, TBB);
2935 F->insert(It, Sink);
2936
2937 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00002938 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002939 BB->end());
2940 Sink->transferSuccessorsAndUpdatePHIs(BB);
2941
2942 // Add successors.
2943 BB->addSuccessor(FBB);
2944 BB->addSuccessor(TBB);
2945 FBB->addSuccessor(Sink);
2946 TBB->addSuccessor(Sink);
2947
2948 // Insert the real bposge32 instruction to $BB.
2949 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB);
Hrvoje Varga6f09cdf2016-05-13 11:32:53 +00002950 // Insert the real bposge32c instruction to $BB.
2951 BuildMI(BB, DL, TII->get(Mips::BPOSGE32C_MMR3)).addMBB(TBB);
Akira Hatanaka96ca1822013-03-13 00:54:29 +00002952
2953 // Fill $FBB.
2954 unsigned VR2 = RegInfo.createVirtualRegister(RC);
2955 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2)
2956 .addReg(Mips::ZERO).addImm(0);
2957 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
2958
2959 // Fill $TBB.
2960 unsigned VR1 = RegInfo.createVirtualRegister(RC);
2961 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1)
2962 .addReg(Mips::ZERO).addImm(1);
2963
2964 // Insert phi function to $Sink.
2965 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
2966 MI->getOperand(0).getReg())
2967 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB);
2968
2969 MI->eraseFromParent(); // The pseudo instruction is gone now.
2970 return Sink;
2971}
Daniel Sandersce09d072013-08-28 12:14:50 +00002972
2973MachineBasicBlock * MipsSETargetLowering::
2974emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB,
2975 unsigned BranchOp) const{
2976 // $bb:
2977 // vany_nonzero $rd, $ws
2978 // =>
2979 // $bb:
2980 // bnz.b $ws, $tbb
2981 // b $fbb
2982 // $fbb:
2983 // li $rd1, 0
2984 // b $sink
2985 // $tbb:
2986 // li $rd2, 1
2987 // $sink:
2988 // $rd = phi($rd1, $fbb, $rd2, $tbb)
2989
2990 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
Eric Christopher96e72c62015-01-29 23:27:36 +00002991 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersce09d072013-08-28 12:14:50 +00002992 const TargetRegisterClass *RC = &Mips::GPR32RegClass;
2993 DebugLoc DL = MI->getDebugLoc();
2994 const BasicBlock *LLVM_BB = BB->getBasicBlock();
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00002995 MachineFunction::iterator It = std::next(MachineFunction::iterator(BB));
Daniel Sandersce09d072013-08-28 12:14:50 +00002996 MachineFunction *F = BB->getParent();
2997 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB);
2998 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB);
2999 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB);
3000 F->insert(It, FBB);
3001 F->insert(It, TBB);
3002 F->insert(It, Sink);
3003
3004 // Transfer the remainder of BB and its successor edges to Sink.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +00003005 Sink->splice(Sink->begin(), BB, std::next(MachineBasicBlock::iterator(MI)),
Daniel Sandersce09d072013-08-28 12:14:50 +00003006 BB->end());
3007 Sink->transferSuccessorsAndUpdatePHIs(BB);
3008
3009 // Add successors.
3010 BB->addSuccessor(FBB);
3011 BB->addSuccessor(TBB);
3012 FBB->addSuccessor(Sink);
3013 TBB->addSuccessor(Sink);
3014
3015 // Insert the real bnz.b instruction to $BB.
3016 BuildMI(BB, DL, TII->get(BranchOp))
3017 .addReg(MI->getOperand(1).getReg())
3018 .addMBB(TBB);
3019
3020 // Fill $FBB.
3021 unsigned RD1 = RegInfo.createVirtualRegister(RC);
3022 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1)
3023 .addReg(Mips::ZERO).addImm(0);
3024 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink);
3025
3026 // Fill $TBB.
3027 unsigned RD2 = RegInfo.createVirtualRegister(RC);
3028 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2)
3029 .addReg(Mips::ZERO).addImm(1);
3030
3031 // Insert phi function to $Sink.
3032 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI),
3033 MI->getOperand(0).getReg())
3034 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB);
3035
3036 MI->eraseFromParent(); // The pseudo instruction is gone now.
3037 return Sink;
3038}
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003039
3040// Emit the COPY_FW pseudo instruction.
3041//
3042// copy_fw_pseudo $fd, $ws, n
3043// =>
3044// copy_u_w $rt, $ws, $n
3045// mtc1 $rt, $fd
3046//
3047// When n is zero, the equivalent operation can be performed with (potentially)
3048// zero instructions due to register overlaps. This optimization is never valid
3049// for lane 1 because it would require FR=0 mode which isn't supported by MSA.
3050MachineBasicBlock * MipsSETargetLowering::
3051emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{
Eric Christopher96e72c62015-01-29 23:27:36 +00003052 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003053 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3054 DebugLoc DL = MI->getDebugLoc();
3055 unsigned Fd = MI->getOperand(0).getReg();
3056 unsigned Ws = MI->getOperand(1).getReg();
3057 unsigned Lane = MI->getOperand(2).getImm();
3058
Daniel Sandersafe27c72015-02-23 17:22:16 +00003059 if (Lane == 0) {
3060 unsigned Wt = Ws;
3061 if (!Subtarget.useOddSPReg()) {
3062 // We must copy to an even-numbered MSA register so that the
3063 // single-precision sub-register is also guaranteed to be even-numbered.
3064 Wt = RegInfo.createVirtualRegister(&Mips::MSA128WEvensRegClass);
3065
3066 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Wt).addReg(Ws);
3067 }
3068
3069 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3070 } else {
3071 unsigned Wt = RegInfo.createVirtualRegister(
3072 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3073 &Mips::MSA128WEvensRegClass);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003074
Daniel Sandersd9207702014-03-04 13:54:30 +00003075 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(Lane);
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003076 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo);
3077 }
3078
3079 MI->eraseFromParent(); // The pseudo instruction is gone now.
3080 return BB;
3081}
3082
3083// Emit the COPY_FD pseudo instruction.
3084//
3085// copy_fd_pseudo $fd, $ws, n
3086// =>
3087// splati.d $wt, $ws, $n
3088// copy $fd, $wt:sub_64
3089//
3090// When n is zero, the equivalent operation can be performed with (potentially)
3091// zero instructions due to register overlaps. This optimization is always
3092// valid because FR=1 mode which is the only supported mode in MSA.
3093MachineBasicBlock * MipsSETargetLowering::
3094emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{
Eric Christopher1c29a652014-07-18 22:55:25 +00003095 assert(Subtarget.isFP64bit());
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003096
Eric Christopher96e72c62015-01-29 23:27:36 +00003097 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders39bb8ba2013-09-27 12:17:32 +00003098 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3099 unsigned Fd = MI->getOperand(0).getReg();
3100 unsigned Ws = MI->getOperand(1).getReg();
3101 unsigned Lane = MI->getOperand(2).getImm() * 2;
3102 DebugLoc DL = MI->getDebugLoc();
3103
3104 if (Lane == 0)
3105 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64);
3106 else {
3107 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3108
3109 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1);
3110 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64);
3111 }
3112
3113 MI->eraseFromParent(); // The pseudo instruction is gone now.
3114 return BB;
3115}
Daniel Sandersa5150702013-09-27 12:31:32 +00003116
3117// Emit the INSERT_FW pseudo instruction.
3118//
3119// insert_fw_pseudo $wd, $wd_in, $n, $fs
3120// =>
3121// subreg_to_reg $wt:sub_lo, $fs
3122// insve_w $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003123MachineBasicBlock *
3124MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI,
3125 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +00003126 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +00003127 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3128 DebugLoc DL = MI->getDebugLoc();
3129 unsigned Wd = MI->getOperand(0).getReg();
3130 unsigned Wd_in = MI->getOperand(1).getReg();
3131 unsigned Lane = MI->getOperand(2).getImm();
3132 unsigned Fs = MI->getOperand(3).getReg();
Daniel Sandersafe27c72015-02-23 17:22:16 +00003133 unsigned Wt = RegInfo.createVirtualRegister(
3134 Subtarget.useOddSPReg() ? &Mips::MSA128WRegClass :
3135 &Mips::MSA128WEvensRegClass);
Daniel Sandersa5150702013-09-27 12:31:32 +00003136
3137 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003138 .addImm(0)
3139 .addReg(Fs)
3140 .addImm(Mips::sub_lo);
Daniel Sandersa5150702013-09-27 12:31:32 +00003141 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003142 .addReg(Wd_in)
3143 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +00003144 .addReg(Wt)
3145 .addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +00003146
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003147 MI->eraseFromParent(); // The pseudo instruction is gone now.
Daniel Sandersa5150702013-09-27 12:31:32 +00003148 return BB;
3149}
3150
3151// Emit the INSERT_FD pseudo instruction.
3152//
3153// insert_fd_pseudo $wd, $fs, n
3154// =>
3155// subreg_to_reg $wt:sub_64, $fs
3156// insve_d $wd[$n], $wd_in, $wt[0]
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003157MachineBasicBlock *
3158MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI,
3159 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +00003160 assert(Subtarget.isFP64bit());
Daniel Sandersa5150702013-09-27 12:31:32 +00003161
Eric Christopher96e72c62015-01-29 23:27:36 +00003162 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa5150702013-09-27 12:31:32 +00003163 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3164 DebugLoc DL = MI->getDebugLoc();
3165 unsigned Wd = MI->getOperand(0).getReg();
3166 unsigned Wd_in = MI->getOperand(1).getReg();
3167 unsigned Lane = MI->getOperand(2).getImm();
3168 unsigned Fs = MI->getOperand(3).getReg();
3169 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3170
3171 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003172 .addImm(0)
3173 .addReg(Fs)
3174 .addImm(Mips::sub_64);
Daniel Sandersa5150702013-09-27 12:31:32 +00003175 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd)
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003176 .addReg(Wd_in)
3177 .addImm(Lane)
Daniel Sandersb50ccf82014-04-01 10:35:28 +00003178 .addReg(Wt)
3179 .addImm(0);
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003180
3181 MI->eraseFromParent(); // The pseudo instruction is gone now.
3182 return BB;
3183}
3184
Daniel Sanderse296a0f2014-04-30 12:09:32 +00003185// Emit the INSERT_([BHWD]|F[WD])_VIDX pseudo instruction.
3186//
3187// For integer:
3188// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $rs)
3189// =>
3190// (SLL $lanetmp1, $lane, <log2size)
3191// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3192// (INSERT_[BHWD], $wdtmp2, $wdtmp1, 0, $rs)
3193// (NEG $lanetmp2, $lanetmp1)
3194// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3195//
3196// For floating point:
3197// (INSERT_([BHWD]|F[WD])_PSEUDO $wd, $wd_in, $n, $fs)
3198// =>
3199// (SUBREG_TO_REG $wt, $fs, <subreg>)
3200// (SLL $lanetmp1, $lane, <log2size)
3201// (SLD_B $wdtmp1, $wd_in, $wd_in, $lanetmp1)
3202// (INSVE_[WD], $wdtmp2, 0, $wdtmp1, 0)
3203// (NEG $lanetmp2, $lanetmp1)
3204// (SLD_B $wd, $wdtmp2, $wdtmp2, $lanetmp2)
3205MachineBasicBlock *
3206MipsSETargetLowering::emitINSERT_DF_VIDX(MachineInstr *MI,
3207 MachineBasicBlock *BB,
3208 unsigned EltSizeInBytes,
3209 bool IsFP) const {
Eric Christopher96e72c62015-01-29 23:27:36 +00003210 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanderse296a0f2014-04-30 12:09:32 +00003211 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3212 DebugLoc DL = MI->getDebugLoc();
3213 unsigned Wd = MI->getOperand(0).getReg();
3214 unsigned SrcVecReg = MI->getOperand(1).getReg();
3215 unsigned LaneReg = MI->getOperand(2).getReg();
3216 unsigned SrcValReg = MI->getOperand(3).getReg();
3217
3218 const TargetRegisterClass *VecRC = nullptr;
Eric Christopherbf33a3c2014-07-02 23:18:40 +00003219 const TargetRegisterClass *GPRRC =
Daniel Sanders4160c802015-05-05 08:48:35 +00003220 Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
Daniel Sanderse296a0f2014-04-30 12:09:32 +00003221 unsigned EltLog2Size;
3222 unsigned InsertOp = 0;
3223 unsigned InsveOp = 0;
3224 switch (EltSizeInBytes) {
3225 default:
3226 llvm_unreachable("Unexpected size");
3227 case 1:
3228 EltLog2Size = 0;
3229 InsertOp = Mips::INSERT_B;
3230 InsveOp = Mips::INSVE_B;
3231 VecRC = &Mips::MSA128BRegClass;
3232 break;
3233 case 2:
3234 EltLog2Size = 1;
3235 InsertOp = Mips::INSERT_H;
3236 InsveOp = Mips::INSVE_H;
3237 VecRC = &Mips::MSA128HRegClass;
3238 break;
3239 case 4:
3240 EltLog2Size = 2;
3241 InsertOp = Mips::INSERT_W;
3242 InsveOp = Mips::INSVE_W;
3243 VecRC = &Mips::MSA128WRegClass;
3244 break;
3245 case 8:
3246 EltLog2Size = 3;
3247 InsertOp = Mips::INSERT_D;
3248 InsveOp = Mips::INSVE_D;
3249 VecRC = &Mips::MSA128DRegClass;
3250 break;
3251 }
3252
3253 if (IsFP) {
3254 unsigned Wt = RegInfo.createVirtualRegister(VecRC);
3255 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt)
3256 .addImm(0)
3257 .addReg(SrcValReg)
3258 .addImm(EltSizeInBytes == 8 ? Mips::sub_64 : Mips::sub_lo);
3259 SrcValReg = Wt;
3260 }
3261
3262 // Convert the lane index into a byte index
3263 if (EltSizeInBytes != 1) {
3264 unsigned LaneTmp1 = RegInfo.createVirtualRegister(GPRRC);
3265 BuildMI(*BB, MI, DL, TII->get(Mips::SLL), LaneTmp1)
3266 .addReg(LaneReg)
3267 .addImm(EltLog2Size);
3268 LaneReg = LaneTmp1;
3269 }
3270
3271 // Rotate bytes around so that the desired lane is element zero
3272 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC);
3273 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), WdTmp1)
3274 .addReg(SrcVecReg)
3275 .addReg(SrcVecReg)
3276 .addReg(LaneReg);
3277
3278 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC);
3279 if (IsFP) {
3280 // Use insve.df to insert to element zero
3281 BuildMI(*BB, MI, DL, TII->get(InsveOp), WdTmp2)
3282 .addReg(WdTmp1)
3283 .addImm(0)
3284 .addReg(SrcValReg)
3285 .addImm(0);
3286 } else {
3287 // Use insert.df to insert to element zero
3288 BuildMI(*BB, MI, DL, TII->get(InsertOp), WdTmp2)
3289 .addReg(WdTmp1)
3290 .addReg(SrcValReg)
3291 .addImm(0);
3292 }
3293
3294 // Rotate elements the rest of the way for a full rotation.
3295 // sld.df inteprets $rt modulo the number of columns so we only need to negate
3296 // the lane index to do this.
3297 unsigned LaneTmp2 = RegInfo.createVirtualRegister(GPRRC);
Daniel Sanders4160c802015-05-05 08:48:35 +00003298 BuildMI(*BB, MI, DL, TII->get(Subtarget.isABI_N64() ? Mips::DSUB : Mips::SUB),
3299 LaneTmp2)
3300 .addReg(Subtarget.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO)
Daniel Sanderse296a0f2014-04-30 12:09:32 +00003301 .addReg(LaneReg);
3302 BuildMI(*BB, MI, DL, TII->get(Mips::SLD_B), Wd)
3303 .addReg(WdTmp2)
3304 .addReg(WdTmp2)
3305 .addReg(LaneTmp2);
3306
3307 MI->eraseFromParent(); // The pseudo instruction is gone now.
3308 return BB;
3309}
3310
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003311// Emit the FILL_FW pseudo instruction.
3312//
3313// fill_fw_pseudo $wd, $fs
3314// =>
3315// implicit_def $wt1
3316// insert_subreg $wt2:subreg_lo, $wt1, $fs
3317// splati.w $wd, $wt2[0]
3318MachineBasicBlock *
3319MipsSETargetLowering::emitFILL_FW(MachineInstr *MI,
3320 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +00003321 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003322 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3323 DebugLoc DL = MI->getDebugLoc();
3324 unsigned Wd = MI->getOperand(0).getReg();
3325 unsigned Fs = MI->getOperand(1).getReg();
3326 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3327 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass);
3328
3329 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3330 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3331 .addReg(Wt1)
3332 .addReg(Fs)
3333 .addImm(Mips::sub_lo);
3334 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0);
3335
3336 MI->eraseFromParent(); // The pseudo instruction is gone now.
3337 return BB;
3338}
3339
3340// Emit the FILL_FD pseudo instruction.
3341//
3342// fill_fd_pseudo $wd, $fs
3343// =>
3344// implicit_def $wt1
3345// insert_subreg $wt2:subreg_64, $wt1, $fs
3346// splati.d $wd, $wt2[0]
3347MachineBasicBlock *
3348MipsSETargetLowering::emitFILL_FD(MachineInstr *MI,
3349 MachineBasicBlock *BB) const {
Eric Christopher1c29a652014-07-18 22:55:25 +00003350 assert(Subtarget.isFP64bit());
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003351
Eric Christopher96e72c62015-01-29 23:27:36 +00003352 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sanders1dfddc72013-10-15 13:14:41 +00003353 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3354 DebugLoc DL = MI->getDebugLoc();
3355 unsigned Wd = MI->getOperand(0).getReg();
3356 unsigned Fs = MI->getOperand(1).getReg();
3357 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3358 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass);
3359
3360 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1);
3361 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2)
3362 .addReg(Wt1)
3363 .addReg(Fs)
3364 .addImm(Mips::sub_64);
3365 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0);
Daniel Sandersa5150702013-09-27 12:31:32 +00003366
3367 MI->eraseFromParent(); // The pseudo instruction is gone now.
3368 return BB;
3369}
Daniel Sandersa9521602013-10-23 10:36:52 +00003370
3371// Emit the FEXP2_W_1 pseudo instructions.
3372//
3373// fexp2_w_1_pseudo $wd, $wt
3374// =>
3375// ldi.w $ws, 1
3376// fexp2.w $wd, $ws, $wt
3377MachineBasicBlock *
3378MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI,
3379 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +00003380 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +00003381 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3382 const TargetRegisterClass *RC = &Mips::MSA128WRegClass;
3383 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3384 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3385 DebugLoc DL = MI->getDebugLoc();
3386
3387 // Splat 1.0 into a vector
3388 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1);
3389 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1);
3390
3391 // Emit 1.0 * fexp2(Wt)
3392 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg())
3393 .addReg(Ws2)
3394 .addReg(MI->getOperand(1).getReg());
3395
3396 MI->eraseFromParent(); // The pseudo instruction is gone now.
3397 return BB;
3398}
3399
3400// Emit the FEXP2_D_1 pseudo instructions.
3401//
3402// fexp2_d_1_pseudo $wd, $wt
3403// =>
3404// ldi.d $ws, 1
3405// fexp2.d $wd, $ws, $wt
3406MachineBasicBlock *
3407MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI,
3408 MachineBasicBlock *BB) const {
Eric Christopher96e72c62015-01-29 23:27:36 +00003409 const TargetInstrInfo *TII = Subtarget.getInstrInfo();
Daniel Sandersa9521602013-10-23 10:36:52 +00003410 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo();
3411 const TargetRegisterClass *RC = &Mips::MSA128DRegClass;
3412 unsigned Ws1 = RegInfo.createVirtualRegister(RC);
3413 unsigned Ws2 = RegInfo.createVirtualRegister(RC);
3414 DebugLoc DL = MI->getDebugLoc();
3415
3416 // Splat 1.0 into a vector
3417 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1);
3418 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1);
3419
3420 // Emit 1.0 * fexp2(Wt)
3421 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg())
3422 .addReg(Ws2)
3423 .addReg(MI->getOperand(1).getReg());
3424
3425 MI->eraseFromParent(); // The pseudo instruction is gone now.
3426 return BB;
3427}