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gerrit-public.fairphone.software / toolchain / llvm-project / 01b4aa94371345be8e19129ccd9c6814f9c0e6aa / . / llvm / test / CodeGen / ARM / select-imm.ll
blob: 4dc297c7ec08d94c0a09474d2f276e7d44ff8a53 [file] [log] [blame]
Evan Cheng8ce967e2010-11-13 00:27:47 +0000[diff] [blame]1; RUN: llc < %s -march=arm | FileCheck %s --check-prefix=ARM
Joerg Sonnenberger002a1472013-12-13 11:16:00 +0000[diff] [blame]2; RUN: llc < %s -march=arm -mcpu=arm1156t2-s -mattr=+thumb2 | \
3; RUN: FileCheck %s --check-prefix=ARMT2
4; RUN: llc < %s -march=thumb -mcpu=arm1156t2-s -mattr=+thumb2 | \
5; RUN: FileCheck %s --check-prefix=THUMB2
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]6
Rafael Espindola29dda212010-06-17 15:18:27 +0000[diff] [blame]7define i32 @t1(i32 %c) nounwind readnone {
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]8entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]9; ARM-LABEL: t1:
Jakob Stoklund Olesen51b35f72011-05-03 22:31:21 +0000[diff] [blame]10; ARM: mov [[R1:r[0-9]+]], #101
Jim Grosbach581da642011-07-11 16:48:36 +0000[diff] [blame]11; ARM: orr [[R1b:r[0-9]+]], [[R1]], #256
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]12; ARM: movgt {{r[0-1]}}, #123
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]13
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]14; ARMT2-LABEL: t1:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]15; ARMT2: movw [[R:r[0-1]]], #357
Tim Northover42180442013-08-22 09:57:11 +0000[diff] [blame]16; ARMT2: movwgt [[R]], #123
Evan Cheng2bcb8da2010-11-13 02:25:14 +0000[diff] [blame]17
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]18; THUMB2-LABEL: t1:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]19; THUMB2: movw [[R:r[0-1]]], #357
20; THUMB2: movgt [[R]], #123
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]21
22 %0 = icmp sgt i32 %c, 1
23 %1 = select i1 %0, i32 123, i32 357
24 ret i32 %1
25}
26
Rafael Espindola29dda212010-06-17 15:18:27 +0000[diff] [blame]27define i32 @t2(i32 %c) nounwind readnone {
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]28entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]29; ARM-LABEL: t2:
Tim Northover42180442013-08-22 09:57:11 +0000[diff] [blame]30; ARM: mov [[R:r[0-9]+]], #101
31; ARM: orr [[R]], [[R]], #256
32; ARM: movle [[R]], #123
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]33
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]34; ARMT2-LABEL: t2:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]35; ARMT2: mov [[R:r[0-1]]], #123
36; ARMT2: movwgt [[R]], #357
Evan Cheng2bcb8da2010-11-13 02:25:14 +0000[diff] [blame]37
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]38; THUMB2-LABEL: t2:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]39; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #123
40; THUMB2: movwgt [[R]], #357
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]41
42 %0 = icmp sgt i32 %c, 1
43 %1 = select i1 %0, i32 357, i32 123
44 ret i32 %1
45}
46
Rafael Espindola29dda212010-06-17 15:18:27 +0000[diff] [blame]47define i32 @t3(i32 %a) nounwind readnone {
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]48entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]49; ARM-LABEL: t3:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]50; ARM: mov [[R:r[0-1]]], #0
51; ARM: moveq [[R]], #1
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]52
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]53; ARMT2-LABEL: t3:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]54; ARMT2: mov [[R:r[0-1]]], #0
Tim Northover42180442013-08-22 09:57:11 +0000[diff] [blame]55; ARMT2: movweq [[R]], #1
Evan Cheng2bcb8da2010-11-13 02:25:14 +0000[diff] [blame]56
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]57; THUMB2-LABEL: t3:
Andrew Trick84852572013-07-25 18:35:14 +0000[diff] [blame]58; THUMB2: mov{{(s|\.w)}} [[R:r[0-1]]], #0
59; THUMB2: moveq [[R]], #1
Evan Cheng81a28512009-11-20 00:54:03 +0000[diff] [blame]60 %0 = icmp eq i32 %a, 160
61 %1 = zext i1 %0 to i32
62 ret i32 %1
63}
Evan Cheng8ce967e2010-11-13 00:27:47 +0000[diff] [blame]64
65define i32 @t4(i32 %a, i32 %b, i32 %x) nounwind {
66entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]67; ARM-LABEL: t4:
Evan Cheng8ce967e2010-11-13 00:27:47 +0000[diff] [blame]68; ARM: ldr
Jakob Stoklund Olesen0a5b72f2012-04-04 18:23:42 +0000[diff] [blame]69; ARM: mov{{lt|ge}}
Evan Cheng8ce967e2010-11-13 00:27:47 +0000[diff] [blame]70
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]71; ARMT2-LABEL: t4:
Jakob Stoklund Olesen51b35f72011-05-03 22:31:21 +0000[diff] [blame]72; ARMT2: movwlt [[R0:r[0-9]+]], #65365
73; ARMT2: movtlt [[R0]], #65365
Evan Cheng2bcb8da2010-11-13 02:25:14 +0000[diff] [blame]74
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]75; THUMB2-LABEL: t4:
Jim Grosbach25d47072011-10-26 17:28:15 +0000[diff] [blame]76; THUMB2: mvnlt [[R0:r[0-9]+]], #11141290
Evan Cheng8ce967e2010-11-13 00:27:47 +0000[diff] [blame]77 %0 = icmp slt i32 %a, %b
78 %1 = select i1 %0, i32 4283826005, i32 %x
79 ret i32 %1
80}
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]81
82; rdar://9758317
83define i32 @t5(i32 %a) nounwind {
84entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]85; ARM-LABEL: t5:
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]86; ARM-NOT: mov
87; ARM: cmp r0, #1
88; ARM-NOT: mov
89; ARM: movne r0, #0
90
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]91; THUMB2-LABEL: t5:
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]92; THUMB2-NOT: mov
93; THUMB2: cmp r0, #1
94; THUMB2: it ne
95; THUMB2: movne r0, #0
96 %cmp = icmp eq i32 %a, 1
97 %conv = zext i1 %cmp to i32
98 ret i32 %conv
99}
100
101define i32 @t6(i32 %a) nounwind {
102entry:
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]103; ARM-LABEL: t6:
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]104; ARM-NOT: mov
105; ARM: cmp r0, #0
106; ARM: movne r0, #1
107
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]108; THUMB2-LABEL: t6:
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]109; THUMB2-NOT: mov
110; THUMB2: cmp r0, #0
111; THUMB2: it ne
112; THUMB2: movne r0, #1
113 %tobool = icmp ne i32 %a, 0
114 %lnot.ext = zext i1 %tobool to i32
115 ret i32 %lnot.ext
116}