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gerrit-public.fairphone.software / toolchain / llvm-project / 72b31eee0b34844841dbddbb1e499dbbdbff8d2d / . / llvm / test / CodeGen / R600 / trunc.ll
blob: 5ccccc8f88f737fd785e0efda6b24a307809bf8d [file] [log] [blame]
Tom Stellard70f13db2013-10-10 17:11:46 +0000[diff] [blame]1; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
Matt Arsenault6f243792013-09-05 19:41:10 +0000[diff] [blame]2; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
3
Matt Arsenault6f243792013-09-05 19:41:10 +0000[diff] [blame]4define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
5; SI-LABEL: @trunc_i64_to_i32_store
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame^]6; SI: S_LOAD_DWORD s0, s[0:1], 11
7; SI: V_MOV_B32_e32 v0, s0
8; SI: BUFFER_STORE_DWORD v0
Matt Arsenault6f243792013-09-05 19:41:10 +0000[diff] [blame]9
10; EG-LABEL: @trunc_i64_to_i32_store
11; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
12; EG: LSHR
13; EG-NEXT: 2(
14
15 %result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
16 ret void
17}
18
Matt Arsenault204cfa62013-10-10 18:04:16 +0000[diff] [blame]19; SI-LABEL: @trunc_shl_i64:
20; SI: S_LOAD_DWORDX2
Matt Arsenault72b31ee2013-11-12 02:35:51 +0000[diff] [blame^]21; SI: S_LOAD_DWORDX2 [[SREG:s\[[0-9]+:[0-9]+\]]]
22; SI: V_LSHL_B64 v{{\[}}[[LO_VREG:[0-9]+]]:{{[0-9]+\]}}, [[SREG]], 2
23; SI: BUFFER_STORE_DWORD v[[LO_VREG]],
Matt Arsenault204cfa62013-10-10 18:04:16 +0000[diff] [blame]24define void @trunc_shl_i64(i32 addrspace(1)* %out, i64 %a) {
25 %b = shl i64 %a, 2
26 %result = trunc i64 %b to i32
27 store i32 %result, i32 addrspace(1)* %out, align 4
28 ret void
29}