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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8/// \file
9//===----------------------------------------------------------------------===//
10
Matt Arsenault6b6a2c32016-03-11 08:00:27 +000011#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
12#define LLVM_LIB_TARGET_AMDGPU_AMDGPU_H
Tom Stellard75aadc22012-12-11 21:25:42 +000013
Konstantin Zhuravlyov60a83732016-10-03 18:47:26 +000014#include "llvm/Target/TargetMachine.h"
15
Tom Stellard75aadc22012-12-11 21:25:42 +000016namespace llvm {
17
Tom Stellard75aadc22012-12-11 21:25:42 +000018class AMDGPUTargetMachine;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000019class FunctionPass;
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +000020class GCNTargetMachine;
Matt Arsenault2ffe8fd2016-08-11 19:18:50 +000021class ModulePass;
22class Pass;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000023class Target;
24class TargetMachine;
Matt Arsenault2ffe8fd2016-08-11 19:18:50 +000025class PassRegistry;
Yaxun Liu1a14bfa2017-03-27 14:04:01 +000026class Module;
Tom Stellard75aadc22012-12-11 21:25:42 +000027
28// R600 Passes
Vincent Lejeunedec18752013-06-05 21:38:04 +000029FunctionPass *createR600VectorRegMerger(TargetMachine &tm);
Tom Stellard75aadc22012-12-11 21:25:42 +000030FunctionPass *createR600ExpandSpecialInstrsPass(TargetMachine &tm);
Tom Stellard1de55822013-12-11 17:51:41 +000031FunctionPass *createR600EmitClauseMarkers();
Vincent Lejeunea4da6fb2013-10-01 19:32:58 +000032FunctionPass *createR600ClauseMergePass(TargetMachine &tm);
Vincent Lejeune147700b2013-04-30 00:14:27 +000033FunctionPass *createR600Packetizer(TargetMachine &tm);
Vincent Lejeunebfaa63a62013-04-01 21:48:05 +000034FunctionPass *createR600ControlFlowFinalizer(TargetMachine &tm);
Tom Stellardf2ba9722013-12-11 17:51:47 +000035FunctionPass *createAMDGPUCFGStructurizerPass();
Tom Stellard75aadc22012-12-11 21:25:42 +000036
37// SI Passes
Tom Stellard9fa17912013-08-14 23:24:45 +000038FunctionPass *createSITypeRewriter();
Tom Stellardf8794352012-12-19 22:10:31 +000039FunctionPass *createSIAnnotateControlFlowPass();
Tom Stellard6596ba72014-11-21 22:06:37 +000040FunctionPass *createSIFoldOperandsPass();
Sam Koltonf60ad582017-03-21 12:51:34 +000041FunctionPass *createSIPeepholeSDWAPass();
Tom Stellard1bd80722014-04-30 15:31:33 +000042FunctionPass *createSILowerI1CopiesPass();
Tom Stellard1aaad692014-07-21 16:55:33 +000043FunctionPass *createSIShrinkInstructionsPass();
Matt Arsenault41033282014-10-10 22:01:59 +000044FunctionPass *createSILoadStoreOptimizerPass(TargetMachine &tm);
Nicolai Haehnle213e87f2016-03-21 20:28:33 +000045FunctionPass *createSIWholeQuadModePass();
Tom Stellard28d13a42015-05-12 17:13:02 +000046FunctionPass *createSIFixControlFlowLiveIntervalsPass();
Matt Arsenault782c03b2015-11-03 22:30:13 +000047FunctionPass *createSIFixSGPRCopiesPass();
Konstantin Zhuravlyova7919322016-05-10 18:33:41 +000048FunctionPass *createSIDebuggerInsertNopsPass();
Tom Stellard6e1967e2016-02-05 17:42:38 +000049FunctionPass *createSIInsertWaitsPass();
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +000050FunctionPass *createAMDGPUCodeGenPreparePass(const GCNTargetMachine *TM = nullptr);
Tom Stellard75aadc22012-12-11 21:25:42 +000051
Matt Arsenaulte823d922017-02-18 18:29:53 +000052ModulePass *createAMDGPUAnnotateKernelFeaturesPass(const TargetMachine *TM = nullptr);
Matt Arsenault39319482015-11-06 18:01:57 +000053void initializeAMDGPUAnnotateKernelFeaturesPass(PassRegistry &);
54extern char &AMDGPUAnnotateKernelFeaturesID;
55
Matt Arsenault0699ef32017-02-09 22:00:42 +000056ModulePass *createAMDGPULowerIntrinsicsPass();
57void initializeAMDGPULowerIntrinsicsPass(PassRegistry &);
58extern char &AMDGPULowerIntrinsicsID;
59
Tom Stellard6596ba72014-11-21 22:06:37 +000060void initializeSIFoldOperandsPass(PassRegistry &);
61extern char &SIFoldOperandsID;
62
Sam Koltonf60ad582017-03-21 12:51:34 +000063void initializeSIPeepholeSDWAPass(PassRegistry &);
64extern char &SIPeepholeSDWAID;
65
Matt Arsenaultc3a01ec2016-06-09 23:18:47 +000066void initializeSIShrinkInstructionsPass(PassRegistry&);
67extern char &SIShrinkInstructionsID;
68
Matt Arsenault782c03b2015-11-03 22:30:13 +000069void initializeSIFixSGPRCopiesPass(PassRegistry &);
70extern char &SIFixSGPRCopiesID;
71
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +000072void initializeSIFixVGPRCopiesPass(PassRegistry &);
73extern char &SIFixVGPRCopiesID;
74
Tom Stellard1bd80722014-04-30 15:31:33 +000075void initializeSILowerI1CopiesPass(PassRegistry &);
76extern char &SILowerI1CopiesID;
77
Matt Arsenault41033282014-10-10 22:01:59 +000078void initializeSILoadStoreOptimizerPass(PassRegistry &);
79extern char &SILoadStoreOptimizerID;
80
Nicolai Haehnle213e87f2016-03-21 20:28:33 +000081void initializeSIWholeQuadModePass(PassRegistry &);
82extern char &SIWholeQuadModeID;
83
Matt Arsenault55d49cf2016-02-12 02:16:10 +000084void initializeSILowerControlFlowPass(PassRegistry &);
Matt Arsenault78fc9da2016-08-22 19:33:16 +000085extern char &SILowerControlFlowID;
Matt Arsenault55d49cf2016-02-12 02:16:10 +000086
Matt Arsenault78fc9da2016-08-22 19:33:16 +000087void initializeSIInsertSkipsPass(PassRegistry &);
88extern char &SIInsertSkipsPassID;
Matt Arsenault55d49cf2016-02-12 02:16:10 +000089
Matt Arsenaulte6740752016-09-29 01:44:16 +000090void initializeSIOptimizeExecMaskingPass(PassRegistry &);
91extern char &SIOptimizeExecMaskingID;
92
Tom Stellard75aadc22012-12-11 21:25:42 +000093// Passes common to R600 and SI
Matt Arsenaulte0132462016-01-30 05:19:45 +000094FunctionPass *createAMDGPUPromoteAlloca(const TargetMachine *TM = nullptr);
95void initializeAMDGPUPromoteAllocaPass(PassRegistry&);
96extern char &AMDGPUPromoteAllocaID;
97
Tom Stellardf8794352012-12-19 22:10:31 +000098Pass *createAMDGPUStructurizeCFGPass();
Konstantin Zhuravlyov60a83732016-10-03 18:47:26 +000099FunctionPass *createAMDGPUISelDag(TargetMachine &TM,
100 CodeGenOpt::Level OptLevel);
Stanislav Mekhanoshin89653df2017-03-30 20:16:02 +0000101ModulePass *createAMDGPUAlwaysInlinePass(bool GlobalOpt = true);
Tom Stellardfd253952015-08-07 23:19:30 +0000102ModulePass *createAMDGPUOpenCLImageTypeLoweringPass();
Tom Stellarda6f24c62015-12-15 20:55:55 +0000103FunctionPass *createAMDGPUAnnotateUniformValues();
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000104
Stanislav Mekhanoshinf6c1feb2017-01-27 16:38:10 +0000105ModulePass* createAMDGPUUnifyMetadataPass();
Stanislav Mekhanoshin50ea93a2016-12-08 19:46:04 +0000106void initializeAMDGPUUnifyMetadataPass(PassRegistry&);
107extern char &AMDGPUUnifyMetadataID;
108
Tom Stellard28d13a42015-05-12 17:13:02 +0000109void initializeSIFixControlFlowLiveIntervalsPass(PassRegistry&);
110extern char &SIFixControlFlowLiveIntervalsID;
111
Tom Stellarda6f24c62015-12-15 20:55:55 +0000112void initializeAMDGPUAnnotateUniformValuesPass(PassRegistry&);
113extern char &AMDGPUAnnotateUniformValuesPassID;
Tom Stellardb2de94e2014-07-02 20:53:48 +0000114
Matt Arsenault86de4862016-06-24 07:07:55 +0000115void initializeAMDGPUCodeGenPreparePass(PassRegistry&);
116extern char &AMDGPUCodeGenPrepareID;
117
Tom Stellard77a17772016-01-20 15:48:27 +0000118void initializeSIAnnotateControlFlowPass(PassRegistry&);
119extern char &SIAnnotateControlFlowPassID;
120
Konstantin Zhuravlyova7919322016-05-10 18:33:41 +0000121void initializeSIDebuggerInsertNopsPass(PassRegistry&);
122extern char &SIDebuggerInsertNopsID;
Tom Stellardcc7067a62016-03-03 03:53:29 +0000123
Tom Stellard6e1967e2016-02-05 17:42:38 +0000124void initializeSIInsertWaitsPass(PassRegistry&);
125extern char &SIInsertWaitsID;
126
Matt Arsenaultb8f8dbc2017-03-24 19:52:05 +0000127void initializeAMDGPUUnifyDivergentExitNodesPass(PassRegistry&);
128extern char &AMDGPUUnifyDivergentExitNodesID;
129
Stanislav Mekhanoshin8e45acf2017-03-17 23:56:58 +0000130ImmutablePass *createAMDGPUAAWrapperPass();
131void initializeAMDGPUAAWrapperPassPass(PassRegistry&);
132
Mehdi Aminif42454b2016-10-09 23:00:34 +0000133Target &getTheAMDGPUTarget();
134Target &getTheGCNTarget();
Tom Stellard75aadc22012-12-11 21:25:42 +0000135
Tom Stellard067c8152014-07-21 14:01:14 +0000136namespace AMDGPU {
137enum TargetIndex {
Tom Stellard95292bb2015-01-20 17:49:47 +0000138 TI_CONSTDATA_START,
139 TI_SCRATCH_RSRC_DWORD0,
140 TI_SCRATCH_RSRC_DWORD1,
141 TI_SCRATCH_RSRC_DWORD2,
142 TI_SCRATCH_RSRC_DWORD3
Tom Stellard067c8152014-07-21 14:01:14 +0000143};
144}
145
Tom Stellard75aadc22012-12-11 21:25:42 +0000146} // End namespace llvm
147
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000148/// OpenCL uses address spaces to differentiate between
149/// various memory regions on the hardware. On the CPU
150/// all of the address spaces point to the same memory,
151/// however on the GPU, each address space points to
Alp Tokercb402912014-01-24 17:20:08 +0000152/// a separate piece of memory that is unique from other
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000153/// memory locations.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000154struct AMDGPUAS {
155 // The following address space values depend on the triple environment.
156 unsigned PRIVATE_ADDRESS; ///< Address space for private memory.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000157 unsigned FLAT_ADDRESS; ///< Address space for flat memory.
158 unsigned REGION_ADDRESS; ///< Address space for region memory.
159
160 // The maximum value for flat, generic, local, private, constant and region.
161 const static unsigned MAX_COMMON_ADDRESS = 5;
162
163 const static unsigned GLOBAL_ADDRESS = 1; ///< Address space for global memory (RAT0, VTX0).
Yaxun Liu76ae47c2017-04-06 19:17:32 +0000164 const static unsigned CONSTANT_ADDRESS = 2; ///< Address space for constant memory (VTX2)
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000165 const static unsigned LOCAL_ADDRESS = 3; ///< Address space for local memory.
166 const static unsigned PARAM_D_ADDRESS = 6; ///< Address space for direct addressible parameter memory (CONST0)
167 const static unsigned PARAM_I_ADDRESS = 7; ///< Address space for indirect addressible parameter memory (VTX1)
Tom Stellard1e803092013-07-23 01:48:18 +0000168
169 // Do not re-order the CONSTANT_BUFFER_* enums. Several places depend on this
170 // order to be able to dynamically index a constant buffer, for example:
171 //
172 // ConstantBufferAS = CONSTANT_BUFFER_0 + CBIdx
173
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000174 const static unsigned CONSTANT_BUFFER_0 = 8;
175 const static unsigned CONSTANT_BUFFER_1 = 9;
176 const static unsigned CONSTANT_BUFFER_2 = 10;
177 const static unsigned CONSTANT_BUFFER_3 = 11;
178 const static unsigned CONSTANT_BUFFER_4 = 12;
179 const static unsigned CONSTANT_BUFFER_5 = 13;
180 const static unsigned CONSTANT_BUFFER_6 = 14;
181 const static unsigned CONSTANT_BUFFER_7 = 15;
182 const static unsigned CONSTANT_BUFFER_8 = 16;
183 const static unsigned CONSTANT_BUFFER_9 = 17;
184 const static unsigned CONSTANT_BUFFER_10 = 18;
185 const static unsigned CONSTANT_BUFFER_11 = 19;
186 const static unsigned CONSTANT_BUFFER_12 = 20;
187 const static unsigned CONSTANT_BUFFER_13 = 21;
188 const static unsigned CONSTANT_BUFFER_14 = 22;
189 const static unsigned CONSTANT_BUFFER_15 = 23;
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000190
191 // Some places use this if the address space can't be determined.
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000192 const static unsigned UNKNOWN_ADDRESS_SPACE = ~0u;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000193};
194
Yaxun Liu1a14bfa2017-03-27 14:04:01 +0000195namespace llvm {
196namespace AMDGPU {
197AMDGPUAS getAMDGPUAS(const Module &M);
198AMDGPUAS getAMDGPUAS(const TargetMachine &TM);
199AMDGPUAS getAMDGPUAS(Triple T);
200} // namespace AMDGPU
201} // namespace llvm
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000202
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000203#endif