Ahmed Bougacha | 6756a2c | 2016-07-27 14:31:55 +0000 | [diff] [blame] | 1 | //===- llvm/CodeGen/GlobalISel/InstructionSelector.cpp -----------*- C++ -*-==// |
| 2 | // |
| 3 | // The LLVM Compiler Infrastructure |
| 4 | // |
| 5 | // This file is distributed under the University of Illinois Open Source |
| 6 | // License. See LICENSE.TXT for details. |
| 7 | // |
| 8 | //===----------------------------------------------------------------------===// |
| 9 | /// \file |
| 10 | /// This file implements the InstructionSelector class. |
| 11 | //===----------------------------------------------------------------------===// |
| 12 | |
| 13 | #include "llvm/CodeGen/GlobalISel/InstructionSelector.h" |
| 14 | #include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h" |
| 15 | #include "llvm/CodeGen/MachineInstr.h" |
| 16 | #include "llvm/Target/TargetInstrInfo.h" |
| 17 | #include "llvm/Target/TargetRegisterInfo.h" |
| 18 | |
| 19 | #define DEBUG_TYPE "instructionselector" |
| 20 | |
| 21 | using namespace llvm; |
| 22 | |
| 23 | InstructionSelector::InstructionSelector() {} |
| 24 | |
| 25 | bool InstructionSelector::constrainSelectedInstRegOperands( |
| 26 | MachineInstr &I, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI, |
| 27 | const RegisterBankInfo &RBI) const { |
| 28 | MachineBasicBlock &MBB = *I.getParent(); |
| 29 | MachineFunction &MF = *MBB.getParent(); |
| 30 | MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 31 | |
| 32 | for (unsigned OpI = 0, OpE = I.getNumExplicitOperands(); OpI != OpE; ++OpI) { |
| 33 | MachineOperand &MO = I.getOperand(OpI); |
Ahmed Bougacha | 6756a2c | 2016-07-27 14:31:55 +0000 | [diff] [blame] | 34 | |
Ahmed Bougacha | 7adfac5 | 2016-07-29 16:56:16 +0000 | [diff] [blame^] | 35 | // There's nothing to be done on immediates. |
| 36 | if (MO.isImm()) |
| 37 | continue; |
| 38 | |
| 39 | DEBUG(dbgs() << "Converting operand: " << MO << '\n'); |
| 40 | assert(MO.isReg() && "Unsupported non-reg operand"); |
Ahmed Bougacha | 6756a2c | 2016-07-27 14:31:55 +0000 | [diff] [blame] | 41 | |
| 42 | const TargetRegisterClass *RC = TII.getRegClass(I.getDesc(), OpI, &TRI, MF); |
| 43 | assert(RC && "Selected inst should have regclass operand"); |
| 44 | |
| 45 | // If the operand is a vreg, we should constrain its regclass, and only |
| 46 | // insert COPYs if that's impossible. |
| 47 | // If the operand is a physreg, we only insert COPYs if the register class |
| 48 | // doesn't contain the register. |
| 49 | if (RBI.constrainGenericRegister(MO.getReg(), *RC, MRI)) |
| 50 | continue; |
| 51 | |
| 52 | DEBUG(dbgs() << "Constraining with COPYs isn't implemented yet"); |
| 53 | return false; |
| 54 | } |
| 55 | return true; |
| 56 | } |