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gerrit-public.fairphone.software / toolchain / llvm-project / 81616a72ea53175f23931b34a1372c7cafb80736 / . / llvm / lib / Target / ARM / ARMISelLowering.h
blob: 047b7e5d1ffcd47b97407db5572595405b9b6cd3 [file] [log] [blame]
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]1//===-- ARMISelLowering.h - ARM DAG Lowering Interface ----------*- C++ -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the interfaces that ARM uses to lower LLVM code into a
11// selection DAG.
12//
13//===----------------------------------------------------------------------===//
14
Benjamin Kramera7c40ef2014-08-13 16:26:38 +0000[diff] [blame]15#ifndef LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
16#define LLVM_LIB_TARGET_ARM_ARMISELLOWERING_H
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]17
Craig Toppera9253262014-03-22 23:51:00 +0000[diff] [blame]18#include "MCTargetDesc/ARMBaseInfo.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]19#include "llvm/CodeGen/CallingConvLower.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]20#include "llvm/CodeGen/SelectionDAG.h"
Chandler Carruth802d7552012-12-04 07:12:27 +0000[diff] [blame]21#include "llvm/Target/TargetLowering.h"
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]22#include <vector>
23
24namespace llvm {
25 class ARMConstantPoolValue;
Craig Toppera9253262014-03-22 23:51:00 +0000[diff] [blame]26 class ARMSubtarget;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]27
28 namespace ARMISD {
29 // ARM Specific DAG Nodes
Matthias Braund04893f2015-05-07 21:33:59 +0000[diff] [blame]30 enum NodeType : unsigned {
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]31 // Start the numbering where the builtin ops and target ops leave off.
Dan Gohmaned1cf1a2008-09-23 18:42:32 +0000[diff] [blame]32 FIRST_NUMBER = ISD::BUILTIN_OP_END,
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]33
34 Wrapper, // Wrapper - A wrapper node for TargetConstantPool,
35 // TargetExternalSymbol, and TargetGlobalAddress.
Evan Chengdfce83c2011-01-17 08:03:18 +0000[diff] [blame]36 WrapperPIC, // WrapperPIC - A wrapper node for TargetGlobalAddress in
37 // PIC mode.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]38 WrapperJT, // WrapperJT - A wrapper node for TargetJumpTable
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]39
Manman Ren9f911162012-06-01 02:44:42 +0000[diff] [blame]40 // Add pseudo op to model memcpy for struct byval.
41 COPY_STRUCT_BYVAL,
42
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]43 CALL, // Function call.
Evan Chengc3c949b42007-06-19 21:05:09 +0000[diff] [blame]44 CALL_PRED, // Function call that's predicable.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]45 CALL_NOLINK, // Function call with branch not branch-and-link.
46 tCALL, // Thumb function call.
47 BRCOND, // Conditional branch.
48 BR_JT, // Jumptable branch.
Evan Chengc6d70ae2009-07-29 02:18:14 +0000[diff] [blame]49 BR2_JT, // Jumptable branch (2 level - jumptable entry is a jump).
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]50 RET_FLAG, // Return with a flag operand.
Tim Northoverd8407452013-10-01 14:33:28 +0000[diff] [blame]51 INTRET_FLAG, // Interrupt return with an LR-offset and a flag operand.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]52
53 PIC_ADD, // Add with a PC operand and a PIC label.
54
55 CMP, // ARM compare instructions.
Bill Wendling4b796472012-06-11 08:07:26 +0000[diff] [blame]56 CMN, // ARM CMN instructions.
David Goodwindbf11ba2009-06-29 15:33:01 +0000[diff] [blame]57 CMPZ, // ARM compare that sets only Z flag.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]58 CMPFP, // ARM VFP compare instruction, sets FPSCR.
59 CMPFPw0, // ARM VFP compare against zero instruction, sets FPSCR.
60 FMSTAT, // ARM fmstat instruction.
Evan Chenge87681c2012-02-23 01:19:06 +0000[diff] [blame]61
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]62 CMOV, // ARM conditional move instructions.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]63
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]64 BCC_i64,
65
Jim Grosbach8546ec92010-01-18 19:58:49 +0000[diff] [blame]66 RBIT, // ARM bitreverse instruction
67
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]68 SRL_FLAG, // V,Flag = srl_flag X -> srl X, 1 + save carry out.
69 SRA_FLAG, // V,Flag = sra_flag X -> sra X, 1 + save carry out.
70 RRX, // V = RRX X, Flag -> srl X, 1 + shift in carry flag.
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]71
Evan Chenge8916542011-08-30 01:34:54 +0000[diff] [blame]72 ADDC, // Add with carry
73 ADDE, // Add using carry
74 SUBC, // Sub with carry
75 SUBE, // Sub using carry
76
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000[diff] [blame]77 VMOVRRD, // double to two gprs.
78 VMOVDRR, // Two gprs to double.
Lauro Ramos Venancioc39c12a2007-04-27 13:54:47 +0000[diff] [blame]79
Jim Grosbachbbdc5d22010-10-19 23:27:08 +0000[diff] [blame]80 EH_SJLJ_SETJMP, // SjLj exception handling setjmp.
81 EH_SJLJ_LONGJMP, // SjLj exception handling longjmp.
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]82 EH_SJLJ_SETUP_DISPATCH, // SjLj exception handling setup_dispatch.
Jim Grosbachaeca45d2009-05-12 23:59:14 +0000[diff] [blame]83
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]84 TC_RETURN, // Tail call return pseudo.
85
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]86 THREAD_POINTER,
87
Evan Chengb972e562009-08-07 00:34:42 +0000[diff] [blame]88 DYN_ALLOC, // Dynamic allocation on the stack.
89
Bob Wilson7ed59712010-10-30 00:54:37 +0000[diff] [blame]90 MEMBARRIER_MCR, // Memory barrier (MCR)
Evan Cheng8740ee32010-11-03 06:34:55 +0000[diff] [blame]91
92 PRELOAD, // Preload
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]93
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]94 WIN__CHKSTK, // Windows' __chkstk call to do stack probing.
95
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]96 VCEQ, // Vector compare equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]97 VCEQZ, // Vector compare equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]98 VCGE, // Vector compare greater than or equal.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]99 VCGEZ, // Vector compare greater than or equal to zero.
100 VCLEZ, // Vector compare less than or equal to zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]101 VCGEU, // Vector compare unsigned greater than or equal.
102 VCGT, // Vector compare greater than.
Owen Andersonc7baee32010-11-08 23:21:22 +0000[diff] [blame]103 VCGTZ, // Vector compare greater than zero.
104 VCLTZ, // Vector compare less than zero.
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]105 VCGTU, // Vector compare unsigned greater than.
106 VTST, // Vector test bits.
107
108 // Vector shift by immediate:
109 VSHL, // ...left
110 VSHRs, // ...right (signed)
111 VSHRu, // ...right (unsigned)
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]112
113 // Vector rounding shift by immediate:
114 VRSHRs, // ...right (signed)
115 VRSHRu, // ...right (unsigned)
116 VRSHRN, // ...right narrow
117
118 // Vector saturating shift by immediate:
119 VQSHLs, // ...left (signed)
120 VQSHLu, // ...left (unsigned)
121 VQSHLsu, // ...left (signed to unsigned)
122 VQSHRNs, // ...right narrow (signed)
123 VQSHRNu, // ...right narrow (unsigned)
124 VQSHRNsu, // ...right narrow (signed to unsigned)
125
126 // Vector saturating rounding shift by immediate:
127 VQRSHRNs, // ...right narrow (signed)
128 VQRSHRNu, // ...right narrow (unsigned)
129 VQRSHRNsu, // ...right narrow (signed to unsigned)
130
131 // Vector shift and insert:
132 VSLI, // ...left
133 VSRI, // ...right
134
135 // Vector get lane (VMOV scalar to ARM core register)
136 // (These are used for 8- and 16-bit element types only.)
137 VGETLANEu, // zero-extend vector extract element
138 VGETLANEs, // sign-extend vector extract element
139
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]140 // Vector move immediate and move negated immediate:
Bob Wilsona3f19012010-07-13 21:16:48 +0000[diff] [blame]141 VMOVIMM,
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]142 VMVNIMM,
143
Evan Cheng7ca4b6e2011-11-15 02:12:34 +0000[diff] [blame]144 // Vector move f32 immediate:
145 VMOVFPIMM,
146
Bob Wilsonbad47f62010-07-14 06:31:50 +0000[diff] [blame]147 // Vector duplicate:
Bob Wilsoneb54d512009-08-14 05:13:08 +0000[diff] [blame]148 VDUP,
Bob Wilsoncce31f62009-08-14 05:08:32 +0000[diff] [blame]149 VDUPLANE,
Bob Wilsonf45dee32009-08-04 00:36:16 +0000[diff] [blame]150
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]151 // Vector shuffles:
Bob Wilson32cd8552009-08-19 17:03:43 +0000[diff] [blame]152 VEXT, // extract
Bob Wilsonea3a4022009-08-12 22:31:50 +0000[diff] [blame]153 VREV64, // reverse elements within 64-bit doublewords
154 VREV32, // reverse elements within 32-bit words
Anton Korobeynikov9a232f42009-08-21 12:41:24 +0000[diff] [blame]155 VREV16, // reverse elements within 16-bit halfwords
Bob Wilsona7062312009-08-21 20:54:19 +0000[diff] [blame]156 VZIP, // zip (interleave)
157 VUZP, // unzip (deinterleave)
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]158 VTRN, // transpose
Bill Wendlinge1fd78f2011-03-14 23:02:38 +0000[diff] [blame]159 VTBL1, // 1-register shuffle with mask
160 VTBL2, // 2-register shuffle with mask
Bob Wilsonc6c13a32010-02-18 06:05:53 +0000[diff] [blame]161
Bob Wilson38ab35a2010-09-01 23:50:19 +0000[diff] [blame]162 // Vector multiply long:
163 VMULLs, // ...signed
164 VMULLu, // ...unsigned
165
Arnold Schwaighoferf00fb1c2012-09-04 14:37:49 +0000[diff] [blame]166 UMLAL, // 64bit Unsigned Accumulate Multiply
167 SMLAL, // 64bit Signed Accumulate Multiply
168
Bob Wilsond8a9a042010-06-04 00:04:02 +0000[diff] [blame]169 // Operands of the standard BUILD_VECTOR node are not legalized, which
170 // is fine if BUILD_VECTORs are always lowered to shuffles or other
171 // operations, but for ARM some BUILD_VECTORs are legal as-is and their
172 // operands need to be legalized. Define an ARM-specific version of
173 // BUILD_VECTOR for this purpose.
174 BUILD_VECTOR,
175
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]176 // Bit-field insert
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]177 BFI,
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]178
Owen Anderson07473072010-11-03 22:44:51 +0000[diff] [blame]179 // Vector OR with immediate
Owen Anderson30c48922010-11-05 19:27:46 +0000[diff] [blame]180 VORRIMM,
181 // Vector AND with NOT of immediate
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]182 VBICIMM,
183
Cameron Zwarich53dd03d2011-03-30 23:01:21 +0000[diff] [blame]184 // Vector bitwise select
185 VBSL,
186
Bob Wilson2d790df2010-11-28 06:51:26 +0000[diff] [blame]187 // Vector load N-element structure to all lanes:
188 VLD2DUP = ISD::FIRST_TARGET_MEMORY_OPCODE,
189 VLD3DUP,
Bob Wilson06fce872011-02-07 17:43:21 +0000[diff] [blame]190 VLD4DUP,
191
192 // NEON loads with post-increment base updates:
193 VLD1_UPD,
194 VLD2_UPD,
195 VLD3_UPD,
196 VLD4_UPD,
197 VLD2LN_UPD,
198 VLD3LN_UPD,
199 VLD4LN_UPD,
200 VLD2DUP_UPD,
201 VLD3DUP_UPD,
202 VLD4DUP_UPD,
203
204 // NEON stores with post-increment base updates:
205 VST1_UPD,
206 VST2_UPD,
207 VST3_UPD,
208 VST4_UPD,
209 VST2LN_UPD,
210 VST3LN_UPD,
Amara Emersonb4ad2f32013-09-26 12:22:36 +0000[diff] [blame]211 VST4LN_UPD
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]212 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]213 }
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]214
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]215 /// Define some predicates that are used for node matching.
216 namespace ARM {
Jim Grosbach11013ed2010-07-16 23:05:05 +0000[diff] [blame]217 bool isBitFieldInvertedMask(unsigned v);
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]218 }
219
Bob Wilsondd0e2362009-05-20 16:30:25 +0000[diff] [blame]220 //===--------------------------------------------------------------------===//
Dale Johannesen8447d342007-03-20 00:30:56 +0000[diff] [blame]221 // ARMTargetLowering - ARM Implementation of the TargetLowering interface
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]222
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]223 class ARMTargetLowering : public TargetLowering {
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]224 public:
Eric Christopher1889fdc2015-01-29 00:19:39 +0000[diff] [blame]225 explicit ARMTargetLowering(const TargetMachine &TM,
226 const ARMSubtarget &STI);
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]227
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]228 unsigned getJumpTableEncoding() const override;
Eric Christopher824f42f2015-05-12 01:26:05 +0000[diff] [blame]229 bool useSoftFloat() const override;
Jim Grosbach8d3ba732010-07-19 17:20:38 +0000[diff] [blame]230
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]231 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]232
233 /// ReplaceNodeResults - Replace the results of node with an illegal result
234 /// type with new values built out of custom code.
235 ///
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]236 void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results,
237 SelectionDAG &DAG) const override;
Duncan Sands6ed40142008-12-01 11:39:25 +0000[diff] [blame]238
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]239 const char *getTargetNodeName(unsigned Opcode) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]240
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]241 bool isSelectSupported(SelectSupportKind Kind) const override {
Nadav Rotem9d832022012-09-02 12:10:19 +0000[diff] [blame]242 // ARM does not support scalar condition selects on vectors.
243 return (Kind != ScalarCondVectorVal);
244 }
245
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]246 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
Mehdi Amini44ede332015-07-09 02:09:04 +0000[diff] [blame]247 EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context,
248 EVT VT) const override;
Duncan Sandsf2641e12011-09-06 19:07:46 +0000[diff] [blame]249
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]250 MachineBasicBlock *
Dan Gohman25c16532010-05-01 00:01:06 +0000[diff] [blame]251 EmitInstrWithCustomInserter(MachineInstr *MI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]252 MachineBasicBlock *MBB) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]253
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]254 void AdjustInstrPostInstrSelection(MachineInstr *MI,
255 SDNode *Node) const override;
Evan Chenge6fba772011-08-30 19:09:48 +0000[diff] [blame]256
Evan Chengf863e3f2011-07-13 00:42:17 +0000[diff] [blame]257 SDValue PerformCMOVCombine(SDNode *N, SelectionDAG &DAG) const;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]258 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]259
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]260 bool isDesirableToTransformToIntegerOp(unsigned Opc, EVT VT) const override;
Evan Chengd42641c2011-02-02 01:06:55 +0000[diff] [blame]261
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]262 /// allowsMisalignedMemoryAccesses - Returns true if the target allows
Evan Cheng79e2ca92012-12-10 23:21:26 +0000[diff] [blame]263 /// unaligned memory accesses of the specified type. Returns whether it
264 /// is "fast" by reference in the second argument.
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000[diff] [blame]265 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
266 unsigned Align,
267 bool *Fast) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]268
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]269 EVT getOptimalMemOpType(uint64_t Size,
270 unsigned DstAlign, unsigned SrcAlign,
271 bool IsMemset, bool ZeroMemset,
272 bool MemcpyStrSrc,
273 MachineFunction &MF) const override;
Lang Hames9929c422011-11-02 22:52:45 +0000[diff] [blame]274
Matt Beaumont-Gay4a04c922012-12-06 23:15:36 +0000[diff] [blame]275 using TargetLowering::isZExtFree;
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]276 bool isZExtFree(SDValue Val, EVT VT2) const override;
Evan Cheng9ec512d2012-12-06 19:13:27 +0000[diff] [blame]277
Ahmed Bougacha4200cc92015-03-05 19:37:53 +0000[diff] [blame]278 bool isVectorLoadExtDesirable(SDValue ExtVal) const override;
279
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]280 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
Tim Northovercc2e9032013-08-06 13:58:03 +0000[diff] [blame]281
282
Chris Lattner1eb94d92007-03-30 23:15:24 +0000[diff] [blame]283 /// isLegalAddressingMode - Return true if the addressing mode represented
284 /// by AM is legal for this target, for a load/store of the specified type.
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000[diff] [blame]285 bool isLegalAddressingMode(const DataLayout &DL, const AddrMode &AM,
286 Type *Ty, unsigned AS) const override;
Evan Chengdc49a8d2009-08-14 20:09:37 +0000[diff] [blame]287 bool isLegalT2ScaledAddressingMode(const AddrMode &AM, EVT VT) const;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]288
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]289 /// isLegalICmpImmediate - Return true if the specified immediate is legal
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]290 /// icmp immediate, that is the target has icmp instructions which can
291 /// compare a register against the immediate without having to materialize
292 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]293 bool isLegalICmpImmediate(int64_t Imm) const override;
Evan Cheng3d3c24a2009-11-11 19:05:52 +0000[diff] [blame]294
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]295 /// isLegalAddImmediate - Return true if the specified immediate is legal
296 /// add immediate, that is the target has add instructions which can
297 /// add a register and the immediate without having to materialize
298 /// the immediate into a register.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]299 bool isLegalAddImmediate(int64_t Imm) const override;
Dan Gohman6136e942011-05-03 00:46:49 +0000[diff] [blame]300
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]301 /// getPreIndexedAddressParts - returns true by value, base pointer and
302 /// offset pointer and addressing mode by reference if the node's address
303 /// can be legally represented as pre-indexed load / store address.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]304 bool getPreIndexedAddressParts(SDNode *N, SDValue &Base, SDValue &Offset,
305 ISD::MemIndexedMode &AM,
306 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]307
308 /// getPostIndexedAddressParts - returns true by value, base pointer and
309 /// offset pointer and addressing mode by reference if this node can be
310 /// combined with a load / store to form a post-indexed load / store.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]311 bool getPostIndexedAddressParts(SDNode *N, SDNode *Op, SDValue &Base,
312 SDValue &Offset, ISD::MemIndexedMode &AM,
313 SelectionDAG &DAG) const override;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]314
Jay Foada0653a32014-05-14 21:14:37 +0000[diff] [blame]315 void computeKnownBitsForTargetNode(const SDValue Op, APInt &KnownZero,
316 APInt &KnownOne,
317 const SelectionDAG &DAG,
318 unsigned Depth) const override;
Bill Wendlingbae6b2c2009-08-15 21:21:19 +0000[diff] [blame]319
320
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]321 bool ExpandInlineAsm(CallInst *CI) const override;
Evan Cheng078b0b02011-01-08 01:24:27 +0000[diff] [blame]322
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]323 ConstraintType getConstraintType(StringRef Constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]324
325 /// Examine constraint string and operand type and determine a weight value.
326 /// The operand object must already have been set up with the operand type.
327 ConstraintWeight getSingleConstraintMatchWeight(
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]328 AsmOperandInfo &info, const char *constraint) const override;
John Thompsone8360b72010-10-29 17:29:13 +0000[diff] [blame]329
Eric Christopher11e4df72015-02-26 22:38:43 +0000[diff] [blame]330 std::pair<unsigned, const TargetRegisterClass *>
331 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]332 StringRef Constraint, MVT VT) const override;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]333
Bob Wilsoncf1ec2c2009-04-01 17:58:54 +0000[diff] [blame]334 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
335 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
336 /// true it means one of the asm constraint of the inline asm instruction
337 /// being processed is 'm'.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]338 void LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
339 std::vector<SDValue> &Ops,
340 SelectionDAG &DAG) const override;
Jim Grosbach91fa7812009-05-13 22:32:43 +0000[diff] [blame]341
Benjamin Kramer9bfb6272015-07-05 19:29:18 +0000[diff] [blame]342 unsigned
343 getInlineAsmMemConstraint(StringRef ConstraintCode) const override {
Daniel Sanders1f58ef72015-06-03 12:33:56 +0000[diff] [blame]344 if (ConstraintCode == "Q")
345 return InlineAsm::Constraint_Q;
346 else if (ConstraintCode.size() == 2) {
347 if (ConstraintCode[0] == 'U') {
348 switch(ConstraintCode[1]) {
349 default:
350 break;
351 case 'm':
352 return InlineAsm::Constraint_Um;
353 case 'n':
354 return InlineAsm::Constraint_Un;
355 case 'q':
356 return InlineAsm::Constraint_Uq;
357 case 's':
358 return InlineAsm::Constraint_Us;
359 case 't':
360 return InlineAsm::Constraint_Ut;
361 case 'v':
362 return InlineAsm::Constraint_Uv;
363 case 'y':
364 return InlineAsm::Constraint_Uy;
365 }
366 }
367 }
368 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
Daniel Sandersbf5b80f2015-03-16 13:13:41 +0000[diff] [blame]369 }
370
Dan Gohman4df9d9c2010-05-11 16:21:03 +0000[diff] [blame]371 const ARMSubtarget* getSubtarget() const {
Dan Gohman544ab2c2008-04-12 04:36:06 +0000[diff] [blame]372 return Subtarget;
Rafael Espindolafa0df552007-11-05 23:12:20 +0000[diff] [blame]373 }
374
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]375 /// getRegClassFor - Return the register class that should be used for the
376 /// specified value type.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]377 const TargetRegisterClass *getRegClassFor(MVT VT) const override;
Evan Cheng4cad68e2010-05-15 02:18:07 +0000[diff] [blame]378
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]379 /// Returns true if a cast between SrcAS and DestAS is a noop.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]380 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
James Molloy8a259922013-12-03 11:23:11 +0000[diff] [blame]381 // Addrspacecasts are always noops.
382 return true;
383 }
384
John Brawn0dbcd652015-03-18 12:01:59 +0000[diff] [blame]385 bool shouldAlignPointerArgs(CallInst *CI, unsigned &MinSize,
386 unsigned &PrefAlign) const override;
387
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]388 /// createFastISel - This method returns a target specific FastISel object,
389 /// or null if the target does not support "fast" ISel.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]390 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
391 const TargetLibraryInfo *libInfo) const override;
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]392
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]393 Sched::Preference getSchedulingPreference(SDNode *N) const override;
Evan Cheng4401f882010-05-20 23:26:43 +0000[diff] [blame]394
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]395 bool
396 isShuffleMaskLegal(const SmallVectorImpl<int> &M, EVT VT) const override;
397 bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]398
399 /// isFPImmLegal - Returns true if the target can instruction select the
400 /// specified FP immediate natively. If false, the legalizer will
401 /// materialize the FP immediate as a load from a constant pool.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]402 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
Evan Cheng4a609f3c2009-10-28 01:44:26 +0000[diff] [blame]403
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]404 bool getTgtMemIntrinsic(IntrinsicInfo &Info,
405 const CallInst &I,
406 unsigned Intrinsic) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]407
408 /// \brief Returns true if it is beneficial to convert a load of a constant
409 /// to just the constant itself.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]410 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
411 Type *Ty) const override;
Juergen Ributzka659ce002014-01-28 01:20:14 +0000[diff] [blame]412
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]413 /// \brief Returns true if an argument of type Ty needs to be passed in a
414 /// contiguous block of registers in calling convention CallConv.
415 bool functionArgumentNeedsConsecutiveRegisters(
416 Type *Ty, CallingConv::ID CallConv, bool isVarArg) const override;
417
Robin Morisset5349e8e2014-09-18 18:56:04 +0000[diff] [blame]418 Instruction *makeDMB(IRBuilder<> &Builder, ARM_MB::MemBOpt Domain) const;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]419 Value *emitLoadLinked(IRBuilder<> &Builder, Value *Addr,
420 AtomicOrdering Ord) const override;
421 Value *emitStoreConditional(IRBuilder<> &Builder, Value *Val,
422 Value *Addr, AtomicOrdering Ord) const override;
423
Ahmed Bougacha81616a72015-09-22 17:22:58 +0000[diff] [blame^]424 void emitAtomicCmpXchgNoStoreLLBalance(IRBuilder<> &Builder) const override;
425
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]426 Instruction* emitLeadingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]427 bool IsStore, bool IsLoad) const override;
Robin Morissetdedef332014-09-23 20:31:14 +0000[diff] [blame]428 Instruction* emitTrailingFence(IRBuilder<> &Builder, AtomicOrdering Ord,
Robin Morisseta47cb412014-09-03 21:01:03 +0000[diff] [blame]429 bool IsStore, bool IsLoad) const override;
430
Hao Liu2cd34bb2015-06-26 02:45:36 +0000[diff] [blame]431 unsigned getMaxSupportedInterleaveFactor() const override { return 4; }
432
433 bool lowerInterleavedLoad(LoadInst *LI,
434 ArrayRef<ShuffleVectorInst *> Shuffles,
435 ArrayRef<unsigned> Indices,
436 unsigned Factor) const override;
437 bool lowerInterleavedStore(StoreInst *SI, ShuffleVectorInst *SVI,
438 unsigned Factor) const override;
439
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]440 TargetLoweringBase::AtomicExpansionKind
441 shouldExpandAtomicLoadInIR(LoadInst *LI) const override;
Robin Morisseted3d48f2014-09-03 21:29:59 +0000[diff] [blame]442 bool shouldExpandAtomicStoreInIR(StoreInst *SI) const override;
Ahmed Bougacha9d677132015-09-11 17:08:17 +0000[diff] [blame]443 TargetLoweringBase::AtomicExpansionKind
JF Bastienf14889e2015-03-04 15:47:57 +0000[diff] [blame]444 shouldExpandAtomicRMWInIR(AtomicRMWInst *AI) const override;
Ahmed Bougacha52468672015-09-11 17:08:28 +0000[diff] [blame]445 bool shouldExpandAtomicCmpXchgInIR(AtomicCmpXchgInst *AI) const override;
Tim Northover037f26f22014-04-17 18:22:47 +0000[diff] [blame]446
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]447 bool useLoadStackGuardNode() const override;
448
Quentin Colombetc32615d2014-10-31 17:52:53 +0000[diff] [blame]449 bool canCombineStoreAndExtract(Type *VectorTy, Value *Idx,
450 unsigned &Cost) const override;
451
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]452 protected:
Eric Christopher23a3a7c2015-02-26 00:00:24 +0000[diff] [blame]453 std::pair<const TargetRegisterClass *, uint8_t>
454 findRepresentativeClass(const TargetRegisterInfo *TRI,
455 MVT VT) const override;
Evan Cheng10f99a32010-07-19 22:15:08 +0000[diff] [blame]456
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]457 private:
458 /// Subtarget - Keep a pointer to the ARMSubtarget around so that we can
459 /// make the right decision when generating code for different targets.
460 const ARMSubtarget *Subtarget;
461
Evan Chengdf907f42010-07-23 22:39:59 +0000[diff] [blame]462 const TargetRegisterInfo *RegInfo;
463
Evan Chengbf407072010-09-10 01:29:16 +0000[diff] [blame]464 const InstrItineraryData *Itins;
465
Bob Wilson844d6c82009-07-13 18:11:36 +0000[diff] [blame]466 /// ARMPCLabelIndex - Keep track of the number of ARM PC labels created.
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]467 ///
468 unsigned ARMPCLabelIndex;
469
Craig Topper4fa625f2012-08-12 03:16:37 +0000[diff] [blame]470 void addTypeForNEON(MVT VT, MVT PromotedLdStVT, MVT PromotedBitwiseVT);
471 void addDRTypeForNEON(MVT VT);
472 void addQRTypeForNEON(MVT VT);
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]473 std::pair<SDValue, SDValue> getARMXALUOOp(SDValue Op, SelectionDAG &DAG, SDValue &ARMcc) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]474
475 typedef SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPassVector;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]476 void PassF64ArgInRegs(SDLoc dl, SelectionDAG &DAG,
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]477 SDValue Chain, SDValue &Arg,
478 RegsToPassVector &RegsToPass,
479 CCValAssign &VA, CCValAssign &NextVA,
480 SDValue &StackPtr,
Craig Topperb94011f2013-07-14 04:42:23 +0000[diff] [blame]481 SmallVectorImpl<SDValue> &MemOpChains,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]482 ISD::ArgFlagsTy Flags) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]483 SDValue GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]484 SDValue &Root, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]485 SDLoc dl) const;
Bob Wilson2e076c42009-06-22 23:27:02 +0000[diff] [blame]486
Oliver Stannardc24f2172014-05-09 14:01:47 +0000[diff] [blame]487 CallingConv::ID getEffectiveCallingConv(CallingConv::ID CC,
488 bool isVarArg) const;
Jim Grosbach84511e12010-06-02 21:53:11 +0000[diff] [blame]489 CCAssignFn *CCAssignFnForNode(CallingConv::ID CC, bool Return,
490 bool isVarArg) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]491 SDValue LowerMemOpCallTo(SDValue Chain, SDValue StackPtr, SDValue Arg,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]492 SDLoc dl, SelectionDAG &DAG,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]493 const CCValAssign &VA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]494 ISD::ArgFlagsTy Flags) const;
Jim Grosbachc98892f2010-05-26 20:22:18 +0000[diff] [blame]495 SDValue LowerEH_SJLJ_SETJMP(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbachbd9485d2010-05-22 01:06:18 +0000[diff] [blame]496 SDValue LowerEH_SJLJ_LONGJMP(SDValue Op, SelectionDAG &DAG) const;
Matthias Braun3cd00c12015-07-16 22:34:16 +0000[diff] [blame]497 SDValue LowerEH_SJLJ_SETUP_DISPATCH(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbacha570d052010-02-08 23:22:00 +0000[diff] [blame]498 SDValue LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]499 const ARMSubtarget *Subtarget) const;
500 SDValue LowerBlockAddress(SDValue Op, SelectionDAG &DAG) const;
501 SDValue LowerGlobalAddressDarwin(SDValue Op, SelectionDAG &DAG) const;
502 SDValue LowerGlobalAddressELF(SDValue Op, SelectionDAG &DAG) const;
Saleem Abdulrasool40bca0a2014-05-09 00:58:32 +0000[diff] [blame]503 SDValue LowerGlobalAddressWindows(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]504 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]505 SDValue LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]506 SelectionDAG &DAG) const;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]507 SDValue LowerToTLSExecModels(GlobalAddressSDNode *GA,
Hans Wennborgaea41202012-05-04 09:40:39 +0000[diff] [blame]508 SelectionDAG &DAG,
509 TLSModel::Model model) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]510 SDValue LowerGLOBAL_OFFSET_TABLE(SDValue Op, SelectionDAG &DAG) const;
511 SDValue LowerBR_JT(SDValue Op, SelectionDAG &DAG) const;
Louis Gerbarg3342bf12014-05-09 17:02:49 +0000[diff] [blame]512 SDValue LowerXALUO(SDValue Op, SelectionDAG &DAG) const;
Bill Wendling6a981312010-08-11 08:43:16 +0000[diff] [blame]513 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]514 SDValue LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
515 SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng25f93642010-07-08 02:08:50 +0000[diff] [blame]516 SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
Evan Cheng168ced92010-05-22 01:47:14 +0000[diff] [blame]517 SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]518 SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
Dan Gohman21cea8a2010-04-17 15:26:15 +0000[diff] [blame]519 SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
520 SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
Nate Begemanb69b1822010-08-03 21:31:55 +0000[diff] [blame]521 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
Lang Hamesc35ee8b2012-03-15 18:49:02 +0000[diff] [blame]522 SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
523 const ARMSubtarget *ST) const;
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]524 SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]525 const ARMSubtarget *ST) const;
Bob Wilsone7dde0c2013-11-03 06:14:38 +0000[diff] [blame]526 SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
Renato Golin87610692013-07-16 09:32:17 +0000[diff] [blame]527 SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
Scott Douglassbdef6042015-08-24 09:17:18 +0000[diff] [blame]528 SDValue LowerREM(SDNode *N, SelectionDAG &DAG) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]529 SDValue LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]530 SDValue LowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const;
531 SDValue LowerFP_EXTEND(SDValue Op, SelectionDAG &DAG) const;
532 SDValue LowerFP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
533 SDValue LowerINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]534
Pat Gavlina717f252015-07-09 17:40:29 +0000[diff] [blame]535 unsigned getRegisterByName(const char* RegName, EVT VT,
536 SelectionDAG &DAG) const override;
Renato Golinc7aea402014-05-06 16:51:25 +0000[diff] [blame]537
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]538 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
539 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
540 /// expanded to FMAs when this method returns true, otherwise fmuladd is
541 /// expanded to fmul + fadd.
542 ///
543 /// ARM supports both fused and unfused multiply-add operations; we already
Stephen Lin2a644732013-07-10 01:57:39 +0000[diff] [blame]544 /// lower a pair of fmul and fadd to the latter so it's not clear that there
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]545 /// would be a gain or that the gain would be worthwhile enough to risk
546 /// correctness bugs.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]547 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override { return false; }
Stephen Lindd502022013-07-10 01:54:24 +0000[diff] [blame]548
Bob Wilson6f2b8962011-01-07 21:37:30 +0000[diff] [blame]549 SDValue ReconstructShuffle(SDValue Op, SelectionDAG &DAG) const;
Rafael Espindola18a831d2007-10-19 14:35:17 +0000[diff] [blame]550
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]551 SDValue LowerCallResult(SDValue Chain, SDValue InFlag,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]552 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]553 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]554 SDLoc dl, SelectionDAG &DAG,
Stephen Linb8bd2322013-04-20 05:14:40 +0000[diff] [blame]555 SmallVectorImpl<SDValue> &InVals,
556 bool isThisReturn, SDValue ThisVal) const;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]557
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]558 SDValue
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]559 LowerFormalArguments(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]560 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]561 const SmallVectorImpl<ISD::InputArg> &Ins,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]562 SDLoc dl, SelectionDAG &DAG,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]563 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]564
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]565 int StoreByValRegs(CCState &CCInfo, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]566 SDLoc dl, SDValue &Chain,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]567 const Value *OrigArg,
Stepan Dyatkovskiy8c02c982013-05-05 07:48:36 +0000[diff] [blame]568 unsigned InRegsParamRecordIdx,
Tim Northover8cda34f2015-03-11 18:54:22 +0000[diff] [blame]569 int ArgOffset,
570 unsigned ArgSize) const;
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]571
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]572 void VarArgStyleRegisters(CCState &CCInfo, SelectionDAG &DAG,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]573 SDLoc dl, SDValue &Chain,
Stepan Dyatkovskiydab80432012-10-19 08:23:06 +0000[diff] [blame]574 unsigned ArgOffset,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]575 unsigned TotalArgRegsSaveSize,
Stepan Dyatkovskiyf5aa83d2013-04-30 07:19:58 +0000[diff] [blame]576 bool ForceMutable = false) const;
Stuart Hastings45fe3c32011-04-20 16:47:52 +0000[diff] [blame]577
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]578 SDValue
Justin Holewinskiaa583972012-05-25 16:35:28 +0000[diff] [blame]579 LowerCall(TargetLowering::CallLoweringInfo &CLI,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]580 SmallVectorImpl<SDValue> &InVals) const override;
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]581
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]582 /// HandleByVal - Target-specific cleanup for ByVal support.
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]583 void HandleByVal(CCState *, unsigned &, unsigned) const override;
Stuart Hastings67c5c3e2011-02-28 17:17:53 +0000[diff] [blame]584
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]585 /// IsEligibleForTailCallOptimization - Check whether the call is eligible
586 /// for tail call optimization. Targets which want to do tail call
587 /// optimization should implement this function.
588 bool IsEligibleForTailCallOptimization(SDValue Callee,
589 CallingConv::ID CalleeCC,
590 bool isVarArg,
591 bool isCalleeStructRet,
592 bool isCallerStructRet,
593 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]594 const SmallVectorImpl<SDValue> &OutVals,
Dale Johannesend679ff72010-06-03 21:09:53 +0000[diff] [blame]595 const SmallVectorImpl<ISD::InputArg> &Ins,
596 SelectionDAG& DAG) const;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]597
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]598 bool CanLowerReturn(CallingConv::ID CallConv,
599 MachineFunction &MF, bool isVarArg,
600 const SmallVectorImpl<ISD::OutputArg> &Outs,
601 LLVMContext &Context) const override;
Benjamin Kramerb1996da2012-11-28 20:55:10 +0000[diff] [blame]602
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]603 SDValue
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]604 LowerReturn(SDValue Chain,
Sandeep Patel68c5f472009-09-02 08:44:58 +0000[diff] [blame]605 CallingConv::ID CallConv, bool isVarArg,
Dan Gohmanf9bbcd12009-08-05 01:29:28 +0000[diff] [blame]606 const SmallVectorImpl<ISD::OutputArg> &Outs,
Dan Gohmanfe7532a2010-07-07 15:54:55 +0000[diff] [blame]607 const SmallVectorImpl<SDValue> &OutVals,
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]608 SDLoc dl, SelectionDAG &DAG) const override;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]609
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]610 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
Evan Chengd4b08732010-11-30 23:55:39 +0000[diff] [blame]611
Craig Topper6bc27bf2014-03-10 02:09:33 +0000[diff] [blame]612 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
Evan Cheng0663f232011-03-21 01:19:09 +0000[diff] [blame]613
Oliver Stannard51b1d462014-08-21 12:50:31 +0000[diff] [blame]614 SDValue getCMOV(SDLoc dl, EVT VT, SDValue FalseVal, SDValue TrueVal,
615 SDValue ARMcc, SDValue CCR, SDValue Cmp,
616 SelectionDAG &DAG) const;
Evan Cheng15b80e42009-11-12 07:13:11 +0000[diff] [blame]617 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]618 SDValue &ARMcc, SelectionDAG &DAG, SDLoc dl) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]619 SDValue getVFPCmp(SDValue LHS, SDValue RHS,
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]620 SelectionDAG &DAG, SDLoc dl) const;
Bob Wilson45acbd02011-03-08 01:17:20 +0000[diff] [blame]621 SDValue duplicateCmp(SDValue Cmp, SelectionDAG &DAG) const;
Evan Cheng0cc4ad92010-07-13 19:27:42 +0000[diff] [blame]622
623 SDValue OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const;
Jim Grosbach5c4e99f2009-12-11 01:42:04 +0000[diff] [blame]624
Bill Wendling030b58e2011-10-06 22:18:16 +0000[diff] [blame]625 void SetupEntryBlockForSjLj(MachineInstr *MI,
626 MachineBasicBlock *MBB,
627 MachineBasicBlock *DispatchBB, int FI) const;
628
Matthias Brauneec4efc2015-04-28 00:37:05 +0000[diff] [blame]629 void EmitSjLjDispatchBlock(MachineInstr *MI, MachineBasicBlock *MBB) const;
Bill Wendling374ee192011-10-03 21:25:38 +0000[diff] [blame]630
Andrew Trick0ed57782011-04-23 03:55:32 +0000[diff] [blame]631 bool RemapAddSubWithFlags(MachineInstr *MI, MachineBasicBlock *BB) const;
Manman Rene8735522012-06-01 19:33:18 +0000[diff] [blame]632
633 MachineBasicBlock *EmitStructByval(MachineInstr *MI,
634 MachineBasicBlock *MBB) const;
Saleem Abdulrasoolabac6e92014-06-09 20:18:42 +0000[diff] [blame]635
636 MachineBasicBlock *EmitLowered__chkstk(MachineInstr *MI,
637 MachineBasicBlock *MBB) const;
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]638 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]639
Owen Andersona4076922010-11-05 21:57:54 +0000[diff] [blame]640 enum NEONModImmType {
641 VMOVModImm,
642 VMVNModImm,
643 OtherModImm
644 };
Andrew Trick1a1f8d42011-04-23 03:24:11 +0000[diff] [blame]645
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]646 namespace ARM {
Bob Wilson3e6fa462012-08-03 04:06:28 +0000[diff] [blame]647 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
648 const TargetLibraryInfo *libInfo);
Eric Christopher84bdfd82010-07-21 22:26:11 +0000[diff] [blame]649 }
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]650}
Evan Cheng10043e22007-01-19 07:51:42 +0000[diff] [blame]651
652#endif // ARMISELLOWERING_H