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Chris Lattner71eb0772009-10-19 20:20:46 +00001//===-- ARMAsmPrinter.cpp - Print machine code to an ARM .s file ----------===//
2//
Rafael Espindolaffdc24b2006-05-14 22:18:28 +00003// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
Rafael Espindolaffdc24b2006-05-14 22:18:28 +00006// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains a printer that converts from our internal representation
11// of machine-dependent LLVM code to GAS-format ARM assembly language.
12//
13//===----------------------------------------------------------------------===//
14
Chris Lattner1ef9cd42006-12-19 22:59:26 +000015#define DEBUG_TYPE "asm-printer"
Jim Grosbachd0d13292010-12-01 03:45:07 +000016#include "ARMAsmPrinter.h"
Craig Topper188ed9d2012-03-17 07:33:42 +000017#include "ARM.h"
Amara Emersond9104c02013-05-03 23:57:17 +000018#include "ARMBuildAttrs.h"
Evan Chenge45d6852011-01-11 21:46:47 +000019#include "ARMConstantPoolValue.h"
Chris Lattner71eb0772009-10-19 20:20:46 +000020#include "ARMMachineFunctionInfo.h"
Chris Lattner71eb0772009-10-19 20:20:46 +000021#include "ARMTargetMachine.h"
Jason W Kim109ff292010-10-11 23:01:44 +000022#include "ARMTargetObjectFile.h"
Evan Chenge45d6852011-01-11 21:46:47 +000023#include "InstPrinter/ARMInstPrinter.h"
Evan Chenga20cde32011-07-20 23:34:39 +000024#include "MCTargetDesc/ARMAddressingModes.h"
25#include "MCTargetDesc/ARMMCExpr.h"
Jim Grosbach330840f2012-10-04 21:33:24 +000026#include "llvm/ADT/SetVector.h"
27#include "llvm/ADT/SmallString.h"
Dan Gohmanef3d4572009-08-13 01:36:44 +000028#include "llvm/Assembly/Writer.h"
Rafael Espindolaffdc24b2006-05-14 22:18:28 +000029#include "llvm/CodeGen/MachineFunctionPass.h"
Evan Cheng10043e22007-01-19 07:51:42 +000030#include "llvm/CodeGen/MachineJumpTableInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000031#include "llvm/CodeGen/MachineModuleInfoImpls.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000032#include "llvm/DebugInfo.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000033#include "llvm/IR/Constants.h"
34#include "llvm/IR/DataLayout.h"
35#include "llvm/IR/Module.h"
36#include "llvm/IR/Type.h"
Chris Lattner6462adc2009-10-19 18:38:33 +000037#include "llvm/MC/MCAsmInfo.h"
Rafael Espindola0ed15432010-10-25 17:50:35 +000038#include "llvm/MC/MCAssembler.h"
Chris Lattner6462adc2009-10-19 18:38:33 +000039#include "llvm/MC/MCContext.h"
Jack Carter718da0b2013-01-30 02:24:33 +000040#include "llvm/MC/MCELFStreamer.h"
Chris Lattner71eb0772009-10-19 20:20:46 +000041#include "llvm/MC/MCInst.h"
Benjamin Kramer4e629f72012-11-26 13:34:22 +000042#include "llvm/MC/MCInstBuilder.h"
Rafael Espindola0ed15432010-10-25 17:50:35 +000043#include "llvm/MC/MCObjectStreamer.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000044#include "llvm/MC/MCSectionMachO.h"
Chris Lattner4b7dadb2009-08-19 05:49:37 +000045#include "llvm/MC/MCStreamer.h"
Chris Lattner4cd44982009-09-13 17:14:04 +000046#include "llvm/MC/MCSymbol.h"
Chris Lattner71eb0772009-10-19 20:20:46 +000047#include "llvm/Support/CommandLine.h"
Devang Patela52ddc42010-08-04 22:39:39 +000048#include "llvm/Support/Debug.h"
Jack Carter718da0b2013-01-30 02:24:33 +000049#include "llvm/Support/ELF.h"
Torok Edwinf8d479c2009-07-08 20:55:50 +000050#include "llvm/Support/ErrorHandling.h"
Evan Cheng2bb40352011-08-24 18:08:43 +000051#include "llvm/Support/TargetRegistry.h"
Chris Lattnerd20699b2010-04-04 08:18:47 +000052#include "llvm/Support/raw_ostream.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000053#include "llvm/Target/Mangler.h"
54#include "llvm/Target/TargetMachine.h"
Rafael Espindolaffdc24b2006-05-14 22:18:28 +000055#include <cctype>
Rafael Espindolaffdc24b2006-05-14 22:18:28 +000056using namespace llvm;
57
Chris Lattner1ef9cd42006-12-19 22:59:26 +000058namespace {
Rafael Espindola0ed15432010-10-25 17:50:35 +000059
60 // Per section and per symbol attributes are not supported.
61 // To implement them we would need the ability to delay this emission
62 // until the assembly file is fully parsed/generated as only then do we
63 // know the symbol and section numbers.
64 class AttributeEmitter {
65 public:
66 virtual void MaybeSwitchVendor(StringRef Vendor) = 0;
67 virtual void EmitAttribute(unsigned Attribute, unsigned Value) = 0;
Jason W Kim85b0af12011-02-07 00:49:53 +000068 virtual void EmitTextAttribute(unsigned Attribute, StringRef String) = 0;
Rafael Espindola0ed15432010-10-25 17:50:35 +000069 virtual void Finish() = 0;
Rafael Espindola752913d2010-10-25 18:38:32 +000070 virtual ~AttributeEmitter() {}
Rafael Espindola0ed15432010-10-25 17:50:35 +000071 };
72
73 class AsmAttributeEmitter : public AttributeEmitter {
74 MCStreamer &Streamer;
75
76 public:
77 AsmAttributeEmitter(MCStreamer &Streamer_) : Streamer(Streamer_) {}
78 void MaybeSwitchVendor(StringRef Vendor) { }
79
80 void EmitAttribute(unsigned Attribute, unsigned Value) {
81 Streamer.EmitRawText("\t.eabi_attribute " +
82 Twine(Attribute) + ", " + Twine(Value));
83 }
84
Jason W Kim85b0af12011-02-07 00:49:53 +000085 void EmitTextAttribute(unsigned Attribute, StringRef String) {
86 switch (Attribute) {
Craig Toppere55c5562012-02-07 02:50:20 +000087 default: llvm_unreachable("Unsupported Text attribute in ASM Mode");
Jason W Kim85b0af12011-02-07 00:49:53 +000088 case ARMBuildAttrs::CPU_name:
Benjamin Kramer20baffb2011-11-06 20:37:06 +000089 Streamer.EmitRawText(StringRef("\t.cpu ") + String.lower());
Jason W Kim85b0af12011-02-07 00:49:53 +000090 break;
Renato Golinec0fc7d2011-02-28 22:04:27 +000091 /* GAS requires .fpu to be emitted regardless of EABI attribute */
92 case ARMBuildAttrs::Advanced_SIMD_arch:
Amara Emersond9104c02013-05-03 23:57:17 +000093 case ARMBuildAttrs::VFP_arch:
Benjamin Kramer20baffb2011-11-06 20:37:06 +000094 Streamer.EmitRawText(StringRef("\t.fpu ") + String.lower());
Jim Grosbach05dec8b12011-09-02 18:46:15 +000095 break;
Jason W Kim85b0af12011-02-07 00:49:53 +000096 }
97 }
Rafael Espindola0ed15432010-10-25 17:50:35 +000098 void Finish() { }
99 };
100
101 class ObjectAttributeEmitter : public AttributeEmitter {
Renato Golinfaff5122011-08-09 09:50:10 +0000102 // This structure holds all attributes, accounting for
103 // their string/numeric value, so we can later emmit them
104 // in declaration order, keeping all in the same vector
105 struct AttributeItemType {
106 enum {
107 HiddenAttribute = 0,
108 NumericAttribute,
109 TextAttribute
110 } Type;
111 unsigned Tag;
112 unsigned IntValue;
113 StringRef StringValue;
114 } AttributeItem;
115
Rafael Espindola0ed15432010-10-25 17:50:35 +0000116 MCObjectStreamer &Streamer;
Rafael Espindola0ed15432010-10-25 17:50:35 +0000117 StringRef CurrentVendor;
Renato Golinfaff5122011-08-09 09:50:10 +0000118 SmallVector<AttributeItemType, 64> Contents;
119
120 // Account for the ULEB/String size of each item,
121 // not just the number of items
122 size_t ContentsSize;
123 // FIXME: this should be in a more generic place, but
124 // getULEBSize() is in MCAsmInfo and will be moved to MCDwarf
125 size_t getULEBSize(int Value) {
126 size_t Size = 0;
127 do {
128 Value >>= 7;
129 Size += sizeof(int8_t); // Is this really necessary?
130 } while (Value);
131 return Size;
132 }
Rafael Espindola0ed15432010-10-25 17:50:35 +0000133
134 public:
135 ObjectAttributeEmitter(MCObjectStreamer &Streamer_) :
Renato Golinfaff5122011-08-09 09:50:10 +0000136 Streamer(Streamer_), CurrentVendor(""), ContentsSize(0) { }
Rafael Espindola0ed15432010-10-25 17:50:35 +0000137
138 void MaybeSwitchVendor(StringRef Vendor) {
139 assert(!Vendor.empty() && "Vendor cannot be empty.");
140
141 if (CurrentVendor.empty())
142 CurrentVendor = Vendor;
143 else if (CurrentVendor == Vendor)
144 return;
145 else
146 Finish();
147
148 CurrentVendor = Vendor;
149
Rafael Espindolad9d0c342010-10-25 22:26:55 +0000150 assert(Contents.size() == 0);
Rafael Espindola0ed15432010-10-25 17:50:35 +0000151 }
152
153 void EmitAttribute(unsigned Attribute, unsigned Value) {
Renato Golinfaff5122011-08-09 09:50:10 +0000154 AttributeItemType attr = {
155 AttributeItemType::NumericAttribute,
156 Attribute,
157 Value,
158 StringRef("")
159 };
160 ContentsSize += getULEBSize(Attribute);
161 ContentsSize += getULEBSize(Value);
162 Contents.push_back(attr);
Rafael Espindola0ed15432010-10-25 17:50:35 +0000163 }
164
Jason W Kim85b0af12011-02-07 00:49:53 +0000165 void EmitTextAttribute(unsigned Attribute, StringRef String) {
Renato Golinfaff5122011-08-09 09:50:10 +0000166 AttributeItemType attr = {
167 AttributeItemType::TextAttribute,
168 Attribute,
169 0,
170 String
171 };
172 ContentsSize += getULEBSize(Attribute);
173 // String + \0
174 ContentsSize += String.size()+1;
175
176 Contents.push_back(attr);
Jason W Kim85b0af12011-02-07 00:49:53 +0000177 }
178
Rafael Espindola0ed15432010-10-25 17:50:35 +0000179 void Finish() {
Rafael Espindolad9d0c342010-10-25 22:26:55 +0000180 // Vendor size + Vendor name + '\0'
181 const size_t VendorHeaderSize = 4 + CurrentVendor.size() + 1;
Rafael Espindola0ed15432010-10-25 17:50:35 +0000182
Rafael Espindolad9d0c342010-10-25 22:26:55 +0000183 // Tag + Tag Size
184 const size_t TagHeaderSize = 1 + 4;
185
186 Streamer.EmitIntValue(VendorHeaderSize + TagHeaderSize + ContentsSize, 4);
Eric Christophere3ab3d02013-01-09 01:57:54 +0000187 Streamer.EmitBytes(CurrentVendor);
Rafael Espindolad9d0c342010-10-25 22:26:55 +0000188 Streamer.EmitIntValue(0, 1); // '\0'
189
190 Streamer.EmitIntValue(ARMBuildAttrs::File, 1);
191 Streamer.EmitIntValue(TagHeaderSize + ContentsSize, 4);
Rafael Espindola0ed15432010-10-25 17:50:35 +0000192
Renato Golinfaff5122011-08-09 09:50:10 +0000193 // Size should have been accounted for already, now
194 // emit each field as its type (ULEB or String)
195 for (unsigned int i=0; i<Contents.size(); ++i) {
196 AttributeItemType item = Contents[i];
Eric Christopherbf7bc492013-01-09 03:52:05 +0000197 Streamer.EmitULEB128IntValue(item.Tag);
Renato Golinfaff5122011-08-09 09:50:10 +0000198 switch (item.Type) {
Craig Toppere55c5562012-02-07 02:50:20 +0000199 default: llvm_unreachable("Invalid attribute type");
Renato Golinfaff5122011-08-09 09:50:10 +0000200 case AttributeItemType::NumericAttribute:
Eric Christopherbf7bc492013-01-09 03:52:05 +0000201 Streamer.EmitULEB128IntValue(item.IntValue);
Renato Golinfaff5122011-08-09 09:50:10 +0000202 break;
203 case AttributeItemType::TextAttribute:
Eric Christophere3ab3d02013-01-09 01:57:54 +0000204 Streamer.EmitBytes(item.StringValue.upper());
Renato Golinfaff5122011-08-09 09:50:10 +0000205 Streamer.EmitIntValue(0, 1); // '\0'
206 break;
Renato Golinfaff5122011-08-09 09:50:10 +0000207 }
208 }
Rafael Espindolad9d0c342010-10-25 22:26:55 +0000209
210 Contents.clear();
Rafael Espindola0ed15432010-10-25 17:50:35 +0000211 }
212 };
213
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000214} // end of anonymous namespace
215
Devang Patel3712c142011-04-21 22:48:26 +0000216/// EmitDwarfRegOp - Emit dwarf register operation.
David Blaikie81a4dc72013-06-19 21:55:13 +0000217void ARMAsmPrinter::EmitDwarfRegOp(const MachineLocation &MLoc,
218 bool Indirect) const {
Devang Patel3712c142011-04-21 22:48:26 +0000219 const TargetRegisterInfo *RI = TM.getRegisterInfo();
David Blaikie141b2ac2013-06-18 18:03:17 +0000220 if (RI->getDwarfRegNum(MLoc.getReg(), false) != -1) {
David Blaikie81a4dc72013-06-19 21:55:13 +0000221 AsmPrinter::EmitDwarfRegOp(MLoc, Indirect);
David Blaikie141b2ac2013-06-18 18:03:17 +0000222 return;
223 }
David Blaikie81a4dc72013-06-19 21:55:13 +0000224 assert(MLoc.isReg() && !Indirect &&
David Blaikie141b2ac2013-06-18 18:03:17 +0000225 "This doesn't support offset/indirection - implement it if needed");
226 unsigned Reg = MLoc.getReg();
227 if (Reg >= ARM::S0 && Reg <= ARM::S31) {
228 assert(ARM::S0 + 31 == ARM::S31 && "Unexpected ARM S register numbering");
229 // S registers are described as bit-pieces of a register
230 // S[2x] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 0)
231 // S[2x+1] = DW_OP_regx(256 + (x>>1)) DW_OP_bit_piece(32, 32)
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000232
David Blaikie141b2ac2013-06-18 18:03:17 +0000233 unsigned SReg = Reg - ARM::S0;
234 bool odd = SReg & 0x1;
235 unsigned Rx = 256 + (SReg >> 1);
Devang Patel3712c142011-04-21 22:48:26 +0000236
David Blaikie141b2ac2013-06-18 18:03:17 +0000237 OutStreamer.AddComment("DW_OP_regx for S register");
238 EmitInt8(dwarf::DW_OP_regx);
Devang Patel3712c142011-04-21 22:48:26 +0000239
David Blaikie141b2ac2013-06-18 18:03:17 +0000240 OutStreamer.AddComment(Twine(SReg));
241 EmitULEB128(Rx);
Devang Patel3712c142011-04-21 22:48:26 +0000242
David Blaikie141b2ac2013-06-18 18:03:17 +0000243 if (odd) {
244 OutStreamer.AddComment("DW_OP_bit_piece 32 32");
245 EmitInt8(dwarf::DW_OP_bit_piece);
246 EmitULEB128(32);
247 EmitULEB128(32);
248 } else {
249 OutStreamer.AddComment("DW_OP_bit_piece 32 0");
250 EmitInt8(dwarf::DW_OP_bit_piece);
251 EmitULEB128(32);
252 EmitULEB128(0);
Devang Patel3712c142011-04-21 22:48:26 +0000253 }
David Blaikie141b2ac2013-06-18 18:03:17 +0000254 } else if (Reg >= ARM::Q0 && Reg <= ARM::Q15) {
255 assert(ARM::Q0 + 15 == ARM::Q15 && "Unexpected ARM Q register numbering");
256 // Q registers Q0-Q15 are described by composing two D registers together.
257 // Qx = DW_OP_regx(256+2x) DW_OP_piece(8) DW_OP_regx(256+2x+1)
258 // DW_OP_piece(8)
259
260 unsigned QReg = Reg - ARM::Q0;
261 unsigned D1 = 256 + 2 * QReg;
262 unsigned D2 = D1 + 1;
263
264 OutStreamer.AddComment("DW_OP_regx for Q register: D1");
265 EmitInt8(dwarf::DW_OP_regx);
266 EmitULEB128(D1);
267 OutStreamer.AddComment("DW_OP_piece 8");
268 EmitInt8(dwarf::DW_OP_piece);
269 EmitULEB128(8);
270
271 OutStreamer.AddComment("DW_OP_regx for Q register: D2");
272 EmitInt8(dwarf::DW_OP_regx);
273 EmitULEB128(D2);
274 OutStreamer.AddComment("DW_OP_piece 8");
275 EmitInt8(dwarf::DW_OP_piece);
276 EmitULEB128(8);
Devang Patel3712c142011-04-21 22:48:26 +0000277 }
278}
279
Jim Grosbach4b63d2a2012-05-18 19:12:01 +0000280void ARMAsmPrinter::EmitFunctionBodyEnd() {
281 // Make sure to terminate any constant pools that were at the end
282 // of the function.
283 if (!InConstantPool)
284 return;
285 InConstantPool = false;
286 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
287}
Owen Anderson0ca562e2011-10-04 23:26:17 +0000288
Jim Grosbach4b63d2a2012-05-18 19:12:01 +0000289void ARMAsmPrinter::EmitFunctionEntryLabel() {
Chris Lattner56db8c32010-01-27 23:58:11 +0000290 if (AFI->isThumbFunction()) {
Jim Grosbach5a2c68d2010-11-05 22:08:08 +0000291 OutStreamer.EmitAssemblerFlag(MCAF_Code16);
Rafael Espindolae90c1cb2011-05-16 16:17:21 +0000292 OutStreamer.EmitThumbFunc(CurrentFnSym);
Chris Lattner56db8c32010-01-27 23:58:11 +0000293 }
Jim Grosbach8ee5cd92010-09-02 01:02:06 +0000294
Chris Lattner56db8c32010-01-27 23:58:11 +0000295 OutStreamer.EmitLabel(CurrentFnSym);
296}
297
James Molloy6685c082012-01-26 09:25:43 +0000298void ARMAsmPrinter::EmitXXStructor(const Constant *CV) {
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000299 uint64_t Size = TM.getDataLayout()->getTypeAllocSize(CV->getType());
James Molloy6685c082012-01-26 09:25:43 +0000300 assert(Size && "C++ constructor pointer had zero size!");
301
Bill Wendlingdfb45f42012-02-15 09:14:08 +0000302 const GlobalValue *GV = dyn_cast<GlobalValue>(CV->stripPointerCasts());
James Molloy6685c082012-01-26 09:25:43 +0000303 assert(GV && "C++ constructor pointer was not a GlobalValue!");
304
305 const MCExpr *E = MCSymbolRefExpr::Create(Mang->getSymbol(GV),
306 (Subtarget->isTargetDarwin()
307 ? MCSymbolRefExpr::VK_None
308 : MCSymbolRefExpr::VK_ARM_TARGET1),
309 OutContext);
310
311 OutStreamer.EmitValue(E, Size);
312}
313
Jim Grosbach080fdf42010-09-30 01:57:53 +0000314/// runOnMachineFunction - This uses the EmitInstruction()
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000315/// method to print assembly for each instruction.
316///
317bool ARMAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
Evan Cheng10043e22007-01-19 07:51:42 +0000318 AFI = MF.getInfo<ARMFunctionInfo>();
Evan Cheng5e3ac182008-09-18 07:27:23 +0000319 MCP = MF.getConstantPool();
Rafael Espindola27f8bdc2006-05-23 02:48:20 +0000320
Chris Lattner73de5fb2010-01-28 01:28:58 +0000321 return AsmPrinter::runOnMachineFunction(MF);
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000322}
323
Evan Chengb23b50d2009-06-29 07:51:04 +0000324void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum,
Chris Lattner76c564b2010-04-04 04:47:45 +0000325 raw_ostream &O, const char *Modifier) {
Evan Chengb23b50d2009-06-29 07:51:04 +0000326 const MachineOperand &MO = MI->getOperand(OpNum);
Anton Korobeynikov25229082009-11-24 00:44:37 +0000327 unsigned TF = MO.getTargetFlags();
328
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000329 switch (MO.getType()) {
Craig Toppere55c5562012-02-07 02:50:20 +0000330 default: llvm_unreachable("<unknown operand type>");
Bob Wilson2e076c42009-06-22 23:27:02 +0000331 case MachineOperand::MO_Register: {
332 unsigned Reg = MO.getReg();
Chris Lattner93e3ef62009-10-19 20:59:55 +0000333 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
Jim Grosbach2c950272010-10-06 21:22:32 +0000334 assert(!MO.getSubReg() && "Subregs should be eliminated!");
Weiming Zhaoc5987002013-02-14 18:10:21 +0000335 if(ARM::GPRPairRegClass.contains(Reg)) {
336 const MachineFunction &MF = *MI->getParent()->getParent();
337 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
338 Reg = TRI->getSubReg(Reg, ARM::gsub_0);
339 }
Jim Grosbach2c950272010-10-06 21:22:32 +0000340 O << ARMInstPrinter::getRegisterName(Reg);
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000341 break;
Bob Wilson2e076c42009-06-22 23:27:02 +0000342 }
Evan Cheng10043e22007-01-19 07:51:42 +0000343 case MachineOperand::MO_Immediate: {
Evan Cheng83e0d482009-09-28 09:14:39 +0000344 int64_t Imm = MO.getImm();
Anton Korobeynikov222b86c2009-10-08 20:43:22 +0000345 O << '#';
Anton Korobeynikov25229082009-11-24 00:44:37 +0000346 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
Jason W Kime9eae0f2011-01-12 23:21:49 +0000347 (TF == ARMII::MO_LO16))
Anton Korobeynikov25229082009-11-24 00:44:37 +0000348 O << ":lower16:";
349 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
Jason W Kime9eae0f2011-01-12 23:21:49 +0000350 (TF == ARMII::MO_HI16))
Anton Korobeynikov25229082009-11-24 00:44:37 +0000351 O << ":upper16:";
Anton Korobeynikov222b86c2009-10-08 20:43:22 +0000352 O << Imm;
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000353 break;
Evan Cheng10043e22007-01-19 07:51:42 +0000354 }
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000355 case MachineOperand::MO_MachineBasicBlock:
Chris Lattner29bdac42010-03-13 21:04:28 +0000356 O << *MO.getMBB()->getSymbol();
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000357 return;
Rafael Espindola75269be2006-07-16 01:02:57 +0000358 case MachineOperand::MO_GlobalAddress: {
Dan Gohmanbcaf6812010-04-15 01:51:59 +0000359 const GlobalValue *GV = MO.getGlobal();
Anton Korobeynikov25229082009-11-24 00:44:37 +0000360 if ((Modifier && strcmp(Modifier, "lo16") == 0) ||
361 (TF & ARMII::MO_LO16))
362 O << ":lower16:";
363 else if ((Modifier && strcmp(Modifier, "hi16") == 0) ||
364 (TF & ARMII::MO_HI16))
365 O << ":upper16:";
Chris Lattner0b822ab2010-03-12 21:19:23 +0000366 O << *Mang->getSymbol(GV);
Anton Korobeynikovbff4b372008-11-22 16:15:34 +0000367
Chris Lattnerf33c7fc2010-04-03 22:28:33 +0000368 printOffset(MO.getOffset(), O);
Jim Grosbachf49540c2010-10-06 21:36:43 +0000369 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +0000370 O << "(PLT)";
Evan Cheng10043e22007-01-19 07:51:42 +0000371 break;
Rafael Espindola75269be2006-07-16 01:02:57 +0000372 }
Evan Cheng10043e22007-01-19 07:51:42 +0000373 case MachineOperand::MO_ExternalSymbol: {
Chris Lattner8b5d55e2010-01-17 21:43:43 +0000374 O << *GetExternalSymbolSymbol(MO.getSymbolName());
Jim Grosbachf49540c2010-10-06 21:36:43 +0000375 if (TF == ARMII::MO_PLT)
Lauro Ramos Venancioee2d1642007-04-22 00:04:12 +0000376 O << "(PLT)";
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000377 break;
Evan Cheng10043e22007-01-19 07:51:42 +0000378 }
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000379 case MachineOperand::MO_ConstantPoolIndex:
Chris Lattnerc55ea3f2010-01-23 07:00:21 +0000380 O << *GetCPISymbol(MO.getIndex());
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000381 break;
Evan Cheng10043e22007-01-19 07:51:42 +0000382 case MachineOperand::MO_JumpTableIndex:
Chris Lattnerc55ea3f2010-01-23 07:00:21 +0000383 O << *GetJTISymbol(MO.getIndex());
Evan Cheng10043e22007-01-19 07:51:42 +0000384 break;
Rafael Espindola91df1ef2006-05-25 12:57:06 +0000385 }
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000386}
387
Evan Chengb23b50d2009-06-29 07:51:04 +0000388//===--------------------------------------------------------------------===//
389
Chris Lattner68d64aa2010-01-25 19:51:38 +0000390MCSymbol *ARMAsmPrinter::
Chris Lattner68d64aa2010-01-25 19:51:38 +0000391GetARMJTIPICJumpTableLabel2(unsigned uid, unsigned uid2) const {
392 SmallString<60> Name;
393 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "JTI"
Chris Lattner8186eec2010-01-25 23:28:03 +0000394 << getFunctionNumber() << '_' << uid << '_' << uid2;
Chris Lattner98970432010-03-30 18:10:53 +0000395 return OutContext.GetOrCreateSymbol(Name.str());
Chris Lattner6330d532010-01-25 19:39:52 +0000396}
397
Jim Grosbach4a6ab132010-09-24 20:47:58 +0000398
Dmitri Gribenko0011bbf2012-11-15 16:51:49 +0000399MCSymbol *ARMAsmPrinter::GetARMSJLJEHLabel() const {
Jim Grosbach4a6ab132010-09-24 20:47:58 +0000400 SmallString<60> Name;
401 raw_svector_ostream(Name) << MAI->getPrivateGlobalPrefix() << "SJLJEH"
402 << getFunctionNumber();
403 return OutContext.GetOrCreateSymbol(Name.str());
404}
405
Evan Chengb23b50d2009-06-29 07:51:04 +0000406bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
Chris Lattner3bb09762010-04-04 05:29:35 +0000407 unsigned AsmVariant, const char *ExtraCode,
408 raw_ostream &O) {
Evan Cheng10043e22007-01-19 07:51:42 +0000409 // Does this asm operand have a single letter operand modifier?
410 if (ExtraCode && ExtraCode[0]) {
411 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Anton Korobeynikovcfed3002009-08-08 23:10:41 +0000412
Evan Cheng10043e22007-01-19 07:51:42 +0000413 switch (ExtraCode[0]) {
Jack Carter5e69cff2012-06-26 13:49:27 +0000414 default:
415 // See if this is a generic print operand
416 return AsmPrinter::PrintAsmOperand(MI, OpNum, AsmVariant, ExtraCode, O);
Bob Wilson9ce44e22009-07-09 23:54:51 +0000417 case 'a': // Print as a memory address.
418 if (MI->getOperand(OpNum).isReg()) {
Jim Grosbach136ed512010-09-30 15:25:22 +0000419 O << "["
420 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg())
421 << "]";
Bob Wilson9ce44e22009-07-09 23:54:51 +0000422 return false;
423 }
424 // Fallthrough
425 case 'c': // Don't print "#" before an immediate operand.
Bob Wilsonceffeb62009-08-21 21:58:55 +0000426 if (!MI->getOperand(OpNum).isImm())
427 return true;
Jim Grosbach080fdf42010-09-30 01:57:53 +0000428 O << MI->getOperand(OpNum).getImm();
Bob Wilson0669f6d2009-04-06 21:46:51 +0000429 return false;
Evan Cheng1e150de2007-04-04 00:13:29 +0000430 case 'P': // Print a VFP double precision register.
Evan Cheng0c2544f2009-12-08 23:06:22 +0000431 case 'q': // Print a NEON quad precision register.
Chris Lattner76c564b2010-04-04 04:47:45 +0000432 printOperand(MI, OpNum, O);
Evan Chengea28fc52007-03-08 22:42:46 +0000433 return false;
Eric Christopher76178832011-05-24 22:10:34 +0000434 case 'y': // Print a VFP single precision register as indexed double.
Eric Christopher76178832011-05-24 22:10:34 +0000435 if (MI->getOperand(OpNum).isReg()) {
436 unsigned Reg = MI->getOperand(OpNum).getReg();
437 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
Jakob Stoklund Olesen5541f602012-05-30 23:00:43 +0000438 // Find the 'd' register that has this 's' register as a sub-register,
439 // and determine the lane number.
440 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid(); ++SR) {
441 if (!ARM::DPRRegClass.contains(*SR))
442 continue;
443 bool Lane0 = TRI->getSubReg(*SR, ARM::ssub_0) == Reg;
444 O << ARMInstPrinter::getRegisterName(*SR) << (Lane0 ? "[0]" : "[1]");
445 return false;
446 }
Eric Christopher76178832011-05-24 22:10:34 +0000447 }
Eric Christopher1b724942011-05-24 23:27:13 +0000448 return true;
Eric Christopherd4562562011-05-24 22:27:43 +0000449 case 'B': // Bitwise inverse of integer or symbol without a preceding #.
Eric Christopherb1dda562011-05-24 23:15:43 +0000450 if (!MI->getOperand(OpNum).isImm())
451 return true;
452 O << ~(MI->getOperand(OpNum).getImm());
453 return false;
Eric Christopherd4562562011-05-24 22:27:43 +0000454 case 'L': // The low 16 bits of an immediate constant.
Eric Christopher1b724942011-05-24 23:27:13 +0000455 if (!MI->getOperand(OpNum).isImm())
456 return true;
457 O << (MI->getOperand(OpNum).getImm() & 0xffff);
458 return false;
Eric Christopherd00e8ad2011-05-28 01:40:44 +0000459 case 'M': { // A register range suitable for LDM/STM.
460 if (!MI->getOperand(OpNum).isReg())
461 return true;
462 const MachineOperand &MO = MI->getOperand(OpNum);
463 unsigned RegBegin = MO.getReg();
464 // This takes advantage of the 2 operand-ness of ldm/stm and that we've
465 // already got the operands in registers that are operands to the
466 // inline asm statement.
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000467
Eric Christopherd00e8ad2011-05-28 01:40:44 +0000468 O << "{" << ARMInstPrinter::getRegisterName(RegBegin);
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000469
Eric Christopherd00e8ad2011-05-28 01:40:44 +0000470 // FIXME: The register allocator not only may not have given us the
471 // registers in sequence, but may not be in ascending registers. This
472 // will require changes in the register allocator that'll need to be
473 // propagated down here if the operands change.
474 unsigned RegOps = OpNum + 1;
475 while (MI->getOperand(RegOps).isReg()) {
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000476 O << ", "
Eric Christopherd00e8ad2011-05-28 01:40:44 +0000477 << ARMInstPrinter::getRegisterName(MI->getOperand(RegOps).getReg());
478 RegOps++;
479 }
480
481 O << "}";
482
483 return false;
484 }
Rafael Espindola36a3abc2011-08-10 16:26:42 +0000485 case 'R': // The most significant register of a pair.
486 case 'Q': { // The least significant register of a pair.
487 if (OpNum == 0)
488 return true;
489 const MachineOperand &FlagsOP = MI->getOperand(OpNum - 1);
490 if (!FlagsOP.isImm())
491 return true;
492 unsigned Flags = FlagsOP.getImm();
493 unsigned NumVals = InlineAsm::getNumOperandRegisters(Flags);
494 if (NumVals != 2)
495 return true;
496 unsigned RegOp = ExtraCode[0] == 'Q' ? OpNum : OpNum + 1;
497 if (RegOp >= MI->getNumOperands())
498 return true;
499 const MachineOperand &MO = MI->getOperand(RegOp);
500 if (!MO.isReg())
501 return true;
502 unsigned Reg = MO.getReg();
503 O << ARMInstPrinter::getRegisterName(Reg);
504 return false;
505 }
506
Eric Christopherd4562562011-05-24 22:27:43 +0000507 case 'e': // The low doubleword register of a NEON quad register.
Bob Wilsonfadc2c82011-12-12 21:45:15 +0000508 case 'f': { // The high doubleword register of a NEON quad register.
509 if (!MI->getOperand(OpNum).isReg())
510 return true;
511 unsigned Reg = MI->getOperand(OpNum).getReg();
512 if (!ARM::QPRRegClass.contains(Reg))
513 return true;
514 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
515 unsigned SubReg = TRI->getSubReg(Reg, ExtraCode[0] == 'e' ?
516 ARM::dsub_0 : ARM::dsub_1);
517 O << ARMInstPrinter::getRegisterName(SubReg);
518 return false;
519 }
520
Eric Christopher7d8b53c2012-08-13 18:18:52 +0000521 // This modifier is not yet supported.
Eric Christopherd4562562011-05-24 22:27:43 +0000522 case 'h': // A range of VFP/NEON registers suitable for VLD1/VST1.
Bob Wilson40e62df2010-05-27 20:23:42 +0000523 return true;
Eric Christopher5f61a742012-08-14 23:32:15 +0000524 case 'H': { // The highest-numbered register of a pair.
Eric Christopher7d8b53c2012-08-13 18:18:52 +0000525 const MachineOperand &MO = MI->getOperand(OpNum);
526 if (!MO.isReg())
527 return true;
Eric Christopher7d8b53c2012-08-13 18:18:52 +0000528 const MachineFunction &MF = *MI->getParent()->getParent();
529 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
Weiming Zhaoc5987002013-02-14 18:10:21 +0000530 unsigned Reg = MO.getReg();
531 if(!ARM::GPRPairRegClass.contains(Reg))
532 return false;
533 Reg = TRI->getSubReg(Reg, ARM::gsub_1);
Eric Christopher7d8b53c2012-08-13 18:18:52 +0000534 O << ARMInstPrinter::getRegisterName(Reg);
535 return false;
Evan Cheng3d3ee872010-05-27 22:08:38 +0000536 }
Eric Christopher5f61a742012-08-14 23:32:15 +0000537 }
Evan Cheng10043e22007-01-19 07:51:42 +0000538 }
Jim Grosbach1eaa90b2009-09-04 01:38:51 +0000539
Chris Lattner76c564b2010-04-04 04:47:45 +0000540 printOperand(MI, OpNum, O);
Evan Cheng10043e22007-01-19 07:51:42 +0000541 return false;
542}
543
Bob Wilsona2c462b2009-05-19 05:53:42 +0000544bool ARMAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI,
Evan Chengb23b50d2009-06-29 07:51:04 +0000545 unsigned OpNum, unsigned AsmVariant,
Chris Lattner3bb09762010-04-04 05:29:35 +0000546 const char *ExtraCode,
547 raw_ostream &O) {
Eric Christopher8c5e4192011-05-25 20:51:58 +0000548 // Does this asm operand have a single letter operand modifier?
549 if (ExtraCode && ExtraCode[0]) {
550 if (ExtraCode[1] != 0) return true; // Unknown modifier.
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000551
Eric Christopher8c5e4192011-05-25 20:51:58 +0000552 switch (ExtraCode[0]) {
Eric Christopher33a73c72011-05-26 18:22:26 +0000553 case 'A': // A memory operand for a VLD1/VST1 instruction.
Eric Christopher8c5e4192011-05-25 20:51:58 +0000554 default: return true; // Unknown modifier.
555 case 'm': // The base register of a memory operand.
556 if (!MI->getOperand(OpNum).isReg())
557 return true;
558 O << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg());
559 return false;
560 }
561 }
Jim Grosbach05dec8b12011-09-02 18:46:15 +0000562
Bob Wilson3b515602009-10-13 20:50:28 +0000563 const MachineOperand &MO = MI->getOperand(OpNum);
564 assert(MO.isReg() && "unexpected inline asm memory operand");
Jim Grosbach080fdf42010-09-30 01:57:53 +0000565 O << "[" << ARMInstPrinter::getRegisterName(MO.getReg()) << "]";
Bob Wilsona2c462b2009-05-19 05:53:42 +0000566 return false;
567}
568
Bob Wilsonb633d7a2009-09-30 22:06:26 +0000569void ARMAsmPrinter::EmitStartOfAsmFile(Module &M) {
Bob Wilson20e5f5e2009-09-30 00:23:42 +0000570 if (Subtarget->isTargetDarwin()) {
571 Reloc::Model RelocM = TM.getRelocationModel();
572 if (RelocM == Reloc::PIC_ || RelocM == Reloc::DynamicNoPIC) {
573 // Declare all the text sections up front (before the DWARF sections
574 // emitted by AsmPrinter::doInitialization) so the assembler will keep
575 // them together at the beginning of the object file. This helps
576 // avoid out-of-range branches that are due a fundamental limitation of
577 // the way symbol offsets are encoded with the current Darwin ARM
578 // relocations.
Jim Grosbach8ee5cd92010-09-02 01:02:06 +0000579 const TargetLoweringObjectFileMachO &TLOFMacho =
Dan Gohman53d4a082010-04-17 16:44:48 +0000580 static_cast<const TargetLoweringObjectFileMachO &>(
581 getObjFileLowering());
Jim Grosbach330840f2012-10-04 21:33:24 +0000582
583 // Collect the set of sections our functions will go into.
584 SetVector<const MCSection *, SmallVector<const MCSection *, 8>,
585 SmallPtrSet<const MCSection *, 8> > TextSections;
586 // Default text section comes first.
587 TextSections.insert(TLOFMacho.getTextSection());
588 // Now any user defined text sections from function attributes.
589 for (Module::iterator F = M.begin(), e = M.end(); F != e; ++F)
590 if (!F->isDeclaration() && !F->hasAvailableExternallyLinkage())
591 TextSections.insert(TLOFMacho.SectionForGlobal(F, Mang, TM));
592 // Now the coalescable sections.
593 TextSections.insert(TLOFMacho.getTextCoalSection());
594 TextSections.insert(TLOFMacho.getConstTextCoalSection());
595
596 // Emit the sections in the .s file header to fix the order.
597 for (unsigned i = 0, e = TextSections.size(); i != e; ++i)
598 OutStreamer.SwitchSection(TextSections[i]);
599
Bob Wilsonb2120755a2009-09-30 22:25:37 +0000600 if (RelocM == Reloc::DynamicNoPIC) {
601 const MCSection *sect =
Chris Lattner433d4062010-04-08 20:40:11 +0000602 OutContext.getMachOSection("__TEXT", "__symbol_stub4",
603 MCSectionMachO::S_SYMBOL_STUBS,
604 12, SectionKind::getText());
Bob Wilsonb2120755a2009-09-30 22:25:37 +0000605 OutStreamer.SwitchSection(sect);
606 } else {
607 const MCSection *sect =
Chris Lattner433d4062010-04-08 20:40:11 +0000608 OutContext.getMachOSection("__TEXT", "__picsymbolstub4",
609 MCSectionMachO::S_SYMBOL_STUBS,
610 16, SectionKind::getText());
Bob Wilsonb2120755a2009-09-30 22:25:37 +0000611 OutStreamer.SwitchSection(sect);
612 }
Bob Wilson4320e2d2010-07-30 19:55:47 +0000613 const MCSection *StaticInitSect =
614 OutContext.getMachOSection("__TEXT", "__StaticInit",
615 MCSectionMachO::S_REGULAR |
616 MCSectionMachO::S_ATTR_PURE_INSTRUCTIONS,
617 SectionKind::getText());
618 OutStreamer.SwitchSection(StaticInitSect);
Bob Wilson20e5f5e2009-09-30 00:23:42 +0000619 }
620 }
621
Jim Grosbachd7cf55c2009-11-09 00:11:35 +0000622 // Use unified assembler syntax.
Jason W Kim645f6c22010-09-30 02:45:56 +0000623 OutStreamer.EmitAssemblerFlag(MCAF_SyntaxUnified);
Anton Korobeynikovf687a822009-06-17 23:43:18 +0000624
Anton Korobeynikovfa6f1ee2009-05-23 19:51:20 +0000625 // Emit ARM Build Attributes
Evan Cheng0460ae82012-02-21 20:46:00 +0000626 if (Subtarget->isTargetELF())
Jason W Kimbff84d42010-10-06 22:36:46 +0000627 emitAttributes();
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000628}
629
Anton Korobeynikov04083522008-08-07 09:54:23 +0000630
Chris Lattneree9399a2009-10-19 17:59:19 +0000631void ARMAsmPrinter::EmitEndOfAsmFile(Module &M) {
Evan Cheng1199c2d2007-01-19 19:25:36 +0000632 if (Subtarget->isTargetDarwin()) {
Chris Lattner73ebe432009-08-03 22:18:15 +0000633 // All darwin targets use mach-o.
Dan Gohman53d4a082010-04-17 16:44:48 +0000634 const TargetLoweringObjectFileMachO &TLOFMacho =
635 static_cast<const TargetLoweringObjectFileMachO &>(getObjFileLowering());
Chris Lattner6462adc2009-10-19 18:38:33 +0000636 MachineModuleInfoMachO &MMIMacho =
637 MMI->getObjFileInfo<MachineModuleInfoMachO>();
Jim Grosbach1eaa90b2009-09-04 01:38:51 +0000638
Evan Cheng10043e22007-01-19 07:51:42 +0000639 // Output non-lazy-pointers for external and common global variables.
Chris Lattner6462adc2009-10-19 18:38:33 +0000640 MachineModuleInfoMachO::SymbolListTy Stubs = MMIMacho.GetGVStubList();
Bill Wendlinga810bdf2010-03-10 22:34:10 +0000641
Chris Lattner6462adc2009-10-19 18:38:33 +0000642 if (!Stubs.empty()) {
Chris Lattnercb307a272009-08-10 01:39:42 +0000643 // Switch with ".non_lazy_symbol_pointer" directive.
Chris Lattner4b7dadb2009-08-19 05:49:37 +0000644 OutStreamer.SwitchSection(TLOFMacho.getNonLazySymbolPointerSection());
Chris Lattner292472d2009-08-10 18:01:34 +0000645 EmitAlignment(2);
Chris Lattner6462adc2009-10-19 18:38:33 +0000646 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
Bill Wendlingf1eae222010-03-09 00:40:17 +0000647 // L_foo$stub:
648 OutStreamer.EmitLabel(Stubs[i].first);
649 // .indirect_symbol _foo
Bill Wendlinge8e79522010-03-11 01:18:13 +0000650 MachineModuleInfoImpl::StubValueTy &MCSym = Stubs[i].second;
651 OutStreamer.EmitSymbolAttribute(MCSym.getPointer(),MCSA_IndirectSymbol);
Bill Wendlingffba5fa2010-03-09 00:43:34 +0000652
Bill Wendlinge8e79522010-03-11 01:18:13 +0000653 if (MCSym.getInt())
Bill Wendlingffba5fa2010-03-09 00:43:34 +0000654 // External to current translation unit.
Eric Christopherbf7bc492013-01-09 03:52:05 +0000655 OutStreamer.EmitIntValue(0, 4/*size*/);
Bill Wendlingffba5fa2010-03-09 00:43:34 +0000656 else
657 // Internal to current translation unit.
Bill Wendling866f5762010-03-31 18:47:10 +0000658 //
Jim Grosbach754e1ef2010-09-22 16:45:13 +0000659 // When we place the LSDA into the TEXT section, the type info
660 // pointers need to be indirect and pc-rel. We accomplish this by
661 // using NLPs; however, sometimes the types are local to the file.
662 // We need to fill in the value for the NLP in those cases.
Bill Wendlinge8e79522010-03-11 01:18:13 +0000663 OutStreamer.EmitValue(MCSymbolRefExpr::Create(MCSym.getPointer(),
664 OutContext),
Eric Christopherbf7bc492013-01-09 03:52:05 +0000665 4/*size*/);
Evan Cheng2a03c7e2008-12-05 01:06:39 +0000666 }
Bill Wendlingf1eae222010-03-09 00:40:17 +0000667
668 Stubs.clear();
669 OutStreamer.AddBlankLine();
Evan Cheng10043e22007-01-19 07:51:42 +0000670 }
671
Chris Lattner3334deb2009-10-19 18:44:38 +0000672 Stubs = MMIMacho.GetHiddenGVStubList();
673 if (!Stubs.empty()) {
Chris Lattner4b7dadb2009-08-19 05:49:37 +0000674 OutStreamer.SwitchSection(getObjFileLowering().getDataSection());
Chris Lattnerfbcafd42009-08-10 18:02:16 +0000675 EmitAlignment(2);
Bill Wendlingf1eae222010-03-09 00:40:17 +0000676 for (unsigned i = 0, e = Stubs.size(); i != e; ++i) {
677 // L_foo$stub:
678 OutStreamer.EmitLabel(Stubs[i].first);
679 // .long _foo
Bill Wendlinga810bdf2010-03-10 22:34:10 +0000680 OutStreamer.EmitValue(MCSymbolRefExpr::
681 Create(Stubs[i].second.getPointer(),
682 OutContext),
Eric Christopherbf7bc492013-01-09 03:52:05 +0000683 4/*size*/);
Bill Wendlingf1eae222010-03-09 00:40:17 +0000684 }
Bill Wendlingffba5fa2010-03-09 00:43:34 +0000685
686 Stubs.clear();
687 OutStreamer.AddBlankLine();
Evan Cheng2a03c7e2008-12-05 01:06:39 +0000688 }
689
Evan Cheng10043e22007-01-19 07:51:42 +0000690 // Funny Darwin hack: This flag tells the linker that no global symbols
691 // contain code that falls through to other global symbols (e.g. the obvious
692 // implementation of multiple entry points). If this doesn't occur, the
693 // linker can safely perform dead code stripping. Since LLVM never
694 // generates code that does this, it is always safe to set.
Chris Lattner685508c2010-01-23 06:39:22 +0000695 OutStreamer.EmitAssemblerFlag(MCAF_SubsectionsViaSymbols);
Rafael Espindola89e5cbd2006-07-27 11:38:51 +0000696 }
Jack Carter718da0b2013-01-30 02:24:33 +0000697 // FIXME: This should eventually end up somewhere else where more
698 // intelligent flag decisions can be made. For now we are just maintaining
699 // the status quo for ARM and setting EF_ARM_EABI_VER5 as the default.
Chandler Carruthe5d8d0d2013-01-31 23:43:14 +0000700 if (MCELFStreamer *MES = dyn_cast<MCELFStreamer>(&OutStreamer))
701 MES->getAssembler().setELFHeaderEFlags(ELF::EF_ARM_EABI_VER5);
Rafael Espindolaffdc24b2006-05-14 22:18:28 +0000702}
Anton Korobeynikov17d28de2008-08-17 13:55:10 +0000703
Chris Lattner71eb0772009-10-19 20:20:46 +0000704//===----------------------------------------------------------------------===//
Jason W Kimbff84d42010-10-06 22:36:46 +0000705// Helper routines for EmitStartOfAsmFile() and EmitEndOfAsmFile()
706// FIXME:
707// The following seem like one-off assembler flags, but they actually need
Jim Grosbach25cd3bf2010-10-06 22:46:47 +0000708// to appear in the .ARM.attributes section in ELF.
Jason W Kimbff84d42010-10-06 22:36:46 +0000709// Instead of subclassing the MCELFStreamer, we do the work here.
710
711void ARMAsmPrinter::emitAttributes() {
Jim Grosbach25cd3bf2010-10-06 22:46:47 +0000712
Jason W Kim109ff292010-10-11 23:01:44 +0000713 emitARMAttributeSection();
714
Renato Golinec0fc7d2011-02-28 22:04:27 +0000715 /* GAS expect .fpu to be emitted, regardless of VFP build attribute */
716 bool emitFPU = false;
Rafael Espindola0ed15432010-10-25 17:50:35 +0000717 AttributeEmitter *AttrEmitter;
Renato Golinec0fc7d2011-02-28 22:04:27 +0000718 if (OutStreamer.hasRawTextSupport()) {
Rafael Espindola0ed15432010-10-25 17:50:35 +0000719 AttrEmitter = new AsmAttributeEmitter(OutStreamer);
Renato Golinec0fc7d2011-02-28 22:04:27 +0000720 emitFPU = true;
721 } else {
Rafael Espindola0ed15432010-10-25 17:50:35 +0000722 MCObjectStreamer &O = static_cast<MCObjectStreamer&>(OutStreamer);
723 AttrEmitter = new ObjectAttributeEmitter(O);
724 }
725
726 AttrEmitter->MaybeSwitchVendor("aeabi");
727
Jason W Kimbff84d42010-10-06 22:36:46 +0000728 std::string CPUString = Subtarget->getCPUString();
Jason W Kim85b0af12011-02-07 00:49:53 +0000729
730 if (CPUString == "cortex-a8" ||
731 Subtarget->isCortexA8()) {
Jason W Kime5ce4c92011-02-07 19:07:11 +0000732 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a8");
Jason W Kim85b0af12011-02-07 00:49:53 +0000733 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
734 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
735 ARMBuildAttrs::ApplicationProfile);
736 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
737 ARMBuildAttrs::Allowed);
738 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
739 ARMBuildAttrs::AllowThumb32);
740 // Fixme: figure out when this is emitted.
741 //AttrEmitter->EmitAttribute(ARMBuildAttrs::WMMX_arch,
742 // ARMBuildAttrs::AllowWMMXv1);
743 //
744
745 /// ADD additional Else-cases here!
Rafael Espindola652bfdb2011-05-20 20:10:34 +0000746 } else if (CPUString == "xscale") {
747 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TEJ);
748 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
749 ARMBuildAttrs::Allowed);
750 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
751 ARMBuildAttrs::Allowed);
Jason W Kim85b0af12011-02-07 00:49:53 +0000752 } else if (CPUString == "generic") {
Amara Emersonec2cd562012-11-08 09:51:45 +0000753 // For a generic CPU, we assume a standard v7a architecture in Subtarget.
754 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
755 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch_profile,
756 ARMBuildAttrs::ApplicationProfile);
Jason W Kim85b0af12011-02-07 00:49:53 +0000757 AttrEmitter->EmitAttribute(ARMBuildAttrs::ARM_ISA_use,
758 ARMBuildAttrs::Allowed);
759 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
Amara Emersonec2cd562012-11-08 09:51:45 +0000760 ARMBuildAttrs::AllowThumb32);
761 } else if (Subtarget->hasV7Ops()) {
762 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v7);
763 AttrEmitter->EmitAttribute(ARMBuildAttrs::THUMB_ISA_use,
764 ARMBuildAttrs::AllowThumb32);
765 } else if (Subtarget->hasV6T2Ops())
766 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6T2);
767 else if (Subtarget->hasV6Ops())
768 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v6);
769 else if (Subtarget->hasV5TEOps())
770 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5TE);
771 else if (Subtarget->hasV5TOps())
772 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v5T);
773 else if (Subtarget->hasV4TOps())
774 AttrEmitter->EmitAttribute(ARMBuildAttrs::CPU_arch, ARMBuildAttrs::v4T);
Jason W Kimbff84d42010-10-06 22:36:46 +0000775
Renato Goline84af172011-03-02 21:20:09 +0000776 if (Subtarget->hasNEON() && emitFPU) {
Renato Golinec0fc7d2011-02-28 22:04:27 +0000777 /* NEON is not exactly a VFP architecture, but GAS emit one of
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000778 * neon/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
Evan Cheng48346c12012-04-11 05:33:07 +0000779 if (Subtarget->hasVFP4())
Jim Grosbach0c509fa2012-04-06 23:43:50 +0000780 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
781 "neon-vfpv4");
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000782 else
Sebastian Pop957a6582012-03-05 17:39:52 +0000783 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::Advanced_SIMD_arch, "neon");
Renato Golinec0fc7d2011-02-28 22:04:27 +0000784 /* If emitted for NEON, omit from VFP below, since you can have both
785 * NEON and VFP in build attributes but only one .fpu */
786 emitFPU = false;
787 }
788
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000789 /* VFPv4 + .fpu */
790 if (Subtarget->hasVFP4()) {
Amara Emersond9104c02013-05-03 23:57:17 +0000791 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000792 ARMBuildAttrs::AllowFPv4A);
793 if (emitFPU)
Amara Emersond9104c02013-05-03 23:57:17 +0000794 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv4");
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000795
Renato Golinec0fc7d2011-02-28 22:04:27 +0000796 /* VFPv3 + .fpu */
Anton Korobeynikov5482b9f2012-01-22 12:07:33 +0000797 } else if (Subtarget->hasVFP3()) {
Amara Emersond9104c02013-05-03 23:57:17 +0000798 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
Renato Golinec0fc7d2011-02-28 22:04:27 +0000799 ARMBuildAttrs::AllowFPv3A);
800 if (emitFPU)
Amara Emersond9104c02013-05-03 23:57:17 +0000801 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv3");
Renato Golinec0fc7d2011-02-28 22:04:27 +0000802
803 /* VFPv2 + .fpu */
804 } else if (Subtarget->hasVFP2()) {
Amara Emersond9104c02013-05-03 23:57:17 +0000805 AttrEmitter->EmitAttribute(ARMBuildAttrs::VFP_arch,
Jason W Kim85b0af12011-02-07 00:49:53 +0000806 ARMBuildAttrs::AllowFPv2);
Renato Golinec0fc7d2011-02-28 22:04:27 +0000807 if (emitFPU)
Amara Emersond9104c02013-05-03 23:57:17 +0000808 AttrEmitter->EmitTextAttribute(ARMBuildAttrs::VFP_arch, "vfpv2");
Renato Golinec0fc7d2011-02-28 22:04:27 +0000809 }
810
811 /* TODO: ARMBuildAttrs::Allowed is not completely accurate,
Cameron Zwarich14822032011-07-07 08:28:52 +0000812 * since NEON can have 1 (allowed) or 2 (MAC operations) */
Renato Golinec0fc7d2011-02-28 22:04:27 +0000813 if (Subtarget->hasNEON()) {
814 AttrEmitter->EmitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
815 ARMBuildAttrs::Allowed);
816 }
Jason W Kimbff84d42010-10-06 22:36:46 +0000817
818 // Signal various FP modes.
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000819 if (!TM.Options.UnsafeFPMath) {
Jason W Kim85b0af12011-02-07 00:49:53 +0000820 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_denormal,
821 ARMBuildAttrs::Allowed);
822 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_exceptions,
823 ARMBuildAttrs::Allowed);
Jason W Kimbff84d42010-10-06 22:36:46 +0000824 }
825
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000826 if (TM.Options.NoInfsFPMath && TM.Options.NoNaNsFPMath)
Jason W Kim85b0af12011-02-07 00:49:53 +0000827 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
828 ARMBuildAttrs::Allowed);
Jason W Kimbff84d42010-10-06 22:36:46 +0000829 else
Jason W Kim85b0af12011-02-07 00:49:53 +0000830 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_FP_number_model,
831 ARMBuildAttrs::AllowIEE754);
Jason W Kimbff84d42010-10-06 22:36:46 +0000832
Jason W Kim85b0af12011-02-07 00:49:53 +0000833 // FIXME: add more flags to ARMBuildAttrs.h
Jason W Kimbff84d42010-10-06 22:36:46 +0000834 // 8-bytes alignment stuff.
Rafael Espindola0ed15432010-10-25 17:50:35 +0000835 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_needed, 1);
836 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_align8_preserved, 1);
Jason W Kimbff84d42010-10-06 22:36:46 +0000837
838 // Hard float. Use both S and D registers and conform to AAPCS-VFP.
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000839 if (Subtarget->isAAPCS_ABI() && TM.Options.FloatABIType == FloatABI::Hard) {
Rafael Espindola0ed15432010-10-25 17:50:35 +0000840 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_HardFP_use, 3);
841 AttrEmitter->EmitAttribute(ARMBuildAttrs::ABI_VFP_args, 1);
Jason W Kimbff84d42010-10-06 22:36:46 +0000842 }
843 // FIXME: Should we signal R9 usage?
Rafael Espindola0ed15432010-10-25 17:50:35 +0000844
Jason W Kim85b0af12011-02-07 00:49:53 +0000845 if (Subtarget->hasDivide())
846 AttrEmitter->EmitAttribute(ARMBuildAttrs::DIV_use, 1);
Rafael Espindola0ed15432010-10-25 17:50:35 +0000847
848 AttrEmitter->Finish();
849 delete AttrEmitter;
Jason W Kimbff84d42010-10-06 22:36:46 +0000850}
851
Jason W Kim109ff292010-10-11 23:01:44 +0000852void ARMAsmPrinter::emitARMAttributeSection() {
853 // <format-version>
854 // [ <section-length> "vendor-name"
855 // [ <file-tag> <size> <attribute>*
856 // | <section-tag> <size> <section-number>* 0 <attribute>*
857 // | <symbol-tag> <size> <symbol-number>* 0 <attribute>*
858 // ]+
859 // ]*
860
861 if (OutStreamer.hasRawTextSupport())
862 return;
863
864 const ARMElfTargetObjectFile &TLOFELF =
865 static_cast<const ARMElfTargetObjectFile &>
866 (getObjFileLowering());
867
868 OutStreamer.SwitchSection(TLOFELF.getAttributesSection());
Jason W Kim109ff292010-10-11 23:01:44 +0000869
Rafael Espindola0ed15432010-10-25 17:50:35 +0000870 // Format version
871 OutStreamer.EmitIntValue(0x41, 1);
Jason W Kim109ff292010-10-11 23:01:44 +0000872}
873
Jason W Kimbff84d42010-10-06 22:36:46 +0000874//===----------------------------------------------------------------------===//
Chris Lattner71eb0772009-10-19 20:20:46 +0000875
Jim Grosbachaf5d6352010-09-18 00:05:05 +0000876static MCSymbol *getPICLabel(const char *Prefix, unsigned FunctionNumber,
877 unsigned LabelId, MCContext &Ctx) {
878
879 MCSymbol *Label = Ctx.GetOrCreateSymbol(Twine(Prefix)
880 + "PC" + Twine(FunctionNumber) + "_" + Twine(LabelId));
881 return Label;
882}
883
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000884static MCSymbolRefExpr::VariantKind
885getModifierVariantKind(ARMCP::ARMCPModifier Modifier) {
886 switch (Modifier) {
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000887 case ARMCP::no_modifier: return MCSymbolRefExpr::VK_None;
888 case ARMCP::TLSGD: return MCSymbolRefExpr::VK_ARM_TLSGD;
889 case ARMCP::TPOFF: return MCSymbolRefExpr::VK_ARM_TPOFF;
890 case ARMCP::GOTTPOFF: return MCSymbolRefExpr::VK_ARM_GOTTPOFF;
891 case ARMCP::GOT: return MCSymbolRefExpr::VK_ARM_GOT;
892 case ARMCP::GOTOFF: return MCSymbolRefExpr::VK_ARM_GOTOFF;
893 }
David Blaikie46a9f012012-01-20 21:51:11 +0000894 llvm_unreachable("Invalid ARMCPModifier!");
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000895}
896
Evan Chengdfce83c2011-01-17 08:03:18 +0000897MCSymbol *ARMAsmPrinter::GetARMGVSymbol(const GlobalValue *GV) {
898 bool isIndirect = Subtarget->isTargetDarwin() &&
899 Subtarget->GVIsIndirectSymbol(GV, TM.getRelocationModel());
900 if (!isIndirect)
901 return Mang->getSymbol(GV);
902
903 // FIXME: Remove this when Darwin transition to @GOT like syntax.
904 MCSymbol *MCSym = GetSymbolWithGlobalValueBase(GV, "$non_lazy_ptr");
905 MachineModuleInfoMachO &MMIMachO =
906 MMI->getObjFileInfo<MachineModuleInfoMachO>();
907 MachineModuleInfoImpl::StubValueTy &StubSym =
908 GV->hasHiddenVisibility() ? MMIMachO.getHiddenGVStubEntry(MCSym) :
909 MMIMachO.getGVStubEntry(MCSym);
910 if (StubSym.getPointer() == 0)
911 StubSym = MachineModuleInfoImpl::
912 StubValueTy(Mang->getSymbol(GV), !GV->hasInternalLinkage());
913 return MCSym;
914}
915
Jim Grosbach38f8e762010-11-09 18:45:04 +0000916void ARMAsmPrinter::
917EmitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) {
Micah Villmowcdfe20b2012-10-08 16:38:25 +0000918 int Size = TM.getDataLayout()->getTypeAllocSize(MCPV->getType());
Jim Grosbach38f8e762010-11-09 18:45:04 +0000919
920 ARMConstantPoolValue *ACPV = static_cast<ARMConstantPoolValue*>(MCPV);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000921
Jim Grosbachca21cd72010-11-10 17:59:10 +0000922 MCSymbol *MCSym;
Jim Grosbach38f8e762010-11-09 18:45:04 +0000923 if (ACPV->isLSDA()) {
Jim Grosbachca21cd72010-11-10 17:59:10 +0000924 SmallString<128> Str;
925 raw_svector_ostream OS(Str);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000926 OS << MAI->getPrivateGlobalPrefix() << "_LSDA_" << getFunctionNumber();
Jim Grosbachca21cd72010-11-10 17:59:10 +0000927 MCSym = OutContext.GetOrCreateSymbol(OS.str());
Jim Grosbach38f8e762010-11-09 18:45:04 +0000928 } else if (ACPV->isBlockAddress()) {
Bill Wendling7753d662011-10-01 08:00:54 +0000929 const BlockAddress *BA =
930 cast<ARMConstantPoolConstant>(ACPV)->getBlockAddress();
931 MCSym = GetBlockAddressSymbol(BA);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000932 } else if (ACPV->isGlobalValue()) {
Bill Wendling7753d662011-10-01 08:00:54 +0000933 const GlobalValue *GV = cast<ARMConstantPoolConstant>(ACPV)->getGV();
Evan Chengdfce83c2011-01-17 08:03:18 +0000934 MCSym = GetARMGVSymbol(GV);
Bill Wendling69bc3de2011-09-29 23:50:42 +0000935 } else if (ACPV->isMachineBasicBlock()) {
Bill Wendling4a4772f2011-10-01 09:30:42 +0000936 const MachineBasicBlock *MBB = cast<ARMConstantPoolMBB>(ACPV)->getMBB();
Bill Wendling69bc3de2011-09-29 23:50:42 +0000937 MCSym = MBB->getSymbol();
Jim Grosbach38f8e762010-11-09 18:45:04 +0000938 } else {
939 assert(ACPV->isExtSymbol() && "unrecognized constant pool value");
Bill Wendlingc214cb02011-10-01 08:58:29 +0000940 const char *Sym = cast<ARMConstantPoolSymbol>(ACPV)->getSymbol();
941 MCSym = GetExternalSymbolSymbol(Sym);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000942 }
943
944 // Create an MCSymbol for the reference.
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000945 const MCExpr *Expr =
946 MCSymbolRefExpr::Create(MCSym, getModifierVariantKind(ACPV->getModifier()),
947 OutContext);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000948
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000949 if (ACPV->getPCAdjustment()) {
950 MCSymbol *PCLabel = getPICLabel(MAI->getPrivateGlobalPrefix(),
951 getFunctionNumber(),
952 ACPV->getLabelId(),
953 OutContext);
954 const MCExpr *PCRelExpr = MCSymbolRefExpr::Create(PCLabel, OutContext);
955 PCRelExpr =
956 MCBinaryExpr::CreateAdd(PCRelExpr,
957 MCConstantExpr::Create(ACPV->getPCAdjustment(),
958 OutContext),
959 OutContext);
960 if (ACPV->mustAddCurrentAddress()) {
961 // We want "(<expr> - .)", but MC doesn't have a concept of the '.'
962 // label, so just emit a local label end reference that instead.
963 MCSymbol *DotSym = OutContext.CreateTempSymbol();
964 OutStreamer.EmitLabel(DotSym);
965 const MCExpr *DotExpr = MCSymbolRefExpr::Create(DotSym, OutContext);
966 PCRelExpr = MCBinaryExpr::CreateSub(PCRelExpr, DotExpr, OutContext);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000967 }
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000968 Expr = MCBinaryExpr::CreateSub(Expr, PCRelExpr, OutContext);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000969 }
Jim Grosbachf23b2d92010-11-10 03:26:07 +0000970 OutStreamer.EmitValue(Expr, Size);
Jim Grosbach38f8e762010-11-09 18:45:04 +0000971}
972
Jim Grosbach284eebc2010-09-22 17:39:48 +0000973void ARMAsmPrinter::EmitJumpTable(const MachineInstr *MI) {
974 unsigned Opcode = MI->getOpcode();
975 int OpNum = 1;
976 if (Opcode == ARM::BR_JTadd)
977 OpNum = 2;
978 else if (Opcode == ARM::BR_JTm)
979 OpNum = 3;
980
981 const MachineOperand &MO1 = MI->getOperand(OpNum);
982 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
983 unsigned JTI = MO1.getIndex();
984
985 // Emit a label for the jump table.
986 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
987 OutStreamer.EmitLabel(JTISymbol);
988
Jim Grosbach4b63d2a2012-05-18 19:12:01 +0000989 // Mark the jump table as data-in-code.
990 OutStreamer.EmitDataRegion(MCDR_DataRegionJT32);
991
Jim Grosbach284eebc2010-09-22 17:39:48 +0000992 // Emit each entry of the table.
993 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
994 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
995 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
996
997 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
998 MachineBasicBlock *MBB = JTBBs[i];
999 // Construct an MCExpr for the entry. We want a value of the form:
1000 // (BasicBlockAddr - TableBeginAddr)
1001 //
1002 // For example, a table with entries jumping to basic blocks BB0 and BB1
1003 // would look like:
1004 // LJTI_0_0:
1005 // .word (LBB0 - LJTI_0_0)
1006 // .word (LBB1 - LJTI_0_0)
1007 const MCExpr *Expr = MCSymbolRefExpr::Create(MBB->getSymbol(), OutContext);
1008
1009 if (TM.getRelocationModel() == Reloc::PIC_)
1010 Expr = MCBinaryExpr::CreateSub(Expr, MCSymbolRefExpr::Create(JTISymbol,
1011 OutContext),
1012 OutContext);
Jim Grosbache1995f22011-08-31 22:23:09 +00001013 // If we're generating a table of Thumb addresses in static relocation
1014 // model, we need to add one to keep interworking correctly.
1015 else if (AFI->isThumbFunction())
1016 Expr = MCBinaryExpr::CreateAdd(Expr, MCConstantExpr::Create(1,OutContext),
1017 OutContext);
Jim Grosbach284eebc2010-09-22 17:39:48 +00001018 OutStreamer.EmitValue(Expr, 4);
1019 }
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001020 // Mark the end of jump table data-in-code region.
1021 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
Jim Grosbach284eebc2010-09-22 17:39:48 +00001022}
1023
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001024void ARMAsmPrinter::EmitJump2Table(const MachineInstr *MI) {
1025 unsigned Opcode = MI->getOpcode();
1026 int OpNum = (Opcode == ARM::t2BR_JT) ? 2 : 1;
1027 const MachineOperand &MO1 = MI->getOperand(OpNum);
1028 const MachineOperand &MO2 = MI->getOperand(OpNum+1); // Unique Id
1029 unsigned JTI = MO1.getIndex();
1030
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001031 MCSymbol *JTISymbol = GetARMJTIPICJumpTableLabel2(JTI, MO2.getImm());
1032 OutStreamer.EmitLabel(JTISymbol);
1033
1034 // Emit each entry of the table.
1035 const MachineJumpTableInfo *MJTI = MF->getJumpTableInfo();
1036 const std::vector<MachineJumpTableEntry> &JT = MJTI->getJumpTables();
1037 const std::vector<MachineBasicBlock*> &JTBBs = JT[JTI].MBBs;
Jim Grosbach1573b292010-09-22 17:15:35 +00001038 unsigned OffsetWidth = 4;
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001039 if (MI->getOpcode() == ARM::t2TBB_JT) {
Jim Grosbach1573b292010-09-22 17:15:35 +00001040 OffsetWidth = 1;
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001041 // Mark the jump table as data-in-code.
1042 OutStreamer.EmitDataRegion(MCDR_DataRegionJT8);
1043 } else if (MI->getOpcode() == ARM::t2TBH_JT) {
Jim Grosbach1573b292010-09-22 17:15:35 +00001044 OffsetWidth = 2;
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001045 // Mark the jump table as data-in-code.
1046 OutStreamer.EmitDataRegion(MCDR_DataRegionJT16);
1047 }
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001048
1049 for (unsigned i = 0, e = JTBBs.size(); i != e; ++i) {
1050 MachineBasicBlock *MBB = JTBBs[i];
Jim Grosbach1573b292010-09-22 17:15:35 +00001051 const MCExpr *MBBSymbolExpr = MCSymbolRefExpr::Create(MBB->getSymbol(),
1052 OutContext);
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001053 // If this isn't a TBB or TBH, the entries are direct branch instructions.
Jim Grosbach1573b292010-09-22 17:15:35 +00001054 if (OffsetWidth == 4) {
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001055 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2B)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001056 .addExpr(MBBSymbolExpr)
1057 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001058 .addReg(0));
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001059 continue;
1060 }
1061 // Otherwise it's an offset from the dispatch instruction. Construct an
Jim Grosbach1573b292010-09-22 17:15:35 +00001062 // MCExpr for the entry. We want a value of the form:
1063 // (BasicBlockAddr - TableBeginAddr) / 2
1064 //
1065 // For example, a TBB table with entries jumping to basic blocks BB0 and BB1
1066 // would look like:
1067 // LJTI_0_0:
1068 // .byte (LBB0 - LJTI_0_0) / 2
1069 // .byte (LBB1 - LJTI_0_0) / 2
1070 const MCExpr *Expr =
1071 MCBinaryExpr::CreateSub(MBBSymbolExpr,
1072 MCSymbolRefExpr::Create(JTISymbol, OutContext),
1073 OutContext);
1074 Expr = MCBinaryExpr::CreateDiv(Expr, MCConstantExpr::Create(2, OutContext),
1075 OutContext);
1076 OutStreamer.EmitValue(Expr, OffsetWidth);
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001077 }
Jim Grosbach2597f832012-05-21 23:34:42 +00001078 // Mark the end of jump table data-in-code region. 32-bit offsets use
1079 // actual branch instructions here, so we don't mark those as a data-region
1080 // at all.
1081 if (OffsetWidth != 4)
1082 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001083}
1084
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001085void ARMAsmPrinter::EmitUnwindingInstruction(const MachineInstr *MI) {
1086 assert(MI->getFlag(MachineInstr::FrameSetup) &&
1087 "Only instruction which are involved into frame setup code are allowed");
1088
1089 const MachineFunction &MF = *MI->getParent()->getParent();
1090 const TargetRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
Anton Korobeynikov9e66cbb2011-03-05 18:43:55 +00001091 const ARMFunctionInfo &AFI = *MF.getInfo<ARMFunctionInfo>();
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001092
1093 unsigned FramePtr = RegInfo->getFrameRegister(MF);
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001094 unsigned Opc = MI->getOpcode();
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001095 unsigned SrcReg, DstReg;
1096
Anton Korobeynikova8d177b2011-03-05 18:43:50 +00001097 if (Opc == ARM::tPUSH || Opc == ARM::tLDRpci) {
1098 // Two special cases:
1099 // 1) tPUSH does not have src/dst regs.
1100 // 2) for Thumb1 code we sometimes materialize the constant via constpool
1101 // load. Yes, this is pretty fragile, but for now I don't see better
1102 // way... :(
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001103 SrcReg = DstReg = ARM::SP;
1104 } else {
Anton Korobeynikova8d177b2011-03-05 18:43:50 +00001105 SrcReg = MI->getOperand(1).getReg();
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001106 DstReg = MI->getOperand(0).getReg();
1107 }
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001108
1109 // Try to figure out the unwinding opcode out of src / dst regs.
Evan Cheng7f8e5632011-12-07 07:15:52 +00001110 if (MI->mayStore()) {
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001111 // Register saves.
1112 assert(DstReg == ARM::SP &&
1113 "Only stack pointer as a destination reg is supported");
1114
1115 SmallVector<unsigned, 4> RegList;
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001116 // Skip src & dst reg, and pred ops.
1117 unsigned StartOp = 2 + 2;
1118 // Use all the operands.
1119 unsigned NumOffset = 0;
1120
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001121 switch (Opc) {
1122 default:
1123 MI->dump();
Craig Toppere55c5562012-02-07 02:50:20 +00001124 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001125 case ARM::tPUSH:
1126 // Special case here: no src & dst reg, but two extra imp ops.
1127 StartOp = 2; NumOffset = 2;
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001128 case ARM::STMDB_UPD:
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001129 case ARM::t2STMDB_UPD:
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001130 case ARM::VSTMDDB_UPD:
1131 assert(SrcReg == ARM::SP &&
1132 "Only stack pointer as a source reg is supported");
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001133 for (unsigned i = StartOp, NumOps = MI->getNumOperands() - NumOffset;
Anton Korobeynikovef731ed2012-08-04 13:25:58 +00001134 i != NumOps; ++i) {
1135 const MachineOperand &MO = MI->getOperand(i);
1136 // Actually, there should never be any impdef stuff here. Skip it
1137 // temporary to workaround PR11902.
1138 if (MO.isImplicit())
1139 continue;
1140 RegList.push_back(MO.getReg());
1141 }
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001142 break;
Owen Anderson2aedba62011-07-26 20:54:26 +00001143 case ARM::STR_PRE_IMM:
1144 case ARM::STR_PRE_REG:
Evgeniy Stepanov4c7eb472012-01-19 12:53:06 +00001145 case ARM::t2STR_PRE:
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001146 assert(MI->getOperand(2).getReg() == ARM::SP &&
1147 "Only stack pointer as a source reg is supported");
1148 RegList.push_back(SrcReg);
1149 break;
1150 }
1151 OutStreamer.EmitRegSave(RegList, Opc == ARM::VSTMDDB_UPD);
1152 } else {
1153 // Changes of stack / frame pointer.
1154 if (SrcReg == ARM::SP) {
1155 int64_t Offset = 0;
1156 switch (Opc) {
1157 default:
1158 MI->dump();
Craig Toppere55c5562012-02-07 02:50:20 +00001159 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001160 case ARM::MOVr:
Evgeniy Stepanov4c7eb472012-01-19 12:53:06 +00001161 case ARM::tMOVr:
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001162 Offset = 0;
1163 break;
1164 case ARM::ADDri:
1165 Offset = -MI->getOperand(2).getImm();
1166 break;
1167 case ARM::SUBri:
Evgeniy Stepanov4c7eb472012-01-19 12:53:06 +00001168 case ARM::t2SUBri:
Jim Grosbacha8a80672011-06-29 23:25:04 +00001169 Offset = MI->getOperand(2).getImm();
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001170 break;
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001171 case ARM::tSUBspi:
Jim Grosbacha8a80672011-06-29 23:25:04 +00001172 Offset = MI->getOperand(2).getImm()*4;
Anton Korobeynikov51537f12011-03-05 18:43:43 +00001173 break;
1174 case ARM::tADDspi:
1175 case ARM::tADDrSPi:
1176 Offset = -MI->getOperand(2).getImm()*4;
1177 break;
Anton Korobeynikov9e66cbb2011-03-05 18:43:55 +00001178 case ARM::tLDRpci: {
1179 // Grab the constpool index and check, whether it corresponds to
1180 // original or cloned constpool entry.
1181 unsigned CPI = MI->getOperand(1).getIndex();
1182 const MachineConstantPool *MCP = MF.getConstantPool();
1183 if (CPI >= MCP->getConstants().size())
1184 CPI = AFI.getOriginalCPIdx(CPI);
1185 assert(CPI != -1U && "Invalid constpool index");
1186
1187 // Derive the actual offset.
1188 const MachineConstantPoolEntry &CPE = MCP->getConstants()[CPI];
1189 assert(!CPE.isMachineConstantPoolEntry() && "Invalid constpool entry");
1190 // FIXME: Check for user, it should be "add" instruction!
1191 Offset = -cast<ConstantInt>(CPE.Val.ConstVal)->getSExtValue();
Anton Korobeynikova8d177b2011-03-05 18:43:50 +00001192 break;
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001193 }
Anton Korobeynikov9e66cbb2011-03-05 18:43:55 +00001194 }
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001195
1196 if (DstReg == FramePtr && FramePtr != ARM::SP)
Anton Korobeynikov692f6332011-03-05 18:44:00 +00001197 // Set-up of the frame pointer. Positive values correspond to "add"
1198 // instruction.
1199 OutStreamer.EmitSetFP(FramePtr, ARM::SP, -Offset);
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001200 else if (DstReg == ARM::SP) {
Anton Korobeynikov692f6332011-03-05 18:44:00 +00001201 // Change of SP by an offset. Positive values correspond to "sub"
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001202 // instruction.
1203 OutStreamer.EmitPad(Offset);
1204 } else {
1205 MI->dump();
Craig Toppere55c5562012-02-07 02:50:20 +00001206 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001207 }
1208 } else if (DstReg == ARM::SP) {
1209 // FIXME: .movsp goes here
1210 MI->dump();
Craig Toppere55c5562012-02-07 02:50:20 +00001211 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001212 }
1213 else {
1214 MI->dump();
Craig Toppere55c5562012-02-07 02:50:20 +00001215 llvm_unreachable("Unsupported opcode for unwinding information");
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001216 }
1217 }
1218}
1219
Chandler Carruthed975232012-01-24 00:30:17 +00001220extern cl::opt<bool> EnableARMEHABI;
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001221
Jim Grosbach95dee402011-07-08 17:40:42 +00001222// Simple pseudo-instructions have their lowering (with expansion to real
1223// instructions) auto-generated.
1224#include "ARMGenMCPseudoLowering.inc"
1225
Jim Grosbach05eccf02010-09-29 15:23:40 +00001226void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001227 // If we just ended a constant pool, mark it as such.
1228 if (InConstantPool && MI->getOpcode() != ARM::CONSTPOOL_ENTRY) {
1229 OutStreamer.EmitDataRegion(MCDR_DataRegionEnd);
1230 InConstantPool = false;
1231 }
Owen Anderson0ca562e2011-10-04 23:26:17 +00001232
Jim Grosbach51b55422011-08-23 21:32:34 +00001233 // Emit unwinding stuff for frame-related instructions
Chandler Carruthed975232012-01-24 00:30:17 +00001234 if (EnableARMEHABI && MI->getFlag(MachineInstr::FrameSetup))
Jim Grosbach51b55422011-08-23 21:32:34 +00001235 EmitUnwindingInstruction(MI);
1236
Jim Grosbach95dee402011-07-08 17:40:42 +00001237 // Do any auto-generated pseudo lowerings.
1238 if (emitPseudoExpansionLowering(OutStreamer, MI))
1239 return;
1240
Andrew Trick924123a2011-09-21 02:20:46 +00001241 assert(!convertAddSubFlagsOpcode(MI->getOpcode()) &&
1242 "Pseudo flag setting opcode should be expanded early");
1243
Jim Grosbach95dee402011-07-08 17:40:42 +00001244 // Check for manual lowerings.
Evan Chengdfce83c2011-01-17 08:03:18 +00001245 unsigned Opc = MI->getOpcode();
1246 switch (Opc) {
Craig Toppere55c5562012-02-07 02:50:20 +00001247 case ARM::t2MOVi32imm: llvm_unreachable("Should be lowered by thumb2it pass");
David Blaikieb735b4d2013-06-16 20:34:27 +00001248 case ARM::DBG_VALUE: llvm_unreachable("Should be handled by generic printing");
Jim Grosbach8c1fabe2010-12-14 21:10:47 +00001249 case ARM::LEApcrel:
Jim Grosbach509dc2a2010-12-14 22:28:03 +00001250 case ARM::tLEApcrel:
Jim Grosbach8c1fabe2010-12-14 21:10:47 +00001251 case ARM::t2LEApcrel: {
Jim Grosbachce2bd8d2010-12-02 00:28:45 +00001252 // FIXME: Need to also handle globals and externals
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001253 MCSymbol *CPISymbol = GetCPISymbol(MI->getOperand(1).getIndex());
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001254 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1255 ARM::t2LEApcrel ? ARM::t2ADR
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001256 : (MI->getOpcode() == ARM::tLEApcrel ? ARM::tADR
1257 : ARM::ADR))
1258 .addReg(MI->getOperand(0).getReg())
1259 .addExpr(MCSymbolRefExpr::Create(CPISymbol, OutContext))
1260 // Add predicate operands.
1261 .addImm(MI->getOperand(2).getImm())
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001262 .addReg(MI->getOperand(3).getReg()));
Jim Grosbachce2bd8d2010-12-02 00:28:45 +00001263 return;
1264 }
Jim Grosbach509dc2a2010-12-14 22:28:03 +00001265 case ARM::LEApcrelJT:
1266 case ARM::tLEApcrelJT:
1267 case ARM::t2LEApcrelJT: {
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001268 MCSymbol *JTIPICSymbol =
1269 GetARMJTIPICJumpTableLabel2(MI->getOperand(1).getIndex(),
1270 MI->getOperand(2).getImm());
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001271 OutStreamer.EmitInstruction(MCInstBuilder(MI->getOpcode() ==
1272 ARM::t2LEApcrelJT ? ARM::t2ADR
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001273 : (MI->getOpcode() == ARM::tLEApcrelJT ? ARM::tADR
1274 : ARM::ADR))
1275 .addReg(MI->getOperand(0).getReg())
1276 .addExpr(MCSymbolRefExpr::Create(JTIPICSymbol, OutContext))
1277 // Add predicate operands.
1278 .addImm(MI->getOperand(3).getImm())
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001279 .addReg(MI->getOperand(4).getReg()));
Jim Grosbachdc35e062010-12-01 19:47:31 +00001280 return;
1281 }
Jim Grosbach3f2096e2011-03-12 00:45:26 +00001282 // Darwin call instructions are just normal call instructions with different
1283 // clobber semantics (they clobber R9).
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001284 case ARM::BX_CALL: {
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001285 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001286 .addReg(ARM::LR)
1287 .addReg(ARM::PC)
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001288 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001289 .addImm(ARMCC::AL)
1290 .addReg(0)
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001291 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001292 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001293
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001294 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
1295 .addReg(MI->getOperand(0).getReg()));
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001296 return;
1297 }
Cameron Zwaricha946f472011-05-25 21:53:50 +00001298 case ARM::tBX_CALL: {
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001299 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001300 .addReg(ARM::LR)
1301 .addReg(ARM::PC)
Jim Grosbachb98ab912011-06-30 22:10:46 +00001302 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001303 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001304 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001305
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001306 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001307 .addReg(MI->getOperand(0).getReg())
Cameron Zwaricha946f472011-05-25 21:53:50 +00001308 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001309 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001310 .addReg(0));
Cameron Zwaricha946f472011-05-25 21:53:50 +00001311 return;
1312 }
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001313 case ARM::BMOVPCRX_CALL: {
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001314 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001315 .addReg(ARM::LR)
1316 .addReg(ARM::PC)
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001317 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001318 .addImm(ARMCC::AL)
1319 .addReg(0)
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001320 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001321 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001322
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001323 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001324 .addReg(ARM::PC)
Benjamin Kramer2f545712013-03-15 17:27:39 +00001325 .addReg(MI->getOperand(0).getReg())
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001326 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001327 .addImm(ARMCC::AL)
1328 .addReg(0)
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001329 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001330 .addReg(0));
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001331 return;
1332 }
Evan Cheng65f9d192012-02-28 18:51:51 +00001333 case ARM::BMOVPCB_CALL: {
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001334 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001335 .addReg(ARM::LR)
1336 .addReg(ARM::PC)
Evan Cheng65f9d192012-02-28 18:51:51 +00001337 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001338 .addImm(ARMCC::AL)
1339 .addReg(0)
Evan Cheng65f9d192012-02-28 18:51:51 +00001340 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001341 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001342
1343 const GlobalValue *GV = MI->getOperand(0).getGlobal();
1344 MCSymbol *GVSym = Mang->getSymbol(GV);
1345 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001346 OutStreamer.EmitInstruction(MCInstBuilder(ARM::Bcc)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001347 .addExpr(GVSymExpr)
Evan Cheng65f9d192012-02-28 18:51:51 +00001348 // Add predicate operands.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001349 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001350 .addReg(0));
Evan Cheng65f9d192012-02-28 18:51:51 +00001351 return;
1352 }
Evan Cheng2f2435d2011-01-21 18:55:51 +00001353 case ARM::MOVi16_ga_pcrel:
1354 case ARM::t2MOVi16_ga_pcrel: {
Evan Chengdfce83c2011-01-17 08:03:18 +00001355 MCInst TmpInst;
Evan Cheng2f2435d2011-01-21 18:55:51 +00001356 TmpInst.setOpcode(Opc == ARM::MOVi16_ga_pcrel? ARM::MOVi16 : ARM::t2MOVi16);
Evan Chengdfce83c2011-01-17 08:03:18 +00001357 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1358
Evan Cheng2f2435d2011-01-21 18:55:51 +00001359 unsigned TF = MI->getOperand(1).getTargetFlags();
1360 bool isPIC = TF == ARMII::MO_LO16_NONLAZY_PIC;
Evan Chengdfce83c2011-01-17 08:03:18 +00001361 const GlobalValue *GV = MI->getOperand(1).getGlobal();
1362 MCSymbol *GVSym = GetARMGVSymbol(GV);
1363 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng2f2435d2011-01-21 18:55:51 +00001364 if (isPIC) {
1365 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1366 getFunctionNumber(),
1367 MI->getOperand(2).getImm(), OutContext);
1368 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1369 unsigned PCAdj = (Opc == ARM::MOVi16_ga_pcrel) ? 8 : 4;
1370 const MCExpr *PCRelExpr =
1371 ARMMCExpr::CreateLower16(MCBinaryExpr::CreateSub(GVSymExpr,
1372 MCBinaryExpr::CreateAdd(LabelSymExpr,
1373 MCConstantExpr::Create(PCAdj, OutContext),
Evan Chengdfce83c2011-01-17 08:03:18 +00001374 OutContext), OutContext), OutContext);
Evan Cheng2f2435d2011-01-21 18:55:51 +00001375 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1376 } else {
1377 const MCExpr *RefExpr= ARMMCExpr::CreateLower16(GVSymExpr, OutContext);
1378 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1379 }
1380
Evan Chengdfce83c2011-01-17 08:03:18 +00001381 // Add predicate operands.
1382 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1383 TmpInst.addOperand(MCOperand::CreateReg(0));
1384 // Add 's' bit operand (always reg0 for this)
1385 TmpInst.addOperand(MCOperand::CreateReg(0));
1386 OutStreamer.EmitInstruction(TmpInst);
1387 return;
1388 }
Evan Cheng2f2435d2011-01-21 18:55:51 +00001389 case ARM::MOVTi16_ga_pcrel:
1390 case ARM::t2MOVTi16_ga_pcrel: {
Evan Chengdfce83c2011-01-17 08:03:18 +00001391 MCInst TmpInst;
Evan Cheng2f2435d2011-01-21 18:55:51 +00001392 TmpInst.setOpcode(Opc == ARM::MOVTi16_ga_pcrel
1393 ? ARM::MOVTi16 : ARM::t2MOVTi16);
Evan Chengdfce83c2011-01-17 08:03:18 +00001394 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1395 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1396
Evan Cheng2f2435d2011-01-21 18:55:51 +00001397 unsigned TF = MI->getOperand(2).getTargetFlags();
1398 bool isPIC = TF == ARMII::MO_HI16_NONLAZY_PIC;
Evan Chengdfce83c2011-01-17 08:03:18 +00001399 const GlobalValue *GV = MI->getOperand(2).getGlobal();
1400 MCSymbol *GVSym = GetARMGVSymbol(GV);
1401 const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
Evan Cheng2f2435d2011-01-21 18:55:51 +00001402 if (isPIC) {
1403 MCSymbol *LabelSym = getPICLabel(MAI->getPrivateGlobalPrefix(),
1404 getFunctionNumber(),
1405 MI->getOperand(3).getImm(), OutContext);
1406 const MCExpr *LabelSymExpr= MCSymbolRefExpr::Create(LabelSym, OutContext);
1407 unsigned PCAdj = (Opc == ARM::MOVTi16_ga_pcrel) ? 8 : 4;
1408 const MCExpr *PCRelExpr =
1409 ARMMCExpr::CreateUpper16(MCBinaryExpr::CreateSub(GVSymExpr,
1410 MCBinaryExpr::CreateAdd(LabelSymExpr,
1411 MCConstantExpr::Create(PCAdj, OutContext),
Evan Chengdfce83c2011-01-17 08:03:18 +00001412 OutContext), OutContext), OutContext);
Evan Cheng2f2435d2011-01-21 18:55:51 +00001413 TmpInst.addOperand(MCOperand::CreateExpr(PCRelExpr));
1414 } else {
1415 const MCExpr *RefExpr= ARMMCExpr::CreateUpper16(GVSymExpr, OutContext);
1416 TmpInst.addOperand(MCOperand::CreateExpr(RefExpr));
1417 }
Evan Chengdfce83c2011-01-17 08:03:18 +00001418 // Add predicate operands.
1419 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1420 TmpInst.addOperand(MCOperand::CreateReg(0));
1421 // Add 's' bit operand (always reg0 for this)
1422 TmpInst.addOperand(MCOperand::CreateReg(0));
1423 OutStreamer.EmitInstruction(TmpInst);
1424 return;
1425 }
Jim Grosbach3d979202010-09-17 23:41:53 +00001426 case ARM::tPICADD: {
1427 // This is a pseudo op for a label + instruction sequence, which looks like:
1428 // LPC0:
1429 // add r0, pc
1430 // This adds the address of LPC0 to r0.
1431
1432 // Emit the label.
Jim Grosbachaf5d6352010-09-18 00:05:05 +00001433 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1434 getFunctionNumber(), MI->getOperand(2).getImm(),
1435 OutContext));
Jim Grosbach3d979202010-09-17 23:41:53 +00001436
1437 // Form and emit the add.
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001438 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDhirr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001439 .addReg(MI->getOperand(0).getReg())
1440 .addReg(MI->getOperand(0).getReg())
1441 .addReg(ARM::PC)
1442 // Add predicate operands.
1443 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001444 .addReg(0));
Jim Grosbach3d979202010-09-17 23:41:53 +00001445 return;
1446 }
Jim Grosbachc8e2e9d2010-09-30 19:53:58 +00001447 case ARM::PICADD: {
Chris Lattneradd57492009-10-19 22:23:04 +00001448 // This is a pseudo op for a label + instruction sequence, which looks like:
1449 // LPC0:
1450 // add r0, pc, r0
1451 // This adds the address of LPC0 to r0.
Jim Grosbach8ee5cd92010-09-02 01:02:06 +00001452
Chris Lattneradd57492009-10-19 22:23:04 +00001453 // Emit the label.
Jim Grosbachaf5d6352010-09-18 00:05:05 +00001454 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1455 getFunctionNumber(), MI->getOperand(2).getImm(),
1456 OutContext));
Jim Grosbach8ee5cd92010-09-02 01:02:06 +00001457
Jim Grosbach7ae94222010-09-14 21:05:34 +00001458 // Form and emit the add.
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001459 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001460 .addReg(MI->getOperand(0).getReg())
1461 .addReg(ARM::PC)
1462 .addReg(MI->getOperand(1).getReg())
1463 // Add predicate operands.
1464 .addImm(MI->getOperand(3).getImm())
1465 .addReg(MI->getOperand(4).getReg())
1466 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001467 .addReg(0));
Chris Lattneradd57492009-10-19 22:23:04 +00001468 return;
1469 }
Jim Grosbacha7d430b2010-09-17 16:25:52 +00001470 case ARM::PICSTR:
1471 case ARM::PICSTRB:
1472 case ARM::PICSTRH:
1473 case ARM::PICLDR:
1474 case ARM::PICLDRB:
1475 case ARM::PICLDRH:
1476 case ARM::PICLDRSB:
1477 case ARM::PICLDRSH: {
Jim Grosbach218e22d2010-09-16 17:43:25 +00001478 // This is a pseudo op for a label + instruction sequence, which looks like:
1479 // LPC0:
Jim Grosbacha7d430b2010-09-17 16:25:52 +00001480 // OP r0, [pc, r0]
Jim Grosbach218e22d2010-09-16 17:43:25 +00001481 // The LCP0 label is referenced by a constant pool entry in order to get
1482 // a PC-relative address at the ldr instruction.
1483
1484 // Emit the label.
Jim Grosbachaf5d6352010-09-18 00:05:05 +00001485 OutStreamer.EmitLabel(getPICLabel(MAI->getPrivateGlobalPrefix(),
1486 getFunctionNumber(), MI->getOperand(2).getImm(),
1487 OutContext));
Jim Grosbach218e22d2010-09-16 17:43:25 +00001488
1489 // Form and emit the load
Jim Grosbacha7d430b2010-09-17 16:25:52 +00001490 unsigned Opcode;
1491 switch (MI->getOpcode()) {
1492 default:
1493 llvm_unreachable("Unexpected opcode!");
Jim Grosbach338de3e2010-10-27 23:12:14 +00001494 case ARM::PICSTR: Opcode = ARM::STRrs; break;
1495 case ARM::PICSTRB: Opcode = ARM::STRBrs; break;
Jim Grosbacha7d430b2010-09-17 16:25:52 +00001496 case ARM::PICSTRH: Opcode = ARM::STRH; break;
Jim Grosbach1e4d9a12010-10-26 22:37:02 +00001497 case ARM::PICLDR: Opcode = ARM::LDRrs; break;
Jim Grosbach5a7c7152010-10-27 00:19:44 +00001498 case ARM::PICLDRB: Opcode = ARM::LDRBrs; break;
Jim Grosbacha7d430b2010-09-17 16:25:52 +00001499 case ARM::PICLDRH: Opcode = ARM::LDRH; break;
1500 case ARM::PICLDRSB: Opcode = ARM::LDRSB; break;
1501 case ARM::PICLDRSH: Opcode = ARM::LDRSH; break;
1502 }
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001503 OutStreamer.EmitInstruction(MCInstBuilder(Opcode)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001504 .addReg(MI->getOperand(0).getReg())
1505 .addReg(ARM::PC)
1506 .addReg(MI->getOperand(1).getReg())
1507 .addImm(0)
1508 // Add predicate operands.
1509 .addImm(MI->getOperand(3).getImm())
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001510 .addReg(MI->getOperand(4).getReg()));
Jim Grosbach218e22d2010-09-16 17:43:25 +00001511
1512 return;
1513 }
Jim Grosbachc8e2e9d2010-09-30 19:53:58 +00001514 case ARM::CONSTPOOL_ENTRY: {
Chris Lattner186c6b02009-10-19 22:33:05 +00001515 /// CONSTPOOL_ENTRY - This instruction represents a floating constant pool
1516 /// in the function. The first operand is the ID# for this instruction, the
1517 /// second is the index into the MachineConstantPool that this is, the third
1518 /// is the size in bytes of this constant pool entry.
Jakob Stoklund Olesen2e05db22011-12-06 01:43:02 +00001519 /// The required alignment is specified on the basic block holding this MI.
Chris Lattner186c6b02009-10-19 22:33:05 +00001520 unsigned LabelId = (unsigned)MI->getOperand(0).getImm();
1521 unsigned CPIdx = (unsigned)MI->getOperand(1).getIndex();
1522
Jim Grosbach4b63d2a2012-05-18 19:12:01 +00001523 // If this is the first entry of the pool, mark it.
1524 if (!InConstantPool) {
1525 OutStreamer.EmitDataRegion(MCDR_DataRegion);
1526 InConstantPool = true;
1527 }
1528
Chris Lattnerc55ea3f2010-01-23 07:00:21 +00001529 OutStreamer.EmitLabel(GetCPISymbol(LabelId));
Chris Lattner186c6b02009-10-19 22:33:05 +00001530
1531 const MachineConstantPoolEntry &MCPE = MCP->getConstants()[CPIdx];
1532 if (MCPE.isMachineConstantPoolEntry())
1533 EmitMachineConstantPoolValue(MCPE.Val.MachineCPVal);
1534 else
1535 EmitGlobalConstant(MCPE.Val.ConstVal);
Chris Lattner186c6b02009-10-19 22:33:05 +00001536 return;
1537 }
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001538 case ARM::t2BR_JT: {
1539 // Lower and emit the instruction itself, then the jump table following it.
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001540 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001541 .addReg(ARM::PC)
1542 .addReg(MI->getOperand(0).getReg())
1543 // Add predicate operands.
1544 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001545 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001546
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001547 // Output the data for the jump table itself
1548 EmitJump2Table(MI);
1549 return;
1550 }
1551 case ARM::t2TBB_JT: {
1552 // Lower and emit the instruction itself, then the jump table following it.
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001553 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBB)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001554 .addReg(ARM::PC)
1555 .addReg(MI->getOperand(0).getReg())
1556 // Add predicate operands.
1557 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001558 .addReg(0));
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001559
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001560 // Output the data for the jump table itself
1561 EmitJump2Table(MI);
1562 // Make sure the next instruction is 2-byte aligned.
1563 EmitAlignment(1);
1564 return;
1565 }
1566 case ARM::t2TBH_JT: {
1567 // Lower and emit the instruction itself, then the jump table following it.
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001568 OutStreamer.EmitInstruction(MCInstBuilder(ARM::t2TBH)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001569 .addReg(ARM::PC)
1570 .addReg(MI->getOperand(0).getReg())
1571 // Add predicate operands.
1572 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001573 .addReg(0));
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001574
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001575 // Output the data for the jump table itself
Jim Grosbachd64f9b82010-09-21 23:28:16 +00001576 EmitJump2Table(MI);
1577 return;
1578 }
Jim Grosbach58bc36a2010-11-29 19:32:47 +00001579 case ARM::tBR_JTr:
Jim Grosbach150b1ad2010-11-29 18:37:44 +00001580 case ARM::BR_JTr: {
1581 // Lower and emit the instruction itself, then the jump table following it.
1582 // mov pc, target
1583 MCInst TmpInst;
Jim Grosbach7ec3d342010-11-29 22:37:40 +00001584 unsigned Opc = MI->getOpcode() == ARM::BR_JTr ?
Jim Grosbache9cc9012011-06-30 23:38:17 +00001585 ARM::MOVr : ARM::tMOVr;
Jim Grosbach58bc36a2010-11-29 19:32:47 +00001586 TmpInst.setOpcode(Opc);
Jim Grosbach150b1ad2010-11-29 18:37:44 +00001587 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1588 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1589 // Add predicate operands.
1590 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1591 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbachcd5e30f2010-11-30 18:30:19 +00001592 // Add 's' bit operand (always reg0 for this)
1593 if (Opc == ARM::MOVr)
1594 TmpInst.addOperand(MCOperand::CreateReg(0));
Jim Grosbach150b1ad2010-11-29 18:37:44 +00001595 OutStreamer.EmitInstruction(TmpInst);
1596
Jim Grosbach58bc36a2010-11-29 19:32:47 +00001597 // Make sure the Thumb jump table is 4-byte aligned.
Jim Grosbache9cc9012011-06-30 23:38:17 +00001598 if (Opc == ARM::tMOVr)
Jim Grosbach58bc36a2010-11-29 19:32:47 +00001599 EmitAlignment(2);
1600
Jim Grosbach150b1ad2010-11-29 18:37:44 +00001601 // Output the data for the jump table itself
1602 EmitJumpTable(MI);
1603 return;
1604 }
1605 case ARM::BR_JTm: {
1606 // Lower and emit the instruction itself, then the jump table following it.
1607 // ldr pc, target
1608 MCInst TmpInst;
1609 if (MI->getOperand(1).getReg() == 0) {
1610 // literal offset
1611 TmpInst.setOpcode(ARM::LDRi12);
1612 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1613 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1614 TmpInst.addOperand(MCOperand::CreateImm(MI->getOperand(2).getImm()));
1615 } else {
1616 TmpInst.setOpcode(ARM::LDRrs);
1617 TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
1618 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(0).getReg()));
1619 TmpInst.addOperand(MCOperand::CreateReg(MI->getOperand(1).getReg()));
1620 TmpInst.addOperand(MCOperand::CreateImm(0));
1621 }
1622 // Add predicate operands.
1623 TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
1624 TmpInst.addOperand(MCOperand::CreateReg(0));
1625 OutStreamer.EmitInstruction(TmpInst);
1626
1627 // Output the data for the jump table itself
Jim Grosbach284eebc2010-09-22 17:39:48 +00001628 EmitJumpTable(MI);
1629 return;
1630 }
Jim Grosbach08c562b2010-11-17 21:05:55 +00001631 case ARM::BR_JTadd: {
1632 // Lower and emit the instruction itself, then the jump table following it.
1633 // add pc, target, idx
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001634 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDrr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001635 .addReg(ARM::PC)
1636 .addReg(MI->getOperand(0).getReg())
1637 .addReg(MI->getOperand(1).getReg())
1638 // Add predicate operands.
1639 .addImm(ARMCC::AL)
1640 .addReg(0)
1641 // Add 's' bit operand (always reg0 for this)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001642 .addReg(0));
Jim Grosbach08c562b2010-11-17 21:05:55 +00001643
1644 // Output the data for the jump table itself
1645 EmitJumpTable(MI);
1646 return;
1647 }
Jim Grosbach85030542010-09-23 18:05:37 +00001648 case ARM::TRAP: {
1649 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1650 // FIXME: Remove this special case when they do.
1651 if (!Subtarget->isTargetDarwin()) {
Jim Grosbachfae83052010-10-01 23:21:38 +00001652 //.long 0xe7ffdefe @ trap
Jim Grosbach7d348372010-09-23 19:42:17 +00001653 uint32_t Val = 0xe7ffdefeUL;
Jim Grosbach85030542010-09-23 18:05:37 +00001654 OutStreamer.AddComment("trap");
1655 OutStreamer.EmitIntValue(Val, 4);
1656 return;
1657 }
1658 break;
1659 }
Eli Bendersky2e2ce492013-01-30 16:30:19 +00001660 case ARM::TRAPNaCl: {
1661 //.long 0xe7fedef0 @ trap
1662 uint32_t Val = 0xe7fedef0UL;
1663 OutStreamer.AddComment("trap");
1664 OutStreamer.EmitIntValue(Val, 4);
1665 return;
1666 }
Jim Grosbach85030542010-09-23 18:05:37 +00001667 case ARM::tTRAP: {
1668 // Non-Darwin binutils don't yet support the "trap" mnemonic.
1669 // FIXME: Remove this special case when they do.
1670 if (!Subtarget->isTargetDarwin()) {
Jim Grosbachfae83052010-10-01 23:21:38 +00001671 //.short 57086 @ trap
Benjamin Kramere38495d2010-09-23 18:57:26 +00001672 uint16_t Val = 0xdefe;
Jim Grosbach85030542010-09-23 18:05:37 +00001673 OutStreamer.AddComment("trap");
1674 OutStreamer.EmitIntValue(Val, 2);
1675 return;
1676 }
1677 break;
1678 }
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001679 case ARM::t2Int_eh_sjlj_setjmp:
1680 case ARM::t2Int_eh_sjlj_setjmp_nofp:
Jim Grosbachc8e2e9d2010-09-30 19:53:58 +00001681 case ARM::tInt_eh_sjlj_setjmp: {
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001682 // Two incoming args: GPR:$src, GPR:$val
1683 // mov $val, pc
1684 // adds $val, #7
1685 // str $val, [$src, #4]
1686 // movs r0, #0
1687 // b 1f
1688 // movs r0, #1
1689 // 1:
1690 unsigned SrcReg = MI->getOperand(0).getReg();
1691 unsigned ValReg = MI->getOperand(1).getReg();
1692 MCSymbol *Label = GetARMSJLJEHLabel();
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001693 OutStreamer.AddComment("eh_setjmp begin");
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001694 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001695 .addReg(ValReg)
1696 .addReg(ARM::PC)
Jim Grosbachb98ab912011-06-30 22:10:46 +00001697 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001698 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001699 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001700
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001701 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tADDi3)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001702 .addReg(ValReg)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001703 // 's' bit operand
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001704 .addReg(ARM::CPSR)
1705 .addReg(ValReg)
1706 .addImm(7)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001707 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001708 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001709 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001710
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001711 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tSTRi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001712 .addReg(ValReg)
1713 .addReg(SrcReg)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001714 // The offset immediate is #4. The operand value is scaled by 4 for the
1715 // tSTR instruction.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001716 .addImm(1)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001717 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001718 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001719 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001720
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001721 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001722 .addReg(ARM::R0)
1723 .addReg(ARM::CPSR)
1724 .addImm(0)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001725 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001726 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001727 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001728
1729 const MCExpr *SymbolExpr = MCSymbolRefExpr::Create(Label, OutContext);
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001730 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tB)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001731 .addExpr(SymbolExpr)
1732 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001733 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001734
1735 OutStreamer.AddComment("eh_setjmp end");
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001736 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVi8)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001737 .addReg(ARM::R0)
1738 .addReg(ARM::CPSR)
1739 .addImm(1)
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001740 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001741 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001742 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001743
Jim Grosbach4a6ab132010-09-24 20:47:58 +00001744 OutStreamer.EmitLabel(Label);
1745 return;
1746 }
1747
Jim Grosbachc0aed712010-09-23 23:33:56 +00001748 case ARM::Int_eh_sjlj_setjmp_nofp:
Jim Grosbachc8e2e9d2010-09-30 19:53:58 +00001749 case ARM::Int_eh_sjlj_setjmp: {
Jim Grosbachc0aed712010-09-23 23:33:56 +00001750 // Two incoming args: GPR:$src, GPR:$val
1751 // add $val, pc, #8
1752 // str $val, [$src, #+4]
1753 // mov r0, #0
1754 // add pc, pc, #0
1755 // mov r0, #1
1756 unsigned SrcReg = MI->getOperand(0).getReg();
1757 unsigned ValReg = MI->getOperand(1).getReg();
1758
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001759 OutStreamer.AddComment("eh_setjmp begin");
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001760 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001761 .addReg(ValReg)
1762 .addReg(ARM::PC)
1763 .addImm(8)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001764 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001765 .addImm(ARMCC::AL)
1766 .addReg(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001767 // 's' bit operand (always reg0 for this).
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001768 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001769
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001770 OutStreamer.EmitInstruction(MCInstBuilder(ARM::STRi12)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001771 .addReg(ValReg)
1772 .addReg(SrcReg)
1773 .addImm(4)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001774 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001775 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001776 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001777
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001778 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001779 .addReg(ARM::R0)
1780 .addImm(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001781 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001782 .addImm(ARMCC::AL)
1783 .addReg(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001784 // 's' bit operand (always reg0 for this).
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001785 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001786
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001787 OutStreamer.EmitInstruction(MCInstBuilder(ARM::ADDri)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001788 .addReg(ARM::PC)
1789 .addReg(ARM::PC)
1790 .addImm(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001791 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001792 .addImm(ARMCC::AL)
1793 .addReg(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001794 // 's' bit operand (always reg0 for this).
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001795 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001796
1797 OutStreamer.AddComment("eh_setjmp end");
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001798 OutStreamer.EmitInstruction(MCInstBuilder(ARM::MOVi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001799 .addReg(ARM::R0)
1800 .addImm(1)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001801 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001802 .addImm(ARMCC::AL)
1803 .addReg(0)
Jim Grosbachc0aed712010-09-23 23:33:56 +00001804 // 's' bit operand (always reg0 for this).
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001805 .addReg(0));
Jim Grosbachc0aed712010-09-23 23:33:56 +00001806 return;
1807 }
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001808 case ARM::Int_eh_sjlj_longjmp: {
1809 // ldr sp, [$src, #8]
1810 // ldr $scratch, [$src, #4]
1811 // ldr r7, [$src]
1812 // bx $scratch
1813 unsigned SrcReg = MI->getOperand(0).getReg();
1814 unsigned ScratchReg = MI->getOperand(1).getReg();
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001815 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001816 .addReg(ARM::SP)
1817 .addReg(SrcReg)
1818 .addImm(8)
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001819 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001820 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001821 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001822
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001823 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001824 .addReg(ScratchReg)
1825 .addReg(SrcReg)
1826 .addImm(4)
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001827 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001828 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001829 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001830
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001831 OutStreamer.EmitInstruction(MCInstBuilder(ARM::LDRi12)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001832 .addReg(ARM::R7)
1833 .addReg(SrcReg)
1834 .addImm(0)
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001835 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001836 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001837 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001838
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001839 OutStreamer.EmitInstruction(MCInstBuilder(ARM::BX)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001840 .addReg(ScratchReg)
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001841 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001842 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001843 .addReg(0));
Jim Grosbach9e9ed982010-09-27 21:47:04 +00001844 return;
1845 }
Jim Grosbach175d6412010-09-27 22:28:11 +00001846 case ARM::tInt_eh_sjlj_longjmp: {
1847 // ldr $scratch, [$src, #8]
1848 // mov sp, $scratch
1849 // ldr $scratch, [$src, #4]
1850 // ldr r7, [$src]
1851 // bx $scratch
1852 unsigned SrcReg = MI->getOperand(0).getReg();
1853 unsigned ScratchReg = MI->getOperand(1).getReg();
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001854 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001855 .addReg(ScratchReg)
1856 .addReg(SrcReg)
Jim Grosbach175d6412010-09-27 22:28:11 +00001857 // The offset immediate is #8. The operand value is scaled by 4 for the
Bill Wendling092a7bd2010-12-14 03:36:38 +00001858 // tLDR instruction.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001859 .addImm(2)
Jim Grosbach175d6412010-09-27 22:28:11 +00001860 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001861 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001862 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001863
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001864 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tMOVr)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001865 .addReg(ARM::SP)
1866 .addReg(ScratchReg)
Jim Grosbach175d6412010-09-27 22:28:11 +00001867 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001868 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001869 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001870
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001871 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001872 .addReg(ScratchReg)
1873 .addReg(SrcReg)
1874 .addImm(1)
Jim Grosbach175d6412010-09-27 22:28:11 +00001875 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001876 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001877 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001878
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001879 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tLDRi)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001880 .addReg(ARM::R7)
1881 .addReg(SrcReg)
1882 .addImm(0)
Jim Grosbach175d6412010-09-27 22:28:11 +00001883 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001884 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001885 .addReg(0));
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001886
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001887 OutStreamer.EmitInstruction(MCInstBuilder(ARM::tBX)
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001888 .addReg(ScratchReg)
Jim Grosbach175d6412010-09-27 22:28:11 +00001889 // Predicate.
Benjamin Kramer4e629f72012-11-26 13:34:22 +00001890 .addImm(ARMCC::AL)
Benjamin Kramerebf576d2012-11-26 18:05:52 +00001891 .addReg(0));
Jim Grosbach175d6412010-09-27 22:28:11 +00001892 return;
1893 }
Chris Lattner71eb0772009-10-19 20:20:46 +00001894 }
Jim Grosbach8ee5cd92010-09-02 01:02:06 +00001895
Chris Lattner71eb0772009-10-19 20:20:46 +00001896 MCInst TmpInst;
Chris Lattnerde16ca82010-11-14 21:00:02 +00001897 LowerARMMachineInstrToMCInst(MI, TmpInst, *this);
Anton Korobeynikove7410dd2011-03-05 18:43:32 +00001898
Chris Lattner6f1f8652010-02-03 01:16:28 +00001899 OutStreamer.EmitInstruction(TmpInst);
Chris Lattner71eb0772009-10-19 20:20:46 +00001900}
Daniel Dunbarf0b3d152009-10-20 05:15:36 +00001901
1902//===----------------------------------------------------------------------===//
1903// Target Registry Stuff
1904//===----------------------------------------------------------------------===//
1905
Daniel Dunbarf0b3d152009-10-20 05:15:36 +00001906// Force static initialization.
1907extern "C" void LLVMInitializeARMAsmPrinter() {
1908 RegisterAsmPrinter<ARMAsmPrinter> X(TheARMTarget);
1909 RegisterAsmPrinter<ARMAsmPrinter> Y(TheThumbTarget);
Daniel Dunbarf0b3d152009-10-20 05:15:36 +00001910}