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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / AMDGPU / fcmp64.ll
blob: 95f7e0be7d9c9c75e49e9cebe6d78097bbcca3fe [file] [log] [blame]
Tom Stellard49f8bfd2015-01-06 18:00:21 +0000[diff] [blame]1; RUN: llc < %s -march=amdgcn -mcpu=tahiti -verify-machineinstrs | FileCheck %s
Matt Arsenault7aad8fd2017-01-24 22:02:15 +0000[diff] [blame]2; RUN: llc < %s -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs | FileCheck %s
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]3
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]4; CHECK-LABEL: {{^}}flt_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]5; CHECK: v_cmp_nge_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]6define amdgpu_kernel void @flt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]7 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]8 %r0 = load double, double addrspace(1)* %in1
9 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]10 %r2 = fcmp ult double %r0, %r1
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]11 %r3 = zext i1 %r2 to i32
12 store i32 %r3, i32 addrspace(1)* %out
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]13 ret void
14}
15
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]16; CHECK-LABEL: {{^}}fle_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]17; CHECK: v_cmp_ngt_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]18define amdgpu_kernel void @fle_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]19 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]20 %r0 = load double, double addrspace(1)* %in1
21 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]22 %r2 = fcmp ule double %r0, %r1
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]23 %r3 = zext i1 %r2 to i32
24 store i32 %r3, i32 addrspace(1)* %out
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]25 ret void
26}
27
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]28; CHECK-LABEL: {{^}}fgt_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]29; CHECK: v_cmp_nle_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]30define amdgpu_kernel void @fgt_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]31 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]32 %r0 = load double, double addrspace(1)* %in1
33 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]34 %r2 = fcmp ugt double %r0, %r1
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]35 %r3 = zext i1 %r2 to i32
36 store i32 %r3, i32 addrspace(1)* %out
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]37 ret void
38}
39
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]40; CHECK-LABEL: {{^}}fge_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]41; CHECK: v_cmp_nlt_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]42define amdgpu_kernel void @fge_f64(i32 addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]43 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]44 %r0 = load double, double addrspace(1)* %in1
45 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]46 %r2 = fcmp uge double %r0, %r1
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]47 %r3 = zext i1 %r2 to i32
48 store i32 %r3, i32 addrspace(1)* %out
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]49 ret void
50}
51
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]52; CHECK-LABEL: {{^}}fne_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]53; CHECK: v_cmp_neq_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]54define amdgpu_kernel void @fne_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]55 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]56 %r0 = load double, double addrspace(1)* %in1
57 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]58 %r2 = fcmp une double %r0, %r1
59 %r3 = select i1 %r2, double %r0, double %r1
60 store double %r3, double addrspace(1)* %out
61 ret void
62}
63
Matt Arsenaultda59f3d2014-11-13 23:03:09 +0000[diff] [blame]64; CHECK-LABEL: {{^}}feq_f64:
Alexander Timofeev982aee62017-07-04 17:32:00 +0000[diff] [blame]65; CHECK: v_cmp_nlg_f64_e32 vcc, {{s[[0-9]+:[0-9]+], v[[0-9]+:[0-9]+]}}
Matt Arsenault3dbeefa2017-03-21 21:39:51 +0000[diff] [blame]66define amdgpu_kernel void @feq_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]67 double addrspace(1)* %in2) {
David Blaikiea79ac142015-02-27 21:17:42 +0000[diff] [blame]68 %r0 = load double, double addrspace(1)* %in1
69 %r1 = load double, double addrspace(1)* %in2
Tom Stellard4e1100a2013-07-12 18:15:19 +0000[diff] [blame]70 %r2 = fcmp ueq double %r0, %r1
71 %r3 = select i1 %r2, double %r0, double %r1
72 store double %r3, double addrspace(1)* %out
73 ret void
74}