Matt Arsenault | 553751b | 2014-04-01 18:34:13 +0000 | [diff] [blame] | 1 | ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s |
Matt Arsenault | e407ae9 | 2014-04-01 18:13:26 +0000 | [diff] [blame] | 2 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 3 | ; EG-LABEL: {{^}}and_setcc_setcc_i32: |
Matt Arsenault | e407ae9 | 2014-04-01 18:13:26 +0000 | [diff] [blame] | 4 | ; EG: AND_INT |
| 5 | ; EG-NEXT: SETE_INT |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 6 | define amdgpu_kernel void @and_setcc_setcc_i32(i32 addrspace(1)* %out, i32 %a, i32 %b) { |
Matt Arsenault | e407ae9 | 2014-04-01 18:13:26 +0000 | [diff] [blame] | 7 | %cmp1 = icmp eq i32 %a, -1 |
| 8 | %cmp2 = icmp eq i32 %b, -1 |
| 9 | %and = and i1 %cmp1, %cmp2 |
| 10 | %ext = sext i1 %and to i32 |
| 11 | store i32 %ext, i32 addrspace(1)* %out, align 4 |
| 12 | ret void |
| 13 | } |
| 14 | |
Tom Stellard | 79243d9 | 2014-10-01 17:15:17 +0000 | [diff] [blame] | 15 | ; EG-LABEL: {{^}}and_setcc_setcc_v4i32: |
Matt Arsenault | e407ae9 | 2014-04-01 18:13:26 +0000 | [diff] [blame] | 16 | ; EG: AND_INT |
| 17 | ; EG: AND_INT |
| 18 | ; EG: SETE_INT |
| 19 | ; EG: AND_INT |
| 20 | ; EG: SETE_INT |
| 21 | ; EG: AND_INT |
| 22 | ; EG: SETE_INT |
Matt Arsenault | 3dbeefa | 2017-03-21 21:39:51 +0000 | [diff] [blame] | 23 | define amdgpu_kernel void @and_setcc_setcc_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> %a, <4 x i32> %b) { |
Matt Arsenault | e407ae9 | 2014-04-01 18:13:26 +0000 | [diff] [blame] | 24 | %cmp1 = icmp eq <4 x i32> %a, <i32 -1, i32 -1, i32 -1, i32 -1> |
| 25 | %cmp2 = icmp eq <4 x i32> %b, <i32 -1, i32 -1, i32 -1, i32 -1> |
| 26 | %and = and <4 x i1> %cmp1, %cmp2 |
| 27 | %ext = sext <4 x i1> %and to <4 x i32> |
| 28 | store <4 x i32> %ext, <4 x i32> addrspace(1)* %out, align 4 |
| 29 | ret void |
Chandler Carruth | 411fb40 | 2014-07-26 05:49:40 +0000 | [diff] [blame] | 30 | } |