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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / PowerPC / testComparesigesi.ll
blob: 93e6c1e1f9cf69ed7aee51773bab1a49560ae7da [file] [log] [blame]
Stefan Pintiliecb4f0c52018-07-04 18:54:25 +0000[diff] [blame]1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]2; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]3; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-BE \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]4; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
5; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]6; RUN: -ppc-gpr-icmps=all -ppc-asm-full-reg-names -mcpu=pwr8 < %s | FileCheck %s --check-prefix=CHECK-LE \
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]7; RUN: --implicit-check-not cmpw --implicit-check-not cmpd --implicit-check-not cmpl
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]8@glob = common local_unnamed_addr global i32 0, align 4
9
10define signext i32 @test_igesi(i32 signext %a, i32 signext %b) {
11; CHECK-LABEL: test_igesi:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]12; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]13; CHECK-NEXT: sub r3, r3, r4
14; CHECK-NEXT: rldicl r3, r3, 1, 63
15; CHECK-NEXT: xori r3, r3, 1
16; CHECK-NEXT: blr
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]17; CHECK-BE-LABEL: test_igesi:
18; CHECK-BE: # %bb.0: # %entry
19; CHECK-BE-NEXT: sub r3, r3, r4
20; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
21; CHECK-BE-NEXT: xori r3, r3, 1
22; CHECK-BE-NEXT: blr
23;
24; CHECK-LE-LABEL: test_igesi:
25; CHECK-LE: # %bb.0: # %entry
26; CHECK-LE-NEXT: sub r3, r3, r4
27; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
28; CHECK-LE-NEXT: xori r3, r3, 1
29; CHECK-LE-NEXT: blr
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]30entry:
31 %cmp = icmp sge i32 %a, %b
32 %conv = zext i1 %cmp to i32
33 ret i32 %conv
34}
35
36define signext i32 @test_igesi_sext(i32 signext %a, i32 signext %b) {
37; CHECK-LABEL: test_igesi_sext:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]38; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]39; CHECK-NEXT: sub r3, r3, r4
40; CHECK-NEXT: rldicl r3, r3, 1, 63
41; CHECK-NEXT: addi r3, r3, -1
42; CHECK-NEXT: blr
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]43; CHECK-BE-LABEL: test_igesi_sext:
44; CHECK-BE: # %bb.0: # %entry
45; CHECK-BE-NEXT: sub r3, r3, r4
46; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
47; CHECK-BE-NEXT: addi r3, r3, -1
48; CHECK-BE-NEXT: blr
49;
50; CHECK-LE-LABEL: test_igesi_sext:
51; CHECK-LE: # %bb.0: # %entry
52; CHECK-LE-NEXT: sub r3, r3, r4
53; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
54; CHECK-LE-NEXT: addi r3, r3, -1
55; CHECK-LE-NEXT: blr
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]56entry:
57 %cmp = icmp sge i32 %a, %b
58 %sub = sext i1 %cmp to i32
59 ret i32 %sub
60}
61
62define void @test_igesi_store(i32 signext %a, i32 signext %b) {
63; CHECK-LABEL: test_igesi_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]64; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]65; CHECK-NEXT: sub r3, r3, r4
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]66; CHECK-NEXT: addis r5, r2, glob@toc@ha
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]67; CHECK-NEXT: rldicl r3, r3, 1, 63
68; CHECK-NEXT: xori r3, r3, 1
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]69; CHECK-NEXT: stw r3, glob@toc@l(r5)
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]70; CHECK-NEXT: blr
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]71; CHECK-BE-LABEL: test_igesi_store:
72; CHECK-BE: # %bb.0: # %entry
73; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
74; CHECK-BE-NEXT: sub r3, r3, r4
75; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
76; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
77; CHECK-BE-NEXT: xori r3, r3, 1
78; CHECK-BE-NEXT: stw r3, 0(r4)
79; CHECK-BE-NEXT: blr
80;
81; CHECK-LE-LABEL: test_igesi_store:
82; CHECK-LE: # %bb.0: # %entry
83; CHECK-LE-NEXT: sub r3, r3, r4
84; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
85; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
86; CHECK-LE-NEXT: xori r3, r3, 1
87; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
88; CHECK-LE-NEXT: blr
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]89entry:
90 %cmp = icmp sge i32 %a, %b
91 %conv = zext i1 %cmp to i32
92 store i32 %conv, i32* @glob, align 4
93 ret void
94}
95
96define void @test_igesi_sext_store(i32 signext %a, i32 signext %b) {
97; CHECK-LABEL: test_igesi_sext_store:
Francis Visoiu Mistrih25528d62017-12-04 17:18:51 +0000[diff] [blame]98; CHECK: # %bb.0: # %entry
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]99; CHECK-NEXT: sub r3, r3, r4
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]100; CHECK-NEXT: addis r5, r2, glob@toc@ha
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]101; CHECK-NEXT: rldicl r3, r3, 1, 63
102; CHECK-NEXT: addi r3, r3, -1
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]103; CHECK-NEXT: stw r3, glob@toc@l(r5)
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]104; CHECK-NEXT: blr
Stefan Pintilie46f840f2018-12-04 20:14:57 +0000[diff] [blame]105; CHECK-BE-LABEL: test_igesi_sext_store:
106; CHECK-BE: # %bb.0: # %entry
107; CHECK-BE-NEXT: addis r5, r2, .LC0@toc@ha
108; CHECK-BE-NEXT: sub r3, r3, r4
109; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r5)
110; CHECK-BE-NEXT: rldicl r3, r3, 1, 63
111; CHECK-BE-NEXT: addi r3, r3, -1
112; CHECK-BE-NEXT: stw r3, 0(r4)
113; CHECK-BE-NEXT: blr
114;
115; CHECK-LE-LABEL: test_igesi_sext_store:
116; CHECK-LE: # %bb.0: # %entry
117; CHECK-LE-NEXT: sub r3, r3, r4
118; CHECK-LE-NEXT: addis r5, r2, glob@toc@ha
119; CHECK-LE-NEXT: rldicl r3, r3, 1, 63
120; CHECK-LE-NEXT: addi r3, r3, -1
121; CHECK-LE-NEXT: stw r3, glob@toc@l(r5)
122; CHECK-LE-NEXT: blr
Nemanja Ivanovicd6f93f52017-09-22 11:50:25 +0000[diff] [blame]123entry:
124 %cmp = icmp sge i32 %a, %b
125 %sub = sext i1 %cmp to i32
126 store i32 %sub, i32* @glob, align 4
127 ret void
128}