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gerrit-public.fairphone.software / toolchain / llvm-project / 81fe1fbf4abd00b24e078a80cb15a2d2c1343f11 / . / llvm / test / CodeGen / SystemZ / atomicrmw-nand-02.ll
blob: c4679bc4e10500315bdebc5f37c1b47d7614f144 [file] [log] [blame]
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]1; Test 16-bit atomic NANDs.
2;
Mandeep Singh Grang029a0562016-04-19 23:51:52 +0000[diff] [blame]3; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]4; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT1
5; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -check-prefix=CHECK-SHIFT2
6
7; Check NAND of a variable.
8; - CHECK is for the main loop.
9; - CHECK-SHIFT1 makes sure that the negated shift count used by the second
10; RLL is set up correctly. The negation is independent of the NILL and L
11; tested in CHECK.
12; - CHECK-SHIFT2 makes sure that %b is shifted into the high part of the word
13; before being used, and that the low bits are set to 1. This sequence is
14; independent of the other loop prologue instructions.
15define i16 @f1(i16 *%src, i16 %b) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]16; CHECK-LABEL: f1:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]17; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]18; CHECK-DAG: sll %r2, 3
19; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]20; CHECK: [[LABEL:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]21; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]22; CHECK: nr [[ROT]], %r3
23; CHECK: xilf [[ROT]], 4294901760
24; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0({{%r[1-9]+}})
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]25; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]26; CHECK: jl [[LABEL]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]27; CHECK: rll %r2, [[OLD]], 16(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]28; CHECK: br %r14
29;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]30; CHECK-SHIFT1-LABEL: f1:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]31; CHECK-SHIFT1: sll %r2, 3
32; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]33; CHECK-SHIFT1: rll
34; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
35; CHECK-SHIFT1: rll
36; CHECK-SHIFT1: br %r14
37;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]38; CHECK-SHIFT2-LABEL: f1:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]39; CHECK-SHIFT2: sll %r3, 16
40; CHECK-SHIFT2: oill %r3, 65535
41; CHECK-SHIFT2: rll
42; CHECK-SHIFT2: nr {{%r[0-9]+}}, %r3
43; CHECK-SHIFT2: rll
44; CHECK-SHIFT2: rll
45; CHECK-SHIFT2: br %r14
46 %res = atomicrmw nand i16 *%src, i16 %b seq_cst
47 ret i16 %res
48}
49
50; Check the minimum signed value. We AND the rotated word with 0x8000ffff.
51define i16 @f2(i16 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]52; CHECK-LABEL: f2:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]53; CHECK: risbg [[RISBG:%r[1-9]+]], %r2, 0, 189, 0{{$}}
Jonas Paulssonc63ed222017-10-06 13:59:28 +0000[diff] [blame]54; CHECK-DAG: sll %r2, 3
55; CHECK-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]56; CHECK: [[LABEL:\.[^:]*]]:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]57; CHECK: rll [[ROT:%r[0-9]+]], [[OLD]], 0(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]58; CHECK: nilh [[ROT]], 32768
59; CHECK: xilf [[ROT]], 4294901760
60; CHECK: rll [[NEW:%r[0-9]+]], [[ROT]], 0([[NEGSHIFT:%r[1-9]+]])
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]61; CHECK: cs [[OLD]], [[NEW]], 0([[RISBG]])
Richard Sandiford3d768e32013-07-31 12:30:20 +0000[diff] [blame]62; CHECK: jl [[LABEL]]
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]63; CHECK: rll %r2, [[OLD]], 16(%r2)
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]64; CHECK: br %r14
65;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]66; CHECK-SHIFT1-LABEL: f2:
Matt Arsenaultab2232c2016-04-29 19:53:16 +0000[diff] [blame]67; CHECK-SHIFT1: sll %r2, 3
68; CHECK-SHIFT1: lcr [[NEGSHIFT:%r[1-9]+]], %r2
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]69; CHECK-SHIFT1: rll
70; CHECK-SHIFT1: rll {{%r[0-9]+}}, {{%r[0-9]+}}, 0([[NEGSHIFT]])
71; CHECK-SHIFT1: rll
72; CHECK-SHIFT1: br %r14
73;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]74; CHECK-SHIFT2-LABEL: f2:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]75; CHECK-SHIFT2: br %r14
76 %res = atomicrmw nand i16 *%src, i16 -32768 seq_cst
77 ret i16 %res
78}
79
80; Check NANDs of -2 (-1 isn't useful). We AND the rotated word with 0xfffeffff.
81define i16 @f3(i16 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]82; CHECK-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]83; CHECK: nilh [[ROT]], 65534
84; CHECK: xilf [[ROT]], 4294901760
85; CHECK: br %r14
86;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]87; CHECK-SHIFT1-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]88; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]89; CHECK-SHIFT2-LABEL: f3:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]90; CHECK-SHIFT2: br %r14
91 %res = atomicrmw nand i16 *%src, i16 -2 seq_cst
92 ret i16 %res
93}
94
95; Check ANDs of 1. We AND the rotated word with 0x0001ffff.
96define i16 @f4(i16 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]97; CHECK-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]98; CHECK: nilh [[ROT]], 1
99; CHECK: xilf [[ROT]], 4294901760
100; CHECK: br %r14
101;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]102; CHECK-SHIFT1-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]103; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]104; CHECK-SHIFT2-LABEL: f4:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]105; CHECK-SHIFT2: br %r14
106 %res = atomicrmw nand i16 *%src, i16 1 seq_cst
107 ret i16 %res
108}
109
110; Check the maximum signed value. We AND the rotated word with 0x7fffffff.
111define i16 @f5(i16 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]112; CHECK-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]113; CHECK: nilh [[ROT]], 32767
114; CHECK: xilf [[ROT]], 4294901760
115; CHECK: br %r14
116;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]117; CHECK-SHIFT1-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]118; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]119; CHECK-SHIFT2-LABEL: f5:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]120; CHECK-SHIFT2: br %r14
121 %res = atomicrmw nand i16 *%src, i16 32767 seq_cst
122 ret i16 %res
123}
124
125; Check NANDs of a large unsigned value. We AND the rotated word with
126; 0xfffdffff.
127define i16 @f6(i16 *%src) {
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]128; CHECK-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]129; CHECK: nilh [[ROT]], 65533
130; CHECK: xilf [[ROT]], 4294901760
131; CHECK: br %r14
132;
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]133; CHECK-SHIFT1-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]134; CHECK-SHIFT1: br %r14
Stephen Lind24ab202013-07-14 06:24:09 +0000[diff] [blame]135; CHECK-SHIFT2-LABEL: f6:
Ulrich Weigand9e3577f2013-05-06 16:17:29 +0000[diff] [blame]136; CHECK-SHIFT2: br %r14
137 %res = atomicrmw nand i16 *%src, i16 65533 seq_cst
138 ret i16 %res
139}