Richard Sandiford | 48ef6ab | 2013-12-06 09:53:09 +0000 | [diff] [blame] | 1 | ; Test an i32 0/-1 SELECTCCC for every floating-point condition. |
| 2 | ; |
| 3 | ; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s |
| 4 | |
| 5 | ; Test CC in { 1, 2, 3 } |
| 6 | define i32 @f1(float %a, float %b) { |
| 7 | ; CHECK-LABEL: f1: |
| 8 | ; CHECK: ipm %r2 |
| 9 | ; CHECK-NEXT: afi %r2, 1879048192 |
| 10 | ; CHECK-NEXT: sra %r2, 31 |
| 11 | ; CHECK: br %r14 |
| 12 | %cond = fcmp oeq float %a, %b |
| 13 | %res = select i1 %cond, i32 0, i32 -1 |
| 14 | ret i32 %res |
| 15 | } |
| 16 | |
| 17 | ; Test CC in { 0, 2, 3 } |
| 18 | define i32 @f2(float %a, float %b) { |
| 19 | ; CHECK-LABEL: f2: |
| 20 | ; CHECK: ipm %r2 |
| 21 | ; CHECK-NEXT: xilf %r2, 268435456 |
| 22 | ; CHECK-NEXT: afi %r2, 1879048192 |
| 23 | ; CHECK-NEXT: sra %r2, 31 |
| 24 | ; CHECK: br %r14 |
| 25 | %cond = fcmp olt float %a, %b |
| 26 | %res = select i1 %cond, i32 0, i32 -1 |
| 27 | ret i32 %res |
| 28 | } |
| 29 | |
| 30 | ; Test CC in { 2, 3 } |
| 31 | define i32 @f3(float %a, float %b) { |
| 32 | ; CHECK-LABEL: f3: |
| 33 | ; CHECK: ipm %r2 |
| 34 | ; CHECK-NEXT: sll %r2, 2 |
| 35 | ; CHECK-NEXT: sra %r2, 31 |
| 36 | ; CHECK: br %r14 |
| 37 | %cond = fcmp ole float %a, %b |
| 38 | %res = select i1 %cond, i32 0, i32 -1 |
| 39 | ret i32 %res |
| 40 | } |
| 41 | |
| 42 | ; Test CC in { 0, 1, 3 } |
| 43 | define i32 @f4(float %a, float %b) { |
| 44 | ; CHECK-LABEL: f4: |
| 45 | ; CHECK: ipm %r2 |
| 46 | ; CHECK-NEXT: xilf %r2, 268435456 |
| 47 | ; CHECK-NEXT: afi %r2, -805306368 |
| 48 | ; CHECK-NEXT: sra %r2, 31 |
| 49 | ; CHECK: br %r14 |
| 50 | %cond = fcmp ogt float %a, %b |
| 51 | %res = select i1 %cond, i32 0, i32 -1 |
| 52 | ret i32 %res |
| 53 | } |
| 54 | |
| 55 | ; Test CC in { 1, 3 } |
| 56 | define i32 @f5(float %a, float %b) { |
| 57 | ; CHECK-LABEL: f5: |
| 58 | ; CHECK: ipm %r2 |
| 59 | ; CHECK-NEXT: sll %r2, 3 |
| 60 | ; CHECK-NEXT: sra %r2, 31 |
| 61 | ; CHECK: br %r14 |
| 62 | %cond = fcmp oge float %a, %b |
| 63 | %res = select i1 %cond, i32 0, i32 -1 |
| 64 | ret i32 %res |
| 65 | } |
| 66 | |
| 67 | ; Test CC in { 0, 3 } |
| 68 | define i32 @f6(float %a, float %b) { |
| 69 | ; CHECK-LABEL: f6: |
| 70 | ; CHECK: ipm %r2 |
| 71 | ; CHECK-NEXT: afi %r2, -268435456 |
| 72 | ; CHECK-NEXT: sll %r2, 2 |
| 73 | ; CHECK-NEXT: sra %r2, 31 |
| 74 | ; CHECK: br %r14 |
| 75 | %cond = fcmp one float %a, %b |
| 76 | %res = select i1 %cond, i32 0, i32 -1 |
| 77 | ret i32 %res |
| 78 | } |
| 79 | |
| 80 | ; Test CC in { 3 } |
| 81 | define i32 @f7(float %a, float %b) { |
| 82 | ; CHECK-LABEL: f7: |
| 83 | ; CHECK: ipm %r2 |
| 84 | ; CHECK-NEXT: afi %r2, 1342177280 |
| 85 | ; CHECK-NEXT: sra %r2, 31 |
| 86 | ; CHECK: br %r14 |
| 87 | %cond = fcmp ord float %a, %b |
| 88 | %res = select i1 %cond, i32 0, i32 -1 |
| 89 | ret i32 %res |
| 90 | } |
| 91 | |
| 92 | ; Test CC in { 0, 1, 2 } |
| 93 | define i32 @f8(float %a, float %b) { |
| 94 | ; CHECK-LABEL: f8: |
| 95 | ; CHECK: ipm %r2 |
| 96 | ; CHECK-NEXT: afi %r2, -805306368 |
| 97 | ; CHECK-NEXT: sra %r2, 31 |
| 98 | ; CHECK: br %r14 |
| 99 | %cond = fcmp uno float %a, %b |
| 100 | %res = select i1 %cond, i32 0, i32 -1 |
| 101 | ret i32 %res |
| 102 | } |
| 103 | |
| 104 | ; Test CC in { 1, 2 } |
| 105 | define i32 @f9(float %a, float %b) { |
| 106 | ; CHECK-LABEL: f9: |
| 107 | ; CHECK: ipm %r2 |
| 108 | ; CHECK-NEXT: afi %r2, 268435456 |
| 109 | ; CHECK-NEXT: sll %r2, 2 |
| 110 | ; CHECK-NEXT: sra %r2, 31 |
| 111 | ; CHECK: br %r14 |
| 112 | %cond = fcmp ueq float %a, %b |
| 113 | %res = select i1 %cond, i32 0, i32 -1 |
| 114 | ret i32 %res |
| 115 | } |
| 116 | |
| 117 | ; Test CC in { 0, 2 } |
| 118 | define i32 @f10(float %a, float %b) { |
| 119 | ; CHECK-LABEL: f10: |
| 120 | ; CHECK: ipm %r2 |
| 121 | ; CHECK-NEXT: xilf %r2, 4294967295 |
| 122 | ; CHECK-NEXT: sll %r2, 3 |
| 123 | ; CHECK-NEXT: sra %r2, 31 |
| 124 | ; CHECK: br %r14 |
| 125 | %cond = fcmp ult float %a, %b |
| 126 | %res = select i1 %cond, i32 0, i32 -1 |
| 127 | ret i32 %res |
| 128 | } |
| 129 | |
| 130 | ; Test CC in { 2 } |
| 131 | define i32 @f11(float %a, float %b) { |
| 132 | ; CHECK-LABEL: f11: |
| 133 | ; CHECK: ipm %r2 |
| 134 | ; CHECK-NEXT: xilf %r2, 268435456 |
| 135 | ; CHECK-NEXT: afi %r2, 1342177280 |
| 136 | ; CHECK-NEXT: sra %r2, 31 |
| 137 | ; CHECK: br %r14 |
| 138 | %cond = fcmp ule float %a, %b |
| 139 | %res = select i1 %cond, i32 0, i32 -1 |
| 140 | ret i32 %res |
| 141 | } |
| 142 | |
| 143 | ; Test CC in { 0, 1 } |
| 144 | define i32 @f12(float %a, float %b) { |
| 145 | ; CHECK-LABEL: f12: |
| 146 | ; CHECK: ipm %r2 |
| 147 | ; CHECK-NEXT: afi %r2, -536870912 |
| 148 | ; CHECK-NEXT: sra %r2, 31 |
| 149 | ; CHECK: br %r14 |
| 150 | %cond = fcmp ugt float %a, %b |
| 151 | %res = select i1 %cond, i32 0, i32 -1 |
| 152 | ret i32 %res |
| 153 | } |
| 154 | |
| 155 | ; Test CC in { 1 } |
| 156 | define i32 @f13(float %a, float %b) { |
| 157 | ; CHECK-LABEL: f13: |
| 158 | ; CHECK: ipm %r2 |
| 159 | ; CHECK-NEXT: xilf %r2, 268435456 |
| 160 | ; CHECK-NEXT: afi %r2, -268435456 |
| 161 | ; CHECK-NEXT: sra %r2, 31 |
| 162 | ; CHECK: br %r14 |
| 163 | %cond = fcmp uge float %a, %b |
| 164 | %res = select i1 %cond, i32 0, i32 -1 |
| 165 | ret i32 %res |
| 166 | } |
| 167 | |
| 168 | ; Test CC in { 0 } |
| 169 | define i32 @f14(float %a, float %b) { |
| 170 | ; CHECK-LABEL: f14: |
| 171 | ; CHECK: ipm %r2 |
| 172 | ; CHECK-NEXT: afi %r2, -268435456 |
| 173 | ; CHECK-NEXT: sra %r2, 31 |
| 174 | ; CHECK: br %r14 |
| 175 | %cond = fcmp une float %a, %b |
| 176 | %res = select i1 %cond, i32 0, i32 -1 |
| 177 | ret i32 %res |
| 178 | } |