blob: 1efe4505f9e3bb870c6aad6abd40581eea4e752c [file] [log] [blame]
Juergen Ributzka1dbc15f2014-09-04 01:29:18 +00001; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=0 -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel=1 -fast-isel-abort -verify-machineinstrs < %s | FileCheck %s
3
4; AND
5define i32 @and_rr_i32(i32 %a, i32 %b) {
6; CHECK-LABEL: and_rr_i32
7; CHECK: and w0, w0, w1
8 %1 = and i32 %a, %b
9 ret i32 %1
10}
11
12define i64 @and_rr_i64(i64 %a, i64 %b) {
13; CHECK-LABEL: and_rr_i64
14; CHECK: and x0, x0, x1
15 %1 = and i64 %a, %b
16 ret i64 %1
17}
18
19define i32 @and_ri_i32(i32 %a) {
20; CHECK-LABEL: and_ri_i32
21; CHECK: and w0, w0, #0xff
22 %1 = and i32 %a, 255
23 ret i32 %1
24}
25
26define i64 @and_ri_i64(i64 %a) {
27; CHECK-LABEL: and_ri_i64
28; CHECK: and x0, x0, #0xff
29 %1 = and i64 %a, 255
30 ret i64 %1
31}
32
33define i32 @and_rs_i32(i32 %a, i32 %b) {
34; CHECK-LABEL: and_rs_i32
35; CHECK: and w0, w0, w1, lsl #8
36 %1 = shl i32 %b, 8
37 %2 = and i32 %a, %1
38 ret i32 %2
39}
40
41define i64 @and_rs_i64(i64 %a, i64 %b) {
42; CHECK-LABEL: and_rs_i64
43; CHECK: and x0, x0, x1, lsl #8
44 %1 = shl i64 %b, 8
45 %2 = and i64 %a, %1
46 ret i64 %2
47}
48
49; OR
50define i32 @or_rr_i32(i32 %a, i32 %b) {
51; CHECK-LABEL: or_rr_i32
52; CHECK: orr w0, w0, w1
53 %1 = or i32 %a, %b
54 ret i32 %1
55}
56
57define i64 @or_rr_i64(i64 %a, i64 %b) {
58; CHECK-LABEL: or_rr_i64
59; CHECK: orr x0, x0, x1
60 %1 = or i64 %a, %b
61 ret i64 %1
62}
63
64define i32 @or_ri_i32(i32 %a) {
65; CHECK-LABEL: or_ri_i32
66; CHECK: orr w0, w0, #0xff
67 %1 = or i32 %a, 255
68 ret i32 %1
69}
70
71define i64 @or_ri_i64(i64 %a) {
72; CHECK-LABEL: or_ri_i64
73; CHECK: orr x0, x0, #0xff
74 %1 = or i64 %a, 255
75 ret i64 %1
76}
77
78define i32 @or_rs_i32(i32 %a, i32 %b) {
79; CHECK-LABEL: or_rs_i32
80; CHECK: orr w0, w0, w1, lsl #8
81 %1 = shl i32 %b, 8
82 %2 = or i32 %a, %1
83 ret i32 %2
84}
85
86define i64 @or_rs_i64(i64 %a, i64 %b) {
87; CHECK-LABEL: or_rs_i64
88; CHECK: orr x0, x0, x1, lsl #8
89 %1 = shl i64 %b, 8
90 %2 = or i64 %a, %1
91 ret i64 %2
92}
93
94; XOR
95define i32 @xor_rr_i32(i32 %a, i32 %b) {
96; CHECK-LABEL: xor_rr_i32
97; CHECK: eor w0, w0, w1
98 %1 = xor i32 %a, %b
99 ret i32 %1
100}
101
102define i64 @xor_rr_i64(i64 %a, i64 %b) {
103; CHECK-LABEL: xor_rr_i64
104; CHECK: eor x0, x0, x1
105 %1 = xor i64 %a, %b
106 ret i64 %1
107}
108
109define i32 @xor_ri_i32(i32 %a) {
110; CHECK-LABEL: xor_ri_i32
111; CHECK: eor w0, w0, #0xff
112 %1 = xor i32 %a, 255
113 ret i32 %1
114}
115
116define i64 @xor_ri_i64(i64 %a) {
117; CHECK-LABEL: xor_ri_i64
118; CHECK: eor x0, x0, #0xff
119 %1 = xor i64 %a, 255
120 ret i64 %1
121}
122
123define i32 @xor_rs_i32(i32 %a, i32 %b) {
124; CHECK-LABEL: xor_rs_i32
125; CHECK: eor w0, w0, w1, lsl #8
126 %1 = shl i32 %b, 8
127 %2 = xor i32 %a, %1
128 ret i32 %2
129}
130
131define i64 @xor_rs_i64(i64 %a, i64 %b) {
132; CHECK-LABEL: xor_rs_i64
133; CHECK: eor x0, x0, x1, lsl #8
134 %1 = shl i64 %b, 8
135 %2 = xor i64 %a, %1
136 ret i64 %2
137}
138