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Jia Liub22310f2012-02-18 12:03:15 +00001//===-- PPCFrameLowering.cpp - PPC Frame Information ----------------------===//
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Anton Korobeynikov2f931282011-01-10 12:39:04 +000010// This file contains the PPC implementation of TargetFrameLowering class.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000011//
12//===----------------------------------------------------------------------===//
13
Anton Korobeynikov2f931282011-01-10 12:39:04 +000014#include "PPCFrameLowering.h"
Roman Divackyc9e23d92012-09-12 14:47:47 +000015#include "PPCInstrBuilder.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000016#include "PPCInstrInfo.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000017#include "PPCMachineFunctionInfo.h"
Eric Christopherd104c312014-06-12 20:54:11 +000018#include "PPCSubtarget.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000019#include "llvm/CodeGen/MachineFrameInfo.h"
20#include "llvm/CodeGen/MachineFunction.h"
21#include "llvm/CodeGen/MachineInstrBuilder.h"
22#include "llvm/CodeGen/MachineModuleInfo.h"
23#include "llvm/CodeGen/MachineRegisterInfo.h"
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +000024#include "llvm/CodeGen/RegisterScavenging.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +000025#include "llvm/IR/Function.h"
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000026#include "llvm/Target/TargetOptions.h"
27
28using namespace llvm;
29
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000030/// VRRegNo - Map from a numbered VR register to its enum value.
31///
Craig Topperca658c22012-03-11 07:16:55 +000032static const uint16_t VRRegNo[] = {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +000033 PPC::V0 , PPC::V1 , PPC::V2 , PPC::V3 , PPC::V4 , PPC::V5 , PPC::V6 , PPC::V7 ,
34 PPC::V8 , PPC::V9 , PPC::V10, PPC::V11, PPC::V12, PPC::V13, PPC::V14, PPC::V15,
35 PPC::V16, PPC::V17, PPC::V18, PPC::V19, PPC::V20, PPC::V21, PPC::V22, PPC::V23,
36 PPC::V24, PPC::V25, PPC::V26, PPC::V27, PPC::V28, PPC::V29, PPC::V30, PPC::V31
37};
38
Eric Christopherd104c312014-06-12 20:54:11 +000039PPCFrameLowering::PPCFrameLowering(const PPCSubtarget &STI)
40 : TargetFrameLowering(TargetFrameLowering::StackGrowsDown,
41 (STI.hasQPX() || STI.isBGQ()) ? 32 : 16, 0),
42 Subtarget(STI) {}
43
Eric Christopherd104c312014-06-12 20:54:11 +000044// With the SVR4 ABI, callee-saved registers have fixed offsets on the stack.
45const PPCFrameLowering::SpillSlot *PPCFrameLowering::getCalleeSavedSpillSlots(
46 unsigned &NumEntries) const {
47 if (Subtarget.isDarwinABI()) {
48 NumEntries = 1;
49 if (Subtarget.isPPC64()) {
50 static const SpillSlot darwin64Offsets = {PPC::X31, -8};
51 return &darwin64Offsets;
52 } else {
53 static const SpillSlot darwinOffsets = {PPC::R31, -4};
54 return &darwinOffsets;
55 }
56 }
57
58 // Early exit if not using the SVR4 ABI.
59 if (!Subtarget.isSVR4ABI()) {
60 NumEntries = 0;
61 return nullptr;
62 }
63
64 // Note that the offsets here overlap, but this is fixed up in
65 // processFunctionBeforeFrameFinalized.
66
67 static const SpillSlot Offsets[] = {
68 // Floating-point register save area offsets.
69 {PPC::F31, -8},
70 {PPC::F30, -16},
71 {PPC::F29, -24},
72 {PPC::F28, -32},
73 {PPC::F27, -40},
74 {PPC::F26, -48},
75 {PPC::F25, -56},
76 {PPC::F24, -64},
77 {PPC::F23, -72},
78 {PPC::F22, -80},
79 {PPC::F21, -88},
80 {PPC::F20, -96},
81 {PPC::F19, -104},
82 {PPC::F18, -112},
83 {PPC::F17, -120},
84 {PPC::F16, -128},
85 {PPC::F15, -136},
86 {PPC::F14, -144},
87
88 // General register save area offsets.
89 {PPC::R31, -4},
90 {PPC::R30, -8},
91 {PPC::R29, -12},
92 {PPC::R28, -16},
93 {PPC::R27, -20},
94 {PPC::R26, -24},
95 {PPC::R25, -28},
96 {PPC::R24, -32},
97 {PPC::R23, -36},
98 {PPC::R22, -40},
99 {PPC::R21, -44},
100 {PPC::R20, -48},
101 {PPC::R19, -52},
102 {PPC::R18, -56},
103 {PPC::R17, -60},
104 {PPC::R16, -64},
105 {PPC::R15, -68},
106 {PPC::R14, -72},
107
108 // CR save area offset. We map each of the nonvolatile CR fields
109 // to the slot for CR2, which is the first of the nonvolatile CR
110 // fields to be assigned, so that we only allocate one save slot.
111 // See PPCRegisterInfo::hasReservedSpillSlot() for more information.
112 {PPC::CR2, -4},
113
114 // VRSAVE save area offset.
115 {PPC::VRSAVE, -4},
116
117 // Vector register save area
118 {PPC::V31, -16},
119 {PPC::V30, -32},
120 {PPC::V29, -48},
121 {PPC::V28, -64},
122 {PPC::V27, -80},
123 {PPC::V26, -96},
124 {PPC::V25, -112},
125 {PPC::V24, -128},
126 {PPC::V23, -144},
127 {PPC::V22, -160},
128 {PPC::V21, -176},
129 {PPC::V20, -192}};
130
131 static const SpillSlot Offsets64[] = {
132 // Floating-point register save area offsets.
133 {PPC::F31, -8},
134 {PPC::F30, -16},
135 {PPC::F29, -24},
136 {PPC::F28, -32},
137 {PPC::F27, -40},
138 {PPC::F26, -48},
139 {PPC::F25, -56},
140 {PPC::F24, -64},
141 {PPC::F23, -72},
142 {PPC::F22, -80},
143 {PPC::F21, -88},
144 {PPC::F20, -96},
145 {PPC::F19, -104},
146 {PPC::F18, -112},
147 {PPC::F17, -120},
148 {PPC::F16, -128},
149 {PPC::F15, -136},
150 {PPC::F14, -144},
151
152 // General register save area offsets.
153 {PPC::X31, -8},
154 {PPC::X30, -16},
155 {PPC::X29, -24},
156 {PPC::X28, -32},
157 {PPC::X27, -40},
158 {PPC::X26, -48},
159 {PPC::X25, -56},
160 {PPC::X24, -64},
161 {PPC::X23, -72},
162 {PPC::X22, -80},
163 {PPC::X21, -88},
164 {PPC::X20, -96},
165 {PPC::X19, -104},
166 {PPC::X18, -112},
167 {PPC::X17, -120},
168 {PPC::X16, -128},
169 {PPC::X15, -136},
170 {PPC::X14, -144},
171
172 // VRSAVE save area offset.
173 {PPC::VRSAVE, -4},
174
175 // Vector register save area
176 {PPC::V31, -16},
177 {PPC::V30, -32},
178 {PPC::V29, -48},
179 {PPC::V28, -64},
180 {PPC::V27, -80},
181 {PPC::V26, -96},
182 {PPC::V25, -112},
183 {PPC::V24, -128},
184 {PPC::V23, -144},
185 {PPC::V22, -160},
186 {PPC::V21, -176},
187 {PPC::V20, -192}};
188
189 if (Subtarget.isPPC64()) {
190 NumEntries = array_lengthof(Offsets64);
191
192 return Offsets64;
193 } else {
194 NumEntries = array_lengthof(Offsets);
195
196 return Offsets;
197 }
198}
199
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000200/// RemoveVRSaveCode - We have found that this function does not need any code
201/// to manipulate the VRSAVE register, even though it uses vector registers.
202/// This can happen when the only registers used are known to be live in or out
203/// of the function. Remove all of the VRSAVE related code from the function.
Bill Schmidt38d94582012-10-10 20:54:15 +0000204/// FIXME: The removal of the code results in a compile failure at -O0 when the
205/// function contains a function call, as the GPR containing original VRSAVE
206/// contents is spilled and reloaded around the call. Without the prolog code,
207/// the spill instruction refers to an undefined register. This code needs
208/// to account for all uses of that GPR.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000209static void RemoveVRSaveCode(MachineInstr *MI) {
210 MachineBasicBlock *Entry = MI->getParent();
211 MachineFunction *MF = Entry->getParent();
212
213 // We know that the MTVRSAVE instruction immediately follows MI. Remove it.
214 MachineBasicBlock::iterator MBBI = MI;
215 ++MBBI;
216 assert(MBBI != Entry->end() && MBBI->getOpcode() == PPC::MTVRSAVE);
217 MBBI->eraseFromParent();
218
219 bool RemovedAllMTVRSAVEs = true;
220 // See if we can find and remove the MTVRSAVE instruction from all of the
221 // epilog blocks.
222 for (MachineFunction::iterator I = MF->begin(), E = MF->end(); I != E; ++I) {
223 // If last instruction is a return instruction, add an epilogue
Evan Cheng7f8e5632011-12-07 07:15:52 +0000224 if (!I->empty() && I->back().isReturn()) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000225 bool FoundIt = false;
226 for (MBBI = I->end(); MBBI != I->begin(); ) {
227 --MBBI;
228 if (MBBI->getOpcode() == PPC::MTVRSAVE) {
229 MBBI->eraseFromParent(); // remove it.
230 FoundIt = true;
231 break;
232 }
233 }
234 RemovedAllMTVRSAVEs &= FoundIt;
235 }
236 }
237
238 // If we found and removed all MTVRSAVE instructions, remove the read of
239 // VRSAVE as well.
240 if (RemovedAllMTVRSAVEs) {
241 MBBI = MI;
242 assert(MBBI != Entry->begin() && "UPDATE_VRSAVE is first instr in block?");
243 --MBBI;
244 assert(MBBI->getOpcode() == PPC::MFVRSAVE && "VRSAVE instrs wandered?");
245 MBBI->eraseFromParent();
246 }
247
248 // Finally, nuke the UPDATE_VRSAVE.
249 MI->eraseFromParent();
250}
251
252// HandleVRSaveUpdate - MI is the UPDATE_VRSAVE instruction introduced by the
253// instruction selector. Based on the vector registers that have been used,
254// transform this into the appropriate ORI instruction.
255static void HandleVRSaveUpdate(MachineInstr *MI, const TargetInstrInfo &TII) {
256 MachineFunction *MF = MI->getParent()->getParent();
Hal Finkelfeea6532013-03-26 20:08:20 +0000257 const TargetRegisterInfo *TRI = MF->getTarget().getRegisterInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000258 DebugLoc dl = MI->getDebugLoc();
259
260 unsigned UsedRegMask = 0;
261 for (unsigned i = 0; i != 32; ++i)
262 if (MF->getRegInfo().isPhysRegUsed(VRRegNo[i]))
263 UsedRegMask |= 1 << (31-i);
264
265 // Live in and live out values already must be in the mask, so don't bother
266 // marking them.
267 for (MachineRegisterInfo::livein_iterator
268 I = MF->getRegInfo().livein_begin(),
269 E = MF->getRegInfo().livein_end(); I != E; ++I) {
Hal Finkelfeea6532013-03-26 20:08:20 +0000270 unsigned RegNo = TRI->getEncodingValue(I->first);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000271 if (VRRegNo[RegNo] == I->first) // If this really is a vector reg.
272 UsedRegMask &= ~(1 << (31-RegNo)); // Doesn't need to be marked.
273 }
Jakob Stoklund Olesenbf034db2013-02-05 17:40:36 +0000274
275 // Live out registers appear as use operands on return instructions.
276 for (MachineFunction::const_iterator BI = MF->begin(), BE = MF->end();
277 UsedRegMask != 0 && BI != BE; ++BI) {
278 const MachineBasicBlock &MBB = *BI;
279 if (MBB.empty() || !MBB.back().isReturn())
280 continue;
281 const MachineInstr &Ret = MBB.back();
282 for (unsigned I = 0, E = Ret.getNumOperands(); I != E; ++I) {
283 const MachineOperand &MO = Ret.getOperand(I);
284 if (!MO.isReg() || !PPC::VRRCRegClass.contains(MO.getReg()))
285 continue;
Hal Finkelfeea6532013-03-26 20:08:20 +0000286 unsigned RegNo = TRI->getEncodingValue(MO.getReg());
Jakob Stoklund Olesenbf034db2013-02-05 17:40:36 +0000287 UsedRegMask &= ~(1 << (31-RegNo));
288 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000289 }
290
291 // If no registers are used, turn this into a copy.
292 if (UsedRegMask == 0) {
293 // Remove all VRSAVE code.
294 RemoveVRSaveCode(MI);
295 return;
296 }
297
298 unsigned SrcReg = MI->getOperand(1).getReg();
299 unsigned DstReg = MI->getOperand(0).getReg();
300
301 if ((UsedRegMask & 0xFFFF) == UsedRegMask) {
302 if (DstReg != SrcReg)
303 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
304 .addReg(SrcReg)
305 .addImm(UsedRegMask);
306 else
307 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
308 .addReg(SrcReg, RegState::Kill)
309 .addImm(UsedRegMask);
310 } else if ((UsedRegMask & 0xFFFF0000) == UsedRegMask) {
311 if (DstReg != SrcReg)
312 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
313 .addReg(SrcReg)
314 .addImm(UsedRegMask >> 16);
315 else
316 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
317 .addReg(SrcReg, RegState::Kill)
318 .addImm(UsedRegMask >> 16);
319 } else {
320 if (DstReg != SrcReg)
321 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
322 .addReg(SrcReg)
323 .addImm(UsedRegMask >> 16);
324 else
325 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg)
326 .addReg(SrcReg, RegState::Kill)
327 .addImm(UsedRegMask >> 16);
328
329 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg)
330 .addReg(DstReg, RegState::Kill)
331 .addImm(UsedRegMask & 0xFFFF);
332 }
333
334 // Remove the old UPDATE_VRSAVE instruction.
335 MI->eraseFromParent();
336}
337
Roman Divackyc9e23d92012-09-12 14:47:47 +0000338static bool spillsCR(const MachineFunction &MF) {
339 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
340 return FuncInfo->isCRSpilled();
341}
342
Hal Finkelcc1eeda2013-03-23 22:06:03 +0000343static bool spillsVRSAVE(const MachineFunction &MF) {
344 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
345 return FuncInfo->isVRSAVESpilled();
346}
347
Hal Finkelbb420f12013-03-15 05:06:04 +0000348static bool hasSpills(const MachineFunction &MF) {
349 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
350 return FuncInfo->hasSpills();
351}
352
Hal Finkelfcc51d42013-03-17 04:43:44 +0000353static bool hasNonRISpills(const MachineFunction &MF) {
354 const PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
355 return FuncInfo->hasNonRISpills();
356}
357
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000358/// determineFrameLayout - Determine the size of the frame and maximum call
359/// frame size.
Hal Finkelbb420f12013-03-15 05:06:04 +0000360unsigned PPCFrameLowering::determineFrameLayout(MachineFunction &MF,
361 bool UpdateMF,
362 bool UseEstimate) const {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000363 MachineFrameInfo *MFI = MF.getFrameInfo();
364
365 // Get the number of bytes to allocate from the FrameInfo
Hal Finkelbb420f12013-03-15 05:06:04 +0000366 unsigned FrameSize =
367 UseEstimate ? MFI->estimateStackSize(MF) : MFI->getStackSize();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000368
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000369 // Get stack alignments. The frame must be aligned to the greatest of these:
370 unsigned TargetAlign = getStackAlignment(); // alignment required per the ABI
371 unsigned MaxAlign = MFI->getMaxAlignment(); // algmt required by data in frame
Hal Finkela7c54e82013-07-17 00:45:52 +0000372 unsigned AlignMask = std::max(MaxAlign, TargetAlign) - 1;
373
374 const PPCRegisterInfo *RegInfo =
375 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000376
377 // If we are a leaf function, and use up to 224 bytes of stack space,
378 // don't have a frame pointer, calls, or dynamic alloca then we do not need
Hal Finkel67369882013-04-15 02:07:05 +0000379 // to adjust the stack pointer (we fit in the Red Zone).
Bill Schmidt8ea7af82013-02-26 21:28:57 +0000380 // The 32-bit SVR4 ABI has no Red Zone. However, it can still generate
381 // stackless code if all local vars are reg-allocated.
Bill Wendling698e84f2012-12-30 10:32:01 +0000382 bool DisableRedZone = MF.getFunction()->getAttributes().
383 hasAttribute(AttributeSet::FunctionIndex, Attribute::NoRedZone);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000384 if (!DisableRedZone &&
Bill Schmidt8ea7af82013-02-26 21:28:57 +0000385 (Subtarget.isPPC64() || // 32-bit SVR4, no stack-
386 !Subtarget.isSVR4ABI() || // allocated locals.
Eric Christopherd1737492014-04-29 00:16:40 +0000387 FrameSize == 0) &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000388 FrameSize <= 224 && // Fits in red zone.
389 !MFI->hasVarSizedObjects() && // No dynamic alloca.
390 !MFI->adjustsStack() && // No calls.
Hal Finkela7c54e82013-07-17 00:45:52 +0000391 !RegInfo->hasBasePointer(MF)) { // No special alignment.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000392 // No need for frame
Hal Finkelbb420f12013-03-15 05:06:04 +0000393 if (UpdateMF)
394 MFI->setStackSize(0);
395 return 0;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000396 }
397
398 // Get the maximum call frame size of all the calls.
399 unsigned maxCallFrameSize = MFI->getMaxCallFrameSize();
400
Ulrich Weigandf316e1d2014-06-23 13:47:52 +0000401 // Maximum call frame needs to be at least big enough for linkage area.
402 unsigned minCallFrameSize = getLinkageSize(Subtarget.isPPC64(),
Ulrich Weigand8658f172014-07-20 23:43:15 +0000403 Subtarget.isDarwinABI(),
404 Subtarget.isELFv2ABI());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000405 maxCallFrameSize = std::max(maxCallFrameSize, minCallFrameSize);
406
407 // If we have dynamic alloca then maxCallFrameSize needs to be aligned so
408 // that allocations will be aligned.
409 if (MFI->hasVarSizedObjects())
410 maxCallFrameSize = (maxCallFrameSize + AlignMask) & ~AlignMask;
411
412 // Update maximum call frame size.
Hal Finkelbb420f12013-03-15 05:06:04 +0000413 if (UpdateMF)
414 MFI->setMaxCallFrameSize(maxCallFrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000415
416 // Include call frame size in total.
417 FrameSize += maxCallFrameSize;
418
419 // Make sure the frame is aligned.
420 FrameSize = (FrameSize + AlignMask) & ~AlignMask;
421
422 // Update frame info.
Hal Finkelbb420f12013-03-15 05:06:04 +0000423 if (UpdateMF)
424 MFI->setStackSize(FrameSize);
425
426 return FrameSize;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000427}
428
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000429// hasFP - Return true if the specified function actually has a dedicated frame
430// pointer register.
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000431bool PPCFrameLowering::hasFP(const MachineFunction &MF) const {
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000432 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000433 // FIXME: This is pretty much broken by design: hasFP() might be called really
434 // early, before the stack layout was calculated and thus hasFP() might return
435 // true or false here depending on the time of call.
436 return (MFI->getStackSize()) && needsFP(MF);
437}
438
439// needsFP - Return true if the specified function should have a dedicated frame
440// pointer register. This is true if the function has variable sized allocas or
441// if frame pointer elimination is disabled.
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000442bool PPCFrameLowering::needsFP(const MachineFunction &MF) const {
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000443 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000444
445 // Naked functions have no stack frame pushed, so we don't have a frame
446 // pointer.
Eric Christopherd1737492014-04-29 00:16:40 +0000447 if (MF.getFunction()->getAttributes().hasAttribute(
448 AttributeSet::FunctionIndex, Attribute::Naked))
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000449 return false;
450
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000451 return MF.getTarget().Options.DisableFramePointerElim(MF) ||
452 MFI->hasVarSizedObjects() ||
453 (MF.getTarget().Options.GuaranteedTailCallOpt &&
454 MF.getInfo<PPCFunctionInfo>()->hasFastCall());
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000455}
456
Hal Finkelaa03c032013-03-21 19:03:19 +0000457void PPCFrameLowering::replaceFPWithRealFP(MachineFunction &MF) const {
458 bool is31 = needsFP(MF);
459 unsigned FPReg = is31 ? PPC::R31 : PPC::R1;
460 unsigned FP8Reg = is31 ? PPC::X31 : PPC::X1;
461
Hal Finkelf05d6c72013-07-17 23:50:51 +0000462 const PPCRegisterInfo *RegInfo =
463 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
464 bool HasBP = RegInfo->hasBasePointer(MF);
Hal Finkel3ee2af72014-07-18 23:29:49 +0000465 unsigned BPReg = HasBP ? (unsigned) RegInfo->getBaseRegister(MF) : FPReg;
Hal Finkelf05d6c72013-07-17 23:50:51 +0000466 unsigned BP8Reg = HasBP ? (unsigned) PPC::X30 : FPReg;
467
Hal Finkelaa03c032013-03-21 19:03:19 +0000468 for (MachineFunction::iterator BI = MF.begin(), BE = MF.end();
469 BI != BE; ++BI)
470 for (MachineBasicBlock::iterator MBBI = BI->end(); MBBI != BI->begin(); ) {
471 --MBBI;
472 for (unsigned I = 0, E = MBBI->getNumOperands(); I != E; ++I) {
473 MachineOperand &MO = MBBI->getOperand(I);
474 if (!MO.isReg())
475 continue;
476
477 switch (MO.getReg()) {
478 case PPC::FP:
479 MO.setReg(FPReg);
480 break;
481 case PPC::FP8:
482 MO.setReg(FP8Reg);
483 break;
Hal Finkelf05d6c72013-07-17 23:50:51 +0000484 case PPC::BP:
485 MO.setReg(BPReg);
486 break;
487 case PPC::BP8:
488 MO.setReg(BP8Reg);
489 break;
490
Hal Finkelaa03c032013-03-21 19:03:19 +0000491 }
492 }
493 }
494}
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000495
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000496void PPCFrameLowering::emitPrologue(MachineFunction &MF) const {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000497 MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB
498 MachineBasicBlock::iterator MBBI = MBB.begin();
499 MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000500 const PPCInstrInfo &TII =
501 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
Hal Finkela7c54e82013-07-17 00:45:52 +0000502 const PPCRegisterInfo *RegInfo =
503 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000504
505 MachineModuleInfo &MMI = MF.getMMI();
Bill Wendlingbc07a892013-06-18 07:20:20 +0000506 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000507 DebugLoc dl;
508 bool needsFrameMoves = MMI.hasDebugInfo() ||
Rafael Espindolafc9bae62011-05-25 03:44:17 +0000509 MF.getFunction()->needsUnwindTableEntry();
Hal Finkel3ee2af72014-07-18 23:29:49 +0000510 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000511
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000512 // Get processor type.
513 bool isPPC64 = Subtarget.isPPC64();
514 // Get the ABI.
515 bool isDarwinABI = Subtarget.isDarwinABI();
516 bool isSVR4ABI = Subtarget.isSVR4ABI();
517 assert((isDarwinABI || isSVR4ABI) &&
518 "Currently only Darwin and SVR4 ABIs are supported for PowerPC.");
519
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000520 // Scan the prolog, looking for an UPDATE_VRSAVE instruction. If we find it,
521 // process it.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000522 if (!isSVR4ABI)
Bill Schmidt38d94582012-10-10 20:54:15 +0000523 for (unsigned i = 0; MBBI != MBB.end(); ++i, ++MBBI) {
524 if (MBBI->getOpcode() == PPC::UPDATE_VRSAVE) {
525 HandleVRSaveUpdate(MBBI, TII);
526 break;
527 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000528 }
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000529
530 // Move MBBI back to the beginning of the function.
531 MBBI = MBB.begin();
532
533 // Work out frame sizes.
Hal Finkelbb420f12013-03-15 05:06:04 +0000534 unsigned FrameSize = determineFrameLayout(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000535 int NegFrameSize = -FrameSize;
Hal Finkela7c54e82013-07-17 00:45:52 +0000536 if (!isInt<32>(NegFrameSize))
537 llvm_unreachable("Unhandled stack size!");
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000538
Hal Finkelaa03c032013-03-21 19:03:19 +0000539 if (MFI->isFrameAddressTaken())
540 replaceFPWithRealFP(MF);
541
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000542 // Check if the link register (LR) must be saved.
543 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
544 bool MustSaveLR = FI->mustSaveLR();
Craig Topperb94011f2013-07-14 04:42:23 +0000545 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
Bill Schmidtf381afc2013-08-20 03:12:23 +0000546 // Do we have a frame pointer and/or base pointer for this function?
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000547 bool HasFP = hasFP(MF);
Hal Finkela7c54e82013-07-17 00:45:52 +0000548 bool HasBP = RegInfo->hasBasePointer(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000549
Bill Schmidtf381afc2013-08-20 03:12:23 +0000550 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
Hal Finkel3ee2af72014-07-18 23:29:49 +0000551 unsigned BPReg = RegInfo->getBaseRegister(MF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000552 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
553 unsigned LRReg = isPPC64 ? PPC::LR8 : PPC::LR;
554 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
555 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
556 // ...(R12/X12 is volatile in both Darwin & SVR4, & can't be a function arg.)
557 const MCInstrDesc& MFLRInst = TII.get(isPPC64 ? PPC::MFLR8
558 : PPC::MFLR );
559 const MCInstrDesc& StoreInst = TII.get(isPPC64 ? PPC::STD
560 : PPC::STW );
561 const MCInstrDesc& StoreUpdtInst = TII.get(isPPC64 ? PPC::STDU
562 : PPC::STWU );
563 const MCInstrDesc& StoreUpdtIdxInst = TII.get(isPPC64 ? PPC::STDUX
564 : PPC::STWUX);
565 const MCInstrDesc& LoadImmShiftedInst = TII.get(isPPC64 ? PPC::LIS8
566 : PPC::LIS );
567 const MCInstrDesc& OrImmInst = TII.get(isPPC64 ? PPC::ORI8
568 : PPC::ORI );
569 const MCInstrDesc& OrInst = TII.get(isPPC64 ? PPC::OR8
570 : PPC::OR );
571 const MCInstrDesc& SubtractCarryingInst = TII.get(isPPC64 ? PPC::SUBFC8
572 : PPC::SUBFC);
573 const MCInstrDesc& SubtractImmCarryingInst = TII.get(isPPC64 ? PPC::SUBFIC8
574 : PPC::SUBFIC);
575
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000576 // Regarding this assert: Even though LR is saved in the caller's frame (i.e.,
577 // LROffset is positive), that slot is callee-owned. Because PPC32 SVR4 has no
578 // Red Zone, an asynchronous event (a form of "callee") could claim a frame &
579 // overwrite it, so PPC32 SVR4 must claim at least a minimal frame to save LR.
580 assert((isPPC64 || !isSVR4ABI || !(!FrameSize && (MustSaveLR || HasFP))) &&
581 "FrameSize must be >0 to save/restore the FP or LR for 32-bit SVR4.");
582
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000583 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000584
585 int FPOffset = 0;
586 if (HasFP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000587 if (isSVR4ABI) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000588 MachineFrameInfo *FFI = MF.getFrameInfo();
589 int FPIndex = FI->getFramePointerSaveIndex();
590 assert(FPIndex && "No Frame Pointer Save Slot!");
591 FPOffset = FFI->getObjectOffset(FPIndex);
592 } else {
Eric Christopherd1737492014-04-29 00:16:40 +0000593 FPOffset =
594 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000595 }
596 }
597
Hal Finkela7c54e82013-07-17 00:45:52 +0000598 int BPOffset = 0;
599 if (HasBP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000600 if (isSVR4ABI) {
Hal Finkela7c54e82013-07-17 00:45:52 +0000601 MachineFrameInfo *FFI = MF.getFrameInfo();
602 int BPIndex = FI->getBasePointerSaveIndex();
603 assert(BPIndex && "No Base Pointer Save Slot!");
604 BPOffset = FFI->getObjectOffset(BPIndex);
605 } else {
606 BPOffset =
Hal Finkel3ee2af72014-07-18 23:29:49 +0000607 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
608 isDarwinABI,
609 isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +0000610 }
611 }
612
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000613 // Get stack alignments.
614 unsigned MaxAlign = MFI->getMaxAlignment();
615 if (HasBP && MaxAlign > 1)
616 assert(isPowerOf2_32(MaxAlign) && isInt<16>(MaxAlign) &&
617 "Invalid alignment!");
618
619 // Frames of 32KB & larger require special handling because they cannot be
620 // indexed into with a simple STDU/STWU/STD/STW immediate offset operand.
621 bool isLargeFrame = !isInt<16>(NegFrameSize);
622
Bill Schmidtf381afc2013-08-20 03:12:23 +0000623 if (MustSaveLR)
624 BuildMI(MBB, MBBI, dl, MFLRInst, ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000625
Bill Schmidtf381afc2013-08-20 03:12:23 +0000626 assert((isPPC64 || MustSaveCRs.empty()) &&
627 "Prologue CR saving supported only in 64-bit mode");
Hal Finkel67369882013-04-15 02:07:05 +0000628
Bill Schmidtf381afc2013-08-20 03:12:23 +0000629 if (!MustSaveCRs.empty()) { // will only occur for PPC64
630 MachineInstrBuilder MIB =
631 BuildMI(MBB, MBBI, dl, TII.get(PPC::MFCR8), TempReg);
632 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
633 MIB.addReg(MustSaveCRs[i], RegState::ImplicitKill);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000634 }
635
Bill Schmidtf381afc2013-08-20 03:12:23 +0000636 if (HasFP)
637 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
638 BuildMI(MBB, MBBI, dl, StoreInst)
639 .addReg(FPReg)
640 .addImm(FPOffset)
641 .addReg(SPReg);
642
643 if (HasBP)
644 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
645 BuildMI(MBB, MBBI, dl, StoreInst)
646 .addReg(BPReg)
647 .addImm(BPOffset)
648 .addReg(SPReg);
649
650 if (MustSaveLR)
651 // FIXME: On PPC32 SVR4, we must not spill before claiming the stackframe.
652 BuildMI(MBB, MBBI, dl, StoreInst)
653 .addReg(ScratchReg)
654 .addImm(LROffset)
655 .addReg(SPReg);
656
657 if (!MustSaveCRs.empty()) // will only occur for PPC64
658 BuildMI(MBB, MBBI, dl, TII.get(PPC::STW8))
659 .addReg(TempReg, getKillRegState(true))
660 .addImm(8)
661 .addReg(SPReg);
662
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000663 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000664 if (!FrameSize) return;
665
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000666 // Adjust stack pointer: r1 += NegFrameSize.
667 // If there is a preferred stack alignment, align R1 now
Hal Finkela7c54e82013-07-17 00:45:52 +0000668
Bill Schmidtf381afc2013-08-20 03:12:23 +0000669 if (HasBP) {
670 // Save a copy of r1 as the base pointer.
671 BuildMI(MBB, MBBI, dl, OrInst, BPReg)
672 .addReg(SPReg)
673 .addReg(SPReg);
674 }
675
676 if (HasBP && MaxAlign > 1) {
677 if (isPPC64)
678 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLDICL), ScratchReg)
679 .addReg(SPReg)
680 .addImm(0)
681 .addImm(64 - Log2_32(MaxAlign));
682 else // PPC32...
683 BuildMI(MBB, MBBI, dl, TII.get(PPC::RLWINM), ScratchReg)
684 .addReg(SPReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000685 .addImm(0)
686 .addImm(32 - Log2_32(MaxAlign))
687 .addImm(31);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000688 if (!isLargeFrame) {
689 BuildMI(MBB, MBBI, dl, SubtractImmCarryingInst, ScratchReg)
690 .addReg(ScratchReg, RegState::Kill)
691 .addImm(NegFrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000692 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000693 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, TempReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000694 .addImm(NegFrameSize >> 16);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000695 BuildMI(MBB, MBBI, dl, OrImmInst, TempReg)
696 .addReg(TempReg, RegState::Kill)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000697 .addImm(NegFrameSize & 0xFFFF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000698 BuildMI(MBB, MBBI, dl, SubtractCarryingInst, ScratchReg)
699 .addReg(ScratchReg, RegState::Kill)
700 .addReg(TempReg, RegState::Kill);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000701 }
Bill Schmidtf381afc2013-08-20 03:12:23 +0000702 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
703 .addReg(SPReg, RegState::Kill)
704 .addReg(SPReg)
705 .addReg(ScratchReg);
Hal Finkela7c54e82013-07-17 00:45:52 +0000706
Bill Schmidtf381afc2013-08-20 03:12:23 +0000707 } else if (!isLargeFrame) {
708 BuildMI(MBB, MBBI, dl, StoreUpdtInst, SPReg)
709 .addReg(SPReg)
710 .addImm(NegFrameSize)
711 .addReg(SPReg);
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000712
Bill Schmidtf381afc2013-08-20 03:12:23 +0000713 } else {
714 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
715 .addImm(NegFrameSize >> 16);
716 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
717 .addReg(ScratchReg, RegState::Kill)
718 .addImm(NegFrameSize & 0xFFFF);
719 BuildMI(MBB, MBBI, dl, StoreUpdtIdxInst, SPReg)
720 .addReg(SPReg, RegState::Kill)
721 .addReg(SPReg)
722 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000723 }
724
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000725 // Add the "machine moves" for the instructions we generated above, but in
726 // reverse order.
727 if (needsFrameMoves) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000728 // Show update of SP.
Rafael Espindola6e8c0d92013-05-16 03:34:58 +0000729 assert(NegFrameSize);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000730 unsigned CFIIndex = MMI.addFrameInst(
731 MCCFIInstruction::createDefCfaOffset(nullptr, NegFrameSize));
Eric Christopher612bb692014-04-29 00:16:46 +0000732 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
733 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000734
735 if (HasFP) {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000736 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000737 CFIIndex = MMI.addFrameInst(
738 MCCFIInstruction::createOffset(nullptr, Reg, FPOffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000739 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000740 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000741 }
742
Hal Finkela7c54e82013-07-17 00:45:52 +0000743 if (HasBP) {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000744 unsigned Reg = MRI->getDwarfRegNum(BPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000745 CFIIndex = MMI.addFrameInst(
746 MCCFIInstruction::createOffset(nullptr, Reg, BPOffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000747 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000748 .addCFIIndex(CFIIndex);
Hal Finkela7c54e82013-07-17 00:45:52 +0000749 }
750
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000751 if (MustSaveLR) {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000752 unsigned Reg = MRI->getDwarfRegNum(LRReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000753 CFIIndex = MMI.addFrameInst(
754 MCCFIInstruction::createOffset(nullptr, Reg, LROffset));
Eric Christopher612bb692014-04-29 00:16:46 +0000755 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000756 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000757 }
758 }
759
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000760 // If there is a frame pointer, copy R1 into R31
761 if (HasFP) {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000762 BuildMI(MBB, MBBI, dl, OrInst, FPReg)
763 .addReg(SPReg)
764 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000765
766 if (needsFrameMoves) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000767 // Mark effective beginning of when frame pointer is ready.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000768 unsigned Reg = MRI->getDwarfRegNum(FPReg, true);
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000769 unsigned CFIIndex = MMI.addFrameInst(
770 MCCFIInstruction::createDefCfaRegister(nullptr, Reg));
771
Eric Christopher612bb692014-04-29 00:16:46 +0000772 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000773 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000774 }
775 }
776
777 if (needsFrameMoves) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000778 // Add callee saved registers to move list.
779 const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
780 for (unsigned I = 0, E = CSI.size(); I != E; ++I) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000781 unsigned Reg = CSI[I].getReg();
782 if (Reg == PPC::LR || Reg == PPC::LR8 || Reg == PPC::RM) continue;
Rafael Espindola08600bc2011-05-30 20:20:15 +0000783
784 // This is a bit of a hack: CR2LT, CR2GT, CR2EQ and CR2UN are just
785 // subregisters of CR2. We just need to emit a move of CR2.
Craig Topperabadc662012-04-20 06:31:50 +0000786 if (PPC::CRBITRCRegClass.contains(Reg))
Rafael Espindola08600bc2011-05-30 20:20:15 +0000787 continue;
Rafael Espindola08600bc2011-05-30 20:20:15 +0000788
Roman Divackyc9e23d92012-09-12 14:47:47 +0000789 // For SVR4, don't emit a move for the CR spill slot if we haven't
790 // spilled CRs.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000791 if (isSVR4ABI && (PPC::CR2 <= Reg && Reg <= PPC::CR4)
792 && MustSaveCRs.empty())
793 continue;
Roman Divackyc9e23d92012-09-12 14:47:47 +0000794
795 // For 64-bit SVR4 when we have spilled CRs, the spill location
796 // is SP+8, not a frame-relative slot.
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000797 if (isSVR4ABI && isPPC64 && (PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000798 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
799 nullptr, MRI->getDwarfRegNum(PPC::CR2, true), 8));
Eric Christopher612bb692014-04-29 00:16:46 +0000800 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000801 .addCFIIndex(CFIIndex);
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000802 continue;
Roman Divackyc9e23d92012-09-12 14:47:47 +0000803 }
804
805 int Offset = MFI->getObjectOffset(CSI[I].getFrameIdx());
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000806 unsigned CFIIndex = MMI.addFrameInst(MCCFIInstruction::createOffset(
807 nullptr, MRI->getDwarfRegNum(Reg, true), Offset));
Eric Christopher612bb692014-04-29 00:16:46 +0000808 BuildMI(MBB, MBBI, dl, TII.get(TargetOpcode::CFI_INSTRUCTION))
Rafael Espindolab1f25f12014-03-07 06:08:31 +0000809 .addCFIIndex(CFIIndex);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000810 }
811 }
812}
813
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000814void PPCFrameLowering::emitEpilogue(MachineFunction &MF,
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000815 MachineBasicBlock &MBB) const {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +0000816 MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
817 assert(MBBI != MBB.end() && "Returning block has no terminator");
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000818 const PPCInstrInfo &TII =
819 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
Hal Finkela7c54e82013-07-17 00:45:52 +0000820 const PPCRegisterInfo *RegInfo =
821 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000822
823 unsigned RetOpcode = MBBI->getOpcode();
824 DebugLoc dl;
825
Anton Korobeynikov0eecf5d2010-11-18 21:19:35 +0000826 assert((RetOpcode == PPC::BLR ||
827 RetOpcode == PPC::TCRETURNri ||
828 RetOpcode == PPC::TCRETURNdi ||
829 RetOpcode == PPC::TCRETURNai ||
830 RetOpcode == PPC::TCRETURNri8 ||
831 RetOpcode == PPC::TCRETURNdi8 ||
832 RetOpcode == PPC::TCRETURNai8) &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000833 "Can only insert epilog into returning blocks");
834
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000835 // Get alignment info so we know how to restore the SP.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000836 const MachineFrameInfo *MFI = MF.getFrameInfo();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000837
838 // Get the number of bytes allocated from the FrameInfo.
839 int FrameSize = MFI->getStackSize();
840
841 // Get processor type.
842 bool isPPC64 = Subtarget.isPPC64();
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000843 // Get the ABI.
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000844 bool isDarwinABI = Subtarget.isDarwinABI();
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000845 bool isSVR4ABI = Subtarget.isSVR4ABI();
Hal Finkel3ee2af72014-07-18 23:29:49 +0000846 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000847
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000848 // Check if the link register (LR) has been saved.
849 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
850 bool MustSaveLR = FI->mustSaveLR();
Craig Topperb94011f2013-07-14 04:42:23 +0000851 const SmallVectorImpl<unsigned> &MustSaveCRs = FI->getMustSaveCRs();
Bill Schmidtf381afc2013-08-20 03:12:23 +0000852 // Do we have a frame pointer and/or base pointer for this function?
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +0000853 bool HasFP = hasFP(MF);
Hal Finkela7c54e82013-07-17 00:45:52 +0000854 bool HasBP = RegInfo->hasBasePointer(MF);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000855
Bill Schmidtf381afc2013-08-20 03:12:23 +0000856 unsigned SPReg = isPPC64 ? PPC::X1 : PPC::R1;
Hal Finkel3ee2af72014-07-18 23:29:49 +0000857 unsigned BPReg = RegInfo->getBaseRegister(MF);
Bill Schmidtf381afc2013-08-20 03:12:23 +0000858 unsigned FPReg = isPPC64 ? PPC::X31 : PPC::R31;
859 unsigned ScratchReg = isPPC64 ? PPC::X0 : PPC::R0;
860 unsigned TempReg = isPPC64 ? PPC::X12 : PPC::R12; // another scratch reg
861 const MCInstrDesc& MTLRInst = TII.get( isPPC64 ? PPC::MTLR8
862 : PPC::MTLR );
863 const MCInstrDesc& LoadInst = TII.get( isPPC64 ? PPC::LD
864 : PPC::LWZ );
865 const MCInstrDesc& LoadImmShiftedInst = TII.get( isPPC64 ? PPC::LIS8
866 : PPC::LIS );
867 const MCInstrDesc& OrImmInst = TII.get( isPPC64 ? PPC::ORI8
868 : PPC::ORI );
869 const MCInstrDesc& AddImmInst = TII.get( isPPC64 ? PPC::ADDI8
870 : PPC::ADDI );
871 const MCInstrDesc& AddInst = TII.get( isPPC64 ? PPC::ADD8
872 : PPC::ADD4 );
873
Anton Korobeynikov2f931282011-01-10 12:39:04 +0000874 int LROffset = PPCFrameLowering::getReturnSaveOffset(isPPC64, isDarwinABI);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000875
876 int FPOffset = 0;
877 if (HasFP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000878 if (isSVR4ABI) {
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000879 MachineFrameInfo *FFI = MF.getFrameInfo();
880 int FPIndex = FI->getFramePointerSaveIndex();
881 assert(FPIndex && "No Frame Pointer Save Slot!");
882 FPOffset = FFI->getObjectOffset(FPIndex);
883 } else {
Eric Christopherd1737492014-04-29 00:16:40 +0000884 FPOffset =
885 PPCFrameLowering::getFramePointerSaveOffset(isPPC64, isDarwinABI);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000886 }
887 }
888
Hal Finkela7c54e82013-07-17 00:45:52 +0000889 int BPOffset = 0;
890 if (HasBP) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000891 if (isSVR4ABI) {
Hal Finkela7c54e82013-07-17 00:45:52 +0000892 MachineFrameInfo *FFI = MF.getFrameInfo();
893 int BPIndex = FI->getBasePointerSaveIndex();
894 assert(BPIndex && "No Base Pointer Save Slot!");
895 BPOffset = FFI->getObjectOffset(BPIndex);
896 } else {
897 BPOffset =
Hal Finkel3ee2af72014-07-18 23:29:49 +0000898 PPCFrameLowering::getBasePointerSaveOffset(isPPC64,
899 isDarwinABI,
900 isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +0000901 }
902 }
903
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000904 bool UsesTCRet = RetOpcode == PPC::TCRETURNri ||
905 RetOpcode == PPC::TCRETURNdi ||
906 RetOpcode == PPC::TCRETURNai ||
907 RetOpcode == PPC::TCRETURNri8 ||
908 RetOpcode == PPC::TCRETURNdi8 ||
909 RetOpcode == PPC::TCRETURNai8;
910
911 if (UsesTCRet) {
912 int MaxTCRetDelta = FI->getTailCallSPDelta();
913 MachineOperand &StackAdjust = MBBI->getOperand(1);
914 assert(StackAdjust.isImm() && "Expecting immediate value.");
915 // Adjust stack pointer.
916 int StackAdj = StackAdjust.getImm();
917 int Delta = StackAdj - MaxTCRetDelta;
918 assert((Delta >= 0) && "Delta must be positive");
919 if (MaxTCRetDelta>0)
920 FrameSize += (StackAdj +Delta);
921 else
922 FrameSize += StackAdj;
923 }
924
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000925 // Frames of 32KB & larger require special handling because they cannot be
926 // indexed into with a simple LD/LWZ immediate offset operand.
927 bool isLargeFrame = !isInt<16>(FrameSize);
928
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000929 if (FrameSize) {
Bill Schmidt8893a3d2013-08-16 20:05:04 +0000930 // In the prologue, the loaded (or persistent) stack pointer value is offset
931 // by the STDU/STDUX/STWU/STWUX instruction. Add this offset back now.
Bill Schmidtf381afc2013-08-20 03:12:23 +0000932
933 // If this function contained a fastcc call and GuaranteedTailCallOpt is
934 // enabled (=> hasFastCall()==true) the fastcc call might contain a tail
935 // call which invalidates the stack pointer value in SP(0). So we use the
936 // value of R31 in this case.
937 if (FI->hasFastCall()) {
938 assert(HasFP && "Expecting a valid frame pointer.");
939 if (!isLargeFrame) {
940 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
941 .addReg(FPReg).addImm(FrameSize);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000942 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +0000943 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
944 .addImm(FrameSize >> 16);
945 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
946 .addReg(ScratchReg, RegState::Kill)
947 .addImm(FrameSize & 0xFFFF);
948 BuildMI(MBB, MBBI, dl, AddInst)
949 .addReg(SPReg)
950 .addReg(FPReg)
951 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000952 }
Bill Schmidtf381afc2013-08-20 03:12:23 +0000953 } else if (!isLargeFrame && !HasBP && !MFI->hasVarSizedObjects()) {
954 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
955 .addReg(SPReg)
956 .addImm(FrameSize);
957 } else {
958 BuildMI(MBB, MBBI, dl, LoadInst, SPReg)
959 .addImm(0)
960 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000961 }
Bill Schmidtf381afc2013-08-20 03:12:23 +0000962
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000963 }
964
Bill Schmidtf381afc2013-08-20 03:12:23 +0000965 if (MustSaveLR)
966 BuildMI(MBB, MBBI, dl, LoadInst, ScratchReg)
967 .addImm(LROffset)
968 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000969
Bill Schmidtf381afc2013-08-20 03:12:23 +0000970 assert((isPPC64 || MustSaveCRs.empty()) &&
971 "Epilogue CR restoring supported only in 64-bit mode");
Hal Finkel67369882013-04-15 02:07:05 +0000972
Bill Schmidtf381afc2013-08-20 03:12:23 +0000973 if (!MustSaveCRs.empty()) // will only occur for PPC64
974 BuildMI(MBB, MBBI, dl, TII.get(PPC::LWZ8), TempReg)
975 .addImm(8)
976 .addReg(SPReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000977
Bill Schmidtf381afc2013-08-20 03:12:23 +0000978 if (HasFP)
979 BuildMI(MBB, MBBI, dl, LoadInst, FPReg)
980 .addImm(FPOffset)
981 .addReg(SPReg);
Hal Finkela7c54e82013-07-17 00:45:52 +0000982
Bill Schmidtf381afc2013-08-20 03:12:23 +0000983 if (HasBP)
984 BuildMI(MBB, MBBI, dl, LoadInst, BPReg)
985 .addImm(BPOffset)
986 .addReg(SPReg);
Hal Finkel67369882013-04-15 02:07:05 +0000987
Bill Schmidtf381afc2013-08-20 03:12:23 +0000988 if (!MustSaveCRs.empty()) // will only occur for PPC64
989 for (unsigned i = 0, e = MustSaveCRs.size(); i != e; ++i)
990 BuildMI(MBB, MBBI, dl, TII.get(PPC::MTOCRF8), MustSaveCRs[i])
991 .addReg(TempReg, getKillRegState(i == e-1));
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000992
Bill Schmidtf381afc2013-08-20 03:12:23 +0000993 if (MustSaveLR)
994 BuildMI(MBB, MBBI, dl, MTLRInst).addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000995
996 // Callee pop calling convention. Pop parameter/linkage area. Used for tail
997 // call optimization
Nick Lewycky50f02cb2011-12-02 22:16:29 +0000998 if (MF.getTarget().Options.GuaranteedTailCallOpt && RetOpcode == PPC::BLR &&
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +0000999 MF.getFunction()->getCallingConv() == CallingConv::Fast) {
1000 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1001 unsigned CallerAllocatedAmt = FI->getMinReservedArea();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001002
1003 if (CallerAllocatedAmt && isInt<16>(CallerAllocatedAmt)) {
Bill Schmidtf381afc2013-08-20 03:12:23 +00001004 BuildMI(MBB, MBBI, dl, AddImmInst, SPReg)
1005 .addReg(SPReg).addImm(CallerAllocatedAmt);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001006 } else {
Bill Schmidtf381afc2013-08-20 03:12:23 +00001007 BuildMI(MBB, MBBI, dl, LoadImmShiftedInst, ScratchReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001008 .addImm(CallerAllocatedAmt >> 16);
Bill Schmidtf381afc2013-08-20 03:12:23 +00001009 BuildMI(MBB, MBBI, dl, OrImmInst, ScratchReg)
1010 .addReg(ScratchReg, RegState::Kill)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001011 .addImm(CallerAllocatedAmt & 0xFFFF);
Bill Schmidtf381afc2013-08-20 03:12:23 +00001012 BuildMI(MBB, MBBI, dl, AddInst)
1013 .addReg(SPReg)
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001014 .addReg(FPReg)
Bill Schmidtf381afc2013-08-20 03:12:23 +00001015 .addReg(ScratchReg);
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001016 }
1017 } else if (RetOpcode == PPC::TCRETURNdi) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001018 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001019 MachineOperand &JumpTarget = MBBI->getOperand(0);
1020 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB)).
1021 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1022 } else if (RetOpcode == PPC::TCRETURNri) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001023 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001024 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1025 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR));
1026 } else if (RetOpcode == PPC::TCRETURNai) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001027 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001028 MachineOperand &JumpTarget = MBBI->getOperand(0);
1029 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA)).addImm(JumpTarget.getImm());
1030 } else if (RetOpcode == PPC::TCRETURNdi8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001031 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001032 MachineOperand &JumpTarget = MBBI->getOperand(0);
1033 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILB8)).
1034 addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset());
1035 } else if (RetOpcode == PPC::TCRETURNri8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001036 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001037 assert(MBBI->getOperand(0).isReg() && "Expecting register operand.");
1038 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBCTR8));
1039 } else if (RetOpcode == PPC::TCRETURNai8) {
Jakob Stoklund Olesen4bc5e382011-01-13 21:28:52 +00001040 MBBI = MBB.getLastNonDebugInstr();
Anton Korobeynikovf7183ed2010-11-15 00:06:54 +00001041 MachineOperand &JumpTarget = MBBI->getOperand(0);
1042 BuildMI(MBB, MBBI, dl, TII.get(PPC::TAILBA8)).addImm(JumpTarget.getImm());
1043 }
1044}
Anton Korobeynikov14ee3442010-11-18 23:25:52 +00001045
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001046/// MustSaveLR - Return true if this function requires that we save the LR
1047/// register onto the stack in the prolog and restore it in the epilog of the
1048/// function.
1049static bool MustSaveLR(const MachineFunction &MF, unsigned LR) {
1050 const PPCFunctionInfo *MFI = MF.getInfo<PPCFunctionInfo>();
1051
1052 // We need a save/restore of LR if there is any def of LR (which is
1053 // defined by calls, including the PIC setup sequence), or if there is
1054 // some use of the LR stack slot (e.g. for builtin_return_address).
1055 // (LR comes in 32 and 64 bit versions.)
1056 MachineRegisterInfo::def_iterator RI = MF.getRegInfo().def_begin(LR);
1057 return RI !=MF.getRegInfo().def_end() || MFI->isLRStoreRequired();
1058}
1059
1060void
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001061PPCFrameLowering::processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
Hal Finkelbb420f12013-03-15 05:06:04 +00001062 RegScavenger *) const {
Hal Finkela7c54e82013-07-17 00:45:52 +00001063 const PPCRegisterInfo *RegInfo =
1064 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001065
1066 // Save and clear the LR state.
1067 PPCFunctionInfo *FI = MF.getInfo<PPCFunctionInfo>();
1068 unsigned LR = RegInfo->getRARegister();
1069 FI->setMustSaveLR(MustSaveLR(MF, LR));
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001070 MachineRegisterInfo &MRI = MF.getRegInfo();
1071 MRI.setPhysRegUnused(LR);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001072
1073 // Save R31 if necessary
1074 int FPSI = FI->getFramePointerSaveIndex();
1075 bool isPPC64 = Subtarget.isPPC64();
1076 bool isDarwinABI = Subtarget.isDarwinABI();
Hal Finkel3ee2af72014-07-18 23:29:49 +00001077 bool isPIC = MF.getTarget().getRelocationModel() == Reloc::PIC_;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001078 MachineFrameInfo *MFI = MF.getFrameInfo();
1079
1080 // If the frame pointer save index hasn't been defined yet.
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001081 if (!FPSI && needsFP(MF)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001082 // Find out what the fix offset of the frame pointer save area.
1083 int FPOffset = getFramePointerSaveOffset(isPPC64, isDarwinABI);
1084 // Allocate the frame index for frame pointer save area.
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001085 FPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, FPOffset, true);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001086 // Save the result.
1087 FI->setFramePointerSaveIndex(FPSI);
1088 }
1089
Hal Finkela7c54e82013-07-17 00:45:52 +00001090 int BPSI = FI->getBasePointerSaveIndex();
1091 if (!BPSI && RegInfo->hasBasePointer(MF)) {
Hal Finkel3ee2af72014-07-18 23:29:49 +00001092 int BPOffset = getBasePointerSaveOffset(isPPC64, isDarwinABI, isPIC);
Hal Finkela7c54e82013-07-17 00:45:52 +00001093 // Allocate the frame index for the base pointer save area.
1094 BPSI = MFI->CreateFixedObject(isPPC64? 8 : 4, BPOffset, true);
1095 // Save the result.
1096 FI->setBasePointerSaveIndex(BPSI);
1097 }
1098
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001099 // Reserve stack space to move the linkage area to in case of a tail call.
1100 int TCSPDelta = 0;
Nick Lewycky50f02cb2011-12-02 22:16:29 +00001101 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1102 (TCSPDelta = FI->getTailCallSPDelta()) < 0) {
Anton Korobeynikov2f931282011-01-10 12:39:04 +00001103 MFI->CreateFixedObject(-1 * TCSPDelta, TCSPDelta, true);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001104 }
1105
Eric Christopherd1737492014-04-29 00:16:40 +00001106 // For 32-bit SVR4, allocate the nonvolatile CR spill slot iff the
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001107 // function uses CR 2, 3, or 4.
Eric Christopherd1737492014-04-29 00:16:40 +00001108 if (!isPPC64 && !isDarwinABI &&
Bill Schmidtc68c6df2013-02-24 17:34:50 +00001109 (MRI.isPhysRegUsed(PPC::CR2) ||
1110 MRI.isPhysRegUsed(PPC::CR3) ||
1111 MRI.isPhysRegUsed(PPC::CR4))) {
1112 int FrameIdx = MFI->CreateFixedObject((uint64_t)4, (int64_t)-4, true);
1113 FI->setCRSpillFrameIndex(FrameIdx);
1114 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001115}
1116
Hal Finkel5a765fd2013-03-14 20:33:40 +00001117void PPCFrameLowering::processFunctionBeforeFrameFinalized(MachineFunction &MF,
Hal Finkelbb420f12013-03-15 05:06:04 +00001118 RegScavenger *RS) const {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001119 // Early exit if not using the SVR4 ABI.
Hal Finkelbb420f12013-03-15 05:06:04 +00001120 if (!Subtarget.isSVR4ABI()) {
1121 addScavengingSpillSlot(MF, RS);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001122 return;
Hal Finkelbb420f12013-03-15 05:06:04 +00001123 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001124
1125 // Get callee saved register information.
1126 MachineFrameInfo *FFI = MF.getFrameInfo();
1127 const std::vector<CalleeSavedInfo> &CSI = FFI->getCalleeSavedInfo();
1128
1129 // Early exit if no callee saved registers are modified!
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001130 if (CSI.empty() && !needsFP(MF)) {
Hal Finkelbb420f12013-03-15 05:06:04 +00001131 addScavengingSpillSlot(MF, RS);
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001132 return;
1133 }
1134
1135 unsigned MinGPR = PPC::R31;
1136 unsigned MinG8R = PPC::X31;
1137 unsigned MinFPR = PPC::F31;
1138 unsigned MinVR = PPC::V31;
1139
1140 bool HasGPSaveArea = false;
1141 bool HasG8SaveArea = false;
1142 bool HasFPSaveArea = false;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001143 bool HasVRSAVESaveArea = false;
1144 bool HasVRSaveArea = false;
1145
1146 SmallVector<CalleeSavedInfo, 18> GPRegs;
1147 SmallVector<CalleeSavedInfo, 18> G8Regs;
1148 SmallVector<CalleeSavedInfo, 18> FPRegs;
1149 SmallVector<CalleeSavedInfo, 18> VRegs;
1150
1151 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1152 unsigned Reg = CSI[i].getReg();
Craig Topperabadc662012-04-20 06:31:50 +00001153 if (PPC::GPRCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001154 HasGPSaveArea = true;
1155
1156 GPRegs.push_back(CSI[i]);
1157
1158 if (Reg < MinGPR) {
1159 MinGPR = Reg;
1160 }
Craig Topperabadc662012-04-20 06:31:50 +00001161 } else if (PPC::G8RCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001162 HasG8SaveArea = true;
1163
1164 G8Regs.push_back(CSI[i]);
1165
1166 if (Reg < MinG8R) {
1167 MinG8R = Reg;
1168 }
Craig Topperabadc662012-04-20 06:31:50 +00001169 } else if (PPC::F8RCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001170 HasFPSaveArea = true;
1171
1172 FPRegs.push_back(CSI[i]);
1173
1174 if (Reg < MinFPR) {
1175 MinFPR = Reg;
1176 }
Craig Topperabadc662012-04-20 06:31:50 +00001177 } else if (PPC::CRBITRCRegClass.contains(Reg) ||
1178 PPC::CRRCRegClass.contains(Reg)) {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001179 ; // do nothing, as we already know whether CRs are spilled
Craig Topperabadc662012-04-20 06:31:50 +00001180 } else if (PPC::VRSAVERCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001181 HasVRSAVESaveArea = true;
Craig Topperabadc662012-04-20 06:31:50 +00001182 } else if (PPC::VRRCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001183 HasVRSaveArea = true;
1184
1185 VRegs.push_back(CSI[i]);
1186
1187 if (Reg < MinVR) {
1188 MinVR = Reg;
1189 }
1190 } else {
1191 llvm_unreachable("Unknown RegisterClass!");
1192 }
1193 }
1194
1195 PPCFunctionInfo *PFI = MF.getInfo<PPCFunctionInfo>();
Hal Finkelfeea6532013-03-26 20:08:20 +00001196 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001197
1198 int64_t LowerBound = 0;
1199
1200 // Take into account stack space reserved for tail calls.
1201 int TCSPDelta = 0;
Nick Lewycky50f02cb2011-12-02 22:16:29 +00001202 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1203 (TCSPDelta = PFI->getTailCallSPDelta()) < 0) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001204 LowerBound = TCSPDelta;
1205 }
1206
1207 // The Floating-point register save area is right below the back chain word
1208 // of the previous stack frame.
1209 if (HasFPSaveArea) {
1210 for (unsigned i = 0, e = FPRegs.size(); i != e; ++i) {
1211 int FI = FPRegs[i].getFrameIdx();
1212
1213 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1214 }
1215
Hal Finkelfeea6532013-03-26 20:08:20 +00001216 LowerBound -= (31 - TRI->getEncodingValue(MinFPR) + 1) * 8;
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001217 }
1218
1219 // Check whether the frame pointer register is allocated. If so, make sure it
1220 // is spilled to the correct offset.
Anton Korobeynikov3eb4fed2010-12-18 19:53:14 +00001221 if (needsFP(MF)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001222 HasGPSaveArea = true;
1223
1224 int FI = PFI->getFramePointerSaveIndex();
1225 assert(FI && "No Frame Pointer Save Slot!");
1226
1227 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1228 }
1229
Hal Finkela7c54e82013-07-17 00:45:52 +00001230 const PPCRegisterInfo *RegInfo =
1231 static_cast<const PPCRegisterInfo*>(MF.getTarget().getRegisterInfo());
1232 if (RegInfo->hasBasePointer(MF)) {
1233 HasGPSaveArea = true;
1234
1235 int FI = PFI->getBasePointerSaveIndex();
1236 assert(FI && "No Base Pointer Save Slot!");
1237
1238 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1239 }
1240
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001241 // General register save area starts right below the Floating-point
1242 // register save area.
1243 if (HasGPSaveArea || HasG8SaveArea) {
1244 // Move general register save area spill slots down, taking into account
1245 // the size of the Floating-point register save area.
1246 for (unsigned i = 0, e = GPRegs.size(); i != e; ++i) {
1247 int FI = GPRegs[i].getFrameIdx();
1248
1249 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1250 }
1251
1252 // Move general register save area spill slots down, taking into account
1253 // the size of the Floating-point register save area.
1254 for (unsigned i = 0, e = G8Regs.size(); i != e; ++i) {
1255 int FI = G8Regs[i].getFrameIdx();
1256
1257 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1258 }
1259
1260 unsigned MinReg =
Hal Finkelfeea6532013-03-26 20:08:20 +00001261 std::min<unsigned>(TRI->getEncodingValue(MinGPR),
1262 TRI->getEncodingValue(MinG8R));
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001263
1264 if (Subtarget.isPPC64()) {
1265 LowerBound -= (31 - MinReg + 1) * 8;
1266 } else {
1267 LowerBound -= (31 - MinReg + 1) * 4;
1268 }
1269 }
1270
Roman Divackyc9e23d92012-09-12 14:47:47 +00001271 // For 32-bit only, the CR save area is below the general register
1272 // save area. For 64-bit SVR4, the CR save area is addressed relative
1273 // to the stack pointer and hence does not need an adjustment here.
1274 // Only CR2 (the first nonvolatile spilled) has an associated frame
1275 // index so that we have a single uniform save area.
1276 if (spillsCR(MF) && !(Subtarget.isPPC64() && Subtarget.isSVR4ABI())) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001277 // Adjust the frame index of the CR spill slot.
1278 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1279 unsigned Reg = CSI[i].getReg();
1280
Roman Divackyc9e23d92012-09-12 14:47:47 +00001281 if ((Subtarget.isSVR4ABI() && Reg == PPC::CR2)
Eric Christopherd1737492014-04-29 00:16:40 +00001282 // Leave Darwin logic as-is.
1283 || (!Subtarget.isSVR4ABI() &&
1284 (PPC::CRBITRCRegClass.contains(Reg) ||
1285 PPC::CRRCRegClass.contains(Reg)))) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001286 int FI = CSI[i].getFrameIdx();
1287
1288 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1289 }
1290 }
1291
1292 LowerBound -= 4; // The CR save area is always 4 bytes long.
1293 }
1294
1295 if (HasVRSAVESaveArea) {
1296 // FIXME SVR4: Is it actually possible to have multiple elements in CSI
1297 // which have the VRSAVE register class?
1298 // Adjust the frame index of the VRSAVE spill slot.
1299 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1300 unsigned Reg = CSI[i].getReg();
1301
Craig Topperabadc662012-04-20 06:31:50 +00001302 if (PPC::VRSAVERCRegClass.contains(Reg)) {
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001303 int FI = CSI[i].getFrameIdx();
1304
1305 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1306 }
1307 }
1308
1309 LowerBound -= 4; // The VRSAVE save area is always 4 bytes long.
1310 }
1311
1312 if (HasVRSaveArea) {
1313 // Insert alignment padding, we need 16-byte alignment.
1314 LowerBound = (LowerBound - 15) & ~(15);
1315
1316 for (unsigned i = 0, e = VRegs.size(); i != e; ++i) {
1317 int FI = VRegs[i].getFrameIdx();
1318
1319 FFI->setObjectOffset(FI, LowerBound + FFI->getObjectOffset(FI));
1320 }
1321 }
Hal Finkelbb420f12013-03-15 05:06:04 +00001322
1323 addScavengingSpillSlot(MF, RS);
1324}
1325
1326void
1327PPCFrameLowering::addScavengingSpillSlot(MachineFunction &MF,
1328 RegScavenger *RS) const {
1329 // Reserve a slot closest to SP or frame pointer if we have a dynalloc or
1330 // a large stack, which will require scavenging a register to materialize a
1331 // large offset.
1332
1333 // We need to have a scavenger spill slot for spills if the frame size is
1334 // large. In case there is no free register for large-offset addressing,
1335 // this slot is used for the necessary emergency spill. Also, we need the
1336 // slot for dynamic stack allocations.
1337
1338 // The scavenger might be invoked if the frame offset does not fit into
1339 // the 16-bit immediate. We don't know the complete frame size here
1340 // because we've not yet computed callee-saved register spills or the
1341 // needed alignment padding.
1342 unsigned StackSize = determineFrameLayout(MF, false, true);
1343 MachineFrameInfo *MFI = MF.getFrameInfo();
Hal Finkelcc1eeda2013-03-23 22:06:03 +00001344 if (MFI->hasVarSizedObjects() || spillsCR(MF) || spillsVRSAVE(MF) ||
1345 hasNonRISpills(MF) || (hasSpills(MF) && !isInt<16>(StackSize))) {
Hal Finkelbb420f12013-03-15 05:06:04 +00001346 const TargetRegisterClass *GPRC = &PPC::GPRCRegClass;
1347 const TargetRegisterClass *G8RC = &PPC::G8RCRegClass;
1348 const TargetRegisterClass *RC = Subtarget.isPPC64() ? G8RC : GPRC;
Hal Finkel9e331c22013-03-22 23:32:27 +00001349 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
Hal Finkelbb420f12013-03-15 05:06:04 +00001350 RC->getAlignment(),
1351 false));
Hal Finkel0dfbb052013-03-26 18:57:22 +00001352
Hal Finkel18607632013-07-18 04:28:21 +00001353 // Might we have over-aligned allocas?
1354 bool HasAlVars = MFI->hasVarSizedObjects() &&
1355 MFI->getMaxAlignment() > getStackAlignment();
1356
Hal Finkel0dfbb052013-03-26 18:57:22 +00001357 // These kinds of spills might need two registers.
Hal Finkel18607632013-07-18 04:28:21 +00001358 if (spillsCR(MF) || spillsVRSAVE(MF) || HasAlVars)
Hal Finkel0dfbb052013-03-26 18:57:22 +00001359 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
1360 RC->getAlignment(),
1361 false));
1362
Hal Finkelbb420f12013-03-15 05:06:04 +00001363 }
Anton Korobeynikov7283b8d2010-11-27 23:05:25 +00001364}
Roman Divackyc9e23d92012-09-12 14:47:47 +00001365
Eric Christopherd1737492014-04-29 00:16:40 +00001366bool
Roman Divackyc9e23d92012-09-12 14:47:47 +00001367PPCFrameLowering::spillCalleeSavedRegisters(MachineBasicBlock &MBB,
Eric Christopherd1737492014-04-29 00:16:40 +00001368 MachineBasicBlock::iterator MI,
1369 const std::vector<CalleeSavedInfo> &CSI,
1370 const TargetRegisterInfo *TRI) const {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001371
1372 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1373 // Return false otherwise to maintain pre-existing behavior.
1374 if (!Subtarget.isSVR4ABI())
1375 return false;
1376
1377 MachineFunction *MF = MBB.getParent();
1378 const PPCInstrInfo &TII =
1379 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1380 DebugLoc DL;
1381 bool CRSpilled = false;
Hal Finkel2f293912013-04-13 23:06:15 +00001382 MachineInstrBuilder CRMIB;
Eric Christopherd1737492014-04-29 00:16:40 +00001383
Roman Divackyc9e23d92012-09-12 14:47:47 +00001384 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1385 unsigned Reg = CSI[i].getReg();
Hal Finkelac1a24b2013-06-28 22:29:56 +00001386 // Only Darwin actually uses the VRSAVE register, but it can still appear
1387 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1388 // Darwin, ignore it.
1389 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1390 continue;
1391
Roman Divackyc9e23d92012-09-12 14:47:47 +00001392 // CR2 through CR4 are the nonvolatile CR fields.
1393 bool IsCRField = PPC::CR2 <= Reg && Reg <= PPC::CR4;
1394
Roman Divackyc9e23d92012-09-12 14:47:47 +00001395 // Add the callee-saved register as live-in; it's killed at the spill.
1396 MBB.addLiveIn(Reg);
1397
Hal Finkel2f293912013-04-13 23:06:15 +00001398 if (CRSpilled && IsCRField) {
1399 CRMIB.addReg(Reg, RegState::ImplicitKill);
1400 continue;
1401 }
1402
Roman Divackyc9e23d92012-09-12 14:47:47 +00001403 // Insert the spill to the stack frame.
1404 if (IsCRField) {
Hal Finkel67369882013-04-15 02:07:05 +00001405 PPCFunctionInfo *FuncInfo = MF->getInfo<PPCFunctionInfo>();
Roman Divackyc9e23d92012-09-12 14:47:47 +00001406 if (Subtarget.isPPC64()) {
Hal Finkel67369882013-04-15 02:07:05 +00001407 // The actual spill will happen at the start of the prologue.
1408 FuncInfo->addMustSaveCR(Reg);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001409 } else {
Hal Finkel67369882013-04-15 02:07:05 +00001410 CRSpilled = true;
Bill Schmidtef3d1a22013-05-14 16:08:32 +00001411 FuncInfo->setSpillsCR();
Hal Finkel67369882013-04-15 02:07:05 +00001412
Eric Christopherd1737492014-04-29 00:16:40 +00001413 // 32-bit: FP-relative. Note that we made sure CR2-CR4 all have
1414 // the same frame index in PPCRegisterInfo::hasReservedSpillSlot.
1415 CRMIB = BuildMI(*MF, DL, TII.get(PPC::MFCR), PPC::R12)
Hal Finkel2f293912013-04-13 23:06:15 +00001416 .addReg(Reg, RegState::ImplicitKill);
1417
Eric Christopherd1737492014-04-29 00:16:40 +00001418 MBB.insert(MI, CRMIB);
1419 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::STW))
1420 .addReg(PPC::R12,
1421 getKillRegState(true)),
1422 CSI[i].getFrameIdx()));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001423 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001424 } else {
1425 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1426 TII.storeRegToStackSlot(MBB, MI, Reg, true,
Eric Christopherd1737492014-04-29 00:16:40 +00001427 CSI[i].getFrameIdx(), RC, TRI);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001428 }
1429 }
1430 return true;
1431}
1432
1433static void
Hal Finkeld85a04b2013-04-13 08:09:20 +00001434restoreCRs(bool isPPC64, bool is31,
1435 bool CR2Spilled, bool CR3Spilled, bool CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001436 MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
1437 const std::vector<CalleeSavedInfo> &CSI, unsigned CSIIndex) {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001438
1439 MachineFunction *MF = MBB.getParent();
1440 const PPCInstrInfo &TII =
1441 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1442 DebugLoc DL;
1443 unsigned RestoreOp, MoveReg;
1444
Hal Finkel67369882013-04-15 02:07:05 +00001445 if (isPPC64)
1446 // This is handled during epilogue generation.
1447 return;
1448 else {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001449 // 32-bit: FP-relative
1450 MBB.insert(MI, addFrameReference(BuildMI(*MF, DL, TII.get(PPC::LWZ),
Eric Christopherd1737492014-04-29 00:16:40 +00001451 PPC::R12),
1452 CSI[CSIIndex].getFrameIdx()));
Ulrich Weigand49f487e2013-07-03 17:59:07 +00001453 RestoreOp = PPC::MTOCRF;
Roman Divackyc9e23d92012-09-12 14:47:47 +00001454 MoveReg = PPC::R12;
1455 }
Eric Christopherd1737492014-04-29 00:16:40 +00001456
Roman Divackyc9e23d92012-09-12 14:47:47 +00001457 if (CR2Spilled)
1458 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR2)
Hal Finkel035b4822013-03-28 03:38:16 +00001459 .addReg(MoveReg, getKillRegState(!CR3Spilled && !CR4Spilled)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001460
1461 if (CR3Spilled)
1462 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR3)
Hal Finkel035b4822013-03-28 03:38:16 +00001463 .addReg(MoveReg, getKillRegState(!CR4Spilled)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001464
1465 if (CR4Spilled)
1466 MBB.insert(MI, BuildMI(*MF, DL, TII.get(RestoreOp), PPC::CR4)
Hal Finkel035b4822013-03-28 03:38:16 +00001467 .addReg(MoveReg, getKillRegState(true)));
Roman Divackyc9e23d92012-09-12 14:47:47 +00001468}
1469
Eli Bendersky8da87162013-02-21 20:05:00 +00001470void PPCFrameLowering::
1471eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
1472 MachineBasicBlock::iterator I) const {
1473 const PPCInstrInfo &TII =
1474 *static_cast<const PPCInstrInfo*>(MF.getTarget().getInstrInfo());
1475 if (MF.getTarget().Options.GuaranteedTailCallOpt &&
1476 I->getOpcode() == PPC::ADJCALLSTACKUP) {
1477 // Add (actually subtract) back the amount the callee popped on return.
1478 if (int CalleeAmt = I->getOperand(1).getImm()) {
1479 bool is64Bit = Subtarget.isPPC64();
1480 CalleeAmt *= -1;
1481 unsigned StackReg = is64Bit ? PPC::X1 : PPC::R1;
1482 unsigned TmpReg = is64Bit ? PPC::X0 : PPC::R0;
1483 unsigned ADDIInstr = is64Bit ? PPC::ADDI8 : PPC::ADDI;
1484 unsigned ADDInstr = is64Bit ? PPC::ADD8 : PPC::ADD4;
1485 unsigned LISInstr = is64Bit ? PPC::LIS8 : PPC::LIS;
1486 unsigned ORIInstr = is64Bit ? PPC::ORI8 : PPC::ORI;
1487 MachineInstr *MI = I;
1488 DebugLoc dl = MI->getDebugLoc();
1489
1490 if (isInt<16>(CalleeAmt)) {
1491 BuildMI(MBB, I, dl, TII.get(ADDIInstr), StackReg)
1492 .addReg(StackReg, RegState::Kill)
1493 .addImm(CalleeAmt);
1494 } else {
1495 MachineBasicBlock::iterator MBBI = I;
1496 BuildMI(MBB, MBBI, dl, TII.get(LISInstr), TmpReg)
1497 .addImm(CalleeAmt >> 16);
1498 BuildMI(MBB, MBBI, dl, TII.get(ORIInstr), TmpReg)
1499 .addReg(TmpReg, RegState::Kill)
1500 .addImm(CalleeAmt & 0xFFFF);
1501 BuildMI(MBB, MBBI, dl, TII.get(ADDInstr), StackReg)
1502 .addReg(StackReg, RegState::Kill)
1503 .addReg(TmpReg);
1504 }
1505 }
1506 }
1507 // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
1508 MBB.erase(I);
1509}
1510
Eric Christopherd1737492014-04-29 00:16:40 +00001511bool
Roman Divackyc9e23d92012-09-12 14:47:47 +00001512PPCFrameLowering::restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
Eric Christopherd1737492014-04-29 00:16:40 +00001513 MachineBasicBlock::iterator MI,
1514 const std::vector<CalleeSavedInfo> &CSI,
1515 const TargetRegisterInfo *TRI) const {
Roman Divackyc9e23d92012-09-12 14:47:47 +00001516
1517 // Currently, this function only handles SVR4 32- and 64-bit ABIs.
1518 // Return false otherwise to maintain pre-existing behavior.
1519 if (!Subtarget.isSVR4ABI())
1520 return false;
1521
1522 MachineFunction *MF = MBB.getParent();
1523 const PPCInstrInfo &TII =
1524 *static_cast<const PPCInstrInfo*>(MF->getTarget().getInstrInfo());
1525 bool CR2Spilled = false;
1526 bool CR3Spilled = false;
1527 bool CR4Spilled = false;
1528 unsigned CSIIndex = 0;
1529
1530 // Initialize insertion-point logic; we will be restoring in reverse
1531 // order of spill.
1532 MachineBasicBlock::iterator I = MI, BeforeI = I;
1533 bool AtStart = I == MBB.begin();
1534
1535 if (!AtStart)
1536 --BeforeI;
1537
1538 for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
1539 unsigned Reg = CSI[i].getReg();
1540
Hal Finkelac1a24b2013-06-28 22:29:56 +00001541 // Only Darwin actually uses the VRSAVE register, but it can still appear
1542 // here if, for example, @llvm.eh.unwind.init() is used. If we're not on
1543 // Darwin, ignore it.
1544 if (Reg == PPC::VRSAVE && !Subtarget.isDarwinABI())
1545 continue;
1546
Roman Divackyc9e23d92012-09-12 14:47:47 +00001547 if (Reg == PPC::CR2) {
1548 CR2Spilled = true;
1549 // The spill slot is associated only with CR2, which is the
1550 // first nonvolatile spilled. Save it here.
1551 CSIIndex = i;
1552 continue;
1553 } else if (Reg == PPC::CR3) {
1554 CR3Spilled = true;
1555 continue;
1556 } else if (Reg == PPC::CR4) {
1557 CR4Spilled = true;
1558 continue;
1559 } else {
1560 // When we first encounter a non-CR register after seeing at
1561 // least one CR register, restore all spilled CRs together.
1562 if ((CR2Spilled || CR3Spilled || CR4Spilled)
Eric Christopherd1737492014-04-29 00:16:40 +00001563 && !(PPC::CR2 <= Reg && Reg <= PPC::CR4)) {
Hal Finkeld85a04b2013-04-13 08:09:20 +00001564 bool is31 = needsFP(*MF);
1565 restoreCRs(Subtarget.isPPC64(), is31,
1566 CR2Spilled, CR3Spilled, CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001567 MBB, I, CSI, CSIIndex);
1568 CR2Spilled = CR3Spilled = CR4Spilled = false;
Roman Divackyc9e23d92012-09-12 14:47:47 +00001569 }
1570
1571 // Default behavior for non-CR saves.
1572 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
1573 TII.loadRegFromStackSlot(MBB, I, Reg, CSI[i].getFrameIdx(),
Eric Christopherd1737492014-04-29 00:16:40 +00001574 RC, TRI);
Roman Divackyc9e23d92012-09-12 14:47:47 +00001575 assert(I != MBB.begin() &&
Eric Christopherd1737492014-04-29 00:16:40 +00001576 "loadRegFromStackSlot didn't insert any code!");
Roman Divackyc9e23d92012-09-12 14:47:47 +00001577 }
1578
1579 // Insert in reverse order.
1580 if (AtStart)
1581 I = MBB.begin();
1582 else {
1583 I = BeforeI;
1584 ++I;
Eric Christopherd1737492014-04-29 00:16:40 +00001585 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001586 }
1587
1588 // If we haven't yet spilled the CRs, do so now.
Hal Finkeld85a04b2013-04-13 08:09:20 +00001589 if (CR2Spilled || CR3Spilled || CR4Spilled) {
Eric Christopherd1737492014-04-29 00:16:40 +00001590 bool is31 = needsFP(*MF);
Hal Finkeld85a04b2013-04-13 08:09:20 +00001591 restoreCRs(Subtarget.isPPC64(), is31, CR2Spilled, CR3Spilled, CR4Spilled,
Eric Christopherd1737492014-04-29 00:16:40 +00001592 MBB, I, CSI, CSIIndex);
Hal Finkeld85a04b2013-04-13 08:09:20 +00001593 }
Roman Divackyc9e23d92012-09-12 14:47:47 +00001594
1595 return true;
1596}