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Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +00001//===-- SIFixVGPRCopies.cpp - Fix VGPR Copies after regalloc --------------===//
2//
Chandler Carruth2946cd72019-01-19 08:50:56 +00003// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +00006//
7//===----------------------------------------------------------------------===//
8//
9/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000010/// Add implicit use of exec to vector register copies.
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +000011///
12//===----------------------------------------------------------------------===//
13
14#include "AMDGPU.h"
15#include "AMDGPUSubtarget.h"
16#include "SIInstrInfo.h"
Tom Stellard44b30b42018-05-22 02:03:23 +000017#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +000018#include "llvm/CodeGen/MachineFunctionPass.h"
19
20using namespace llvm;
21
22#define DEBUG_TYPE "si-fix-vgpr-copies"
23
24namespace {
25
26class SIFixVGPRCopies : public MachineFunctionPass {
27public:
28 static char ID;
29
30public:
31 SIFixVGPRCopies() : MachineFunctionPass(ID) {
32 initializeSIFixVGPRCopiesPass(*PassRegistry::getPassRegistry());
33 }
34
35 bool runOnMachineFunction(MachineFunction &MF) override;
36
37 StringRef getPassName() const override { return "SI Fix VGPR copies"; }
38};
39
40} // End anonymous namespace.
41
42INITIALIZE_PASS(SIFixVGPRCopies, DEBUG_TYPE, "SI Fix VGPR copies", false, false)
43
44char SIFixVGPRCopies::ID = 0;
45
46char &llvm::SIFixVGPRCopiesID = SIFixVGPRCopies::ID;
47
48bool SIFixVGPRCopies::runOnMachineFunction(MachineFunction &MF) {
Tom Stellard5bfbae52018-07-11 20:59:01 +000049 const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +000050 const SIRegisterInfo *TRI = ST.getRegisterInfo();
51 const SIInstrInfo *TII = ST.getInstrInfo();
52 bool Changed = false;
53
54 for (MachineBasicBlock &MBB : MF) {
55 for (MachineInstr &MI : MBB) {
56 switch (MI.getOpcode()) {
57 case AMDGPU::COPY:
58 if (TII->isVGPRCopy(MI) && !MI.readsRegister(AMDGPU::EXEC, TRI)) {
59 MI.addOperand(MF,
60 MachineOperand::CreateReg(AMDGPU::EXEC, false, true));
Nicola Zaghend34e60c2018-05-14 12:53:11 +000061 LLVM_DEBUG(dbgs() << "Add exec use to " << MI);
Stanislav Mekhanoshin22a56f22017-01-24 17:46:17 +000062 Changed = true;
63 }
64 break;
65 default:
66 break;
67 }
68 }
69 }
70
71 return Changed;
72}