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Evan Cheng0d639a22011-07-01 21:01:15 +00001//===-- TargetSubtargetInfo.cpp - General Target Information ---------------==//
Nate Begemanf26625e2005-07-12 01:41:54 +00002//
3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +00005// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Nate Begemanf26625e2005-07-12 01:41:54 +00007//
8//===----------------------------------------------------------------------===//
9//
10// This file describes the general parts of a Subtarget.
11//
12//===----------------------------------------------------------------------===//
13
Andrew Trick71e8bb62013-09-26 05:53:35 +000014#include "llvm/Support/CommandLine.h"
David Goodwin0d412c22009-11-10 00:48:55 +000015#include "llvm/ADT/SmallVector.h"
Chandler Carruth8a8cd2b2014-01-07 11:48:04 +000016#include "llvm/Target/TargetSubtargetInfo.h"
Nate Begemanf26625e2005-07-12 01:41:54 +000017using namespace llvm;
18
19//---------------------------------------------------------------------------
Evan Cheng0d639a22011-07-01 21:01:15 +000020// TargetSubtargetInfo Class
Nate Begemanf26625e2005-07-12 01:41:54 +000021//
Evan Cheng0d639a22011-07-01 21:01:15 +000022TargetSubtargetInfo::TargetSubtargetInfo() {}
Nate Begemanf26625e2005-07-12 01:41:54 +000023
Evan Cheng0d639a22011-07-01 21:01:15 +000024TargetSubtargetInfo::~TargetSubtargetInfo() {}
David Goodwin0d412c22009-11-10 00:48:55 +000025
Andrew Trick71e8bb62013-09-26 05:53:35 +000026// Temporary option to compare overall performance change when moving from the
Andrew Trickd0d8cb12014-05-06 22:18:43 +000027// SD scheduler to the MachineScheduler pass pipeline. This is convenient for
28// benchmarking during the transition from SD to MI scheduling. Once armv7 makes
29// the switch, it should go away. The normal way to enable/disable the
30// MachineScheduling pass itself is by using -enable-misched. For targets that
31// already use MI sched (via MySubTarget::enableMachineScheduler())
32// -misched-bench=false negates the subtarget hook.
Andrew Trick71e8bb62013-09-26 05:53:35 +000033static cl::opt<bool> BenchMachineSched("misched-bench", cl::Hidden,
34 cl::desc("Migrate from the target's default SD scheduler to MI scheduler"));
35
36bool TargetSubtargetInfo::useMachineScheduler() const {
37 if (BenchMachineSched.getNumOccurrences())
38 return BenchMachineSched;
39 return enableMachineScheduler();
40}
41
Andrew Trick108c88c2012-11-13 08:47:29 +000042bool TargetSubtargetInfo::enableMachineScheduler() const {
43 return false;
44}
45
Andrew Trick8d2ee372014-06-04 07:06:27 +000046bool TargetSubtargetInfo::enablePostMachineScheduler() const {
47 return false;
48}
49
Evan Cheng0d639a22011-07-01 21:01:15 +000050bool TargetSubtargetInfo::enablePostRAScheduler(
David Goodwin0d412c22009-11-10 00:48:55 +000051 CodeGenOpt::Level OptLevel,
52 AntiDepBreakMode& Mode,
David Goodwinb9fe5d52009-11-13 19:52:48 +000053 RegClassVector& CriticalPathRCs) const {
David Goodwin0d412c22009-11-10 00:48:55 +000054 Mode = ANTIDEP_NONE;
David Goodwinb9fe5d52009-11-13 19:52:48 +000055 CriticalPathRCs.clear();
David Goodwin0d412c22009-11-10 00:48:55 +000056 return false;
57}
58
Hal Finkelb350ffd2013-08-29 03:25:05 +000059bool TargetSubtargetInfo::useAA() const {
60 return false;
61}