blob: 74b201c1b783227467f453b06f5dbb6ffe33f5fc [file] [log] [blame]
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00001; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
Matt Arsenault7aad8fd2017-01-24 22:02:15 +00002; RUN: llc -march=amdgcn -mcpu=fiji -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00003
4declare half @llvm.ceil.f16(half %a)
5declare <2 x half> @llvm.ceil.v2f16(<2 x half> %a)
6
Matt Arsenault86e02ce2017-03-15 19:04:26 +00007; GCN-LABEL: {{^}}ceil_f16:
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00008; GCN: buffer_load_ushort v[[A_F16:[0-9]+]]
9; SI: v_cvt_f32_f16_e32 v[[A_F32:[0-9]+]], v[[A_F16]]
10; SI: v_ceil_f32_e32 v[[R_F32:[0-9]+]], v[[A_F32]]
11; SI: v_cvt_f16_f32_e32 v[[R_F16:[0-9]+]], v[[R_F32]]
12; VI: v_ceil_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]]
13; GCN: buffer_store_short v[[R_F16]]
14; GCN: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000015define amdgpu_kernel void @ceil_f16(
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000016 half addrspace(1)* %r,
17 half addrspace(1)* %a) {
18entry:
19 %a.val = load half, half addrspace(1)* %a
20 %r.val = call half @llvm.ceil.f16(half %a.val)
21 store half %r.val, half addrspace(1)* %r
22 ret void
23}
24
Matt Arsenault86e02ce2017-03-15 19:04:26 +000025; GCN-LABEL: {{^}}ceil_v2f16:
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000026; GCN: buffer_load_dword v[[A_V2_F16:[0-9]+]]
27; SI: v_cvt_f32_f16_e32 v[[A_F32_0:[0-9]+]], v[[A_V2_F16]]
28; GCN: v_lshrrev_b32_e32 v[[A_F16_1:[0-9]+]], 16, v[[A_V2_F16]]
29; SI: v_cvt_f32_f16_e32 v[[A_F32_1:[0-9]+]], v[[A_F16_1]]
30; SI: v_ceil_f32_e32 v[[R_F32_0:[0-9]+]], v[[A_F32_0]]
31; SI: v_cvt_f16_f32_e32 v[[R_F16_0:[0-9]+]], v[[R_F32_0]]
32; SI: v_ceil_f32_e32 v[[R_F32_1:[0-9]+]], v[[A_F32_1]]
33; SI: v_cvt_f16_f32_e32 v[[R_F16_1:[0-9]+]], v[[R_F32_1]]
Matt Arsenault8edfaee2017-03-31 19:53:03 +000034; VI-DAG: v_ceil_f16_e32 v[[R_F16_0:[0-9]+]], v[[A_V2_F16]]
35; VI-DAG: v_ceil_f16_e32 v[[R_F16_1:[0-9]+]], v[[A_F16_1]]
36; GCN-DAG: v_lshlrev_b32_e32 v[[R_F16_HI:[0-9]+]], 16, v[[R_F16_1]]
37; GCN-NOT: and
Matt Arsenault86e02ce2017-03-15 19:04:26 +000038; GCN: v_or_b32_e32 v[[R_V2_F16:[0-9]+]], v[[R_F16_HI]], v[[R_F16_0]]
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000039; GCN: buffer_store_dword v[[R_V2_F16]]
40; GCN: s_endpgm
Matt Arsenault3dbeefa2017-03-21 21:39:51 +000041define amdgpu_kernel void @ceil_v2f16(
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000042 <2 x half> addrspace(1)* %r,
43 <2 x half> addrspace(1)* %a) {
44entry:
45 %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
46 %r.val = call <2 x half> @llvm.ceil.v2f16(<2 x half> %a.val)
47 store <2 x half> %r.val, <2 x half> addrspace(1)* %r
48 ret void
49}