| Amara Emerson | 854d10d | 2018-01-02 16:30:47 +0000 | [diff] [blame] | 1 | ; RUN: llc -O0 -fast-isel -verify-machineinstrs -mtriple=arm64-eabi < %s | FileCheck --enable-var-scope %s |
| I-Jui (Ray) Sung | 21fde38 | 2017-06-09 22:40:50 +0000 | [diff] [blame] | 2 | |
| 3 | ; Test fptosi |
| 4 | define i32 @fptosi_wh(half %a) nounwind ssp { |
| 5 | entry: |
| 6 | ; CHECK-LABEL: fptosi_wh |
| 7 | ; CHECK: fcvt s1, h0 |
| 8 | ; CHECK: fcvtzs [[REG:w[0-9]+]], s1 |
| 9 | ; CHECK: mov w0, [[REG]] |
| 10 | %conv = fptosi half %a to i32 |
| 11 | ret i32 %conv |
| 12 | } |
| 13 | |
| 14 | ; Test fptoui |
| 15 | define i32 @fptoui_swh(half %a) nounwind ssp { |
| 16 | entry: |
| 17 | ; CHECK-LABEL: fptoui_swh |
| 18 | ; CHECK: fcvt s1, h0 |
| 19 | ; CHECK: fcvtzu [[REG:w[0-9]+]], s1 |
| 20 | ; CHECK: mov w0, [[REG]] |
| 21 | %conv = fptoui half %a to i32 |
| 22 | ret i32 %conv |
| 23 | } |
| 24 | |
| 25 | ; Test sitofp |
| 26 | define half @sitofp_hw_i1(i1 %a) nounwind ssp { |
| 27 | entry: |
| 28 | ; CHECK-LABEL: sitofp_hw_i1 |
| 29 | ; CHECK: sbfx w0, w0, #0, #1 |
| 30 | ; CHECK: scvtf s0, w0 |
| 31 | ; CHECK: fcvt h0, s0 |
| 32 | %conv = sitofp i1 %a to half |
| 33 | ret half %conv |
| 34 | } |
| 35 | |
| 36 | ; Test sitofp |
| 37 | define half @sitofp_hw_i8(i8 %a) nounwind ssp { |
| 38 | entry: |
| 39 | ; CHECK-LABEL: sitofp_hw_i8 |
| 40 | ; CHECK: sxtb w0, w0 |
| 41 | ; CHECK: scvtf s0, w0 |
| 42 | ; CHECK: fcvt h0, s0 |
| 43 | %conv = sitofp i8 %a to half |
| 44 | ret half %conv |
| 45 | } |
| 46 | |
| 47 | ; Test sitofp |
| 48 | define half @sitofp_hw_i16(i16 %a) nounwind ssp { |
| 49 | entry: |
| 50 | ; CHECK-LABEL: sitofp_hw_i16 |
| 51 | ; CHECK: sxth w0, w0 |
| 52 | ; CHECK: scvtf s0, w0 |
| 53 | ; CHECK: fcvt h0, s0 |
| 54 | %conv = sitofp i16 %a to half |
| 55 | ret half %conv |
| 56 | } |
| 57 | |
| 58 | ; Test sitofp |
| 59 | define half @sitofp_hw_i32(i32 %a) nounwind ssp { |
| 60 | entry: |
| 61 | ; CHECK-LABEL: sitofp_hw_i32 |
| 62 | ; CHECK: scvtf s0, w0 |
| 63 | ; CHECK: fcvt h0, s0 |
| 64 | %conv = sitofp i32 %a to half |
| 65 | ret half %conv |
| 66 | } |
| 67 | |
| 68 | ; Test sitofp |
| 69 | define half @sitofp_hx(i64 %a) nounwind ssp { |
| 70 | entry: |
| 71 | ; CHECK-LABEL: sitofp_hx |
| 72 | ; CHECK: scvtf s0, x0 |
| 73 | ; CHECK: fcvt h0, s0 |
| 74 | %conv = sitofp i64 %a to half |
| 75 | ret half %conv |
| 76 | } |
| 77 | |
| 78 | ; Test uitofp |
| 79 | define half @uitofp_hw_i1(i1 %a) nounwind ssp { |
| 80 | entry: |
| 81 | ; CHECK-LABEL: uitofp_hw_i1 |
| 82 | ; CHECK: and w0, w0, #0x1 |
| 83 | ; CHECK: ucvtf s0, w0 |
| 84 | ; CHECK: fcvt h0, s0 |
| 85 | %conv = uitofp i1 %a to half |
| 86 | ret half %conv |
| 87 | } |
| 88 | |
| 89 | ; Test uitofp |
| 90 | define half @uitofp_hw_i8(i8 %a) nounwind ssp { |
| 91 | entry: |
| 92 | ; CHECK-LABEL: uitofp_hw_i8 |
| 93 | ; CHECK: and w0, w0, #0xff |
| 94 | ; CHECK: ucvtf s0, w0 |
| 95 | ; CHECK: fcvt h0, s0 |
| 96 | %conv = uitofp i8 %a to half |
| 97 | ret half %conv |
| 98 | } |
| 99 | |
| 100 | ; Test uitofp |
| 101 | define half @uitofp_hw_i16(i16 %a) nounwind ssp { |
| 102 | entry: |
| 103 | ; CHECK-LABEL: uitofp_hw_i16 |
| 104 | ; CHECK: and w0, w0, #0xffff |
| 105 | ; CHECK: ucvtf s0, w0 |
| 106 | ; CHECK: fcvt h0, s0 |
| 107 | %conv = uitofp i16 %a to half |
| 108 | ret half %conv |
| 109 | } |
| 110 | |
| 111 | ; Test uitofp |
| 112 | define half @uitofp_hw_i32(i32 %a) nounwind ssp { |
| 113 | entry: |
| 114 | ; CHECK-LABEL: uitofp_hw_i32 |
| 115 | ; CHECK: ucvtf s0, w0 |
| 116 | ; CHECK: fcvt h0, s0 |
| 117 | %conv = uitofp i32 %a to half |
| 118 | ret half %conv |
| 119 | } |
| 120 | |
| 121 | ; Test uitofp |
| 122 | define half @uitofp_hx(i64 %a) nounwind ssp { |
| 123 | entry: |
| 124 | ; CHECK-LABEL: uitofp_hx |
| 125 | ; CHECK: ucvtf s0, x0 |
| 126 | ; CHECK: fcvt h0, s0 |
| 127 | %conv = uitofp i64 %a to half |
| 128 | ret half %conv |
| 129 | } |
| 130 | |
| 131 | |